FUJITSU SEMICONDUCTOR DATA SHEET Revision 2.0 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89470 Series MB89475/P475/PV470 DESCRIPTION The MB89470 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21-bit time-base timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, external interrupt 1 (edge), external interrupt 2 (level), 10-bit A/D converter, UART/SIO, buzzer, watchdog timer reset. The MB89470 series is designed suitable for home appliance as well as in a wide range of applications for consumer product. *: F2MC stands for FUJITSU Flexible Microcontroller. FEATURES * Package used QFP package and SH-DIP package for MB89P475, MB89475 MQFP package for MB89PV470 * High-speed operating capability at low voltage * Minimum execution time: 0.32 s/12.5MHz (Continued) PACKAGE 48-pin Plastic SH-DIP (DIP-48P-M01) 48-pin Plastic QFP 48-pin Ceramic MQFP (FPT-48P-M05) (MQP-48C-P01) MB89470 Series (Continued) * F2MC-8L family CPU core Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. * Six timers PWC timer (also usable as a interval timer) PWM timer 8/16-bit timer/counter x 2 21-bit timebase timer Watch prescaler * Buzzer 7 frequency types are selectable by software * External interrupts Edge detection (Selectable edge) : 4 channels Low-level interrupt (Wake-up function) : 5 channels * A/D converter (8 channels) 10-bit successive approximation type * UART/SIO Synchronous/asynchronous data transfer capable * Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) Subclock mode (for dual clock product) Watch mode (for dual clock product) * Watch dog timer reset * I/O ports: max. 39 channels 2 MB89470 Series PRODUCT LINEUP Part number number MB89475 MB89P475 MB89PV470 Classification Mass production products (mask ROM product) OTP (read protection) Piggy-back ROM size 16K x 8-bit (internal ROM) 16K x 8-bit (internal PROM, can be written to by FLASH programmer) Parameter Parameter RAM size 32K x 8-bit (external ROM) 1K x 8 bits 512 x 8 bits CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Minimum interrupt processing time: : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.32 s/12.5 MHz : 2.88 s/12.5 MHz Ports Output-only ports (N-channel open drain) Input-only ports : 7 pins : 3 pins (1 pin in product with dual clock) : 29 pins : 39 pins I/O ports (CMOS) Total 21-Bit Time-base timer Interrupt period (0.82ms, 3.3 ms, 26.2 ms, 419.4 ms) at 10 MHz Interrupt period (0.66ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz Watchdog timer Reset period (209.7 ms to 419.4 ms) at 10 MHz Reset period (167.8 ms to 335.5 ms) at 12.5 MHz Pulse width count timer 2 channels 8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 tinst, external) 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external) 8-bit pulse width measurement operation (supports continuous measurement, H width, L width, rising edge to rising edge, falling edge to falling edge measurement and both edge measurement) PWM timer 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external) 8-bit resolution PWM operation Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its 8/16-Bit timer/counter own independent operating clock cycle), or as one 16-bit timer/counter 1, 2 In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable Can be operated either as a 2-channel 8-bit timer/counter (Timer 3 and Timer 4, each with its 8/16-Bit timer/counter own independent operating clock cycle), or as one 16-bit timer/counter 3, 4 In Timer 3 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable External interrupt 4 independent channels (selectable edge, interrupt vector, request flag) 5 channels (low level interrupt) A/D converter 10-bit resolution x 8 channels A/D conversion function (conversion time: 60 tinst ) Supports repeated activation by internal clock. UART/SIO Synchronous/asynchronous data transfer capable (Max. baud rate: 78.125 Kbps at 10 MHz) (7 and 8 bits with parity bit ; 8 and 9 bits without parity bit) Note : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock. (Continued) 3 MB89470 Series (Continued) Part number number MB89475 Parameter Parameter MB89P475 MB89PV470 Buzzer output 7 frequency types (FCH/212, FCH/211, FCH/210, FCH/29, FCL/25, FCL/24, FCL/23, ) are selectable by software. Standby mode Sleep mode, stop mode, subclock mode(dual clock product) and watch mode(dual clock product) Process CMOS Operating Voltage 2.2V ~ 5.5V 3.5V ~ 5.5V 2.7V ~ 5.5V PACKAGE AND CORRESPONDING PRODUCTS Device MB89475 MB89P475 MB89PV470 DIP-48P-M01 O O X FPT-48P-M05 O O X MQP-48C-P01 X X O Package O : Availabe X : Not available DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption * For the MB89PV470, add the current consumed by the EPROM mounted in the piggy-back socket. * When operating at low speed, the current consumed by the one-time PROM product is greater than that for the mask ROM product. However, the current consumption are roughly the same in sleep or stop mode. * For more information, see " Electrical Characteristics." 3. Oscillation stabilization time after power-on reset * For MB89PV470, there is no power-on stabilization time after power-on reset * For MB89P475, there is power-on stabilization time after power-on reset * For MB89475, the power-on stabilization time can be select. * For more information, refer to " Mask Option". 4 MB89470 Series PIN ASSIGNMENT VSS C(see note) P40/X0A P41/X1A P17/TO2 P16/EC2 P15/TO1 P14/EC1 P13/INT13 P12/INT12 P11/INT11 P10/INT10 P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss AVcc P54/INT24 P53/INT23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 X1 X0 MODE P42 RST P20/SCK1 P21/SO1 P22/SI1 P23/PWC P24/PWM P25/SI2 VCC P26/SO2 P27/SCK2 P30/BUZ * P31 * P32 * P33 * P34 * P35 * P36 * P50/INT20 P51/INT21 P52/INT22 (DIP-48P-M01) Note : For pin no. 2, connect this pin to an external 0.1F capacitor to ground (for MB89P475 only). For MB89PV470 and MB89475, this pin should be left unconnected. * High current drive type 5 MB89470 Series 48 47 46 45 44 43 42 41 40 39 38 37 P34 * P35 * P36 * P50/INT20 P51/INT21 P52/INT22 P53/INT23 P54/INT24 AVcc AVss P00/AN0 P01/AN1 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14/EC1 P15/TO1 P20/SCK1 RST P42 MODE X0 X1 VSS C(see note) P40/X0A P41/X1A P17/TO2 P16/EC2 13 14 15 16 17 18 19 20 21 22 23 24 * P33 * P32 * P31 * P30/BUZ P27/SCK2 P26/SO2 VCC P25/SI2 P24/PWM P23/PWC P22/SI1 P21/SO1 (FPT-48P-M05) Note : For pin no. 20, connect this pin to an external 0.1F capacitor to ground (for MB89P475only). For MB89PV470 and MB89475, this pin should be left unconnected. * High current drive type 6 MB89470 Series *1 60 59 58 57 56 55 54 53 69 70 71 72 73 74 75 76 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14/EC1 P15/TO1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 77 78 79 80 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 * P33 * P32 * P31 * P30/BUZ P27/SCK2 P26/SO2 VCC P25/SI2 P24/PWM P23/PWC P22/SI1 P21/SO1 68 67 66 65 64 63 62 61 48 47 46 45 44 43 42 41 40 39 38 37 P34 * P35 * P36 * P50/INT20 P51/INT21 P52/INT22 P53/INT23 P54/INT24 AVcc AVss P00/AN0 P01/AN1 (TOP VIEW) P20/SCK1 RST P42 MODE X0 X1 VSS C(see note) P40/X0A P41/X1A P17/TO2 P16/EC2 (MQP-48C-P01) *1: Package upper-side pin assignment ( MB89PV470 only) Pin No. Pin Symbol Pin No. Pin Symbol Pin No. Pin Symbol Pin No. Pin Symbol 49 Vpp 57 N.C. 65 O4 73 OE 50 A12 58 A2 66 O5 74 N.C. 51 A7 59 A1 67 O6 75 A11 52 A6 60 A0 68 O7 76 A9 53 A5 61 O1 69 O8 77 A8 54 A4 62 O2 70 CE 78 A13 55 A3 63 O3 71 A10 79 A14 56 N.C. 64 Vss 72 N.C. 80 Vcc N.C.: As connected internally, do not use. Note : Pin no. 20 should be left unconnected. * High current drive type 7 MB89470 Series PIN DESCRIPTION Pin no. Pin name QFP/MQFP* 17 2 1 SDIP* 47 I/O circuit X0 Function A Connection pins for a crystal or other oscillator. An external clock can be connected to X0. In this case, leave X1 open. 18 48 X1 16 46 MODE B Input pins for setting the memory access mode. Connect directly to VSS. 14 44 RST C Reset I/O pin. The pin is a N-ch open-drain type with pull-up resistor and a hysteresis input. The pin outputs a "L" level when an internal reset request is present. Inputting an "L" level initializes internal circuits. 38 - 31 20 - 13 P00/AN0 P07/AN7 D General-purpose I/O port. The pins are shared with the analog inputs for the A/D converter. 30 - 27 12 - 9 P10/INT10 P13/INT13 E General-purpose I/O port. A hysteresis input for INT10~13. The pin is shared with an external interrupt 1 input. 26 8 P14/EC1 E General-purpose I/O port. A hysteresis input for EC1. The pin is shared with the 8/16 bit timer 1 input. 25 7 P15/TO1 F General-purpose I/O port. The pin is shared with the output of 8/16-bit timer 1. 24 6 P16/EC2 E General-purpose I/O port. A hysteresis input for EC2. The pin is shared with the 8/16 bit timer 2 input. 23 5 P17/TO2 F General-purpose I/O port. The pin is shared with the output of 8/16-bit timer 2. 13 43 P20/SCK1 E General-purpose I/O port. A hysteresis input for SCK1. The pin is shared with the clock I/O of UART/SIO 1. 12 42 P21/SO1 F General-purpose I/O port. The pin is shared with the serial data output of UART/SIO 1. 11 41 P22/SI1 E General-purpose I/O port. A hysteresis input for SI1. The pin is shared with the serial data input of UART/SIO 1. 10 40 P23/PWC E General-purpose I/O port. A hysteresis input for PWC. This pin is shared with PWC input. 9 39 P24/PWM F General-purpose input port. This pin is shared with PWM output. 8 38 P25/SI2 E General-purpose I/O port. A hysteresis input for SI2. The pin is shared with the serial data input of UART/SIO 2. 6 36 P26/SO2 F General-purpose I/O port. The pin is shared with the serial data output of UART/SIO 2. 5 35 P27/SCK2 E General-purpose I/O port. A hysteresis input for SCK2. The pin is shared with the clock I/O of UART/SIO 2. (Continued) 8 MB89470 Series (Continued) Pin no. Pin name I/O circuit Function QFP/MQFP*2 SDIP*1 4 34 P30/BUZ G N-channel open-drain output. The pin is shared with buzzer output. 3 - 1, 48 - 46 33 - 28 P31 - P36 G N-channel open-drain output. H General-purpose input port. (single clock system) 21 4 P40/X0A A Connection pins for a crystal or other oscillator. (dual clock system) An external clock can be connected to X0A. In this case, leave X1A open. H General-purpose input port. (single clock system) A Connection pins for a crystal or other oscillator. (dual clock system) An external clock can be connected to X0A. In this case, leave X1A open. 22 3 P41/X1A 15 45 P42 H General-purpose input port. 45 - 41 27 - 23 P50/INT20 P54/INT24 E General-purpose I/O port. A hysteresis input for INT20~INT24. The pin is shared with an external interrupt 2 input. 20 2 C -- Capacitor connection pin *3 7 37 VCC -- Power supply pin (+5V). 19 1 VSS -- Power supply pin (GND). 40 22 AVCC -- A/D converter power supply pin. 39 21 AVSS -- A/D converter power supply pin. Use at the same voltage level as VSS. *1: DIP-48P-M01 *2: FPT-48P-M05 / MQP-48C-P01 *3: When MB89475 or MB89PV470 is used, this pin will become a N.C. pin without internal connection. When MB89P475 is used, connect this pin to an external 0.1uF capacitor to ground. 9 MB89470 Series * External EPROM Socket (MB89PV470 only) Pin Number I/O MQFP Pin Name 49 Vpp O "H" level output pin 50 51 52 53 54 55 58 59 60 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins. 61 62 63 O1 O2 O3 I Data input pins. 64 VSS O Power supply pin (GND). 65 66 67 68 69 O4 O5 O6 O7 O8 I Data input pins. 70 CE O Chip enable pin for the ROM. Outputs "H" in standby mode. 71 A10 O Address output pin. 72 OE O Output enable pin for the ROM. Always outputs "L". 75 76 77 78 79 A11 A9 A8 A13 A14 O Address output pins. 80 VCC O Power supply pin for the EPROM. 56 57 72 74 N.C. -- Internally connected pins. Always leave open. *1 *1: MQP-48C-P01 10 Function MB89470 Series I/O CIRCUIT TYPE Circuit Class Circuit Remarks X1 (X1A) Nch Pch Pch X0 (X0A) A * Main and sub-clock circuits Nch Stop mode control signal * Hysteresis input * The pull-down resistor is approx. 50k. (No pull-down resistor in MB89P475) B R Pch * The pull-up resistance (Pchannel) is approx. 50 k. * Hysteresis input C Nch pull-up resistor register R * CMOS output * CMOS input * Selectable pull-up resistor Approx. 50 k Pch D Nch ADIN pull-up resistor register R Pch * CMOS output * CMOS input * Selectable pull-up resistor Approx. 50 k E Nch port resources (Continued) 11 MB89470 Series (Continued) pull-up resistor register R * CMOS output * CMOS input * Selectable pull-up resistor Approx. 50 k Pch F Nch pull-up resistor register R Pch * N-channel open-drain output * Selectable pull-up resistor Approx. 50 k G Nch H 12 port * CMOS input MB89470 Series HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in " Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = VCC and AVSS = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 13 MB89470 Series PROGRAMMING OTPROM IN MB89P475 WITH SERIAL PROGRAMMER 1. Programming the OTPROM with serial programmer * All OTP products can be programmed with serial programmer 2. Programming the OTPROM * To program the OTPROM using EPROM programmer AF200 (manufacturer: Yokogawa Digital Computer Corp.). Inquiry : Yokogawa Digital Computer Corp. : TEL (81)-42-333-6224 * To program the OTPROM using FUJITSU MCU programmer MB91919-001. Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770 FAX (65)-2810220 3. Programming Adaptor for OTPROM * To program the OTPROM using EPROM programmer AF200, use the programming adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package Compatible socker adaptor DIP-48P-M01 N/A FPT-48P-M05 T.B.D. Inquiry : Sun Hayato Co., Ltd : TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 * To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter listed below. Package Compatible socker adaptor DIP-48P-M01 T.B.D. FPT-48P-M05 T.B.D. Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770 FAX (65)-2810220 4. OTPROM Content Protection For product with OTPROM content protection feature (MB89P475-102, MB89P475-202), OTPROM content can be read using serial programmer if the OTPROM content protection mechanism is not activated. One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM content. If the protection code "00H" is written in this address (FFFCH), the OTPROM content cannot be read by any serial programmer. Note: The program written into the OTPROM cannot be verified once the OTPROM protection code is written ("00H" in FFFCH). It is advised to write the OTPROM protection code at last. 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 14 MB89470 Series PROGRAMMING OTPROM IN MB89P475 WITH GENERAL PURPOSE EPROM PROGRAMMER 1. Programming OTPROM with general purpose EPROM programmmer * Only products without protection feature (i.e. MB89P475-101 and MB89P475-201) can be programmed with general purpose EPROM programmer. Product with protection feature (i.e. MB89P475-102 and MB89P475202) cannot be programmed with general purpose programmer. 2. ROM Writer Adapters and Recommended ROM Writers * The following shows ROM writer adapters and recommended ROM writers. Applicable adapter model Recommended writer maker and writer Package name San Hayato Co., Ltd. Minato electronics Co., Ltd. MODEL1890A DIP-64P-M01 N/A N/A FPT-48P-M05 T.B.D Under evaluation * Contact information Sun Hayato Co., Ltd.: Phone 03-3986-0403 Minato electronics Co., Ltd.: Phone 045-591-5611 3. Writing data to the EPROM (1) Set the EPROM writer for the CU50-OTP (device code: cdB6DC). (2) Load the program data to the EPROM writer. (3) Write data using the EPROM writer. 4. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 15 MB89470 Series PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Square) Adapter socket part number ROM-32LC-28DP-S Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403 3. Memory Space Memory space in each mode is diagrammed below. Address Normal operating mode Corresponding addresses on the EPROM programmer 0000H I/O 0080H RAM 0880H 8000H Not available 0000H PROM 32KB FFFFH EPROM 32KB 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 16 MB89470 Series Block Diagram X0 X1 CMOS I/O Port 0 Oscillator 8 8 Clock controller P40/X0A P41/X1A P42 AVCC 10-bit A/D converter Sub-clock Oscillator P00/AN0 to P07/AN7 AVSS Watch Prescaler External interrupt 1 (Edge) Reset circuit (Watchdog timer) RST 21-bit Time-base timer P50/INT20 to P54/INT24 5 5 External interrupt 2 (Level) CMOS I/O port 5 1K Byte RAM / 512 Byte RAM F2MC-8L CPU Internal data bus CMOS Input port 4 4 4 P10/INT10 to P13/INT13 P14/EC1 P15/TO1 P16/EC2 P17/TO2 8/16-bit Timer 1,2 8/16-bit Timer 3,4 CMOS I/O port 1 UART/SIO 1 P20/SCK1 P21/SO1 P22/SI1 8-bit PWC P23/PWC 8-bit PWM P24/PWM P25/SI2 P26/SO2 P27/SCK2 UART/SIO 2 CMOS I/O port 2 16K Byte ROM Buzzer Other pins MODE, VCC, VSS, C *2 P30/BUZ *1 6 N-ch open-drain output port 3 P31*1 to P36 *1 *1 : High Current Pins *2 : Unconnected pin for MB89PV470 and MB89475 17 MB89470 Series CPU CORE 1. Memory Space The microcontrollers of the MB89470 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89470 series is structured as illustrated below. Memory Space MB89475 0000H MB89P475 0080H RAM 0080H 0280H RAM RAM 0100H 0100H Generalpurpose registers I/O I/O 0080H 0100H 0200H 0000H 0000H I/O MB89PV470 0200H Generalpurpose registers Generalpurpose 0200H registers 0280H 0480H Vacant Vacant Vacant 8000H C000H C000H FFC0H FFFFH ROM FFC0H FFFFH ROM FFC0H FFFFH Vector table (reset, interrupt, vector call instruction) 18 External ROM (32K) MB89470 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator. When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits PC FFFDH : Program counter A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 12 RP 11 10 9 8 Vacancy Vacancy Vacancy RP 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR 19 MB89470 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0 Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 20 MB89470 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit resister for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB89470 series. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 21 MB89470 Series I/O MAP Address Register name Register Description Read/Write Initial value 00H PDR0 Port 0 data register R/W XXXXXXXXB 01H DDR0 Port 0 data direction register W* 00000000B 02H PDR1 Port 1 data register R/W XXXXXXXXB 03H DDR1 Port 1 data direction register W* 00000000B 04H PDR2 Port 2 data register R/W 00000000B 05H (Reserved) 06H DDR2 Port 2 data direction register R/W 00000000B 07H SYCC System clock control register R/W -XXMM-00B 08H STBC Standby control register R/W 0001XXXXB 09H WDTC Watchdog timer control register W* 0---XXXXB 0AH TBTC Timebase timer control register R/W 00---000B 0BH WPCR Watch prescaler control register R/W 00--0000B 0CH PDR3 Port 3 data register R/W -1111111B 0DH PDR4 Port 4 data register R -----XXXB 0EH RSFR Reset flag register R XXXX----B 0FH BUZR Buzzer register R/W -----000B 10H PDR5 Port 5 data register R/W ---XXXXXB 11H DDR5 Port 5 data direction register R/W ---00000B 14H T4CR Timer 4 control register R/W 000000X0B 15H T3CR Timer 3 control register R/W 000000X0B 16H T4DR Timer 4 data register R/W XXXXXXXXB 17H T3DR Timer 3 data register R/W XXXXXXXXB 18H T2CR Timer 2 control register R/W 000000X0B 12H to 13H (Reserved) 19H T1CR Timer 1 control register R/W 000000X0B 1AH T2DR Timer 2 data register R/W XXXXXXXXB 1BH T1DR Timer 1 data register R/W XXXXXXXXB 1CH to 1FH (Reserved) 20H ADC1 A/D control register 1 R/W -00000X0B 21H ADC2 A/D control register 2 R/W -0000001B 22H ADDH A/D data register (Upper byte) R ------XXB 23H ADDL A/D data register (Lower byte) R XXXXXXXXB 24H ADER A/D input enable register R/W 11111111B 25H (Reserved) 26H SMC11 UART/SIO serial mode control register 11 R/W 00000000B 27H SMC12 UART/SIO serial mode control register 12 R/W 00000000B 28H SSD1 UART/SIO serial status and data register 1 R 00001---B 29H SIDR1/SODR1 UART/SIO serial data register 1 R/W * XXXXXXXXB 2AH SRC1 UART/SIO serial rate control register 1 R/W XXXXXXXXB (Continued) 22 MB89470 Series (Continued) Address Register name Register Description Read/Write Initial value 2BH SMC21 UART serial mode control register 21 R/W 00000000B 2CH SMC22 UART serial mode control register 22 R/W 00000000B 2DH SSD2 UART serial status and data register 2 R 00001---B 2EH SIDR2/SODR2 UART serial data register 2 R/W * XXXXXXXXB 2FH SRC2 UART serial rate control register 2 R/W XXXXXXXXB 30H EIC1 External interrupt 1 control register 1 R/W 00000000B 31H EIC2 External interrupt 1 control register 2 R/W 00000000B 32H EIE2 External interrupt 2 enable register R/W ---00000B 33H EIF2 External interrupt 2 flag register R/W -------0B 34H PCR1 PWC control register 1 R/W 0-0--000B 35H PCR2 PWC control register 2 R/W 00000000B 36H PLBR PWC reload buffer register R/W XXXXXXXXB 38H CNTR PWM timer control register R/W 0-00000000B 39H COMR PWM timer compare register W* XXXXXXXXB 37H (Reserved) 3AH to 6FH (Reserved) 70H PURC0 Port 0 pull up resistor control register R/W 11111111B 71H PURC1 Port 1 pull up resistor control register R/W 11111111B 72H PURC2 Port 2 pull up resistor control register R/W 11111111B 73H PURC3 Port 3 pull up resistor control register R/W -1111111B PURC5 Port 5 pull up resistor control register R/W ---1111B 7BH ILR1 Interrupt level setting register 1 W* 11111111B 7CH ILR2 Interrupt level setting register 2 W* 11111111B 7DH ILR3 Interrupt level setting register 3 W* 11111111B 7EH ILR4 Interrupt level setting register 4 W* 11111111B 74H 75H (Reserved) 76H to 7AH (Reserved) 7FH (Reserved) * Bit manipulation instruction cannot be used. Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only Initial value symbols 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is undefined. - : Unused bit. M: The initial value of this bit is determined by mask option. 23 MB89470 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Min. Max. Unit Power supply voltage VCC AVCC VSS - 0.3 VSS + 6.0 V Input voltage VI VSS - 0.3 VCC + 0.3 V Output voltage VO VSS - 0.3 VCC + 0.3 V "L" level maximum output current IOL 15 mA "L" level average output current IOLAV 4 mA "L" level total maximum output current IOL 100 mA "L" level total average output current IOLAV 40 mA "H" level maximum output current IOH -15 mA "H" level average output current IOHAV -4 mA "H" level total maximum output current IOH -50 mA "H" level total average output current IOHAV -20 mA Power consumption PD 300 mW Operating temperature TA -40 +85 C Storage temperature Tstg -55 +150 C Remarks AVCC must not exceed VCC Average value (operating current x operating rate) Average value (operating current x operating rate) Average value (operating current x operating rate) Average value (operating current x operating rate) Precautions: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 24 MB89470 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Symbol Parameter VCC AVCC Power supply voltage Operating temperature TA Value Unit Remarks Min. Max. 2.2* 5.5 V Operation assurance range MB89475 3.5* 5.5 V Operation assurance range MB89P475 2.7* 5.5 V Operation assurance range MB89PV470 1.5 5.5 V Retains the RAM state in stop mode -40 +85 C * : These values depend on the operating conditions and the analog assurance range. See Figure 1 and "5. A/D Converter Electrical Characteristics." Operating Voltage (V) 5.5 Analog accuracy assurance range : Vcc = AVcc =4.5V~5.5V 5.0 4.5 4.0 3.5 3.0 2.7 2.2 2.0 Main clock operating Freq. (MHz) 10.0 11.0 12.0 12.5 4.0 2.0 1.33 1.0 0.8 0.66 0.57 0.50 0.44 0.4 Note: The shaded area is not assured for MB89P475 The dotted area is not assured for MB89PV470 and MB89P475 0.36 0.33 0.32 1.0 2.0 3.0 Figure 1 4.0 5.0 6.0 7.0 8.0 9.0 Min execution time (inst. cycle) (s) Operating Voltage vs. Main Clock Operating Frequency Figure 1 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 25 MB89470 Series 3. DC Characteristics (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Condition Value Min. Typ. Max. Unit VIH P00 ~ P07, P10 ~ P17, P20 ~ P27, P40 ~ P42, P50 ~ P54 -- 0.7 VCC -- VCC + 0.3 V VIHS RST, MODE, EC1, EC2, SCK1, SI1, SCK2, SI2, PWC, INT10 ~ INT13, INT20 ~ INT24 -- 0.8 VCC -- VCC + 0.3 V VIL P00 ~ P07, P10 ~ P17, P20 ~ P27, P40 ~ P42, P50 ~ P54 -- VSS - 0.3 -- 0.3 VCC V VILS RST, MODE, EC1, EC2, SCK1, SI1, SCK2, SI2, PWC, INT10 ~ INT13, INT20 ~ INT24 -- VSS - 0.3 -- 0.2 VCC V VD P30 ~ P36 -- VSS - 0.3 -- VCC + 0.3 V "H" level input voltage "L" level input voltage Open-drain output pin application voltage Pin P00 ~ P07, P10 ~ P17, P20 ~ P27, P50 ~ P54 IOH = -2.0mA 4.0 -- -- V P00 ~ P07, P10 ~ P17, P20 ~ P27, P50 ~ P54, RST IOL = 4.0 mA -- -- 0.4 V VOL2 P30 ~ P36 IOL = 12.0 mA -- -- 0.4 V ILI P00 ~ P07, P10 ~ P17, P20 ~ P27, P50 ~ P54 0.45 V < VI < VCC -5 -- +5 A Open drain output leakage ILOD current P30 ~ P36 0.45 V < VI < VCC -5 -- +5 A Pull-down resistance RDOWN MODE VI = VCC 25 50 100 k RPULL P00 ~ P07, P10 ~ P17, P20 ~ P27, P30 ~ P36, P50 ~ P54, RST "H" level VOH output voltage VOL1 "L" level output voltage Input leakage current Pull-up resistance VI = 0.0 V 25 50 100 k Remarks Without pull-up Resister Except MB89P475 When pull-up resistor is selected (except RST) (Continued) 26 MB89470 Series (Continued) AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Pin Unit Remarks Typ. Max. ICC1 FCH = 10.0MHz tinst = 0.4 s Main clock run mode -- 8 13 mA ICC2 FCH = 10.0MHz tinst = 6.4 s Main clock run mode -- 0.7 3 mA ICCS1 FCH = 10.0MHz tinst = 0.4 s Main clock sleep mode -- 2.5 5 mA ICCS2 FCH = 10.0MHz tinst = 6.4 s Main clock sleep mode -- 0.8 2 mA FCL = 32.768kHz Subclock mode -- 50 85 A MB89PV470 MB89475 -- 350 785 A MB89P475 FCL = 32.768kHz Subclock sleep mode -- 15 30 A MB89PV470 MB89475 -- 19 36 A MB89P475 -- 1.6 15 A MB89PV470 MB89475 -- 5.6 21 A MB89P475 3 10 A -- 2.8 5.5 mA A/D converting, MB89PV470. MB89475 -- 2.3 6 mA MB89P475 Ta=+250C -- 1 5 A A/D stop f=1MHz -- 10 -- pF ICCL ICCLS FCL = 32.768kHz * Watch mode * Main clock stop mode ICCT Ta=+250C Subclock stop mode ICCH IA AVcc IAH Input capacitance Value Min. VCC Power supply current Condition CIN Other than VCC,VSS,AVCC,AVSS FCH=10MHz 27 MB89470 Series 4. AC Characteristics (1) Reset Timing (VCC = 5.0V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Symbol Parameter RST "L" pulse width Value Condition tZLZH -- Min. Max. 48 tHCYL -- Unit Remarks ns Note: tHCYL is the oscillation cycle (1/FC) to input to the X0 pin. The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition -- Value Unit Min. Max. -- 50 ms 1 -- ms Remarks Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 3.5 V VCC 28 0.2 V 0.2 V 0.2 V MB89470 Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = -40C to +85C) Symbol Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Value Pin Min. Typ. Max. Unit FCH X0, X1 1 -- 12.5 MHz FCL X0A, X1A -- 32.768 -- kHz tHCYL X0, X1 80 -- 1000 ns tLCYL X0A, X1A -- 30.5 -- s PWH PWL X0 20 -- -- ns PWHL PWLL X0A -- 15.2 -- s tCR tCF X0, X0A -- -- 10 ns Remarks External clock X0 and X1 Timing and Conditions tHCYL PWH PWL tCR tCF 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic reasonator is used X0 When an external clock is used X1 X0 X1 Open FCH C1 C2 FCH 29 MB89470 Series Subclock Timing and Conditions tLCYL 0.8 VCC X0A 0.2 VCC PWHL PWLL When a crystal or ceramic oscillator is used X0A When an external clock is used When sub-clock is not used in dual clock product X0A X1A FCL tCR tCF Subclock Conditions X1A Rd X0A Open Open FCL C0 X1A C1 (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) 30 Symbol Value Unit Remarks 4/FCH, 8/FCH, 16/FCH, 64/FCH s (4/FCH)tinst = 0.32 s when operating at FCH = 12.5 MHz 2/FCL s tinst = 61.036 s when operating at FCL = 32.768 kHz tinst MB89470 Series (5) Serial I/O Timing (VCC = 5.0 V, AVSS = VSS= 0.0 V, TA = -40C to +85C) Parameter Serial clock cycle time Symbol tSCYC Pin Value Condition Max. 2 tinst* -- s -200 200 ns 1/2 tinst* -- ns 1/2 tinst* -- ns 1 tinst* -- s 1 tinst* -- s 0 200 ns 1/2 tinst* -- ns 1/2 tinst* -- ns SCK1, SCK2 SCK SO time tSLOV SCK1, SO1, SCK2, SO2, Valid SI SCK tIVSH SI1, SCK1, SI2, SCK2 SCK valid SI hold time tSHIX SCK1, SI1, SCK2, SI2 Serial clock "H" pulse width tSHSL Serial clock "L" pulse width tSLSH SCK SO time tSLOV SCK1, SO1, SCK2, SO2 Valid SI SCK tIVSH SI1, SCK1, SI2, SCK2 SCK valid SI hold time tSHIX SCK1, SI1, SCK2, SI2 Internal shift clock mode SCK1, SCK2 External shift clock mode Unit Min. * : For information on tinst, see "(4) Instruction Cycle." Internal Clock Operation tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV SO 2.4 V 0.8 V tIVSH SI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Clock Operation tSLSH tSHSL SCK 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH SI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 31 MB89470 Series (6) Peripheral Input Timing (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Peripheral input "H" pulse width 1 tILIH1 Peripheral input "L" pulse width 1 tIHIL1 Value Pin INT10 ~ 13, INT20 ~ INT24, EC1, EC2, PWC Unit Min. Max. 2 tinst* -- s 2 tinst* -- s * : For information on tinst, see "(4) Instruction Cycle." t IHIL1 INT10 to 13, INT20 to 24, EC1, EC2, PWC 32 t ILIH1 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC Remarks MB89470 Series 5. A/D Converter Electrical Characteristics (1) A/D Converter Electrical Characteristics (AVCC = VCC = 4.5 V ~ 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Pin Resolution Total error -- Linearity error Differential linearity error -- Value Unit Min. Typ. Max. -- 10 -- bit -- -- 3.0 LSB -- -- 2.5 LSB -- -- 1.9 LSB Zero transition voltage VOT AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB LSB Full-scale transition voltage VFST AVCC - 3.5 LSB AVCC - 1.5 LSB AVCC + 0.5 LSB LSB A/D mode conversion time -- Analog port input current IAIN Analog input voltage VAIN AN0 to AN3 -- -- 60 tinst* s -- -- 10 A AVSS -- AVCC V Remarks * : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics". (2) A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics. * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. * Total error (unit: LSB) The difference between theoretical and actual conversion values. 33 MB89470 Series Theoretical I/O characteristics 3FF Total error 3FF VFST 3FE 3FE 3FD 1.5 LSB Digital output Digital output 3FD 004 003 Actual conversion value {1 LSB x N + VOT} 004 VNT 003 VOT 002 Actual conversion value 002 1 LSB Theoretical value 001 001 0.5 LSB AVCC AVSS 1 LSB = Analog input VFST - VOT 1022 Total error = VNT - {1 LSB x N + 0.5 LSB} 1 LSB (V) Zero transition error Full-scale transition error 004 Theoretical value Actual conversion value 3FF Actual conversion value Digital output 003 Digital output AVCC AVSS Analog input 002 3FE VFST (Actual measurement) 3FD Actual conversion value 001 Actual conversion value 3FC VOT (Actual measurement) AVCC AVSS Analog input Analog input Differential linearity error Linearity error Theoretical value 3FF Actual conversion value 3FE N+1 {1 LSB x N + VOT} Actual conversion value VNT VFST (Actual measurement) 004 Digital output Digital output 3FD V(N + 1)T N N-1 003 VNT Actual conversion value Actual conversion value 002 Theoretical value 001 N-2 VOT (Actual measurement) AVCC AVSS Analog input Linearity error = 34 VNT - {1 LSB x N + VOT} 1 LSB AVCC AVSS Analog input Differential linearity error = V(N + 1)T - VNT 1 LSB -1 MB89470 Series (3) Notes on Using A/D Converter * Input impedance of the analog input pins The A/D converter used for the MB89470 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activation A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low. Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin. Analog Input Circuit Model Sample hold circuit Analog input pin Comparator If the analog input impedance is too low, it is recommended to connect an external capacitor of approx. 0.1 F. R C Close for 16 instruction cycles after activating A/D conversion. Analog channel selector R: analog input equivalent resistance C: analog input equivalent capacitance MB89475 MB89PV470 2.2 k 45 pF MB89P475 2.6 k 28 pF * Error The smaller the |AVR - AVSS|, the greater the error would become relatively. 35 MB89470 Series INSTRUCTIONS Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 36 MB89470 Series (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) x Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (x) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( x )) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F. 37 MB89470 Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 - - - - - AL AL AL AL AL AL AL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 - - - AL AL AL - - - AH AH AH - - - dH dH dH ---- ---- ---- ++-- ++-- ++-- D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) AL AL AL - - - - - - - - - - - - - - - AL AL - - - - AH AH AH - - - - - - - - - - - - - - - - AH - - - - dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 38 MB89470 Series Table 3 Arithmetic Operation Instructions (62 instructions) Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Operation TL TH AH NZVC OP code (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C A - - - ++-+ 02 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (Continued) 39 MB89470 Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 TL TH AH NZVC OP code - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Table 4 Branch Instructions (17 instructions) Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Operation If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt TL TH AH NZVC OP code - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - dH - - ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 TL TH AH NZVC OP code - - - - - - - - - - - - - - - - - - - dH - - - - - - - ---- ---- ---- ---- ---- ---R ---S ---- ---- 40 50 41 51 00 81 91 80 90 Table 5 Other Instructions (9 instructions) Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 40 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 9 A B C D E F A A A SUBC A XCH A, T XOR A AND A OR ADDC A,@IX +d SUBC A,@IX +d MOV @IX +d,A A A XOR AND @A,IX A,@IX +d +d OR A,@IX +d CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel MOV CMP CLRB BBC MOVW MOVW MOVW XCHW @IX @IX dir: 6 dir: 6,rel A,@IX @IX IX,#d16 A,IX +d,#d8 +d,#d8 +d +d,A DAS MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 8 CMP A,@IX +d CMPW CMP SETC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP F 7 E MOV A,@IX +d D 6 C MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A 5 A A JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A SETI 9 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 8 4 7 RORC 6 3 A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 ROLC DIVU RETI 3 2 A RET 2 MULU SWAP 1 1 0 NOP H 0 L MB89470 Series INSTRUCTION MAP 41 MB89470 Series MASK OPTIONS No. Part number MB89475 MB89P475 MB89PV470 Specifying procedure Specify when ordering masking Setting not possible Setting not possible 1 Selection of clock mode * Single clock mode * Dual clock mode 2 Selection of OTPROM content protection feature * No protection feature * With protection feature 3 Selection of oscillation stabilization time (OSC) Selectable * The initial value of the oscillation OSC stabilization time for the main 1 : 214/FCH clock can be set by selecting the 2 : 217/FCH 3 : 218/FCH values of the WTM1 and WTM0 bits on the right. Fixed to oscillation stabilization time of 218/FCH Fixed to oscillation stabilization time of 218/FCH 4 Selection of power-on stabilization time * Nil * 217/FCH Fixed to power-on stabilization time of 217/FCH Fixed to nil 101/102: Single clock 201/202: Dual clock Selectable -- Selectable 101: Single clock 201: Dual clock 101/201: No protection 102/202: with protection -- ORDERING INFORMATION Part number MB89475PFV MB89P475PFV-101 MB89P475PFV-102 MB89P475PFV-201 MB89P475PFV-202 42 Package 48-pin Plastic QFP (FPT-48P-M05) MB89475P-SH MB89P475P-SH-101 MB89P475P-SH-102 MB89P475P-SH-201 MB89P475P-SH-202 48-pin Plastic SH-DIP (DIP-48P-M01) MB89PV470CF-101 MB89PV470CF-201 48-pin Ceramic MQFP (MQP-48C-P01) Remarks 101: Single clock, without content protection 102: Single clock, with content protection 201: Dual clock, without content protection 202: Dual clock, with content protection MB89470 Series PACKAGE DIMENSIONS 48-pin Plastic SH-DIP DIP-48P-M01 +0.20 43.69 -0.30 +.008 1.720 -.012 INDEX-1 13.800.25 (.543.010) INDEX-2 0.51(.020)MIN 5.25(.207) MAX 0.250.05 (.010.002) 3.00(.118) MIN +0.50 1.00 -0 0.450.10 (.018.004) +.020 .039 -0 15.24(.600) TYP 15MAX 1.7780.18 (.070.007) 1.778(.070) MAX C 40.894(1.610)REF Dimensions in mm (inches) 1994 FUJITSU LIMITED D48002S-3C-3 48-pin Plastic LQFP FPT-48P-M05 9.000.20(.354.008)SQ 7.000.10(.276.004)SQ 36 0.1450.055 (.006.002) 25 24 37 0.08(.003) Details of "A" part +0.20 1.50 -0.10 +.008 .059 -.004 INDEX 13 48 "A" 0~8 LEAD No. 1 0.50(.020) C 2000 FUJITSU LIMITED F48013S-c-4-8 (Mounting height) 0.100.10 (.004.004) (Stand off) 12 0.200.05 (.008.002) 0.08(.003) M 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) Dimensions in mm (inches) 43 MB89470 Series 48-pin Ceramic MQFP MQP-48C-P01 17.20(.677)TYP PIN No.1 INDEX 15.000.25 (.591.010) 14.820.35 (.583.014) 1.50(.059)TYP 8.80(.346)REF 1.00(.040)TYP 0.800.22 (.0315.0087) PIN No.1 INDEX 1.020.13 (.040.005) +0.13 10.92 -0.0 +.005 .430 -0 7.14(.281) 8.71(.343) TYP TYP PAD No.1 INDEX 0.30(.012)TYP +0.45 4.50(.177)TYP 1.10 -0.25 +.018 .043 -.010 0.400.08 (.016.003) 0.60(.024)TYP 8.50(.335)MAX 0.150.05 (.006.002) C 44 1994 FUJITSU LIMITED M48001SC-4-2 Dimensions in mm (inches) MB89470 Series MEMO 45 MB89470 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. 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