STM32H743xI 32-bit Arm(R) Cortex(R)-M7 400MHz MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces Datasheet - production data Features )%*$ Core 32-bit Arm(R) Cortex(R)-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 400 MHz, MPU, 856 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions TFBGA240+25 (14x14 mm) TFBGA100 (8x8 mm)(1) )%*$ UFBGA176+25 (10x10 mm) UFBGA169 (7x7 mm) LQFP208 (28x28 mm) LQFP176 (24x24 mm) LQFP144 (20x20 mm) LQFP100 (14x14 mm) Memories Up to 2 Mbytes of Flash memory with readwhile-write support 1.62 to 3.6 V application supply and I/Os 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs Dual mode Quad-SPI memory interface running up to 133 MHz Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 133 MHz in Synchronous mode POR, PDR, PVD and BOR Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry Voltage scaling in Run and Stop mode (5 configurable ranges) Backup regulator (~0.9 V) Voltage reference for analog peripheral/VREF+ Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging Low-power consumption CRC calculation unit Total current consumption down to 4 A Security ROP, PC-ROP, active tamper Clock management General-purpose input/outputs Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI Up to 168 I/O ports with interrupt capability Reset and power management 3 separate power domains which can be independently clock-gated or switched off: - D1: high-performance capabilities - D2: communication peripherals and timers - D3: reset/clock control/power management July 2018 This is information on a product in full production. External oscillators: 4-48 MHz HSE, 32.768 kHz LSE 3x PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode Interconnect matrix 3 bus matrices (1 AXI and 2 AHB) Bridges (5x AHB2-APB, 2x AXI2-AHB) DS12110 Rev 5 1/231 www.st.com STM32H743xI 4 DMA controllers to unload the CPU 2x operational amplifiers (8 MHz bandwidth) 1x high-speed master direct memory access controller (MDMA) with linked list support 1x digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters 2x dual-port DMAs with FIFO 1x basic DMA with request router capabilities Up to 35 communication peripherals Graphics LCD-TFT controller up to XGA resolution Chrom-ART graphical hardware AcceleratorTM (DMA2D) to reduce CPU load 4x I2Cs FM+ interfaces (SMBus/PMBus) 4x USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART 6x SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 133 MHz) 4x SAIs (serial audio interface) SPDIFRX interface SWPMI single-wire protocol master I/F Hardware JPEG Codec Up to 22 timers and watchdogs 1x high-resolution timer (2.5 ns max resolution) 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 200 MHz) 2x 16-bit advanced motor control timers (up to 200 MHz) MDIO Slave interface 2x SD/SDIO/MMC interfaces (up to 125 MHz) 2x CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) 10x 16-bit general-purpose timers (up to 200 MHz) 5x 16-bit low-power timers (up to 200 MHz) 2x USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD 2x watchdogs (independent and window) Ethernet MAC interface with DMA controller RTC with sub-second accuracy & HW calendar HDMI-CEC 8- to 14-bit camera interface (up to 80 MHz) 1x SysTick timer Debug mode SWD & JTAG interfaces 11 analog peripherals 3x ADCs with 16-bit max. resolution (up to 36 channels, 4.5 MSPS at 12 bits) 1x temperature sensor 2x 12-bit D/A converters (1 MHz) 2x ultra-low-power comparators 4-Kbyte Embedded Trace Buffer True random number generators (3 oscillators each) 96-bit unique ID All packages are ECOPACK(R)2 compliant Table 1. Device summary Reference STM32H743xI 2/231 Part number STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI, STM32H743AI DS12110 Rev 5 STM32H743xI Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm(R) Cortex(R)-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.11 Chrom-ART AcceleratorTM (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 28 3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 28 3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 28 3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DS12110 Rev 5 3/231 6 Contents 4 4/231 STM32H743xI 3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 32 3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.28 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.28.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.28.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.28.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.28.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 38 3.28.6 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.28.7 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.28.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.29 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 39 3.30 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.31 Universal synchronous/asynchronous receiver transmitter (USART) . . . 40 3.32 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 41 3.33 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 42 3.34 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.35 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.36 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 43 3.37 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 44 3.38 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 44 3.39 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 44 3.40 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 45 3.41 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 45 3.42 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.43 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DS12110 Rev 5 STM32H743xI Contents 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 101 6.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 102 6.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 129 6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DS12110 Rev 5 5/231 6 Contents 7 STM32H743xI 6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.3.27 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 176 6.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 179 6.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 180 6.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.3.32 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.3.33 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.2 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.4 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 7.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 7.6 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 7.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 7.8 TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 7.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 6/231 DS12110 Rev 5 STM32H743xI List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32H743xI features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STM32H743xI pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 101 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Typical consumption in Run mode and corresponding performance versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 107 Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 108 Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 108 Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 109 Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 116 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 DS12110 Rev 5 7/231 9 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. 8/231 STM32H743xI HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 127 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 140 Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 140 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 141 Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 142 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 143 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 145 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 150 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 154 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Quad SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 DS12110 Rev 5 STM32H743xI Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. List of tables DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 191 Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 192 USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 195 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 196 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 197 Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 206 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 220 UFBGA 176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . 221 TFBG - 240 +25 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 TFBGA - 240+25ball recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . 225 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 STM32H743xI ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 DS12110 Rev 5 9/231 9 List of figures STM32H743xI List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 10/231 STM32H743xI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32H743xI bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 139 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 141 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 142 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 144 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 150 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 153 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 154 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 165 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 165 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 DS12110 Rev 5 STM32H743xI Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. List of figures SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 200 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 207 LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline . . . . . . . . . . . . . . 212 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 216 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 TFBGA - 240+25 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 TFBGA - 240+25 ball, 14x14 mm 0.8 mm pitch recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 DS12110 Rev 5 11/231 11 Introduction 1 STM32H743xI Introduction This document provides information on STM32H743xI microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering information. This document should be read in conjunction with the STM32H743xI reference manual (RM0433), available from the STMicroelectronics website www.st.com. For information on the Arm(R)(a) Cortex(R)-M7 core, please refer to the Cortex(R)-M7 Technical Reference Manual, available from the http://www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/231 DS12110 Rev 5 STM32H743xI 2 Description Description STM32H743xI devices are based on the high-performance Arm(R) Cortex(R)-M7 32-bit RISC core operating at up to 400 MHz. The Cortex(R) -M7 core features a floating point unit (FPU) which supports Arm(R) double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. STM32H743xI devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. STM32H743xI devices incorporate high-speed embedded memories with a dual-bank Flash memory up to 2 Mbytes, 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces. Standard peripherals - Four I2Cs - Four USARTs, four UARTs and one LPUART - Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked by a dedicated internal audio PLL or by an external clock to allow synchronization. - Four SAI serial audio interfaces - One SPDIFRX interface - One SWPMI (Single Wire Protocol Master Interface) - Management Data Input/Output (MDIO) slaves - Two SDMMC interfaces - A USB OTG full-speed and a USB OTG high-speed interface with full-speed capability (with the ULPI) - One FDCAN plus one TT-CAN interface - An Ethernet interface - Chrom-ART AcceleratorTM - HDMI-CEC Advanced peripherals including - A flexible memory control (FMC) interface - A Quad-SPI Flash memory interface - A camera interface for CMOS sensors - An LCD-TFT display controller - A JPEG hardware compressor/decompressor Refer to Table 2: STM32H743xI features and peripheral counts for the list of peripherals available on each part number. DS12110 Rev 5 13/231 47 Description STM32H743xI STM32H743xI devices operate in the -40 to +85 C temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled. Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages except LQFP100 to allow a greater power supply choice. A comprehensive set of power-saving modes allows the design of low-power applications. STM32H743xI devices are offered in 8 packages ranging from 100 pins to 240 pins/balls. The set of included peripherals changes with the device chosen. These features make STM32H743xI microcontrollers suitable for a wide range of applications: Motor drive and application control Medical equipment Industrial applications: PLC, inverters, circuit breakers Printers, and scanners Alarm systems, video intercom, and HVAC Home audio appliances Mobile applications, Internet of Things Wearable devices: smart watches. Figure 1 shows the general block diagram of the device family. Table 2. STM32H743xI features and peripheral counts Peripherals STM32H 743VI STM32H 743ZI Flash memory in Kbytes SRAM in Kbytes TCM RAM in Kbytes 14/231 STM32H 743AI 2048 SRAM mapped onto AXI bus 512 SRAM1 (D2 domain) 128 SRAM2 (D2 domain) 128 SRAM3 (D2 domain) 32 SRAM4 (D3 domain) 64 ITCM RAM (instruction) 64 DTCM RAM (data) 128 Backup SRAM (Kbytes) 4 FMC Yes Quad-SPI Yes Ethernet Yes DS12110 Rev 5 STM32H 743II STM32H 743BI STM32H 743XI STM32H743xI Description Table 2. STM32H743xI features and peripheral counts (continued) STM32H 743VI Peripherals Timers STM32H 743ZI STM32H 743AI High-resolution 1 General-purpose 10 Advanced-control (PWM) 2 Basic 2 Low-power 5 Random number generator I2C 4 USART/UART/ LPUART 4/4 /1 SAI 4 SPDIFRX 4 inputs SWPMI Yes MDIO Yes SDMMC 2 FDCAN/TT-CAN 1/1 USB OTG_FS Yes USB OTG_HS Yes Ethernet and camera interface Yes LCD-TFT Yes JPEG Codec Yes Chrom-ART AcceleratorTM (DMA2D) Yes 82 114 131 140 168 3 16-bit ADCs Number of channels Up to 36 12-bit DAC Number of channels Yes 2 Comparators 2 Operational amplifiers 2 DFSDM Yes Maximum CPU frequency 400 MHz Operating voltage STM32H 743XI 6/3(1) SPI / I GPIOs STM32H 743BI Yes 2S Communicati on interfaces STM32H 743II 1.71 to 3.6 V(2) DS12110 Rev 5 1.62 to 3.6 V(3) 15/231 47 Description STM32H743xI Table 2. STM32H743xI features and peripheral counts (continued) Peripherals STM32H 743VI STM32H 743AI STM32H 743II STM32H 743BI STM32H 743XI Ambient temperatures: -40 up to +85 C(4) Operating temperatures Package STM32H 743ZI Junction temperature: -40 to + 125 C LQFP100 TFBGA100(5) LQFP144 UFBGA 169(5) LQFP176 UFBGA 176+25 LQFP208 TFBGA 240+25 1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 2. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this package is 1.71 V. 3. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled. 4. The product junction temperature must be kept within the -40 to +125 C temperature range. 5. This package is under development. Please contact STMicroelectronics for details. 16/231 DS12110 Rev 5 STM32H743xI Description Figure 1. STM32H743xI block diagram 0,,50,, 7R$3% SHULSKHUDOV 0',2 DV$) '3'0673 6'00&B 1;78/3,&. '3'0,' '>@ 9%86 '>@',5 &0'&.DV$) ,'9%86 $+%0+] '7&0 .% '7&0 .% '0$ $;,0 0%)/$6+ '&DFKH .% /&'7)7 ::'* -3(* 6'6&.)60&/. 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It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex(R)-M7 processor is a highly efficient high-performance featuring: Six-stage dual-issue pipeline Dynamic branch prediction Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache) 64-bit AXI interface 64-bit ITCM interface 2x32-bit DTCM interfaces The following memory interfaces are supported: Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses AXI Bus interface to optimize Burst transfers Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 1 shows the general block diagram of the STM32H743xI family. Note: Cortex(R)-M7 with FPU core is binary compatible with the Cortex(R)-M4 core. 3.2 Memory protection unit (MPU) The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated. 18/231 DS12110 Rev 5 STM32H743xI Functional overview 3.3 Memories 3.3.1 Embedded Flash memory The STM32H743xI devices embed up to 2 Mbytes of Flash memory that can be used for storing programs and data. The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of: One Flash word (8 words, 32 bytes or 256 bits) 10 ECC bits. The Flash memory is divided into two independent banks. Each bank is organized as follows: 3.3.2 * A 1-Mbyte user Flash memory block containing eight user sectors of 128 Kbytes(4 K Flash words) * 128 Kbytes of System Flash memory from which the device can boot 2 Kbytes (64 Flash words) of user option bytes for user configuration Embedded SRAM All devices feature: 512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain. SRAM1 mapped on D2 domain: 128 Kbytes SRAM2 mapped on D2 domain: 128 Kbytes SRAM3 mapped on D2 domain: 32 Kbytes SRAM4 mapped on D3 domain: 64 Kbytes 4 Kbytes of backup SRAM The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. RAM mapped to TCM interface (ITCM and DTCM): Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the CPU(AHBP): - 64 Kbytes of ITCM-RAM (instruction RAM) This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the CPU. - 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports) The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex(R)-M7 dual issue capability. The MDMA can be used to load code or data in ITCM or DTCM RAMs. DS12110 Rev 5 19/231 47 Functional overview STM32H743xI Error code correction (ECC) Over the product lifetime, and/or due to external events such as radiations, invalid bits in memories may occur. They can be detected and corrected by ECC. This is an expected behavior that has to be managed at final-application software level in order to ensure data integrity through ECC algorithms implementation. SRAM data are protected by ECC: 7 ECC bits are added per 32-bit word. 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM. The ECC mechanism is based on the SECDED algorithm. It supports single-error correction and double-error detection. 3.4 Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: All Flash address space All RAM address space: ITCM, DTCM RAMs and SRAMs The System memory bootloader The boot loader is located in non-user System memory. It is used to reprogram the Flash memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32 microcontroller System memory Boot mode application note (AN2606) for details. 3.5 Power supply management 3.5.1 Power supply scheme STM32H743xI power supply voltages are the following: VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD pins. VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and OPAMP. VDD33USB and VDD50USB: VDD50USB can be supplied through the USB cable to generate the VDD33USB via the USB internal regulator. This allows supporting a VDD supply different from 3.3 V. The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V. 20/231 VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present. VCAP: VCORE supply voltage, which values depend on voltage scaling (0.7 V, 0.9 V, 1.0 V, 1.1 V or 1.2 V). They are configured through VOS bits in PWR_D3CR register. DS12110 Rev 5 STM32H743xI Functional overview The VCORE domain is split into the following power domains that can be independently switch off. - D1 domain containing some peripherals and the Cortex(R)-M7 core. - D2 domain containing a large part of the peripherals. - D3 domain containing some peripherals and the system control. During power-up and power-down phases, the following power sequence requirements must be respected (see Figure 2): When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must remain below VDD + 300 mV. When VDD is above 1 V, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. Figure 2. Power-up/power-down sequence 9 9''; 9'' 9%25 3RZHURQ ,QYDOLGVXSSO\DUHD 2SHUDWLQJPRGH 9'';9''P9 3RZHUGRZQ 9'';LQGHSHQGHQWIURP9'' WLPH 06Y9 1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB. DS12110 Rev 5 21/231 47 Functional overview 3.5.2 STM32H743xI Power supply supervisor The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry: Power-on reset (POR) The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in Reset mode when VDD is below this threshold, Power-down reset (PDR) The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold. The PDR supervisor can be enabled/disabled through PDR_ON pin. Brownout reset (BOR) The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be configured through option bytes. A reset is generated when VDD drops below this threshold. 3.5.3 Voltage regulator The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can be independently switched off. Voltage regulator output can be adjusted according to application needs through 5 power supply levels: Run mode (VOS1 to VOS3) - Scale 1: high performance - Scale 2: medium performance and consumption - Scale 3: optimized performance and low-power consumption Stop mode (SVOS3 to SVOS5) - Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C, LPTIM) are operational - Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled The peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or asynchronous interrupt. 22/231 DS12110 Rev 5 STM32H743xI 3.6 Functional overview Low-power strategy There are several ways to reduce power consumption on STM32H743xI: Decrease dynamic power consumption by slowing down the system clocks even in Run mode and individually clock gating the peripherals that are not used. Save power consumption when the CPU is idle, by selecting among the available lowpower mode according to the user application needs. This allows achieving the best compromise between short startup time, low-power consumption, as well as available wakeup sources. The devices feature several low-power modes: CSleep (CPU clock stopped) CStop (CPU sub-system clock stopped) DStop (Domain bus matrix clock stopped) Stop (System clock stopped) DStandby (Domain powered down) Standby (System powered down) CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex(R)-Mx core is set after returning from an interrupt service routine. A domain can enter low-power mode (DStop or DStandby) when the processor, its subsystem and the peripherals allocated in the domain enter low-power mode. If part of the domain is not in low-power mode, the domain remains in the current mode. Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains are in DStop or DStandby mode. Table 3. System vs domain low-power mode System power mode D1 domain power mode D2 domain power mode D3 domain power mode Run DRun/DStop/DStandby DRun/DStop/DStandby DRun Stop DStop/DStandby DStop/DStandby DStop Standby DStandby DStandby DStandby DS12110 Rev 5 23/231 47 Functional overview 3.7 STM32H743xI Reset and clock controller (RCC) The clock and reset controller is located in D3 domain. The RCC manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the baudrate. 3.7.1 Clock management The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal oscillators with fast startup time and three PLLs. The RCC receives the following clock source inputs: Internal oscillators: - 64 MHz HSI clock - 48 MHz RC oscillator - 4 MHz CSI clock - 32 kHz LSI clock External oscillators: - 4-48 MHz HSE clock - 32.768 kHz LSE clock The RCC provides three PLLs: one for system clock, two for kernel clocks. The system starts on the HSI clock. The user application can then select the clock configuration. 3.7.2 System reset sources Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the RCC and power controller status registers, as well as the backup power domain. A system reset is generated in the following cases: 24/231 Power-on reset (pwr_por_rst) Brownout reset Low level on NRST pin (external reset) Window watchdog Independent watchdog Software reset Low-power mode security reset Exit from Standby DS12110 Rev 5 STM32H743xI 3.8 Functional overview General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. After reset, all GPIOs (except debug pins) are in Analog mode to reduce power consumption (refer to GPIOs register reset values in the device reference manual). The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.9 Bus-interconnect matrix The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow interconnecting bus masters with bus slaves (see Figure 3). DS12110 Rev 5 25/231 47 Functional overview 26/231 Figure 3. STM32H743xI bus matrix $+%6 &38 ,7&0 .E\WH 0'0$ '0$' '0$B0(0 6'00& /7'& 'WR'$+% '0$ '0$B0(0 '0$ (WKHUQHW 6'00& 86%+6 0$& 86%+6 '0$B3(5,3+ '7&0 .E\WH $+%3 $;,0 , ' .% .% '0$B3(5,3+ &RUWH[0 $3% 65$0 .E\WH $+% 65$0 .E\WH 65$0 .E\WH )ODVK$ 0E\WH DS12110 Rev 5 $+% )ODVK% 0E\WH $+% $;,65$0 .E\WH $3% 463, $3% )0& ELW$;,EXVPDWUL[ 'GRPDLQ ELW$+%EXVPDWUL[ 'GRPDLQ 'WR'$+% 'WR'$+% 'WR'$+% %'0$ ELW$+%EXVPDWUL[ 'GRPDLQ /HJHQG $+% 7&0 $+% $;, $3% ELWEXV 0DVWHULQWHUIDFH %XVPXOWLSOH[HU 6ODYHLQWHUIDFH $3% 65$0 .E\WH %DFNXS 65$0 .E\WH 06Y9 STM32H743xI ELWEXV STM32H743xI 3.10 Functional overview DMA controllers . The devices feature four DMA instances to unload CPU activity: A master direct memory access (MDMA) The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface and a dedicated AHB interface to access Cortex(R)-M7 TCM memories. The MDMA is located in D1 domain. It is able to interface with the other DMA controllers located in D2 domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly. Each of the 16 channels can perform single block transfers, repeated block transfers and linked list transfers. Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request router capabilities. One basic DMA (BDMA) located in D3 domain, with request router capabilities. The DMA request router could be considered as an extension of the DMA controller. It routes the DMA peripheral requests to the DMA controller itself. This allowing managing the DMA requests with a high flexibility, maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output trigger or DMA event. 3.11 Chrom-ART AcceleratorTM (DMA2D) The Chrom-Art AcceleratorTM (DMA2D) is a graphical accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: Rectangle filling with a fixed color Rectangle copy Rectangle copy with pixel format conversion Rectangle composition with blending and pixel format conversion Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also supports block based YCbCr to handle JPEG decoder output. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. DS12110 Rev 5 27/231 47 Functional overview 3.12 STM32H743xI Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)-M7 with FPU core. Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Allows early processing of interrupts Processing of late arriving, higher-priority interrupts Support tail chaining Processor context automatically saved on interrupt entry, and restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.13 Extended interrupt and event controller (EXTI) The EXTI controller performs interrupt and event management. In addition, it can wake up the processor, power domains and/or D3 domain from Stop mode. The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events and 61 direct events . Configurable events have dedicated pending flags, active edge selection, and software trigger capable. Direct events provide interrupts or events from peripherals having a status flag. 3.14 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 28/231 DS12110 Rev 5 STM32H743xI 3.15 Functional overview Flexible memory controller (FMC) The FMC controller main features are the following: Interface with static-memory mapped devices including: - 3.16 Static random access memory (SRAM) - NOR Flash memory/OneNAND Flash memory - PSRAM (4 memory banks) - NAND Flash memory with ECC hardware to check up to 8 Kbytes of data Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories 8-,16-,32-bit data bus width Independent Chip Select control for each memory bank Independent configuration for each memory bank Write FIFO Read FIFO for SDRAM controller The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the FMC kernel clock divided by 2. Quad-SPI memory interface (QUADSPI) All devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and double datarate operations. It can operate in any of the following modes: Direct mode through registers External Flash status register polling mode Memory mapped mode. Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data accesses are supported as well as code execution. The opcode and the frame format are fully programmable. 3.17 Analog-to-digital converters (ADCs) The STM32H743xI devices embed three analog-to-digital converters, which resolution can be configured to 16, 14, 12, 10 or 8 bits. The sampling rates are respectively 3.6 MSPS, 4 MSPS, 4.5 MSPS, 5 MSPS and 6 MSPS when the ADC frequency (fADC) is 36 MHz. Each ADC shares up to 20 external channels, performing conversions in the Single-shot or Scan mode. In Scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: Simultaneous sample and hold Interleaved sample and hold The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC converted values to a destination location without any software action. DS12110 Rev 5 29/231 47 Functional overview STM32H743xI In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer. 3.18 Temperature sensor STM32H743xI devices embed a temperature sensor that generates a voltage (VTS) that varies linearly with the temperature. This temperature sensor is internally connected to ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device junction temperature ranging from - 40 to +125 C. The temperature sensor have a good linearity, but it has to be calibrated to obtain a good overall accuracy of the temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the System memory area, which is accessible in Read-only mode. 3.19 VBAT operation The VBAT power domain contains the RTC, the backup registers and the backup SRAM. To optimize battery duration, this power domain is supplied by VDD when available or by the voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD dropped below the PDR level. The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by VDD, in which case, the VDD mode is not functional. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 30/231 DS12110 Rev 5 STM32H743xI 3.20 Functional overview Digital-to-analog converters (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel including DMA underrun error detection external triggers for conversion input voltage reference VREF+ or internal VREFBUF reference. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.21 Ultra-low-power comparators (COMP) STM32H743xI devices embed two rail-to-rail comparators (COMP1 and COMP2). They feature programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) as well as selectable output polarity. The reference voltage can be one of the following: An external I/O A DAC output channel An internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and be combined into a window comparator. 3.22 Operational amplifiers (OPAMP) STM32H743xI devices embed two rail-to-rail operational amplifiers (OPAMP1 and OPAMP2) with external or internal follower routing and PGA capability. The operational amplifier main features are: PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3, -7 or -15 One positive input connected to DAC Output connected to internal ADC Low input bias current down to 1 nA Low input offset voltage down to 1.5 mV Gain bandwidth up to 8 MHz DS12110 Rev 5 31/231 47 Functional overview STM32H743xI The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs and one output each. These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15. 3.23 Digital filter for sigma-delta modulators (DFSDM) The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM features optional parallel data stream inputs from internal ADC peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: 8 multiplexed input digital serial channels: - configurable SPI interface to connect various SD modulator(s) - configurable Manchester coded 1 wire interface support - PDM (Pulse Density Modulation) microphone input support - maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) - clock output for SD modulator(s): 0..20 MHz alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): - - Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) - integrator: oversampling ratio (1..256) up to 24-bit output data resolution, signed output data format automatic data offset correction (offset stored in register by user) continuous or single conversion start-of-conversion triggered by: 32/231 internal sources: ADC data or memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: - software trigger - internal timers - external events - start-of-conversion synchronously with first digital filter module (DFSDM0) analog watchdog feature: - low value and high value data threshold registers - dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) - input from final output data or from selected input digital serial channels - continuous monitoring independently from standard conversion DS12110 Rev 5 STM32H743xI Functional overview short circuit detector to detect saturated analog input values (bottom and top range): - up to 8-bit counter to detect 1..256 consecutive 0's or 1's on serial data stream - monitoring continuously each input serial channel break signal generation on analog watchdog event or on short circuit detector event extremes detector: - storage of minimum and maximum values of final conversion data - refreshed by software DMA capability to read the final conversion data interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence "regular" or "injected" conversions: - "regular" conversions can be requested at any time or even in Continuous mode without having any impact on the timing of "injected" conversions - "injected" conversions for precise timing and with high conversion priority Table 4. DFSDM implementation DFSDM features 3.24 DFSDM1 Number of filters 4 Number of input transceivers/channels 8 Internal ADC parallel input X Number of external triggers 16 Regular channel information in identification register X Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It features: Programmable polarity for the input pixel clock and synchronization signals Parallel data communication can be 8-, 10-, 12- or 14-bit Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) Supports Continuous mode or Snapshot (a single frame) mode Capability to automatically crop the image DS12110 Rev 5 33/231 47 Functional overview 3.25 STM32H743xI LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 3.26 2 display layers with dedicated FIFO (64x64-bit) Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer Up to 8 input color formats selectable per layer Flexible blending between two layers using alpha value (per pixel or constant) Flexible programmable parameters for each layer Color keying (transparency color) Up to 4 programmable interrupt events AXI master interface with burst of 16 words JPEG Codec (JPEG) The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 109181 specification. It provides an fast and simple hardware compressor and decompressor of JPEG images with full management of JPEG headers. The JPEG codec main features are as follows: 3.27 8-bit/channel pixel depths Single clock per pixel encoding and decoding Support for JPEG header generation and parsing Up to four programmable quantization tables Fully programmable Huffman tables (two AC and two DC) Fully programmable minimum coded unit (MCU) Encode/decode support (non simultaneous) Single clock Huffman coding and decoding Two-channel interface: Pixel/Compress In, Pixel/Compressed Out Support for single greyscale component Ability to enable/disable header processing Fully synchronous design Configuration for High-speed decode mode Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.28 Timers and watchdogs The devices include one high-resolution timer, two advanced-control timers, ten generalpurpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer. 34/231 DS12110 Rev 5 STM32H743xI Functional overview All timer counters can be frozen in Debug mode. Table 5 compares the features of the advanced-control, general-purpose and basic timers. Table 5. Timer feature comparison Timer type Timer Highresolution HRTIM1 timer Advanced -control TIM1, TIM8 TIM2, TIM5 TIM3, TIM4 TIM12 DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels TIM15 TIM16, TIM17 Max interface clock (MHz) Max timer clock (MHz) (1) /1 /2 /4 (x2 x4 x8 x16 x32, with DLL) Yes 10 Yes 400 400 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 100 200 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 100 200 16-bit Any integer Up, Down, between 1 Up/down and 65536 Yes 4 No 100 200 16-bit Up Any integer between 1 and 65536 No 2 No 100 200 Up Any integer between 1 and 65536 No 1 No 100 200 Up Any integer between 1 and 65536 Yes 2 1 100 200 Up Any integer between 1 and 65536 Yes 1 1 100 200 16-bit Up General purpose TIM13, TIM14 Complementary output 16-bit 16-bit 16-bit DS12110 Rev 5 35/231 47 Functional overview STM32H743xI Table 5. Timer feature comparison (continued) Timer type Timer DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Lowpower timer LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 Complementary output Max interface clock (MHz) Max timer clock (MHz) (1) Yes 0 No 100 200 No 0 No 100 200 1. The maximum timer clock is up to 400 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in RCC_D2CFGR register. 3.28.1 High-resolution timer (HRTIM1) The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy timings, such as PWM or phase-shifted pulses. It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection purposes and 10 inputs to handle external events such as current limitation, zero voltage or zero current switching. The HRTIM1 timer is made of a digital kernel clocked at 400 MHz The high-resolution is available on the 10 outputs in all operating modes: variable duty cycle, variable frequency, and constant ON time. The slave timers can be combined to control multiswitch complex converters or operate independently to manage multiple independent converters. The waveforms are defined by a combination of user-defined timings and external events such as analog or digital feedbacks signals. HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also offers specific modes and features to offload the CPU: DMA requests, Burst mode controller, Push-pull and Resonant mode. It supports many topologies including LLC, Full bridge phase shifted, buck or boost converters, either in voltage or current mode, as well as lighting application (fluorescent or LED). It can also be used as a general purpose timer, for instance to achieve high-resolution PWM-emulated DAC. 36/231 DS12110 Rev 5 STM32H743xI 3.28.2 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: Input capture Output compare PWM generation (Edge- or Center-aligned modes) One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.28.3 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32H743xI devices (see Table 5 for differences). TIM2, TIM3, TIM4, TIM5 The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels for input capture/output compare, PWM or One-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM or One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers or used as simple timebases. DS12110 Rev 5 37/231 47 Functional overview 3.28.4 STM32H743xI Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) The low-power timers have an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.28.6 16-bit up counter with 16-bit autoreload register 16-bit compare register Configurable output: pulse, PWM Continuous / One-shot mode Selectable software / hardware input trigger Selectable clock source: Internal clock source: LSE, LSI, HSI or APB clock External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) Programmable digital glitch filter Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.28.7 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in Debug mode. 3.28.8 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 38/231 A 24-bit downcounter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source. DS12110 Rev 5 STM32H743xI 3.29 Functional overview Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. Two programmable alarms. On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. Three anti-tamper detection pins with programmable filter. Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC clock sources can be: A 32.768 kHz external crystal (LSE) An external resonator or oscillator (LSE) The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. DS12110 Rev 5 39/231 47 Functional overview 3.30 STM32H743xI Inter-integrated circuit interface (I2C) STM32H743xI devices embed four I2C interfaces. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: 3.31 I2C-bus specification and user manual rev. 5 compatibility: - Slave and Master modes, multimaster capability - Standard-mode (Sm), with a bitrate up to 100 kbit/s - Fast-mode (Fm), with a bitrate up to 400 kbit/s - Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os - 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses - Programmable setup and hold times - Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: - Hardware PEC (Packet Error Checking) generation and verification with ACK control - Address resolution protocol (ARP) support - SMBus alert Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Wakeup from Stop mode on address match Programmable analog and digital noise filters 1-byte buffer with DMA capability Universal synchronous/asynchronous receiver transmitter (USART) STM32H743xI devices have four embedded universal synchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7 and UART8). Refer to Table 6 for a summary of USARTx and UARTx features. These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire Half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 12.5 Mbit/s. USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability. The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. 40/231 DS12110 Rev 5 STM32H743xI Functional overview All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can be done on: Start bit detection Any received data frame A specific programmed data frame Specific TXFIFO/RXFIFO status when FIFO mode is enabled. All USART interfaces can be served by the DMA controller. Table 6. USART features USART modes/features(1) USART1/2/3/6 UART4/5/7/8 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode (Master/Slave) X - Smartcard mode X - Single-wire Half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain and wakeup from low power mode X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X USART data length 7, 8 and 9 bits Tx/Rx FIFO X Tx/Rx FIFO size X 16 1. X = supported. 3.32 Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART (LPUART1). The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. DS12110 Rev 5 41/231 47 Functional overview STM32H743xI The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wakeup from Stop mode are programmable and can be done on: Start bit detection Any received data frame A specific programmed data frame Specific TXFIFO/RXFIFO status when FIFO mode is enabled. Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 3.33 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Fullduplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode, Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in Master or Slave mode, in Simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in Master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8bit embedded Rx and Tx FIFOs with DMA capability. 3.34 Serial audio interfaces (SAI) The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC'97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller. Audio sampling frequencies up to 192 kHz are supported. In addition, up to 8 microphones can be supported thanks to an embedded PDM interface. The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to work synchronously. 42/231 DS12110 Rev 5 STM32H743xI 3.35 Functional overview SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main SPDIFRX features are the following: Up to 4 inputs available Automatic symbol rate detection Maximum symbol rate: 12.288 MHz Stereo stream from 32 to 192 kHz supported Supports Audio IEC-60958 and IEC-61937, consumer applications Parity bit management Communication using DMA for audio samples Communication using DMA for control and user channel information Interrupt capabilities The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms. 3.36 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: Full-duplex communication mode automatic SWP bus state management (active, suspend, resume) configurable bitrate up to 2 Mbit/s automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. DS12110 Rev 5 43/231 47 Functional overview 3.37 STM32H743xI Management Data Input/Output (MDIO) slaves The devices embed an MDIO slave interface it includes the following features: - 32 x 16-bit firmware read/write, MDIO read-only output data registers - 32 x 16-bit firmware read-only, MDIO write-only input data registers Configurable slave (port) address Independently maskable interrupts/events: 3.38 32 MDIO Registers addresses, each of which is managed using separate input and output data registers: - MDIO Register write - MDIO Register read - MDIO protocol error Able to operate in and wake up from Stop mode SD/SDIO/MMC card host interfaces (SDMMC) Two SDMMC host interfaces are available. They support MultiMediaCard System Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits. Both interfaces support the SD memory card specifications version 4.1. and the SDIO card specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits. Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version 4.51 or previous. The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the interface and the SRAM. 3.39 Controller area network (FDCAN1, FDCAN2) The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory and a clock calibration unit. Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event synchronized time-triggered communication, global system time, and clock drift compensation. The FDCAN1 contains additional registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and time-triggered CAN communication. A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers (and triggers for TTCAN). This message RAM is shared between the two FDCAN1 and FDCAN2 modules. The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1. 44/231 DS12110 Rev 5 STM32H743xI 3.40 Functional overview Universal serial bus on-the-go high-speed (OTG_HS) The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2 supports only full-speed operations. They both integrate the transceivers for full-speed operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1 features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the OTG 2.0 specification. They have software-configurable endpoint setting and supports suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The main features are: Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing Supports the session request protocol (SRP) and host negotiation protocol (HNP) 9 bidirectional endpoints (including EP0) 16 host channels with periodic OUT support Software configurable to OTG1.3 and OTG2.0 modes of operation USB 2.0 LPM (Link Power Management) support Battery Charging Specification Revision 1.2 support Internal FS OTG PHY support External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only) The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. 3.41 Internal USB DMA HNP/SNP/IP inside (no need for any external resistor) For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Ethernet MAC interface with dedicated DMA controller (ETH) The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. DS12110 Rev 5 45/231 47 Functional overview STM32H743xI The devices include the following features: 3.42 Supports 10 and 100 Mbit/s rates Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors Tagged MAC frame support (VLAN support) Half-duplex (CSMA/CD) and full-duplex operation MAC control sublayer (control frames) support 32-bit CRC generation and removal Several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input Triggers interrupt when system time becomes greater than target time High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on data reception. 3.43 Debug infrastructure The devices offer a comprehensive set of debug and trace features to support software development and system integration. Breakpoint debugging Code execution tracing Software instrumentation JTAG debug port Serial-wire debug port Trigger input and output Serial-wire trace port Trace port Arm(R) CoreSightTM debug and trace components The debug can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools. The trace port performs data capture for logging and analysis. 46/231 DS12110 Rev 5 STM32H743xI 4 Memory mapping Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. DS12110 Rev 5 47/231 47 Pin descriptions 5 STM32H743xI Pin descriptions 3$ 3$ 3& 3& 3& 3' 3' 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3% %227 3% 3% 3( 3( 966 9'' Figure 4. LQFP100 pinout 3( 9'' 3( 966 3( 9&$3 3( 3$ 3( 3$ 9%$7 3$ 3& 3$ 3&26&B,1 3$ 3&26&B287 3$ 966 3& 9'' 3& 3+26&B,1 3& SLQV 3+26&B287 3& 1567 3' 3& 3' 3& 3' 3&B& 3' 3&B& 3' 966$ 3' 95() 3' 9''$ 3' 3$ 3% 3$ 3% 3$ 3% 3$ 3% 9'' 966 9&$3 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3% 3& 3$ 3& 3$ 3$ 3$ 9'' 966 06Y9 1. The above figure shows the package top view. 48/231 DS12110 Rev 5 STM32H743xI Pin descriptions Figure 5. TFBGA100 pinout $ 3& 26&B,1 3& 3( 3% 3% 3% 3% 3$ 3$ 3$ % 3& 26&B287 9%$7 3( 3% 3% 3' 3' 3& 3& 3$ & 3+26&B,1 966 3( 3( 3% 3' 3' 3& 3$ 3$ ' 3+ 26&B287 9'' 3( 3( %227 3' 3' 3' 3$ 3$ ( 1567 3&B& 3( 966 966 966 9&$3 3' 3& 3& ) 3& 3& 3&B& 9''/'2 9'' 9''86% 3'5B21 9&$3 3& 3& * 966$ 3$ 3$ 3& 3% 3( 3( 3' 3' 3% + 9''$ 3$ 3$ 3& 3( 3( 3( 3' 3' 3% - 966 3$ 3$ 3% 3( 3( 3% 3% 3' 3' . 9'' 3$ 3$ 3% 3( 3( 3% 3% 3' 3' 06Y9 1. The above figure shows the package top view. DS12110 Rev 5 49/231 95 Pin descriptions STM32H743xI SLQV 9'' 966 9&$3 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9''86% 966 3* 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 966 9'' 3) 3) 3) 3* 3* 3( 3( 3( 966 9'' 3( 3( 3( 3( 3( 3( 3% 3% 9&$3 9'' 3( 3( 3( 3( 3( 9%$7 3& 3&26&B,1 3&26&B287 3) 3) 3) 3) 3) 3) 966 9'' 3) 3) 3) 3) 3) 3+26&B,1 3+26&B287 1567 3& 3& 3&B& 3&B& 9'' 966$ 95() 9''$ 3$ 3$ 3$ 9'' 3'5B21 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'' 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 6. LQFP144 pinout 06Y9 1. The above figure shows the package top view. 50/231 DS12110 Rev 5 STM32H743xI Pin descriptions Figure 7. UFBGA169 ballout $ % & 3( 3( 9'' 3, 3% 3, 9'' 3( 966 9''/'2 3% 3% 3, 3( 3( 3'5B21 3% 3% 3& 26&B 287 3& 26&B ,1 3* 3' 9'' 3* 3' 966 3* 3* 3' 3& 3& 3, 3& 3$ 3, 3' 3$ 966 9'' ' 9'' 966 3& 3( 3( 3% 3* 3' 3' 3' 3$ 9''/'2 9&$3 ( 3, 3, 9%$7 3) 3) %227 3* 3* 3' 3$ 3$ 3$ 3$ ) 3, 3, 3) 3) 3) 3) 3% 3* 3& 3& 3& 3& 3$ * 9'' 966 3) 3) 3) 1567 3) 3( 3* 3* 3* 9''B 86% 9''B 86% + 3+ 26&B ,1 3+ 26&B 287 3) 3) 3- 3$ 3) 3( 3* 3* 3* 966 9'' - 3& 3& 966$ 3- 3$ 3$ 3) 3( 3( 3' 3' 3' 3' . 3&B& 3&B& 3+ 3$ 3$ 3& 3* 3( 3+ 3+ 3' 3' 3' / 9''$ 95() 3+ 3$ 3% 3% 3* 3( 3% 3+ 3% 966 9'' 0 9'' 966 3+ 966 3% 3) 966 3( 3% 9''/'2 966 3' 3% 1 3$ 3+ 3$ 9'' 3& 3) 9'' 3( 3( 9&$3 9'' 3% 3% 06Y9 1. The above figure shows the package top view. DS12110 Rev 5 51/231 95 Pin descriptions STM32H743xI PINOUT UNDER DEVELOPMENT SLQV 3, 3, 3+ 3+ 3+ 9'' 966 9&$3 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9''86% 966 3* 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 9'' 966 3+ 3+ 3+ 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 966 9'' 3) 3) 3) 3* 3* 3( 3( 3( 966 9'' 3( 3( 3( 3( 3( 3( 3% 3% 9&$3 9'' 3+ 3+ 3+ 3+ 3+ 3+ 3( 3( 3( 3( 3( 9%$7 3, 3& 3&26&B,1 3&26&B287 3, 3, 3, 966 9'' 3) 3) 3) 3) 3) 3) 966 9'' 3) 3) 3) 3) 3) 3+26&B,1 3+26&B287 1567 3& 3& 3&B& 3&B& 9'' 966$ 95() 9''$ 3$ 3$ 3$ 3+ 3+ 3, 3, 3, 3, 9'' 3'5B21 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'' 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 9'' 966 3, 3, Figure 8. LQFP176 pinout 06Y9 1. The above figure shows the package top view. 52/231 DS12110 Rev 5 STM32H743xI Pin descriptions Figure 9. UFBGA176+25 ballout $ 3( 3( 3( 3( 3% 3% 3* 3* 3% 3% 3' % 3( 3( 3( 3% 3% 3% 3* 3* 3* 3* & 9%$7 3, 3, 3, 9'' 3'5B21 9'' 9'' 9'' ' 3& 3, 3, 3, 966 %227 966 966 966 3) 3, 3, 966 9'' 3+ 966 966 966 966 ( ) 3& 26&B ,1 3& 26&B 287 3& 3$ 3$ 3$ 3' 3' 3& 3& 3$ 3* 3' 3' 3, 3, 3$ 3' 3' 3' 3+ 3, 3$ 3+ 3+ 3, 3$ 966 966 9&$3 3& 3$ * 3+ 26&B,1 966 9'' 3+ 966 966 966 966 966 966 9'' 3& 3& + 3+ 26&B 287 3) 3) 3+ 966 966 966 966 966 966 9'' 86% 3* 3& - 1567 3) 3) 3+ 966 966 966 966 966 9'' 9'' 3* 3* . 3) 3) 3) 9'' 966 966 966 966 966 3+ 3* 3* 3* / 3) 3) 3) 966 3+ 3+ 3' 3* 0 966$ 3& 3& 3&B& 3&B& 3% 3* 966 966 9&$3 3+ 3+ 3+ 3' 3' 1 95() 3$ 3$ 3$ 3& 3) 3* 9'' 9'' 9'' 3( 3+ 3' 3' 3' 3 95() 3$ 3$ 3$ 3& 3) 3) 3( 3( 3( 3( 3% 3% 3' 3' 5 9''$ 3$ 3$ 3% 3% 3) 3) 3( 3( 3( 3( 3% 3% 3% 3% 06Y9 1. The above figure shows the package top view. DS12110 Rev 5 53/231 95 Pin descriptions STM32H743xI SLQV 3, 3, 3, 3+ 3+ 3+ 9'' 966 9&$3 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9''86% 966 3* 3* 3* 3* 3* 3* 3* 3. 3. 3. 966 9'' 3- 3- 3- 3- 3- 3- 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3$ 3$ 3$ 3$ 3& 3& 9'' 966 3% 3% 3% 3, 3- 3- 3- 3- 3- 3) 3) 966 9'' 3) 3) 3) 3* 3* 3( 3( 3( 966 9'' 3( 3( 3( 3( 3( 3( 3% 3% 9&$3 966 9'' 3- 3+ 3+ 3+ 3+ 3+ 3+ 3+ 9'' 3% 3( 3( 3( 3( 3( 9%$7 3, 3& 3&26&B,1 3&26&B287 3, 3, 3, 966 9'' 3) 3) 3) 3, 3, 3, 3) 3) 3) 966 9'' 3) 3) 3) 3) 3) 3+26&B,1 3+26&B287 1567 3& 3& 3&B& 3&B& 9'' 966$ 95() 9''$ 3$ 3$ 3$ 3+ 3+ 3+ 3+ 3$ 966 9'' 3, 3, 3, 3, 9'' 3'5B21 966 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 3. 3. 3. 3. 3. 9'' 966 3* 3* 3* 3* 3* 3* 3- 3- 3- 3- 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 9'' 3, Figure 10. LQFP208 pinout 06Y9 1. The above figure shows the package top view. 54/231 DS12110 Rev 5 STM32H743xI Pin descriptions Figure 11. TFBGA240+25 ballout 9&$3 3. 3* 3* 3' 3& 3$ 3, 3, 966 $ 966 3, 3, 3, 3% 9'' /'2 % 9%$7 966 3, 3( 3% 966 3% 3. 3* 3- 3' 3' 3& 3$ 3, 3+ 3+ 3( 3( 3% 3% 3. 3. 3* 966 3' 3& 966 3, 3$ 966 9'' /'2 3% 3% 3* 3. 3* 3* 3- 3- 3' 3' 3$ 3$ 3+ 9&$3 9'' 9'' 3- 9'' 3' 3& 3& 3$ 3$ 3$ 3& 3* 3* 9'' 86% 3* 3* 966 9'' 86% & ' 3& 3& 26&B 26&B 287 ,1 3( 3( 3( ( 1& 3, 3& 3, 3( ) 1& 1& 3, 3, 9'' * 3) 1& 3) 3) 9'' 3, 3, 3'5B 21 %22 7 3' 3& 966 966 966 966 966 9'' 966 966 966 966 966 9'' + 3, - 3+ 3+ 26&B 26&B,1 287 966 3) 3) 966 966 966 966 966 9'' 3. . 1567 3) 3) 3) 9'' 966 966 966 966 966 9'' / 9''$ 3& 3) 3) 9'' 966 966 966 966 966 0 95() 3& 3& 3& 9'' 1 95() 3+ 3$ 3$ 3$ 3- 9'' 9'' 3( 9'' 9'' 3 966$ 3+ 3+ 3+ 3, 3- 3) 3) 3( 3( 5 3&B& 3&B& 3$ 966 3$ 3% 3) 966 3) 7 3$B& 3$B& 3$ 3& 3% 3- 3) 3* 8 966 3$ 3$ 3& 3% 3- 3- 3* 3) 9'' 3* 3* 3* 3. 3. 966 966 3- 966 1& 1& 9'' 3- 966 1& 1& 9'' 3- 966 1& 1& 9'' 3- 3- 3- 966 1& 3% 3% 3+ 3+ 3' 3' 9'' 3( 3( 3- 3+ 3+ 3' 3' 3' 3( 3( 3+ 966 3+ 3% 3% 3' 3' 3( 3( 9&$3 9'' /'2 3+ 3% 3% 3' 966 06Y9 1. The above figure shows the package top view. DS12110 Rev 5 55/231 95 Pin descriptions STM32H743xI Table 7. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin ANA Analog-only Input FT 5 V tolerant I/O TT 3.3 V tolerant I/O B Dedicated BOOT0 pin RST I/O structure Notes Pin functions 56/231 Definition Bidirectional reset pin with embedded weak pull-up resistor Option for TT and FT I/Os _f I2C FM+ option _a analog option (supplied by VDDA) _u USB option (supplied by VDD33USB) _h High Speed Low Voltage Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset. Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DS12110 Rev 5 STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - 1 A3 1 A2 A2 1 1 C3 PE2 I/O FT_h - TRACECLK, SAI1_CK1, SPI4_SCK, SAI1_MCLK_A, SAI4_MCLK_A, QUADSPI_BK1_IO2, SAI4_CK1, ETH_MII_TXD3, FMC_A23, EVENTOUT 2 B3 2 B2 A1 2 2 D3 PE3 I/O FT_h - TRACED0, TIM15_BKIN, SAI1_SD_B, SAI4_SD_B, FMC_A19, EVENTOUT - - TRACED1, SAI1_D2, DFSDM_DATIN3, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, SAI4_FS_A, SAI4_D2, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT - - TRACED2, SAI1_CK2, DFSDM_CKIN3, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, SAI4_SCK_A, SAI4_CK2, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT - - 3 4 C3 D3 3 4 A1 C3 B1 B2 3 4 3 4 D2 D1 PE4 PE5 I/O I/O FT_h FT_h 5 E3 5 C2 B3 5 5 E5 PE6 I/O FT_h - TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI4_SD_A, SAI4_D1, SAI2_MCK_B, TIM1_BKIN2_COMP12, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT - - - M4 H10 - - A1 VSS S - - - - - - - A3 - - - - VDD S - - - - 6 B2 6 E3 C1 6 6 B1 VBAT S - - - - - - - - J6 - - B2 VSS - - - - - - - - - D2 7 7 E4 PI8 I/O FT - EVENTOUT RTC_TAMP_2/ RTC_TS/ WKUP3 7 A2 7 D3 D1 8 8 E3 PC13 I/O FT - EVENTOUT RTC_TAMP_1/ RTC_TS/ WKUP2 - - - - J7 - - B6 VSS - - - - - DS12110 Rev 5 57/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) B1 E1 F1 9 10 9 10 Additional functions FT - EVENTOUT OSC32_IN - EVENTOUT OSC32_ OUT - C2 PC14OSC32_ IN (OSC32_ IN)(1) I/O C1 PC15OSC32_ OUT (OSC32_ OUT)(1) I/O FT TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 9 C1 Notes B1 8 I/O structure 9 A1 Alternate functions Pin name (function after reset) Pin type 8 TFBGA100 LQFP100 Pin/ball name - - - - D3 11 11 E2 PI9 I/O FT_h - UART4_RX, FDCAN1_RX, FMC_D30, LCD_VSYNC, EVENTOUT - - - - E3 12 12 F3 PI10 I/O FT_h - FDCAN1_RXFD_MODE, ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, EVENTOUT - - - E1 E4 13 13 F4 PI11 I/O FT - LCD_G6, OTG_HS_ULPI_DIR, EVENTOUT WKUP4 - C2 - D2 F2 14 14 A17 VSS S - - - - - D2 - D1 F3 15 15 E6 - - - - - - - VDD S - - - - (2) NC - - - - - (3) NC - - - - - (4) NC - - - - - E1 F1 - - - - - - - - - 10 F3 E2 16 16 G4 PF0 I/O FT_f - I2C2_SDA, FMC_A0, EVENTOUT - - - 11 E4 H3 17 17 G3 PF1 I/O FT_f - I2C2_SCL, FMC_A1, EVENTOUT - - - 12 F4 H2 18 18 G1 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - - - - F2 - - 19 H1 PI12 I/O FT - LCD_HSYNC, EVENTOUT - - - - F1 - - 20 H2 PI13 I/O FT - LCD_VSYNC, EVENTOUT - - - - - - - 21 H3 PI14 I/O FT_h - LCD_CLK, EVENTOUT - - - 13 E5 J2 19 22 H4 PF3 I/O FT_ ha - FMC_A3, EVENTOUT ADC3_INP5 58/231 G2 DS12110 Rev 5 STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) LQFP100 TFBGA100 LQFP144 UFBGA169 UFBGA176+25 LQFP176 LQFP208 TFBGA240 +25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - - 14 G3 J3 20 23 J5 PF4 I/O FT_ ha - FMC_A4, EVENTOUT ADC3_INN5, ADC3_INP9 - - 15 F5 K3 21 24 J4 PF5 I/O FT_ ha - FMC_A5, EVENTOUT ADC3_INP4 10 - 16 B10 G2 22 25 C10 VSS S - - - - 11 - 17 G1 G3 23 26 E9 VDD S - - - - - TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, SAI4_SD_B, QUADSPI_BK1_IO3, EVENTOUT ADC3_INN4, ADC3_INP8 - TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, SAI4_MCLK_B, QUADSPI_BK1_IO2, EVENTOUT ADC3_INP3 - TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS, SAI4_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT ADC3_INN3, ADC3_INP7 ADC3_INP2 - - - - - - 18 19 20 G4 F6 H4 K2 K1 L3 24 25 26 27 28 29 K2 K3 K4 PF6 PF7 PF8 I/O I/O I/O FT_ ha FT_ ha FT_ ha Additional functions - - 21 G5 L2 27 30 L4 PF9 I/O FT_ ha - TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, SAI4_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT - - 22 H3 L1 28 31 L3 PF10 I/O FT_ ha - TIM16_BKIN, SAI1_D3, QUADSPI_CLK, SAI4_D3, DCMI_D11, LCD_DE, EVENTOUT ADC3_INN2, ADC3_INP6 12 C1 23 H1 G1 29 32 J2 PH0OSC_IN (PH0) I/O FT - EVENTOUT OSC_IN 13 D1 24 H2 H1 30 33 J1 PH1OSC_OUT (PH1) I/O FT - EVENTOUT OSC_OUT 14 E1 25 G6 J1 31 34 K1 NRST I/O RST - - - DS12110 Rev 5 59/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) 15 16 F1 F2 - 17 (6) - (6) 26 27 - J2 - M2 M3 - 32 33 - 35 36 - - - - - - - F3(6) 29(6) K1(6) M5(6) 35(6) 38(6) L2 M2 M3 (5) R1(5) PC0 PC1 PC2 PC2_C M4(5) PC3 R2(5) PC3_C Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 J1 E2(6) 28(6) K2(6) M4(6) 34(6) 37(6) - 18 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - DFSDM_CKIN0, DFSDM_DATIN4, SAI2_FS_B, OTG_HS_ULPI_STP, FMC_SDNWE, LCD_R5, EVENTOUT ADC123_ INP10 - TRACED0, SAI1_D1, DFSDM_DATIN0, DFSDM_CKIN4, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, SAI4_SD_A, SDMMC2_CK, SAI4_D1, ETH_MDC, MDIOS_MDC, EVENTOUT ADC123_ INN10, ADC123_ INP11, RTC_TAMP_3/ WKUP5 FT_a - DFSDM_CKIN1, SPI2_MISO/I2S2_SDI, DFSDM_CKOUT, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT ADC123_ INN11, ADC123_ INP12 ANA TT_a - - ADC3_INN1, ADC3_INP0 FT_a - DFSDM_DATIN1, SPI2_MOSI/I2S2_SDO, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT ADC12_INN12, ADC12_INP13 ANA TT_a - - ADC3_INP1 I/O I/O I/O I/O FT_a FT_ ha - F5 30 - G3 36 39 E11 VDD S - - - - - E6 - B3 J10 - - C13 VSS S - - - - 19 G1 31 J3 M1 37 40 P1 VSSA S - - - - - - - - N1 - - N1 VREF- S - - - - 20 (7) - 32 L2 P1 38 41 M1 VREF+ S - - - - 21 H1 33 L1 R1 39 42 L1 VDDA S - - - - 60/231 DS12110 Rev 5 STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) G2 34 J5 N3 40 43 N5(5) PA0 - - - - - - - T1(5) PA0_C 23 H2 35 K4 N2 41 44 N4(5) PA1 - - - - - - - T2(5) PA1_C 24 J2 36 N1 P2 42 45 N3 PA2 Notes 22 I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions FT_a - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, TIM15_BKIN, USART2_CTS_NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH_MII_CRS, EVENTOUT ANA TT_a - - ADC12_INN1, ADC12_INP0 FT_ ha - TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCK_B, ETH_MII_RX_CLK/ETH_ RMII_REF_CLK, LCD_R2, EVENTOUT ADC1_INN16, ADC1_INP17 ANA TT_a - - ADC12_INP1 - TIM2_CH3, TIM5_CH3, LPTIM4_OUT, TIM15_CH1, USART2_TX, SAI2_SCK_B, ETH_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT ADC12_INP14, WKUP1 ADC3_INP13 I/O I/O I/O FT_a Additional functions ADC1_INP16, WKUP0 - - - N2 F4 43 46 N2 PH2 I/O FT_ ha - LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, ETH_MII_CRS, FMC_SDCKE0, LCD_R0, EVENTOUT - K1 - M1 - - - F5 VDD S - - - - - J1 - M7 J8 - - C16 VSS S - - - - - QUADSPI_BK2_IO1, SAI2_MCK_B, ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT ADC3_INN13, ADC3_INP14 - - - M3 G4 44 47 P2 PH3 I/O DS12110 Rev 5 FT_ ha 61/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) LQFP100 TFBGA100 LQFP144 UFBGA169 UFBGA176+25 LQFP176 LQFP208 TFBGA240 +25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - - - K3 H4 45 48 P3 PH4 I/O FT_fa - I2C2_SCL, LCD_G5, OTG_HS_ULPI_NXT, LCD_G4, EVENTOUT ADC3_INN14, ADC3_INP15 - - - L3 J4 46 49 P4 PH5 I/O FT_fa - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT ADC3_INN15, ADC3_INP16 ADC12_INP15 Additional functions 25 K2 37 N3 R2 47 50 U2 PA3 I/O FT_ ha - TIM2_CH4, TIM5_CH4, LPTIM5_OUT, TIM15_CH2, USART2_RX, LCD_B2, OTG_HS_ULPI_D0, ETH_MII_COL, LCD_B5, EVENTOUT 26 - 38 G2 K6 - 51 F2(4) VSS S - - - - - - - - L4 48 - - VSS S - - - - 27 - 39 - K4 49 52 G5 VDD S - - - - - TIM5_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, OTG_HS_SOF, DCMI_HSYNC, LCD_VSYNC, EVENTOUT ADC12_INP18, DAC1_OUT1 - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, SPI6_SCK, OTG_HS_ULPI_CK, LCD_R4, EVENTOUT ADC12_INN18, ADC12_INP19, DAC1_OUT2 - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, SPI6_MISO, TIM13_CH1, TIM8_BKIN_COMP12, MDIOS_MDC, TIM1_BKIN_COMP12, DCMI_PIXCLK, LCD_G2, EVENTOUT ADC12_INP3 28 29 30 G3 H3 J3 62/231 40 41 42 H6 L4 K5 N4 P4 P3 50 51 52 53 54 55 U3 T3 R3 PA4 PA5 PA6 I/O I/O I/O DS12110 Rev 5 TT_a TT_ ha FT_a STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) 31 32 K3 G4 43 44 J6 K6 R3 N5 53 54 56 57 R5 T4 PA7 PC4 I/O I/O TT_a TT_a Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, ADC12_INN3, SPI6_MOSI, TIM14_CH1, ADC12_INP7, ETH_MII_RX_DV/ETH_R OPAMP1_VINM MII_CRS_DV, FMC_SDNWE, EVENTOUT - DFSDM_CKIN2, I2S1_MCK, SPDIFRX_IN2, ETH_MII_RXD0/ETH_R MII_RXD0, FMC_SDNE0, EVENTOUT ADC12_INP4, OPAMP1_ VOUT, COMP_1_INM ADC12_INN4, ADC12_INP8, OPAMP1_ VINM 33 H4 45 N5 P5 55 58 U4 PC5 I/O TT_a - SAI1_D3, DFSDM_DATIN2, SPDIFRX_IN3, SAI4_D3, ETH_MII_RXD1/ETH_R MII_RXD1, FMC_SDCKE0, COMP_1_OUT, EVENTOUT - - - N4 - - 59 G13 VDD S - - - - - - - H12 J9 - 60 G16 VSS S - - - - - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, DFSDM_CKOUT, UART4_CTS, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, LCD_G1, EVENTOUT ADC12_INN5, ADC12_INP9, OPAMP1_VINP, COMP_1_INP - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM_DATIN1, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, LCD_G0, EVENTOUT ADC12_INP5, COMP_1_INM - SAI1_D1, DFSDM_CKIN1, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, SAI4_SD_A, QUADSPI_CLK, SAI4_D1, EVENTOUT COMP_1_INP, RTC_OUT 34 35 36 J4 K4 G5 46 47 48 M5 L5 L6 R5 R4 M6 56 57 58 61 62 63 U5 T5 R6 PB0 PB1 PB2 I/O I/O I/O DS12110 Rev 5 FT_a TT_u FT_ ha 63/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) LQFP100 TFBGA100 LQFP144 UFBGA169 UFBGA176+25 LQFP176 LQFP208 TFBGA240 +25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - - - - - - 64 P5 PI15 I/O FT - LCD_G2, LCD_R0, EVENTOUT - - - - J4 - - 65 N6 PJ0 I/O FT - LCD_R7, LCD_R1, EVENTOUT - - - - H5 - - 66 P6 PJ1 I/O FT - LCD_R2, EVENTOUT - - - - - - - 67 T6 PJ2 I/O FT - LCD_R3, EVENTOUT - - - - - - - 68 U6 PJ3 I/O FT - LCD_R4, EVENTOUT - - - - - - - 69 U7 PJ4 I/O FT - LCD_R5, EVENTOUT - - - 49 M6 R6 59 70 T7 PF11 I/O FT_a - SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT ADC1_INP2 - - 50 N6 P6 60 71 R7 PF12 I/O FT_ ha - FMC_A6, EVENTOUT ADC1_INN2, ADC1_INP6 - - 51 M11 M8 61 72 J3 VSS S - - - - - - 52 - N8 62 73 H5 VDD S - - - - - - 53 G7 N6 63 74 P7 PF13 I/O FT_ ha - DFSDM_DATIN6, I2C4_SMBA, FMC_A7, EVENTOUT ADC2_INP2 - - 54 H7 R7 64 75 P8 PF14 I/O FT_ fha - DFSDM_CKIN6, I2C4_SCL, FMC_A8, EVENTOUT ADC2_INN2, ADC2_INP6 - - 55 J7 P7 65 76 R9 PF15 I/O FT_fh - I2C4_SDA, FMC_A9, EVENTOUT - - - 56 K7 N7 66 77 T8 PG0 I/O FT_h - FMC_A10, EVENTOUT - - - - M2 F6 - - J16 VSS S - - - - - - - A10 - - - H13 VDD S - - - - - - 57 L7 M7 67 78 U8 PG1 I/O TT_h - FMC_A11, EVENTOUT OPAMP2_ VINM - TIM1_ETR, DFSDM_DATIN2, UART7_RX, QUADSPI_BK2_IO0, FMC_D4/FMC_DA4, EVENTOUT OPAMP2_ VOUT, COMP_2_INM 37 H5 64/231 58 G8 R8 68 79 U9 PE7 I/O DS12110 Rev 5 TT_ ha Additional functions STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) J5 H8 P8 69 80 T9 PE8 I/O I/O structure Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 59 Pin name (function after reset) TT_ ha Notes 38 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - TIM1_CH1N, DFSDM_CKIN2, UART7_TX, QUADSPI_BK2_IO1, FMC_D5/FMC_DA5, COMP_2_OUT, EVENTOUT OPAMP2_ VINM OPAMP2_VINP, COMP_2_INP 39 K5 60 J8 P9 70 81 P9 PE9 I/O TT_ ha - TIM1_CH1, DFSDM_CKOUT, UART7_RTS, QUADSPI_BK2_IO2, FMC_D6/FMC_DA6, EVENTOUT - - 61 C12 M9 71 82 J17 VSS S - - - - - - 62 C13 N9 72 83 J13 VDD S - - - - - TIM1_CH2N, DFSDM_DATIN4, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7/FMC_DA7, EVENTOUT COMP_2_INM - TIM1_CH2, DFSDM_CKIN4, SPI4_NSS, SAI2_SD_B, FMC_D8/FMC_DA8, LCD_G3, EVENTOUT COMP_2_INP - TIM1_CH3N, DFSDM_DATIN5, SPI4_SCK, SAI2_SCK_B, FMC_D9/FMC_DA9, COMP_1_OUT, LCD_B4, EVENTOUT - - 40 41 42 G6 H6 J6 63 64 65 M8 N8 L8 R9 P10 R10 73 74 75 84 85 86 N9 P10 R10 PE10 PE11 PE12 I/O I/O I/O FT_ ha FT_ ha FT_h 43 K6 66 K8 N11 76 87 T10 PE13 I/O FT_h - TIM1_CH3, DFSDM_CKIN5, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_DA10, COMP_2_OUT, LCD_DE, EVENTOUT - - - L12 F7 - - K15 VSS S - - - - - - - H13 - - - K13 VDD S - - - - DS12110 Rev 5 65/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) 44 45 46 G7 H7 J7 67 68 69 J9 N9 L9 P11 R11 R12 77 78 79 88 89 90 U10 R11 P11 PE14 PE15 PB10 I/O I/O I/O FT_h FT_h FT_f Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - TIM1_CH4, SPI4_MOSI, SAI2_MCK_B, FMC_D11/FMC_DA11, LCD_CLK, EVENTOUT - - TIM1_BKIN, HDMI__TIM1_BKIN, FMC_D12/FMC_DA12, TIM1_BKIN_COMP12, LCD_R7, EVENTOUT - - TIM2_CH3, HRTIM_SCOUT, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM_DATIN7, USART3_TX, QUADSPI_BK1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT - - 47 K7 70 M9 R13 80 91 P12 PB11 I/O FT_f - TIM2_CH4, HRTIM_SCIN, LPTIM2_ETR, I2C2_SDA, DFSDM_CKIN7, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_R MII_TX_EN, LCD_G5, EVENTOUT 48 F8 71 N10 M10 81 92 U11 VCAPVCA P S - - - - 49 E4 - - K7 - 93 L15 VSS S - - - - - - - M10 - - - U12 VDDLDO S - - - - 50 - 72 M1 N10 82 94 L13 VDD S - - - - - - - - - - 95 R12 PJ5 I/O FT - LCD_R6, EVENTOUT - - TIM12_CH1, I2C2_SMBA, SPI5_SCK, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, EVENTOUT - - I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, EVENTOUT - - - 66/231 - - - - - - M11 N12 83 84 96 97 T11 U13 PH6 PH7 I/O I/O DS12110 Rev 5 FT FT_fa STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) PH8 I/O - - - - F8 - - M15 VSS S - - - - - - - L13 - - - M13 VDD S - - - - - - - - M13 86 99 R13 PH9 I/O FT_h - TIM12_CH2, I2C3_SMBA, FMC_D17, DCMI_D0, LCD_R3, EVENTOUT - - - - K9 L13 87 100 P13 PH10 I/O FT_h - TIM5_CH1, I2C4_SMBA, FMC_D18, DCMI_D1, LCD_R4, EVENTOUT - - - - L10 L12 88 101 P14 PH11 I/O FT_fh - TIM5_CH2, I2C4_SCL, FMC_D19, DCMI_D2, LCD_R5, EVENTOUT - - - - K10 K12 89 102 R14 PH12 I/O FT_fh - TIM5_CH3, I2C4_SDA, FMC_D20, DCMI_D3, LCD_R6, EVENTOUT - - - - - H12 90 - N16 VSS S - - - - - - - N11 J12 91 103 P17 VDD S - - - - - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM_DATIN1, USART3_CK, FDCAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_RM II_TXD0, OTG_HS_ID, TIM1_BKIN_COMP12, UART5_RX, EVENTOUT - TIM1_CH1N, LPTIM2_OUT, SPI2_SCK/I2S2_CK, DFSDM_CKIN1, USART3_CTS_NSS, FDCAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_RM II_TXD1, UART5_TX, EVENTOUT 51 52 K8 J8 73 74 N12 L11 P12 P13 92 93 104 105 T14 U14 Pin name (function after reset) PB12 PB13 I/O I/O DS12110 Rev 5 FT_u FT_u Notes I/O structure T13 TFBGA240 +25 98 LQFP208 85 LQFP176 M12 UFBGA176+25 - UFBGA169 - LQFP144 - TFBGA100 - FT_fh a LQFP100 Pin type Pin/ball name Alternate functions Additional functions - - TIM5_ETR, I2C3_SDA, FMC_D16, DCMI_HSYNC, LCD_R2, EVENTOUT OTG_HS_ VBUS 67/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) 53 54 55 56 H10 G10 K9 J9 75 76 77 78 N13 M13 M12 K11 R14 R15 P15 P14 94 95 96 97 106 107 108 109 U15 T15 U16 T17 PB14 PB15 PD8 PD9 I/O I/O I/O I/O FT_u FT_u FT_h FT_h Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, DFSDM_DATIN2, USART3_RTS, UART4_RTS, SDMMC2_D0, OTG_HS_DM, EVENTOUT - - RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, DFSDM_CKIN2, UART4_CTS, SDMMC2_D1, OTG_HS_DP, EVENTOUT - - DFSDM_CKIN3, SAI3_SCK_B, USART3_TX, SPDIFRX_IN1, FMC_D13/FMC_DA13, EVENTOUT - - DFSDM_DATIN3, SAI3_SD_B, USART3_RX, FDCAN2_RXFD_MODE, FMC_D14/FMC_DA14, EVENTOUT - - 57 H9 79 K12 N15 98 110 T16 PD10 I/O FT_h - DFSDM_CKOUT, SAI3_FS_B, USART3_CK, FDCAN2_TXFD_MODE, FMC_D15/FMC_DA15, LCD_B3, EVENTOUT - - - N7 - - - N12 VDD S - - - - - - - - F9 - - U17 VSS S - - - - 68/231 DS12110 Rev 5 STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) 58 59 G9 K10 80 81 J10 K13 N14 N13 99 100 111 112 R15 R16 PD11 PD12 I/O I/O FT_h FT_fh Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - LPTIM2_IN2, I2C4_SMBA, USART3_CTS_NSS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, EVENTOUT - - LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17, EVENTOUT - - 60 J10 82 J11 M15 101 113 R17 PD13 I/O FT_fh - LPTIM1_OUT, TIM4_CH2, I2C4_SDA, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT - - 83 - K8 102 114 T12 VSS S - - - - - - 84 - J13 103 115 N11 VDD S - - - - - TIM4_CH3, SAI3_MCLK_B, UART8_CTS, FMC_D0/FMC_DA0, EVENTOUT - - 61 H8 85 J13 M14 104 116 P16 PD14 I/O FT_h 62 G8 86 J12 L14 105 117 P15 PD15 I/O FT_h - TIM4_CH4, SAI3_MCLK_A, UART8_RTS, FMC_D1/FMC_DA1, EVENTOUT - - - - - - 118 N15 PJ6 I/O FT - TIM8_CH2, LCD_R7, EVENTOUT - - - - - - - 119 N14 PJ7 I/O FT - TRGIN, TIM8_CH2N, LCD_G0, EVENTOUT - - - - - - - - N10 VDD S - - - - - - F10 - - R8 VSS S - - - - - - - - 120 N13 PJ8 I/O FT - TIM1_CH3N, TIM8_CH1, UART8_TX, LCD_G1, EVENTOUT - - - - - - - 121 M14 PJ9 I/O FT - TIM1_CH3, TIM8_CH1N, UART8_RX, LCD_G2, EVENTOUT - DS12110 Rev 5 69/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) LQFP100 TFBGA100 LQFP144 UFBGA169 UFBGA176+25 LQFP176 LQFP208 TFBGA240 +25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name - - - - - - 122 L14 PJ10 I/O FT - TIM1_CH2N, TIM8_CH2, SPI5_MOSI, LCD_G3, EVENTOUT - - - - - - - 123 K14 PJ11 I/O FT - TIM1_CH2, TIM8_CH2N, SPI5_MISO, LCD_G4, EVENTOUT - - - - - - - 124 N8 VDD S - - - - G6 - 125 U1 VSS S - - - - - - - - - - - NC - - - - - - - - - - - - NC - - - - - - - - - - - - (2) NC - - - - - - - - - - - - L7 - - - - - - - N17 (2) M16 (2) M17 Alternate functions Additional functions - - VSS S - - - - L16 (2) NC - - - - - L17 (2) NC - - - - - NC - - - - - (2) NC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - L8 VSS S - - - - - - - - - - 126 J14 PK0 I/O FT - TIM1_CH1N, TIM8_CH3, SPI5_SCK, LCD_G5, EVENTOUT - - - - - - - 127 J15 PK1 I/O FT - TIM1_CH1, TIM8_CH3N, SPI5_NSS, LCD_G6, EVENTOUT - - - - - - - 128 H17 PK2 I/O FT - TIM1_BKIN, TIM8_BKIN, TIM8_BKIN_COMP12, TIM1_BKIN_COMP12, LCD_G7, EVENTOUT - - - 87 H9 L15 106 129 H16 PG2 I/O FT_h - TIM8_BKIN, TIM8_BKIN_COMP12, FMC_A12, EVENTOUT - - - 88 H10 K15 107 130 H15 PG3 I/O FT_h - TIM8_BKIN2, TIM8_BKIN2_COMP12, FMC_A13, EVENTOUT - - - - - G7 - - - VSS S - - - - 70/231 K16 (2) K17 DS12110 Rev 5 STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) UFBGA169 UFBGA176+25 LQFP176 LQFP208 TFBGA240 +25 - - - - - - N7 VDD S - Notes LQFP144 - I/O structure TFBGA100 Pin name (function after reset) Pin type LQFP100 Pin/ball name Alternate functions Additional functions - - - - - - 89 F8 K14 108 131 H14 PG4 I/O FT_h - TIM1_BKIN2, TIM1_BKIN2_COMP12, FMC_A14/FMC_BA0, EVENTOUT - - 90 H11 K13 109 132 G14 PG5 I/O FT_h - TIM1_ETR, FMC_A15/FMC_BA1, EVENTOUT - - TIM17_BKIN, HRTIM_CHE1, QUADSPI_BK1_NCS, FMC_NE3, DCMI_D12, LCD_R7, EVENTOUT - - HRTIM_CHE2, SAI1_MCLK_A, USART6_CK, FMC_INT, DCMI_D13, LCD_CLK, EVENTOUT - - - - - - 91 92 G9 G10 J15 J14 110 111 133 134 G15 F16 PG6 PG7 I/O I/O FT_h FT_h - - 93 G11 H14 112 135 F15 PG8 I/O FT_h - TIM8_ETR, SPI6_NSS, USART6_RTS, SPDIFRX_IN2, ETH_PPS_OUT, FMC_SDCLK, LCD_G7, EVENTOUT - - 94 - G12 113 136 - VSS S - - - - - - - G12 - - - G17 VDD50 USB S - - - - - F6 95 G13 H13 114 137 F17 VDD33 USB S - - - - - - - - - - - M5 VDD S - - - - - HRTIM_CHA1, TIM3_CH1, TIM8_CH1, DFSDM_CKIN3, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, SDMMC1_D6, DCMI_D0, LCD_HSYNC, EVENTOUT SWPMI_IO 63 F10 96 F9 H15 115 138 F14 PC6 I/O DS12110 Rev 5 FT_h 71/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) 64 65 E10 F9 97 98 F10 F12 G15 G14 116 117 139 140 F13 E13 PC7 PC8 I/O I/O FT_h FT_h Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - TRGIO, HRTIM_CHA2, TIM3_CH2, TIM8_CH2, DFSDM_DATIN3, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, SWPMI_TX, SDMMC1_D7, DCMI_D1, LCD_G6, EVENTOUT - - TRACED1, HRTIM_CHB1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS, FMC_NE2/FMC_NCE, SWPMI_RX, SDMMC1_D0, DCMI_D2, EVENTOUT - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, LCD_G3, SWPMI_SUSPEND, SDMMC1_D1, DCMI_D3, LCD_B2, EVENTOUT - 66 E9 99 F11 F14 118 141 E14 PC9 I/O FT_fh - - - - - G8 - - - VSS S - - - - - - - - - - L5 VDD S - - - 67 D9 72/231 100 E12 F15 119 142 E15 PA8 I/O DS12110 Rev 5 FT_ fha - MCO1, TIM1_CH1, HRTIM_CHB2, TIM8_BKIN2, I2C3_SCL, USART1_CK, OTG_FS_SOF, UART7_RX, TIM8_BKIN2_COMP12, LCD_B3, LCD_R6, EVENTOUT - STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) 68 69 70 C9 D10 C10 101 102 103 E11 E10 F13 E15 D15 C15 120 121 122 143 144 145 D15 D14 E17 PA9 PA10 PA11 I/O I/O I/O FT_u FT_u FT_u Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - TIM1_CH2, HRTIM_CHC1, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, OTG_FS_VBUS USART1_TX, FDCAN1_RXFD_MODE, DCMI_D0, LCD_R5, EVENTOUT - TIM1_CH3, HRTIM_CHC2, LPUART1_RX, USART1_RX, FDCAN1_TXFD_MODE, OTG_FS_ID, MDIOS_MDIO, LCD_B4, DCMI_D1, LCD_B1, EVENTOUT - - TIM1_CH4, HRTIM_CHD1, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS_NSS, FDCAN1_RX, OTG_FS_DM, LCD_R4, EVENTOUT - - 71 B10 104 E13 B15 123 146 E16 PA12 I/O FT_u - TIM1_ETR, HRTIM_CHD2, LPUART1_RTS, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS, SAI2_FS_B, FDCAN1_TX, OTG_FS_DP, LCD_R5, EVENTOUT 72 A10 105 D11 A15 124 147 C15 PA13 (JTMS/SW DIO) I/O FT - JTMS-SWDIO, EVENTOUT - 73 E7 106 D13 F13 125 148 D17 VCAPVCA P S - - - - 74 E5 107 - F12 126 149 - VSS S - - - - - - - D12 - - - C17 VDDLDO - - - - 75 - 108 - G13 127 150 K5 VDD - - - - S DS12110 Rev 5 73/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) UFBGA169 UFBGA176+25 LQFP176 LQFP208 TFBGA240 +25 - - - E12 128 151 D16 PH13 - - - - - - - - E13 D13 129 130 152 153 B17 B16 PH14 PH15 I/O FT_h I/O I/O FT_h FT_h Notes LQFP144 - I/O structure TFBGA100 Pin name (function after reset) Pin type LQFP100 Pin/ball name Alternate functions Additional functions - TIM8_CH1N, UART4_TX, FDCAN1_TX, FMC_D21, LCD_G2, EVENTOUT - - TIM8_CH2N, UART4_RX, FDCAN1_RX, FMC_D22, DCMI_D4, LCD_G3, EVENTOUT - - TIM8_CH3N, FDCAN1_TXFD_MODE, FMC_D23, DCMI_D11, LCD_G4, EVENTOUT - - - - - A13 E14 131 154 A16 PI0 I/O FT_h - TIM5_CH4, SPI2_NSS/I2S2_WS, FDCAN1_RXFD_MODE, FMC_D24, DCMI_D13, LCD_G5, EVENTOUT - - - - G9 - - - VSS S - - - - - - - - B13 D14 132 155 A15 PI1 I/O FT_h - TIM8_BKIN2, SPI2_SCK/I2S2_CK, TIM8_BKIN2_COMP12, FMC_D25, DCMI_D8, LCD_G6, EVENTOUT - - - A6 C14 133 156 B15 PI2 I/O FT_h - TIM8_CH4, SPI2_MISO/I2S2_SDI, FMC_D26, DCMI_D9, LCD_G7, EVENTOUT - - - - - B7 C13 134 157 C14 PI3 I/O FT_h - TIM8_ETR, SPI2_MOSI/I2S2_SDO, FMC_D27, DCMI_D10, EVENTOUT - - - - D9 135 - - VSS S - - - - - - - - C9 136 158 - VDD S - - - - 76 A9 109 B12 A14 137 159 B14 PA14 (JTCK/SW CLK) I/O FT - JTCK-SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, HRTIM_FLT1, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS, UART7_TX, EVENTOUT - 77 A8 74/231 110 C11 A13 138 160 A14 PA15 (JTDI) I/O DS12110 Rev 5 FT STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) 79 B9 B8 112 A12 B11 B14 B13 139 140 161 162 A13 B13 PC10 PC11 I/O I/O I/O structure Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 111 Pin name (function after reset) FT_ ha FT_h Notes 78 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - HRTIM_EEV1, DFSDM_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, DCMI_D8, LCD_R2, EVENTOUT - - HRTIM_FLT2, DFSDM_DATIN5, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, DCMI_D4, EVENTOUT - - 80 C8 113 A11 A12 141 163 C12 PC12 I/O FT_h - TRACED3, HRTIM_EEV2, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9, EVENTOUT - - - - G10 - - - VSS S - - - - - DFSDM_CKIN6, SAI3_SCK_A, UART4_RX, FDCAN1_RX, FMC_D2/FMC_DA2, EVENTOUT - - 81 D8 114 D10 B12 142 164 D13 PD0 I/O FT_h 82 E8 115 C10 C12 143 165 E12 PD1 I/O FT_h - DFSDM_DATIN6, SAI3_SD_A, UART4_TX, FDCAN1_TX, FMC_D3/FMC_DA3, EVENTOUT 83 B7 116 E9 D12 144 166 D12 PD2 I/O FT_h - TRACED2, TIM3_ETR, UART5_RX, SDMMC1_CMD, DCMI_D11, EVENTOUT - - DFSDM_CKOUT, SPI2_SCK/I2S2_CK, USART2_CTS_NSS, FMC_CLK, DCMI_D5, LCD_G7, EVENTOUT - 84 C7 117 D9 D11 145 167 B12 PD3 I/O DS12110 Rev 5 FT_h 75/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) 85 D7 118 C9 D10 146 168 A12 PD4 I/O FT_h Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - HRTIM_FLT3, SAI3_FS_A, USART2_RTS, FDCAN1_RXFD_MODE, FMC_NOE, EVENTOUT - - 86 B6 119 A9 C11 147 169 A11 PD5 I/O FT_h - HRTIM_EEV3, USART2_TX, FDCAN1_TXFD_MODE, FMC_NWE, EVENTOUT - - 120 - D8 148 170 R4 VSS S - - - - - - 121 - C8 149 171 - VDD S - - - - - SAI1_D1, DFSDM_CKIN4, DFSDM_DATIN1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, SAI4_SD_A, FDCAN2_RXFD_MODE, SAI4_D1, SDMMC2_CK, FMC_NWAIT, DCMI_D10, LCD_B2, EVENTOUT - - 87 C6 122 B9 B11 150 172 B11 PD6 I/O FT_h 88 D6 123 D8 A11 151 173 C11 PD7 I/O FT_h - DFSDM_DATIN4, SPI1_MOSI/I2S1_SDO, DFSDM_CKIN1, USART2_CK, SPDIFRX_IN0, SDMMC2_CMD, FMC_NE1, EVENTOUT - - - - - - 174 D11 PJ12 I/O FT - TRGOUT, LCD_G3, LCD_B0, EVENTOUT - - - - - - - 175 E10 PJ13 I/O FT - LCD_B4, LCD_B1, EVENTOUT - - - - - - - 176 D10 PJ14 I/O FT - LCD_B2, EVENTOUT - - - - - - - 177 B10 PJ15 I/O FT - LCD_B3, EVENTOUT - - - - - H6 - - - VSS S - - - - - - - A7 - - - - VDD S - - - - 76/231 DS12110 Rev 5 STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) - - - - - - - - - - 124 125 126 127 128 C8 A8 B8 E8 D7 C10 B10 B9 B8 A8 152 153 154 155 156 178 179 180 181 182 A10 A9 B9 C9 D9 PG9 PG10 PG11 PG12 PG13 I/O I/O I/O I/O I/O FT_h FT_h FT_h FT_h FT_h Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - SPI1_MISO/I2S1_SDI, USART6_RX, SPDIFRX_IN3, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE, DCMI_VSYNC, EVENTOUT - - HRTIM_FLT5, SPI1_NSS/I2S1_WS, LCD_G3, SAI2_SD_B, FMC_NE3, DCMI_D2, LCD_B2, EVENTOUT - - HRTIM_EEV4, SPI1_SCK/I2S1_CK, SPDIFRX_IN0, SDMMC2_D2, ETH_MII_TX_EN/ETH_R MII_TX_EN, DCMI_D3, LCD_B3, EVENTOUT - - LPTIM1_IN1, HRTIM_EEV5, SPI6_MISO, USART6_RTS, SPDIFRX_IN1, LCD_B4, ETH_MII_TXD1/ETH_RM II_TXD1, FMC_NE4, LCD_B1, EVENTOUT - - TRACED0, LPTIM1_OUT, HRTIM_EEV10, SPI6_SCK, USART6_CTS_NSS, ETH_MII_TXD0/ETH_RM II_TXD0, FMC_A24, LCD_R0, EVENTOUT - - - - 129 C7 A7 157 183 D8 PG14 I/O FT_h - TRACED1, LPTIM1_ETR, SPI6_MOSI, USART6_TX, QUADSPI_BK2_IO3, ETH_MII_TXD1/ETH_RM II_TXD1, FMC_A25, LCD_B0, EVENTOUT - - 130 - D7 158 184 - VSS S - - - - - - 131 - C7 159 185 - VDD S - - - - DS12110 Rev 5 77/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) LQFP100 TFBGA100 LQFP144 UFBGA169 UFBGA176+25 LQFP176 LQFP208 TFBGA240 +25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - - - - - - 186 C8 PK3 I/O FT - LCD_B4, EVENTOUT - - - - - - - 187 B8 PK4 I/O FT - LCD_B5, EVENTOUT - - - - - - - 188 A8 PK5 I/O FT - LCD_B6, EVENTOUT - - - - - - - 189 C7 PK6 I/O FT - LCD_B7, EVENTOUT - - - - - - - 190 D7 PK7 I/O FT - LCD_DE, EVENTOUT - - - - - H7 - - - VSS S - - - - - - 132 E7 B7 160 191 D6 PG15 I/O FT_h - USART6_CTS_NSS, FMC_SDNCAS, DCMI_D13, EVENTOUT - - JTDO/TRACESWO, TIM2_CH2, HRTIM_FLT4, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK, SDMMC2_D2, UART7_RX, EVENTOUT - - NJTRST, TIM16_BKIN, TIM3_CH1, HRTIM_EEV6, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, UART7_TX, EVENTOUT - - - 89 90 A7 A6 133 134 F7 B6 A10 A9 161 162 192 193 C6 B7 PB3(JTDO /TRACES WO) PB4(NJTR ST) I/O I/O FT FT 91 C5 135 C6 A6 163 194 A5 PB5 I/O FT - TIM17_BKIN, TIM3_CH2, HRTIM_EEV7, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, FDCAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10, UART5_RX, EVENTOUT - - - - H8 - - - VSS S - - - 78/231 DS12110 Rev 5 Additional functions STM32H743xI Pin descriptions Table 8. STM32H743xI pin/ball definition (continued) 92 B5 136 A5 B6 164 195 B5 PB6 I/O FT_f Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - TIM16_CH1N, TIM4_CH1, HRTIM_EEV8, I2C1_SCL, HDMI_CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, QUADSPI_BK1_NCS, DFSDM_DATIN5, FMC_SDNE1, DCMI_D5, UART5_TX, EVENTOUT - PVD_IN 93 A5 137 D6 B5 165 196 C5 PB7 I/O FT_fa - TIM17_CH1N, TIM4_CH2, HRTIM_EEV9, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, FDCAN2_TXFD_MODE, DFSDM_CKIN5, FMC_NL, DCMI_VSYNC, EVENTOUT 94 D5 138 E6 D6 166 197 E8 BOOT0 I B - - VPP - TIM16_CH1, TIM4_CH3, DFSDM_CKIN7, I2C1_SCL, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6, LCD_B6, EVENTOUT - - TIM17_CH1, TIM4_CH4, DFSDM_DATIN7, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, I2C4_SMBA, SDMMC1_D5, DCMI_D7, LCD_B7, EVENTOUT - 95 96 B4 A4 139 140 B5 C5 A5 B4 167 168 198 199 D5 D4 PB8 PB9 I/O I/O DS12110 Rev 5 FT_fh FT_fh 79/231 95 Pin descriptions STM32H743xI Table 8. STM32H743xI pin/ball definition (continued) 97 D4 141 D5 A4 169 200 C4 PE0 I/O FT_h Notes I/O structure Pin name (function after reset) Pin type TFBGA240 +25 LQFP208 LQFP176 UFBGA176+25 UFBGA169 LQFP144 TFBGA100 LQFP100 Pin/ball name Alternate functions Additional functions - LPTIM1_ETR, TIM4_ETR, HRTIM_SCIN, LPTIM2_ETR, UART8_RX, FDCAN1_RXFD_MODE, SAI2_MCK_A, FMC_NBL0, DCMI_D2, EVENTOUT - - 98 C4 142 D4 A3 170 201 B4 PE1 I/O FT_h - LPTIM1_IN2, HRTIM_SCOUT, UART8_TX, FDCAN1_TXFD_MODE, FMC_NBL1, DCMI_D3, EVENTOUT - - - - - - - A7 VCAP S - - - - 99 - - - D5 - 202 - VSS S - - - - - F7 143 C4 C6 171 203 E7 PDR_ON S - - - - - F4 - B4 - - - A6 VDDLDO S - - - - 100 - 144 - C5 172 204 - VDD S - - - - - TIM8_BKIN, SAI2_MCK_A, TIM8_BKIN_COMP12, FMC_NBL2, DCMI_D5, LCD_B4, EVENTOUT - - - - - - D4 173 205 A4 PI4 I/O FT_h - - - - C4 174 206 A3 PI5 I/O FT_h - TIM8_CH1, SAI2_SCK_A, FMC_NBL3, DCMI_VSYNC, LCD_B5, EVENTOUT - - - A4 C3 175 207 A2 PI6 I/O FT_h - TIM8_CH2, SAI2_SD_A, FMC_D28, DCMI_D6, LCD_B6, EVENTOUT - - - - E2 C2 176 208 B3 PI7 I/O FT_h - TIM8_CH3, SAI2_FS_A, FMC_D29, DCMI_D7, LCD_B7, EVENTOUT - - - - - H9 - - - VSS S - - - - - - - - K9 - - - VSS S - - - - - - - - K10 - - - VSS S - - - - 1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is valid for all resets except for power-on reset. 2. This ball should remain floating. 80/231 DS12110 Rev 5 STM32H743xI Pin descriptions 3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use. 4. This ball should be connected to VSS. 5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. 6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. 7. VREF+ pin, and consequently the internal voltage reference, are not available on the TFBGA100 package. On this package, this pin is double-bonded to VDDA which can be connected to an external reference. The internal voltage reference buffer is not available and must be kept disabled DS12110 Rev 5 81/231 95 AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1/ 3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/S PDIFRX SAI4/ FDCAN1/2/ TIM13/14/Q UADSPI/F MC/ SDMMC2/ LCD/ SPDIFRX TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 PA0 - TIM2_CH1/ TIM2_ETR TIM5_CH1 TIM8_ETR TIM15_BKIN - - USART2_ CTS_NSS UART4_TX SDMMC2_ CMD SAI2_SD_B ETH_MII_ CRS - - - EVENTOUT PA1 - TIM2_CH2 TIM5_CH2 LPTIM3_ OUT TIM15_ CH1N - - USART2_ RTS UART4_RX QUADSPI_ BK1_IO3 SAI2_MCK_ B ETH_MII_ RX_CLK/ ETH_RMII_ REF_CLK - - LCD_R2 EVENTOUT PA2 - TIM2_CH3 TIM5_CH3 LPTIM4_ OUT TIM15_CH1 - - USART2_ TX SAI2_SCK_ B - - ETH_MDIO MDIOS_ MDIO - LCD_R1 EVENTOUT PA3 - TIM2_CH4 TIM5_CH4 LPTIM5_ OUT TIM15_CH2 - - USART2_ RX - LCD_B2 OTG_HS_ ULPI_D0 ETH_MII_ COL - - LCD_B5 EVENTOUT PA4 - - TIM5_ETR - - SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS USART2_ CK SPI6_NSS - - - OTG_HS_ SOF DCMI_ HSYNC LCD_ VSYNC EVENTOUT PA5 - TIM2_CH1/ TIM2_ETR - TIM8_ CH1N - SPI1_SCK /I2S1_CK - - SPI6_SCK - OTG_HS_ ULPI_CK - - - LCD_R4 EVENTOUT PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO /I2S1_SDI - - SPI6_MISO TIM13_CH 1 TIM8_BKIN _COMP12 MDIOS_ MDC TIM1_BKIN _COMP12 DCMI_PIX CLK LCD_G2 EVENTOUT PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1 N - SPI1_MOSI /I2S1_SDO - - SPI6_MOSI TIM14_CH 1 - ETH_MII_ RX_DV/ ETH_RMII_ CRS_DV FMC_SDN WE - - EVENTOUT PA8 MCO1 TIM1_CH1 HRTIM_CH B2 TIM8_BKIN 2 I2C3_SCL - - USART1_ CK - - OTG_FS_ SOF UART7_RX TIM8_BKIN 2_COMP12 LCD_B3 LCD_R6 EVENTOUT PA9 - TIM1_CH2 HRTIM_CH C1 LPUART1_ TX I2C3_SMBA SPI2_SCK/ I2S2_CK - USART1_ TX - FDCAN1_ RXFD_ MODE - - - DCMI_D0 LCD_R5 EVENTOUT PA10 - TIM1_CH3 HRTIM_CH C2 LPUART1_ RX - - - USART1_ RX - FDCAN1_ TXFD_ MODE OTG_FS_ID MDIOS_ MDIO LCD_B4 DCMI_D1 LCD_B1 EVENTOUT PA11 - TIM1_CH4 HRTIM_CH D1 LPUART1_ CTS - SPI2_NSS /I2S2_WS UART4_RX USART1_ CTS_NSS - FDCAN1_ RX OTG_FS_ DM - - - LCD_R4 EVENTOUT PA12 - TIM1_ETR HRTIM_CH D2 LPUART1_ RTS - SPI2_SCK/ I2S2_CK UART4_TX USART1_ RTS SAI2_FS_B FDCAN1_ TX OTG_FS_ DP - - - LCD_R5 EVENTOUT PA13 JTMSSWDIO - - - - - - - - - - - - - - EVENTOUT DS12110 Rev 5 STM32H743xI SYS LPUART/ TIM8/ LPTIM2/3/4/ 5/HRTIM1/ DFSDM Port Port A AF1 Pin descriptions 82/231 Table 9. Port A alternate functions AF2 AF3 AF4 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4/ 5/HRTIM1/ DFSDM PA14 JTCKSWCLK - - PA15 JTDI TIM2_CH1/ TIM2_ETR HRTIM_ FLT1 Port A Port AF1 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1/ 3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/S PDIFRX SAI4/ FDCAN1/2/ TIM13/14/Q UADSPI/F MC/ SDMMC2/ LCD/ SPDIFRX SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS - - - - - - - - - - - - EVENTOUT - HDMI_CEC SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS SPI6_NSS UART4_ RTS - - UART7_TX - - - EVENTOUT STM32H743xI Table 9. Port A alternate functions (continued) AF0 Table 10. Port B alternate functions AF0 Port B DS12110 Rev 5 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/ CEC SPI1/2/3/4/5/ 6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/3 /6/UART7/S DMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCM I/LCD/ COMP UART5/ LCD SYS PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2 N - - DFSDM_CK OUT - UART4_ CTS LCD_R3 OTG_HS_ ULPI_D1 ETH_MII_ RXD2 - - LCD_G1 EVENTOUT PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3 N - - DFSDM_ DATIN1 - - LCD_R6 OTG_HS_ ULPI_D2 ETH_MII_ RXD3 - - LCD_G0 EVENTOUT PB2 - - SAI1_D1 - DFSDM_ CKIN1 - SAI1_SD_A SPI3_ MOSI/I2S3_ SDO SAI4_SD_ A QUADSPI_ CLK SAI4_D1 - - - - EVENTOUT PB3 JTDO/TRA CESWO TIM2_CH2 HRTIM_ FLT4 - - SPI1_SCK/ I2S1_CK SPI3_SCK/ I2S3_CK - SPI6_SCK SDMMC2_ D2 - UART7_RX - - - EVENTOUT PB4 NJTRST TIM16_ BKIN TIM3_CH1 HRTIM_EE V6 - SPI1_MISO/ I2S1_SDI SPI3_MISO/ I2S3_SDI SPI2_NSS/I 2S2_WS SPI6_ MISO SDMMC2_ D3 - UART7_TX - - - EVENTOUT PB5 - TIM17_ BKIN TIM3_CH2 HRTIM_ EEV7 I2C1_SMBA SPI1_MOSI/ I2S1_SDO I2C4_SMBA SPI3_MOSI/ I2S3_SDO SPI6_ MOSI FDCAN2_ RX OTG_HS_ ULPI_D7 ETH_PPS_ OUT FMC_ SDCKE1 DCMI_D1 0 UART5_ RX EVENTOUT PB6 - TIM16_CH1 N TIM4_CH1 HRTIM_ EEV8 I2C1_SCL HDMI_CEC I2C4_SCL USART1_ TX LPUART1_ TX FDCAN2_ TX QUADSPI_ BK1_NCS DFSDM_ DATIN5 FMC_SDNE 1 DCMI_D5 UART5_ TX EVENTOUT PB7 - TIM17_CH1 N TIM4_CH2 HRTIM_ EEV9 I2C1_SDA - I2C4_SDA USART1_ RX LPUART1_ RX FDCAN2_ TXFD_ MODE - DFSDM_ CKIN5 FMC_NL DCMI_ VSYNC - EVENTOUT PB8 - TIM16_CH1 TIM4_CH3 DFSDM_ CKIN7 I2C1_SCL - I2C4_SCL SDMMC1_ CKIN UART4_RX FDCAN1_ RX SDMMC2_ D4 ETH_MII_ TXD3 SDMMC1_ D4 DCMI_D6 LCD_B6 EVENTOUT Pin descriptions 83/231 AF5 Port AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/ CEC SPI1/2/3/4/5/ 6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/3 /6/UART7/S DMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCM I/LCD/ COMP UART5/ LCD SYS PB9 - TIM17_CH1 TIM4_CH4 DFSDM_ DATIN7 I2C1_SDA SPI2_NSS/ I2S2_WS I2C4_SDA SDMMC1_ CDIR UART4_TX FDCAN1_ TX SDMMC2_ D5 I2C4_SMB A SDMMC1_ D5 DCMI_D7 LCD_B7 EVENTOUT PB10 - TIM2_CH3 HRTIM_ SCOUT LPTIM2_IN 1 I2C2_SCL SPI2_SCK/ I2S2_CK DFSDM_ DATIN7 USART3_ TX - QUADSPI_ BK1_NCS OTG_HS_ ULPI_D3 ETH_MII_ RX_ER - - LCD_G4 EVENTOUT PB11 - TIM2_CH4 HRTIM_ SCIN LPTIM2_ ETR I2C2_SDA - DFSDM_ CKIN7 USART3_ RX - - OTG_HS_ ULPI_D4 ETH_MII_ TX_EN/ ETH_RMII_ TX_EN - - LCD_G5 EVENTOUT PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS/ I2S2_WS DFSDM_ DATIN1 USART3_ CK - FDCAN2_ RX OTG_HS_ ULPI_D5 ETH_MII_ TXD0/ETH_ RMII_TXD0 OTG_HS_ ID TIM1_ BKIN_ COMP12 UART5_ RX EVENTOUT PB13 - TIM1_CH1N - LPTIM2_ OUT - SPI2_SCK/ I2S2_CK DFSDM_CK IN1 USART3_ CTS_NSS - FDCAN2_ TX OTG_HS_ ULPI_D6 ETH_MII_ TXD1/ETH_ RMII_TXD1 - - UART5_ TX EVENTOUT PB14 - TIM1_CH2N TIM12_CH 1 TIM8_ CH2N USART1_TX SPI2_MISO/ I2S2_SDI DFSDM_ DATIN2 USART3_ RTS UART4_ RTS SDMMC2_ D0 - - OTG_HS_ DM - - EVENTOUT PB15 RTC_ REFIN TIM1_CH3N TIM12_CH 2 TIM8_CH3 N USART1_RX SPI2_MOSI/ I2S2_SDO DFSDM_CK IN2 - UART4_ CTS SDMMC2_ D1 - - OTG_HS_ DP - - EVENTOUT Port B Port AF1 Pin descriptions 84/231 Table 10. Port B alternate functions (continued) AF0 DS12110 Rev 5 STM32H743xI AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 PC0 - - - DFSDM_ CKIN0 - - DFSDM_ DATIN4 - SAI2_FS_B - OTG_HS_ ULPI_STP - FMC_ SDNWE - LCD_R5 EVENTOUT PC1 TRACED0 - SAI1_D1 DFSDM_ DATIN0 DFSDM_ CKIN4 SPI2_ MOSI/I2S2 _SDO SAI1_SD_A - SAI4_SD_ A SDMMC2_ CK SAI4_D1 ETH_MDC MDIOS_ MDC - - EVENTOUT PC2 - - - DFSDM_ CKIN1 - SPI2_ MISO/I2S2 _SDI DFSDM_CK OUT - - - OTG_HS_ ULPI_DIR ETH_MII_ TXD2 FMC_SDNE 0 - - EVENTOUT PC3 - - - DFSDM_ DATIN1 - SPI2_ MOSI/I2S2 _SDO - - - - OTG_HS_ ULPI_NXT ETH_MII_ TX_CLK FMC_SDCK E0 - - EVENTOUT PC4 - - - DFSDM_ CKIN2 - I2S1_MCK - - - SPDIFRX_ IN2 - ETH_MII_ RXD0/ETH_ RMII_RXD0 FMC_SDNE 0 - - EVENTOUT PC5 - - SAI1_D3 DFSDM_ DATIN2 - - - - SPDIFRX_ IN3 SAI4_D3 ETH_MII_ RXD1/ETH_ RMII_RXD1 FMC_SDCK E0 COMP_1_ OUT - EVENTOUT PC6 - HRTIM_CH A1 TIM3_CH1 TIM8_CH1 DFSDM_ CKIN3 I2S2_MCK - USART6_ TX SDMMC1_ D0DIR FMC_ NWAIT SDMMC2_ D6 - SDMMC1_ D6 DCMI_D0 LCD_ HSYNC EVENTOUT PC7 TRGIO HRTIM_CH A2 TIM3_CH2 TIM8_CH2 DFSDM_ DATIN3 - I2S3_MCK USART6_ RX SDMMC1_ D123DIR FMC_NE1 SDMMC2_ D7 SWPMI_TX SDMMC1_ D7 DCMI_D1 LCD_G6 EVENTOUT PC8 TRACED1 HRTIM_CH B1 TIM3_CH3 TIM8_CH3 - - - USART6_ CK UART5_ RTS FMC_NE2/ FMC_NCE - SWPMI_RX SDMMC1_ D0 DCMI_D2 - EVENTOUT PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - - UART5_ CTS QUADSPI_ BK1_IO0 LCD_G3 SWPMI_ SUSPEND SDMMC1_ D1 DCMI_D3 LCD_B2 EVENTOUT PC10 - - HRTIM_ EEV1 DFSDM_ CKIN5 - - SPI3_SCK/ I2S3_CK USART3_ TX UART4_TX QUADSPI_ BK1_IO1 - - SDMMC1_ D2 DCMI_D8 LCD_R2 EVENTOUT PC11 - - HRTIM_ FLT2 DFSDM_ DATIN5 - - SPI3_MISO/ I2S3_SDI USART3_ RX UART4_RX QUADSPI_ BK2_NCS - - SDMMC1_ D3 DCMI_D4 - EVENTOUT PC12 TRACED3 - HRTIM_ EEV2 - - - SPI3_MOSI/ I2S3_SDO USART3_ CK UART5_TX - - - SDMMC1_ CK DCMI_D9 - EVENTOUT PC13 - - - - - - - - - - - - - - - EVENTOUT DS12110 Rev 5 85/231 Pin descriptions SYS LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM Port Port C AF1 STM32H743xI Table 11. Port C alternate functions AF2 AF3 AF4 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PC14 - - - PC15 - - - Port C Port AF1 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS - - - - - - - - - - - - EVENTOUT - - - - - - - - - - - - EVENTOUT Pin descriptions 86/231 Table 11. Port C alternate functions (continued) AF0 DS12110 Rev 5 STM32H743xI AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/Q UADSPI/FM C/ SDMMC2/ LCD/ SPDIFRX TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 PD0 - - - DFSDM_ CKIN6 - - SAI3_SCK_ A - UART4_RX FDCAN1_ RX - - FMC_D2/ FMC_DA2 - - EVENTOUT PD1 - - - DFSDM_ DATIN6 - - SAI3_SD_A - UART4_TX FDCAN1_ TX - - FMC_D3/ FMC_DA3 - - EVENTOUT PD2 TRACED2 - TIM3_ETR - - - - - UART5_RX - - - SDMMC1_ CMD DCMI_D11 - EVENTOUT PD3 - - - DFSDM_ CKOUT - SPI2_SCK/ I2S2_CK - USART2_ CTS_NSS - - - - FMC_CLK DCMI_D5 LCD_G7 EVENTOUT PD4 - - HRTIM_ FLT3 - - - SAI3_FS_A USART2_ RTS - FDCAN1_R XFD_MODE - - FMC_NOE - - EVENTOUT PD5 - - HRTIM_ EEV3 - - - - USART2_ TX - FDCAN1_T XFD_MODE - - FMC_NWE - - EVENTOUT PD6 - - SAI1_D1 DFSDM_ CKIN4 DFSDM_ DATIN1 SPI3_ MOSI/I2S3 _SDO SAI1_SD_A USART2_ RX SAI4_SD_ A FDCAN2_R XFD_MODE SAI4_D1 SDMMC2_ CK FMC_ NWAIT DCMI_D10 LCD_B2 EVENTOUT PD7 - - - DFSDM_ DATIN4 - SPI1_ MOSI/I2S1 _SDO DFSDM_CK IN1 USART2_ CK - SPDIFRX_ IN0 - SDMMC2_ CMD FMC_NE1 - - EVENTOUT PD8 - - - DFSDM_ CKIN3 - - SAI3_SCK_ B USART3_ TX - SPDIFRX_ IN1 - - FMC_D13/ FMC_DA13 - - EVENTOUT PD9 - - - DFSDM_ DATIN3 - - SAI3_SD_B USART3_ RX - FDCAN2_R XFD_MODE - - FMC_D14/ FMC_DA14 - - EVENTOUT PD10 - - - DFSDM_ CKOUT - - SAI3_FS_B USART3_ CK - FDCAN2_T XFD_MODE - - FMC_D15/ FMC_DA15 - LCD_B3 EVENTOUT PD11 - - - LPTIM2_IN 2 I2C4_SMBA - - USART3_ CTS_NSS - QUADSPI_ BK1_IO0 SAI2_SD_A - FMC_A16 - - EVENTOUT PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN 1 I2C4_SCL - - USART3_ RTS - QUADSPI_ BK1_IO1 SAI2_FS_A - FMC_A17 - - EVENTOUT PD13 - LPTIM1_ OUT TIM4_CH2 - I2C4_SDA - - - QUADSPI_ BK1_IO3 SAI2_SCK_ A - FMC_A18 - - EVENTOUT PD14 - - TIM4_CH3 - - - SAI3_MCLK _B - UART8_ CTS - - - FMC_D0/ FMC_DA0 - - EVENTOUT PD15 - - TIM4_CH4 - - - SAI3_MCLK _A - UART8_ RTS - - - FMC_D1/ FMC_DA1 - - EVENTOUT DS12110 Rev 5 87/231 Pin descriptions SYS LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM Port Port D AF1 STM32H743xI Table 12. Port D alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 PE0 - LPTIM1_ ETR TIM4_ETR HRTIM_ SCIN LPTIM2_ ETR - - - UART8_RX FDCAN1_ RXFD_ MODE SAI2_MCK _A - FMC_NBL0 DCMI_D2 - EVENTOUT PE1 - LPTIM1_IN2 - HRTIM_ SCOUT - - - - UART8_TX FDCAN1_ TXFD_ MODE - - FMC_NBL1 DCMI_D3 - EVENTOUT PE2 TRACE CLK - SAI1_CK1 - - SPI4_SCK SAI1_MCLK _A - SAI4_ MCLK_A QUADSPI_ BK1_IO2 SAI4_CK1 ETH_MII_ TXD3 FMC_A23 - - EVENTOUT PE3 TRACED0 - - - TIM15_BKIN - SAI1_SD_B - SAI4_SD_ B - - - FMC_A19 - - EVENTOUT PE4 TRACED1 - SAI1_D2 DFSDM_ DATIN3 TIM15_CH1 N SPI4_NSS SAI1_FS_A - SAI4_FS_A - SAI4_D2 - FMC_A20 DCMI_D4 LCD_B0 EVENTOUT PE5 TRACED2 - SAI1_CK2 DFSDM_ CKIN3 TIM15_CH1 SPI4_ MISO SAI1_SCK_ A - SAI4_SCK _A - SAI4_CK2 - FMC_A21 DCMI_D6 LCD_G0 EVENTOUT PE6 TRACED3 TIM1_BKIN 2 SAI1_D1 - TIM15_CH2 SPI4_ MOSI SAI1_SD_A - SAI4_SD_ A SAI4_D1 SAI2_MCK _B TIM1_BKIN 2_COMP12 FMC_A22 DCMI_D7 LCD_G1 EVENTOUT PE7 - TIM1_ETR - DFSDM_ DATIN2 - - - UART7_RX - - QUADSPI_ BK2_IO0 - FMC_D4/ FMC_DA4 - - EVENTOUT PE8 - TIM1_CH1N - DFSDM_ CKIN2 - - - UART7_TX - - QUADSPI_ BK2_IO1 - FMC_D5/ FMC_DA5 COMP_2_ OUT - EVENTOUT PE9 - TIM1_CH1 - DFSDM_ CKOUT - - - UART7_ RTS - - QUADSPI_ BK2_IO2 - FMC_D6/ FMC_DA6 - - EVENTOUT PE10 - TIM1_CH2N - DFSDM_ DATIN4 - - - UART7_ CTS - - QUADSPI_ BK2_IO3 - FMC_D7/ FMC_DA7 - - EVENTOUT PE11 - TIM1_CH2 - DFSDM_ CKIN4 - SPI4_NSS - - - - SAI2_SD_B - FMC_D8/ FMC_DA8 - LCD_G3 EVENTOUT PE12 - TIM1_CH3N - DFSDM_ DATIN5 - SPI4_SCK - - - - SAI2_SCK_ B - FMC_D9/ FMC_DA9 COMP_1_ OUT LCD_B4 EVENTOUT PE13 - TIM1_CH3 - DFSDM_ CKIN5 - SPI4_ MISO - - - - SAI2_FS_B - FMC_D10/ FMC_DA10 COMP_2_ OUT LCD_DE EVENTOUT PE14 - TIM1_CH4 - - - SPI4_ MOSI - - - - SAI2_MCK _B - FMC_D11/ FMC_DA11 - LCD_CLK EVENTOUT PE15 - TIM1_BKIN - - - HDMI__ TIM1_BKIN - - - - - FMC_D12/ FMC_DA12 TIM1_BKIN _COMP12 LCD_R7 EVENTOUT DS12110 Rev 5 STM32H743xI SYS LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM Port Port E AF1 Pin descriptions 88/231 Table 13. Port E alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 - - EVENTOUT PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 - - EVENTOUT PF2 - - - - I2C2_SMBA - - - - - - - FMC_A2 - - EVENTOUT PF3 - - - - - - - - - - - - FMC_A3 - - EVENTOUT PF4 - - - - - - - - - - - - FMC_A4 - - EVENTOUT PF5 - - - - - - - - - - - - FMC_A5 - - EVENTOUT PF6 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B UART7_RX SAI4_SD_ B QUADSPI_ BK1_IO3 - - - - - EVENTOUT PF7 - TIM17_CH1 - - - SPI5_SCK SAI1_MCLK _B UART7_TX SAI4_ MCLK_B QUADSPI_ BK1_IO2 - - - - - EVENTOUT PF8 - TIM16_ CH1N - - - SPI5_ MISO SAI1_SCK_ B UART7_ RTS SAI4_SCK _B TIM13_ CH1 QUADSPI_ BK1_IO0 - - - - EVENTOUT PF9 - TIM17_ CH1N - - - SPI5_ MOSI SAI1_FS_B UART7_ CTS SAI4_FS_B TIM14_CH 1 QUADSPI_ BK1_IO1 - - - - EVENTOUT PF10 - TIM16_ BKIN SAI1_D3 - - - - - - QUADSPI_ CLK SAI4_D3 - - DCMI_D11 LCD_DE EVENTOUT PF11 - - - - - SPI5_ MOSI - - - - SAI2_SD_B - FMC_ SDNRAS DCMI_D12 - EVENTOUT PF12 - - - - - - - - - - - - FMC_A6 - - EVENTOUT PF13 - - - DFSDM_ DATIN6 I2C4_SMBA - - - - - - - FMC_A7 - - EVENTOUT PF14 - - - DFSDM_ CKIN6 I2C4_SCL - - - - - - - FMC_A8 - - EVENTOUT PF15 - - - - I2C4_SDA - - - - - - - FMC_A9 - - EVENTOUT DS12110 Rev 5 89/231 Pin descriptions SYS LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM Port Port F AF1 STM32H743xI Table 14. Port F alternate functions AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/UART7 /SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD /COMP UART5/ LCD SYS SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX - - - - - - - - FMC_A10 - - EVENT -OUT - - - - - - - - - FMC_A11 - - EVENT -OUT - TIM8_BKIN - - - - - - - TIM8_BKIN_ COMP12 FMC_A12 - - EVENT -OUT - - TIM8_ BKIN2 - - - - - - - TIM8_BKIN2 _COMP12 FMC_A13 - - EVENT -OUT - TIM1_BKIN 2 - - - - - - - - - TIM1_BKIN2 _COMP12 FMC_A14/ FMC_BA0 - - EVENT -OUT PG5 - TIM1_ETR - - - - - - - - - - FMC_A15/ FMC_BA1 - - EVENT -OUT PG6 - TIM17_ BKIN HRTIM_ CHE1 - - - - - - - QUADSPI_ BK1_NCS - FMC_NE3 DCMI_D1 2 LCD_R 7 EVENT -OUT PG7 - - HRTIM_ CHE2 - - - SAI1_ MCLK_A USART6_ CK - - - - FMC_INT DCMI_D1 3 LCD_ CLK EVENT -OUT PG8 - - - TIM8_ETR - SPI6_NSS - USART6_ RTS SPDIFRX_ IN2 - - ETH_PPS_ OUT FMC_ SDCLK - LCD_ G7 EVENT -OUT PG9 - - - - - SPI1_ MISO/I2S1 _SDI - USART6_ RX SPDIFRX_ IN3 QUADSPI_BK 2_IO2 SAI2_FS_B - FMC_NE2/ FMC_NCE DCMI_ VSYNC - EVENT -OUT PG10 - - HRTIM_ FLT5 - - SPI1_NSS/ I2S1_WS - - - LCD_G3 SAI2_SD_B - FMC_NE3 DCMI_D2 LCD_B 2 EVENT -OUT PG11 - - HRTIM_ EEV4 - - SPI1_SCK/ I2S1_CK - - SPDIFRX_ IN0 - SDMMC2_D2 ETH_MII_ TX_EN/ ETH_RMII_ TX_EN - DCMI_D3 LCD_B 3 EVENT -OUT PG12 - LPTIM1_IN1 HRTIM_ EEV5 - - SPI6_ MISO USART6_ RTS SPDIFRX_ IN1 LCD_B4 - ETH_MII_ TXD1/ETH_ RMII_TXD1 FMC_NE4 - LCD_ B1 EVENT -OUT PG13 TRACED0 LPTIM1_ OUT HRTIM_ EEV10 - - SPI6_SCK USART6_ CTS_NSS - - - ETH_MII_ TXD0/ETH_ RMII_TXD0 FMC_A24 - LCD_ R0 EVENT -OUT SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC PG0 - - - - PG1 - - - PG2 - - PG3 - PG4 DS12110 Rev 5 - STM32H743xI SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/SPDIFRX Port Port G AF1 Pin descriptions 90/231 Table 15. Port G alternate functions AF1 AF2 AF3 AF4 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PG14 TRACED1 LPTIM1_ ETR - PG15 - - - Port G Port AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/SPDIFRX SAI2/4/TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/UART7 /SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD /COMP UART5/ LCD SYS - - SPI6_ MOSI - USART6_ TX QUADSPI_ BK2_IO3 - ETH_MII_ TXD1/ETH_ RMII_TXD1 FMC_A25 - LCD_ B0 EVENT -OUT - - - - USART6_ CTS_NSS - - - FMC_ SDNCAS DCMI_ D13 - EVENT -OUT - STM32H743xI Table 15. Port G alternate functions (continued) AF0 DS12110 Rev 5 Pin descriptions 91/231 AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 PH0 - - - - - - - - - - - - - - - EVENTOUT PH1 - - - - - - - - - - - - - - - EVENTOUT PH2 - LPTIM1_IN2 - - - - - - - QUADSPI_ BK2_IO0 SAI2_SCK_ B ETH_MII_ CRS FMC_ SDCKE0 - LCD_R0 EVENTOUT PH3 - - - - - - - - - QUADSPI_ BK2_IO1 SAI2_MCK _B ETH_MII_ COL FMC_ SDNE0 - LCD_R1 EVENTOUT PH4 - - - - I2C2_SCL - - - - LCD_G5 OTG_HS_ ULPI_NXT - - - LCD_G4 EVENTOUT PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - FMC_ SDNWE - - EVENTOUT PH6 - - TIM12_ CH1 - I2C2_SMBA SPI5_SCK - - - - - ETH_MII_ RXD2 FMC_ SDNE1 DCMI_D8 - EVENTOUT PH7 - - - - I2C3_SCL SPI5_ MISO - - - - - ETH_MII_ RXD3 FMC_ SDCKE1 DCMI_D9 - EVENTOUT PH8 - - TIM5_ETR - I2C3_SDA - - - - - - - FMC_D16 DCMI_ HSYNC LCD_R2 EVENTOUT PH9 - - TIM12_ CH2 - I2C3_SMBA - - - - - - - FMC_D17 DCMI_D0 LCD_R3 EVENTOUT PH10 - - TIM5_CH1 - I2C4_SMBA - - - - - - - FMC_D18 DCMI_D1 LCD_R4 EVENTOUT PH11 - - TIM5_CH2 - I2C4_SCL - - - - - - - FMC_D19 DCMI_D2 LCD_R5 EVENTOUT PH12 - - TIM5_CH3 - I2C4_SDA - - - - - - - FMC_D20 DCMI_D3 LCD_R6 EVENTOUT PH13 - - - TIM8_ CH1N - - - - UART4_TX FDCAN1_ TX - - FMC_D21 - LCD_G2 EVENTOUT PH14 - - - TIM8_CH 2N - - - - UART4_RX FDCAN1_ RX - - FMC_D22 DCMI_D4 LCD_G3 EVENTOUT PH15 - - - TIM8_ CH3N - - - - - FDCAN1_ TXFD_ MODE - - FMC_D23 DCMI_D11 LCD_G4 EVENTOUT DS12110 Rev 5 STM32H743xI SYS LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM Port Port H AF1 Pin descriptions 92/231 Table 16. Port H alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 PI0 - - TIM5_CH4 - - SPI2_NSS/ I2S2_WS - - - FDCAN1_ RXFD_ MODE - - FMC_D24 DCMI_D13 LCD_G5 EVENTOUT PI1 - - - TIM8_BKIN 2 - SPI2_SCK/ I2S2_CK - - - - - TIM8_BKIN 2_COMP12 FMC_D25 DCMI_D8 LCD_G6 EVENTOUT PI2 - - - TIM8_CH4 - SPI2_ MISO/I2S2 _SDI - - - - - - FMC_D26 DCMI_D9 LCD_G7 EVENTOUT PI3 - - - TIM8_ETR - SPI2_ MOSI/I2S2 _SDO - - - - - - FMC_D27 DCMI_D10 - EVENTOUT PI4 - - - TIM8_BKIN - - - - - - SAI2_MCK _A TIM8_BKIN _COMP12 FMC_NBL2 DCMI_D5 LCD_B4 EVENTOUT PI5 - - - TIM8_CH1 - - - - - - SAI2_SCK_ A - FMC_NBL3 DCMI_ VSYNC LCD_B5 EVENTOUT PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 DCMI_D6 LCD_B6 EVENTOUT PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 DCMI_D7 LCD_B7 EVENTOUT PI8 - - - - - - - - - - - - - - - EVENTOUT PI9 - - - - - - - - UART4_RX FDCAN1_ RX - - FMC_D30 - LCD_ VSYNC EVENTOUT PI10 - - - - - - - - - FDCAN1_ RXFD_ MODE - ETH_MII_ RX_ER FMC_D31 - LCD_ HSYNC EVENTOUT PI11 - - - - - - - - - LCD_G6 OTG_HS_ ULPI_DIR - - - - EVENTOUT PI12 - - - - - - - - - - - - - - LCD_ HSYNC EVENTOUT PI13 - - - - - - - - - - - - - - LCD_ VSYNC EVENTOUT PI14 - - - - - - - - - - - - - - LCD_CLK EVENTOUT PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0 EVENTOUT DS12110 Rev 5 93/231 Pin descriptions SYS LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM Port Port I AF1 STM32H743xI Table 17. Port I alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1 EVENTOUT PJ1 - - - - - - - - - - - - - - LCD_R2 EVENTOUT PJ2 - - - - - - - - - - - - - - LCD_R3 EVENTOUT PJ3 - - - - - - - - - - - - - - LCD_R4 EVENTOUT PJ4 - - - - - - - - - - - - - - LCD_R5 EVENTOUT PJ5 - - - - - - - - - - - - - - LCD_R6 EVENTOUT PJ6 - - - TIM8_CH2 - - - - - - - - - - LCD_R7 EVENTOUT PJ7 TRGIN - - TIM8_ CH2N - - - - - - - - - - LCD_G0 EVENTOUT PJ8 - TIM1_CH3N - TIM8_CH1 - - - - UART8_TX - - - - - LCD_G1 EVENTOUT PJ9 - TIM1_CH3 - TIM8_ CH1N - - - - UART8_RX - - - - - LCD_G2 EVENTOUT PJ10 - TIM1_CH2N - TIM8_CH2 - SPI5_ MOSI - - - - - - - - LCD_G3 EVENTOUT PJ11 - TIM1_CH2 - TIM8_ CH2N - SPI5_ MISO - - - - - - - - LCD_G4 EVENTOUT PJ12 TRGOUT - - - - - - - - LCD_G3 - - - - LCD_B0 EVENTOUT PJ13 - - - - - - - - - LCD_B4 - - - - LCD_B1 EVENTOUT PJ14 - - - - - - - - - - - - - - LCD_B2 EVENTOUT PJ15 - - - - - - - - - - - - - - LCD_B3 EVENTOUT DS12110 Rev 5 STM32H743xI SYS LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM Port Port J AF1 Pin descriptions 94/231 Table 18. Port J alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ ETH TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD TIM1/DCMI /LCD/ COMP UART5/ LCD SYS SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1 SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PK0 - TIM1_CH1N - TIM8_CH3 - SPI5_SCK - - - - - - - - LCD_G5 EVENTOUT PK1 - TIM1_CH1 - TIM8_ CH3N - SPI5_NSS - - - - - - - - LCD_G6 EVENTOUT PK2 - TIM1_BKIN - TIM8_BKIN - - - - - - TIM8_BKIN _COMP12 TIM1_BKIN _COMP12 - - LCD_G7 EVENTOUT PK3 - - - - - - - - - - - - - - LCD_B4 EVENTOUT PK4 - - - - - - - - - - - - - - LCD_B5 EVENTOUT PK5 - - - - - - - - - - - - - - LCD_B6 EVENTOUT PK6 - - - - - - - - - - - - - - LCD_B7 EVENTOUT PK7 - - - - - - - - - - - - - - LCD_DE EVENTOUT Port Port K AF1 STM32H743xI Table 19. Port K alternate functions DS12110 Rev 5 Pin descriptions 95/231 Electrical characteristics 6 6.1 STM32H743xI Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 C and TJ = TJmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TJ = 25 C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 12. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 13. Figure 12. Pin loading conditions Figure 13. Pin input voltage 0&8SLQ 0&8SLQ & S) 9,1 069 96/231 DS12110 Rev 5 069 STM32H743xI 6.1.6 Electrical characteristics Power supply scheme 9''86% Q) Q) Figure 14. Power supply scheme 9''86% 9''86% 86% ,2V 86% UHJXODWRU 9''/'2 9&$3 /HYHOVKLIWHU ,2V 1 [Q) [) 'GRPDLQ SHULSKHUDOV 5$0 'GRPDLQ &38SHULSKHUDOV 5$0 9''GRPDLQ 9%$7 FKDUJLQJ +6,&6, +6, +6(3//V %DFNXSGRPDLQ %DFNXS 9%.3 UHJXODWRU 96: 9%$7 3RZHUVZLWFK 3RZHUVZLWFK /6,/6( 57&:DNHXS ORJLFEDFNXS ,2 UHJLVWHUV ORJLF 5HVHW %.83 ,2V 95() Q)[) Q)[) 9''$ 9''$ )ODVK 966 9'' 9%$7 WR9 'GRPDLQ 6\VWHP ORJLF (;7, ,2 ORJLF 3HULSKHUDOV 5$0 3RZHU VZLWFK 3RZHU VZLWFK 966 9'' 966 &RUHGRPDLQ9&25( 9ROWDJH UHJXODWRU 9''/'2 ) [) 966 9''86% 966 $QDORJGRPDLQ 5()B%8) 95() $'&'$& 95() 95() 95() %DFNXS 5$0 966 23$03 &RPSDUDWRU 966$ 06Y9 1. N corresponds to the number of VDD pins available on the package. 2. A tolerance of +/- 20% is acceptable on decoupling capacitors. Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the DS12110 Rev 5 97/231 199 Electrical characteristics STM32H743xI device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 6.1.7 Current consumption measurement Figure 15. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics, Table 21: Current characteristics, and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 20. Voltage characteristics (1) Symbols VDDX - VSS VIN(2) Ratings Min Max Unit -0.3 4.0 V Input voltage on FT_xxx pins VSS-0.3 Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4) V Input voltage on TT_xx pins VSS-0.3 4.0 V Input voltage on BOOT0 pin VSS 9.0 V VSS-0.3 4.0 V - 50 mV - 50 mV External main supply voltage (including VDD, VDDLDO, VDDA, VDD33USB, VBAT) Input voltage on any other pins |VDDX| Variations between different VDDX power pins of the same domain |VSSx-VSS| Variations between all the different ground pins 1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 58 for the maximum allowed injected current values. 3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. 4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled. 98/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Table 21. Current characteristics Symbols Ratings Max IVDD Total current into sum of all VDD power lines (source)(1) 620 IVSS (1) 620 Total current out of sum of all VSS ground lines (sink) IVDD (1) Maximum current into each VDD power pin (source) 100 IVSS Maximum current out of each VSS ground pin (sink)(1) 100 Output current sunk by any I/O and control pin IIO 20 (2) I(PIN) Total output current sunk by sum of all I/Os and control pins 140 Total output current sourced by sum of all I/Os and control pins(2) 140 Injected current on FT_xxx, TT_xx, RST and B pins except PA4, IINJ(PIN)(3)(4) PA5 Injected current on PA4, PA5 IINJ(PIN) Total injected current (sum of all I/Os and control Unit mA -5/+0 -0/0 pins)(5) 25 1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 22. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DS12110 Rev 5 Value - 65 to +150 125 Unit C 99/231 199 Electrical characteristics STM32H743xI 6.3 Operating conditions 6.3.1 General operating conditions Table 23. General operating conditions Symbol Parameter Operating conditions Min Max (1) 3.6 VDD Standard operating voltage - VDDLDO Supply voltage for the internal regulator VDDLDO VDD 1.62(1) 3.6 USB used 3.0 3.6 USB not used 0 3.6 ADC or COMP used 1.62 DAC used 1.8 OPAMP used 2.0 VREFBUF used 1.8 ADC, DAC, OPAMP, COMP, VREFBUF not used 0 TT_xx I/O -0.3 VDD+0.3 BOOT0 0 9 All I/O except BOOT0 and TT_xx -0.3 Min(VDD, VDDA, VDD33USB) +3.6V < 5.5V(2)(3) TFBGA240+25 - - 1093 LQFP208 - - 943 LQFP176 - - 930 UFBGA176+25 - - 1070 UFBGA169 - - 1061 LQFP144 - - 915 LQFP100 - - 889 TFBGA100 - - 1018 Ambient temperature for Maximum power dissipation the suffix 6 version Low-power dissipation(5) -40 85 -40 105 Ambient temperature for Maximum power dissipation the suffix 3 version Low-power dissipation(5) -40 125 -40 130 -40 125 VDD33USB Standard operating voltage, USB domain VDDA VIN PD TA TJ Analog operating voltage 1.62 I/O Input voltage Power dissipation at TA = 85 C for suffix 6(4) Junction temperature range Suffix 6 version 3.6 Unit V mW C C 1. When RESET is released functionality is guaranteed down to VBOR0 min 2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. 3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must be disabled. 100/231 DS12110 Rev 5 STM32H743xI Electrical characteristics 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.9: Thermal characteristics). 5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.9: Thermal characteristics). 6.3.2 VCAP external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 24. Two external capacitors can be connected to VCAP pins. Figure 16. External capacitor CEXT & (65 5/HDN 069 1. Legend: ESR is the equivalent series resistance. Table 24. VCAP operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 F(2) ESR ESR of external capacitor < 100 m 1. When bypassing the voltage regulator, the two 2.2 F VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated. 6.3.3 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 25. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD tVDDA tVDDUSB Parameter Min Max VDD rise time rate 0 VDD fall time rate 10 VDDA rise time rate 0 VDDA fall time rate 10 VDDUSB rise time rate 0 VDDUSB fall time rate 10 DS12110 Rev 5 Unit s/V 101/231 199 Electrical characteristics 6.3.4 STM32H743xI Embedded reset and power control block characteristics The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 26. Reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit tRSTTEMPO(1) Reset temporization after BOR0 released - - 377 - s VBOR0 Brown-out reset threshold 0 Rising edge(1) 1.62 1.67 1.71 Falling edge 1.58 1.62 1.68 VBOR1 Brown-out reset threshold 1 2.04 2.10 2.15 1.95 2.00 2.06 VBOR2 Brown-out reset threshold 2 2.34 2.41 2.47 2.25 2.31 2.37 VBOR3 Brown-out reset threshold 3 2.63 2.70 2.78 2.54 2.61 2.68 VPVD0 Programmable Voltage Detector threshold 0 Rising edge 1.90 1.96 2.01 1.81 1.86 1.91 VPVD1 Programmable Voltage Detector threshold 1 Rising edge 2.05 2.10 2.16 1.96 2.01 2.06 VPVD2 Programmable Voltage Detector threshold 2 Rising edge 2.19 2.26 2.32 2.10 2.15 2.21 VPVD3 Programmable Voltage Detector threshold 3 Rising edge 2.35 2.41 2.47 2.25 2.31 2.37 VPVD4 Programmable Voltage Detector threshold 4 Rising edge 2.49 2.56 2.62 2.39 2.45 2.51 VPVD5 Programmable Voltage Detector threshold 5 Rising edge 2.64 2.71 2.78 2.55 2.61 2.68 VPVD6 Programmable Voltage Detector threshold 6 Rising edge 2.78 2.86 2.94 2.69 2.76 2.83 Vhyst_BOR_PVD Hysteresis voltage of BOR (unless BOR0) and PVD Hysteresis in Run mode - 100 - mV IDD_BOR_PVD(1) BOR(2) (unless BOR0) and PVD consumption from VDD - - 0.630 A 102/231 Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge in Run mode DS12110 Rev 5 V STM32H743xI Electrical characteristics Table 26. Reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max VAVM_0 Analog voltage detector for VDDA threshold 0 Rising edge 1.66 1.71 1.76 1.56 1.61 1.66 VAVM_1 Analog voltage detector for VDDA threshold 1 Rising edge 2.06 2.12 2.19 1.96 2.02 2.08 VAVM_2 Analog voltage detector for VDDA threshold 2 Rising edge 2.42 2.50 2.58 2.35 2.42 2.49 VAVM_3 Analog voltage detector for VDDA threshold 3 Rising edge 2.74 2.83 2.91 2.64 2.72 2.80 Vhyst_VDDA Hysteresis of VDDA voltage detector - - 100 - mV IDD_PVM PVM consumption from VDD(1) - - - 0.25 A IDD_VDDA Voltage detector consumption on VDDA(1) - - 2.5 A Falling edge Falling edge Falling edge Falling edge Resistor bridge Unit V 1. Guaranteed by design. 2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to Section 6.3.6: Supply current characteristics). 6.3.5 Embedded reference voltage The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 27. Embedded reference voltage Symbol VREFINT tS_vrefint(1)(2) tS_vbat(1)(2) Irefbuf(2) VREFINT(2) Tcoeff(2) VDDcoeff(2) Parameter Conditions Min Typ Max Unit -40C < TJ < 105C, VDD = 3.3 V 1.180 1.216 1.255 V ADC sampling time when reading the internal reference voltage - 4.3 - - VBAT sampling time when reading the internal VBAT reference voltage - 9 - - VDDA=3.3 V 9 13.5 23 A -40C < TJ < 105C - 5 15 mV Average temperature coefficient - 20 70 ppm/C 3.0V < VDD < 3.6V - 10 1370 ppm/V Internal reference voltages Reference Buffer consumption for ADC Internal reference voltage spread over the temperature range Average temperature coefficient Average Voltage coefficient s DS12110 Rev 5 103/231 199 Electrical characteristics STM32H743xI Table 27. Embedded reference voltage (continued) Symbol Parameter Conditions Min Typ Max VREFINT_DIV1 1/4 reference voltage - - 25 - VREFINT_DIV2 1/2 reference voltage - - 50 - VREFINT_DIV3 3/4 reference voltage - - 75 - 1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. Unit % VREFINT Table 28. Internal reference voltage calibration values Symbol Parameter Raw data acquired at temperature of 30 C, VDDA = 3.3 V VREFIN_CAL 6.3.6 Memory address 1FF1E860 - 1FF1E861 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 15: Current consumption measurement scheme. All the run-mode current consumption measurements given in this section are performed with a CoreMark code. Typical and maximum current consumption The MCU is placed under the following conditions: All I/O pins are in analog input mode. All peripherals are disabled except when explicitly mentioned. The Flash memory access time is adjusted with the minimum wait states number, depending on the fACLK frequency (refer to the table "Number of wait states according to CPU clock (frcc_c_ck) frequency and VCORE range" available in the reference manual). When the peripherals are enabled, the AHB clock frequency is the CPU frequency divided by 2 and the APB clock frequency is AHB clock frequency divided by 2. The parameters given in Table 29 to Table 37 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. 104/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Table 29. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator ON(1) Symbol Parameter Conditions VOS1 VOS2 All peripherals disabled IDD Supply current in Run mode VOS3 VOS1 All peripherals VOS2 enabled VOS3 Max(2) frcc_c_ck (MHz) Typ TJ = 25C TJ = 85C TJ = 105C TJ = 125C 400 71 110 210 290 540 300 56 - - - - 300 50 72 170 230 370 216 37 58 150 210 380 200 35.5 - - - - 200 33 50 130 190 300 180 30 47 130 180 290 168 28 45 130 180 290 144 25 41 120 180 290 60 13 28 110 160 280 25 10 24 99 160 270 400 165 220(3) 400 500(3) 840 300 130 - - - - 300 120 170 300 390 570 200 83 - - - - 200 78 110 220 300 470 unit mA 1. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 2. Guaranteed by characterization results unless otherwise specified. 3. Guaranteed by test in production. DS12110 Rev 5 105/231 199 Electrical characteristics STM32H743xI Table 30. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON, regulator ON Symbol Parameter Conditions VOS1 VOS2 All peripherals disabled IDD Supply current in Run mode VOS3 VOS1 All peripherals VOS2 enabled VOS3 Max(1) frcc_c_ck (MHz) Typ TJ = 25C TJ = 85C TJ = 105C TJ = 125C 400 105 160 310 420 750 300 55 - - - - 300 50 72 160 230 370 216 38 - - - - 200 36 - - - - 200 33 50 130 190 300 180 30 - - - - 168 29 - - - - 144 26 - - - - 60 14 - - - - 25 14 - - - - 400 160 220 400 500 750 300 130 - - - - 300 120 160 300 390 560 200 81 - - - - 200 77 110 220 300 460 unit mA 1. Guaranteed by characterization results unless otherwise specified. Table 31. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache OFF, regulator ON Symbol IDD Parameter Supply current in Run mode Conditions Max(1) frcc_c_ck (MHz) Typ TJ = 25C TJ = 85C TJ = 105C TJ = 125C VOS1 All peripherals VOS2 disabled VOS3 400 73 110 220 290 540 300 52 75 170 230 370 200 34 52 130 190 300 VOS1 400 135 190 360 470 730 300 100 150 270 370 550 200 70 100 210 300 460 All peripherals VOS2 enabled VOS3 1. Guaranteed by characterization results. 106/231 DS12110 Rev 5 unit mA STM32H743xI Electrical characteristics Table 32. Typical consumption in Run mode and corresponding performance versus code position Symbol Parameter Conditions All peripherals disabled, cache ON Supply current in Run mode IDD Code frcc_c_ck (MHz) CoreMark Typ ITCM 400 2012 71 35 FLASH A 400 2012 105 52 AXI SRAM 400 2012 105 52 SRAM1 400 2012 105 52 SRAM4 400 2012 105 ITCM 400 2012 71 FLASH A 400 593 70.5 119 AXI SRAM 400 344 70.5 205 SRAM1 400 472 74.5 158 SRAM4 400 432 72 167 Peripheral All peripherals disabled cache OFF Unit IDD/ CoreMark 52 mA Unit A/ CoreMark 35 Table 33. Typical current consumption batch acquisition mode Symbol Parameter IDD Supply current in batch acquisition mode Conditions D1Standby, D2Standby, D3Run VOS3 D1Stop, D2Stop, D3Run VOS3 frcc_ahb_ck(AHB4) (MHz) Typ 64 6.5 unit mA 64 12 Table 34. Typical and maximum current consumption in Sleep mode, regulator ON Symbol Parameter Conditions VOS1 IDD(Sleep) Supply current in Sleep mode All peripherals VOS2 disabled VOS3 Max(1) frcc_c_ck (MHz) Typ TJ = 25C TJ = 85C TJ = 105C TJ = 125C 400 31.0 64 220 330 660 300 24.5 57 210 330 650 300 22.0 48 180 270 500 200 17.0 42 170 270 490 200 15.5 37 150 230 400 unit mA 1. Guaranteed by characterization results. DS12110 Rev 5 107/231 199 Electrical characteristics STM32H743xI Table 35. Typical and maximum current consumption in Stop mode, regulator ON Max(1) Symbol Parameter Flash memory in low-power mode, no IWDG D1Stop, D2Stop, D3Stop IDD(Stop) Conditions Flash memory ON, no IWDG D1Stop, D2Standby, D3Stop Flash memory OFF, no IWDG Flash memory ON, no IWDG D1Standby, D2Stop, D3Stop Flash OFF, no IWDG D1Standby, D2Standby, D3Stop Typ TJ = 25C TJ = 85C TJ = 105C TJ = 125C SVOS5 1.4 7.2(2) 49 75(2) 140 SVOS4 1.95 11 66 110 200 SVOS3 2.85 16(2) 91 150(2) 240 SVOS5 1.65 7.2 49 75 140 SVOS4 2.2 11 66 110 180 SVOS3 3.15 16 91 150 300 SVOS5 0.99 5.1 35 60 97 SVOS4 1.4 7.5 47 79 130 SVOS3 2.05 12 64 110 170 SVOS5 1.25 5.5 35 61 98 SVOS4 1.65 7.8 47 80 130 SVOS3 2.3 12 65 110 170 SVOS5 0.57 3 21 36 57 SVOS4 0.805 4.5 27 47 74 SVOS3 1.2 6.7 37 63 99 8 13(2) 20 1.1 (2) SVOS5 0.17 SVOS4 0.245 1.5 11 17 26 SVOS3 0.405 2.4(2) 15 23(2) 35 unit mA 1. Guaranteed by characterization results. 2. Guaranteed by test in production. Table 36. Typical and maximum current consumption in Standby mode Typ(3) Conditions Symbol IDD (Standby) Parameter Supply current in Standby mode Backup SRAM RTC 1.62 V & LSE Max (3 V)(1) 2.4 V 3V 3.3 V TJ = 25C TJ = 85C TJ = TJ = 105C 125C OFF OFF 1.8 1.9 1.95 2.05 4(2) 18(3) 40(2) 90(3) ON OFF 3.4 3.4 3.5 3.7 8.2(3) 47(3) 83(3) 141(3) OFF ON 2.4 3.5 3.86 4.12 - - - - ON ON 3.95 5.1 5.46 5.97 - - - - 1. The maximum current consumption values are given for PDR OFF (internal reset OFF). When the PDR is OFF (internal reset OFF), the current consumption is reduced by 1.2 A compared to PDR ON. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. 108/231 DS12110 Rev 5 Unit A STM32H743xI Electrical characteristics Table 37. Typical and maximum current consumption in VBAT mode Typ(1) Conditions Symbol IDD (VBAT) Parameter Supply current in standby mode Backup SRAM RTC & LSE 1.2 V OFF OFF 0.024 ON OFF 1.4 1.6 1.8 OFF ON 0.24 0.45 ON ON 1.97 2.37 Max (3 V) TJ = 25C TJ = 85C 0.035 0.062 0.096 0.5(1) 4.1(1) 10(1) 24(1) 1.8 4.4(1) 22(1) 48(1) 87(1) 0.62 0.73 - - - - 2.57 2.77 - - - - 2V 3V 3.4 V TJ = TJ = 105C 125C Unit A 1. Guaranteed by characterization results. I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 59: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (see Table 38: Peripheral current consumption in Run mode), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDx f SW C L where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDx is the MCU supply voltage fSW is the I/O switching frequency CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT DS12110 Rev 5 109/231 199 Electrical characteristics STM32H743xI The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. On-chip peripheral current consumption The MCU is placed under the following conditions: At startup, all I/O pins are in analog input configuration. All peripherals are disabled unless otherwise mentioned. The I/O compensation cell is enabled. frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2. The given value is calculated by measuring the difference of current consumption 110/231 - with all peripherals clocked off - with only one peripheral clocked on - frcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz (Scale 2), frcc_c_ck = 200 MHz (Scale 3) The ambient operating temperature is 25 C and VDD=3.3 V. DS12110 Rev 5 STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode IDD(Typ) Peripheral AHB3 Unit VOS1 VOS2 VOS3 MDMA 8.3 7.6 7 DMA2D 21 20 18 JPEG 24 23 21 FLASH 9.9 9 8.3 FMC registers 0.9 0.9 0.8 FMC kernel 6.1 5.5 5.3 QUADSPI registers 1.5 1.4 1.3 QUADSPI kernel 0.9 0.8 0.7 SDMMC1 registers 8 7.2 6.8 SDMMC1 kernel 2.4 2 1.8 DTCM1 5.7 5 4.5 DTCM2 5.5 4.8 4.3 ITCM 3.2 2.9 2.6 D1SRAM1 7.6 6.8 6.1 Bridge AHB3 7.5 6.8 6.3 DMA1 1.1 1 1 DMA2 1.7 1.4 1.1 ADC1/2 registers 3.9 3.2 3.1 ADC1/2 kernel 0.9 0.8 0.7 ART 5.5 4.5 4.2 16 14 13 USB1OTG registers 15 14 13 USB1OTG kernel - 8.5 8.5 USB1ULPI 0.3 0.3 0.1 USB2OTG registers 15 13 12 USB2OTG kernel - 8.6 8.6 USB2ULPI 16 16 16 Bridge AHB1 10 9.6 8.6 A/MHz ETH1MAC ETH1TX ETH1RX AHB1 DS12110 Rev 5 111/231 199 Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral AHB2 AHB4 APB3 112/231 Unit VOS1 VOS2 VOS3 DCMI 1.7 1.7 1.7 RNG registers 1.8 1.4 1.2 RNG kernel - 9.6 9.6 SDMMC2 registers 13 12 11 SDMMC2 kernel 2.7 2.5 2.4 D2SRAM1 3.3 3.1 2.8 D2SRAM2 2.9 2.7 2.5 D2SRAM3 1.9 1.8 1.7 Bridge AHB2 0.1 0.1 0.1 GPIOA 1.1 1 0.9 GPIOB 1 0.9 0.9 GPIOC 1.4 1.3 1.3 GPIOD 1.1 1 0.9 GPIOE 1 0.9 0.8 GPIOF 0.9 0.8 0.8 GPIOG 0.9 0.7 0.7 GPIOH 1 0.9 0.9 GPIOI 0.9 0.9 0.8 GPIOJ 0.9 0.8 0.8 GPIOK 0.9 0.8 0.7 CRC 0.5 0.4 0.4 BDMA 6.2 5.8 5.5 ADC3 registers 1.8 1.7 1.7 ADC3 kernel 0.1 0.1 0.1 Backup SRAM 1.9 1.8 1.8 Bridge AHB4 0.1 0.1 0.1 LCD-TFT 12 11 10 WWDG1 0.5 0.4 0.3 Bridge APB3 0.5 0.2 0.1 DS12110 Rev 5 A/MHz A/MHz STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB1 Unit VOS1 VOS2 VOS3 TIM2 3.5 3.2 2.9 TIM3 3.4 3.1 2.7 TIM4 2.7 2.5 1.9 TIM5 3.2 2.9 2.5 TIM6 1 0.8 0.7 TIM7 1 0.9 0.7 TIM12 1.7 1.5 1.2 TIM13 1.5 1.3 1 TIM14 1.4 1.3 0.9 LPTIM1 registers 0.7 0.6 0.5 LPTIM1 kernel 2.3 2.1 1.9 WWDG2 0.6 0.4 0.4 SPI2 registers 1.8 1.5 1.2 SPI2 kernel 0.6 0.5 0.5 SPI3 registers 1.5 1.3 1.1 SPI3 kernel 0.6 0.5 0.5 SPDIFRX registers 0.6 0.5 0.3 SPDIFRX kernel 2.9 2.4 2.4 USART2 registers 1.4 1.3 1 USART2 kernel 4.7 4.1 4 USART3 registers 1.4 1.3 1 USART3 kernel 4.2 3.8 3.5 UART4 registers 1.5 1.1 1 UART4 kernel 3.7 3.6 3.2 DS12110 Rev 5 A/MHz 113/231 199 Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB1 (continued) 114/231 Unit VOS1 VOS2 VOS3 UART5 registers 1.4 1.4 1 UART5 kernel 3.6 3.2 3.1 I2C1 registers 0.8 0.8 0.6 I2C1 kernel 2 1.8 1.7 I2C2 registers 0.7 0.7 0.4 I2C2 kernel 1.9 1.7 1.6 I2C3 registers 0.9 0.7 0.6 I2C3 kernel 2.1 1.9 1.9 HDMI-CEC registers 0.5 0.3 0.3 DAC1/2 1.4 1.1 0.9 USART7 registers 1.9 1.8 1.3 USART7 kernel 4 3.5 3.3 USART8 registers 1.6 1.5 1.2 USART8 kernel 4 3.6 3.3 CRS 3.4 3.1 2.9 SWPMI registers 2.3 2 2 SWPMI kernel 0.1 0.1 0.1 OPAMP 0.5 0.4 0.4 MDIO 2.7 2.4 2.3 FDCAN registers 16 15 14 FDCAN kernel 7.8 7.6 7.1 Bridge APB1 0.1 0.1 0.1 DS12110 Rev 5 A/MHz STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB2 Unit VOS1 VOS2 VOS3 TIM1 5.1 4.8 4.3 TIM8 5.4 4.9 4.6 USART1 registers 2.7 2.6 2.5 USART1 kernel 0.1 0.1 0.1 USART6 registers 2.6 2.5 2.5 USART6 kernel 0.1 0.1 0.1 SPI1 registers 1.8 1.6 1.6 SPI1 kernel 1 0.8 0.6 SPI4 registers 1.6 1.5 1.5 SPI4 kernel 0.5 0.4 0.4 TIM15 3.1 2.8 2.7 TIM16 2.4 2.1 2.1 TIM17 2.2 2 1.9 SPI5 registers 1.8 1.7 1.7 SPI5 kernel 0.6 0.5 0.3 SAI1 registers 1.5 1.4 1.4 SAI1 kernel 2 1.7 1.5 SAI2 registers 1.5 1.5 1.3 SAI2 kernel 2.2 1.9 1.8 SAI3 registers 1.8 1.6 1.6 SAI3 kernel 2.5 2.3 2.1 DFSDM1 registers 6 5.4 5.2 DFSDM1 kernel 0.9 0.8 0.7 HRTIM 40 37 35 Bridge APB2 0.1 0.1 0.1 DS12110 Rev 5 A/MHz 115/231 199 Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB4 Unit VOS1 VOS2 VOS3 SYSCFG 1 0.7 0.7 LPUART1 registers 1.1 1.1 1.1 LPUART1 kernel 2.6 2.4 2.1 SPI6 registers 1.6 1.5 1.4 SPI6 kernel 0.2 0.2 0.2 I2C4 registers 0.1 0.1 0.1 I2C4 kernel 2.4 2.1 2 LPTIM2 registers 0.5 0.5 0.5 LPTIM2 kernel 2.3 2.1 1.8 LPTIM3 registers 0.5 0.5 0.5 LPTIM3 kernel 2 2.1 1.5 LPTIM4 registers 0.5 0.5 0.5 LPTIM4 kernel 2 2 1.9 LPTIM5 registers 0.5 0.5 0.5 LPTIM5 kernel 2 1.8 1.5 COMP1/2 0.7 0.5 0.5 VREFBUF 0.6 0.4 0.4 RTC 1.2 1.1 1.1 SAI4 registers 1.6 1.5 1.4 SAI4 kernel 1.3 1.3 1.2 Bridge APB4 0.1 0.1 0.1 A/MHz Table 39. Peripheral current consumption in Stop, Standby and VBAT mode Symbol IDD 116/231 Typ Parameter Conditions RTC+LSE low drive - 2.32 RTC+LSE mediumlow drive - 2.4 RTC+LSE mediumhigh drive - 2.7 RTC+LSE High drive - 3 DS12110 Rev 5 3V Unit A STM32H743xI 6.3.7 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 40 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: For Stop or Sleep modes: the wakeup event is WFE. WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 40. Low-power mode wakeup timings Symbol Parameter Conditions Typ(1) Max(1) Unit tWUSLEEP(2) Wakeup from Sleep - 9 10 CPU clock cycles VOS3, HSI, Flash memory in normal mode 4.4 5.6 VOS3, HSI, Flash memory in low-power mode 12 15 VOS4, HSI, Flash memory in normal mode 15 20 VOS4, HSI, Flash memory in low-power mode 23 28 VOS5, HSI, Flash memory in normal mode 30 71 VOS5, HSI, Flash memory in low-power mode 38 47 VOS3, CSI, Flash memory in normal mode 27 37 VOS3, CSI, Flash memory in low power mode 36 50 VOS4, CSI, Flash memory in normal mode 38 48 VOS4, CSI, Flash memory in low-power mode 47 61 VOS5, CSI, Flash memory in normal mode 52 64 VOS5, CSI, Flash memory in low-power mode 62 77 VOS3, HSI, Flash memory in normal mode 2.6 3.4 VOS3, CSI, Flash memory in normal mode 26 36 - 390 500 tWUSTOP (2) Wakeup from Stop tWUSTOP2(2) Wakeup from Stop, clock kept running tWUSTDBY(2) Wakeup from Standby mode s 1. Guaranteed by characterization results. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. DS12110 Rev 5 117/231 199 Electrical characteristics 6.3.8 STM32H743xI External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 59: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 17. Table 41. High-speed external user clock characteristics(1) Symbol Parameter Min Typ Max Unit fHSE_ext User external clock source frequency 4 25 50 MHz 0.7VDD - VDD VSS - 0.3VSS 7 - - VSW OSC_IN amplitude (VHSEH - VHSEL) VDC OSC_IN input voltage tW(HSE) OSC_IN high or low time V ns 1. Guaranteed by design. Figure 17. High-speed external clock source AC timing diagram 9+6(+ 9+6(/ WU+6( WI+6( W:+6( W W:+6( 7+6( ([WHUQDO FORFNVRXUFH I+6(BH[W 26&B,1 ,/ 670 DLE 118/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 59: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 18. Table 42. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) V ns 1. Guaranteed by design. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 18. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU/6( WI/6( W:/6( 26&B,1 ,/ W:/6( W 7/6( ([WHUQDO FORFNVRXUFH I/6(BH[W 670 DLE DS12110 Rev 5 119/231 199 Electrical characteristics STM32H743xI High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 43. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 43. 4-48 MHz HSE oscillator characteristics(1) Symbol Parameter Operating conditions(2) Min Typ Max Unit F Oscillator frequency - 4 - 48 MHz RF Feedback resistor - - 200 - k During startup(3) - - 4 VDD=3 V, Rm=30 CL=10pF@4MHz - 0.35 - VDD=3 V, Rm=30 CL=10 pF at 8 MHz - 0.40 - VDD=3 V, Rm=30 CL=10 pF at 16 MHz - 0.45 - VDD=3 V, Rm=30 CL=10 pF at 32 MHz - 0.65 - VDD=3 V, Rm=30 CL=10 pF at 48 MHz - 0.95 - IDD(HSE) HSE current consumption mA Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V tSU(4) Start-up time VDD is stabilized - 2 - ms 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 19). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: 120/231 For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DS12110 Rev 5 STM32H743xI Electrical characteristics Figure 19. Typical application with an 8 MHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ 0+] UHVRQDWRU &/ I+6( 26&B,1 5(;7 5) %LDV FRQWUROOHG JDLQ 26&B28 7 670 DLE 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 44. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 44. Low-speed external user clock characteristics(1) Symbol Parameter Operating conditions(2) Min Typ Max Unit F Oscillator frequency - - 32.768 - kHz LSEDRV[1:0] = 00, Low drive capability - 290 - LSEDRV[1:0] = 01, Medium Low drive capability - 390 - LSEDRV[1:0] = 10, Medium high drive capability - 550 - LSEDRV[1:0] = 11, High drive capability - 900 - LSEDRV[1:0] = 00, Low drive capability - - 0.5 LSEDRV[1:0] = 01, Medium Low drive capability - - 0.75 LSEDRV[1:0] = 10, Medium high drive capability - - 1.7 LSEDRV[1:0] = 11, High drive capability - - 2.7 VDD is stabilized - 2 - IDD Gmcritmax tSU(3) LSE current consumption Maximum critical crystal gm Startup time nA A/V s 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers. 3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. DS12110 Rev 5 121/231 199 Electrical characteristics Note: STM32H743xI For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 20. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ I/6( 26&B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26&B28 7 &/ 670 DLE 1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.9 Internal clock source characteristics The parameters given in Table 45 and Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. 48 MHz high-speed internal RC oscillator (HSI48) Table 45. HSI48 oscillator characteristics Symbol fHSI48 TRIM(2) Parameter HSI48 frequency Conditions Min Typ Max Unit VDD=3.3 V, TJ=30 C 47.7(1) 48 48.3(1) MHz - - 0.17 - % 32 steps - 5.45 - % - 45 - 55 % % USER trimming step USER TRIM COVERAGE(3) USER TRIMMING Coverage DuCy(HSI48)(2) Duty Cycle ACCHSI48_REL(3) Accuracy of the HSI48 oscillator over temperature (factory calibrated) VDD=1.62 to 3.6 V, TJ=-40 to 125 C -4.5 - 3.5 DVDD(HSI48)(3) HSI48 oscillator frequency drift with VDD(4) VDD=3 to 3.6 V - 0.025 0.05 VDD=1.62 V to 3.6 V - 0.05 0.1 % tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 3.5 s IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 A NT jitter Next transition jitter Accumulated jitter on 28 cycles(5) - - 0.15 - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(5) - - 0.25 - ns 1. Guaranteed by test in production. 2. Guaranteed by design. 3. Guaranteed by characterization. 4. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) / Freq(1.62V). 122/231 DS12110 Rev 5 STM32H743xI Electrical characteristics 5. Jitter measurements are performed without clock source activated in parallel. 64 MHz high-speed internal RC oscillator (HSI) Table 46. HSI oscillator characteristics(1) Symbol Parameter HSI frequency fHSI TRIM HSI user trimming step DuCy(HSI) Duty Cycle VDD (HSI) HSI oscillator frequency drift over VDD (reference is 3.3 V) TEMP (HSI) HSI oscillator frequency drift over temperature (reference is 64 MHz) tsu(HSI) HSI oscillator start-up time tstab(HSI) HSI oscillator stabilization time IDD(HSI) HSI oscillator power consumption Conditions Min Typ Max Unit VDD=3.3 V, TJ=30 C 63.7(2) 64 64.3(2) MHz Trimming is not a multiple of 32 - 0.24 0.32 Trimming is 128, 256 and 384 -5.2 -1.8 - Trimming is 64, 192, 320 and 448 -1.4 -0.8 - Other trimming are a multiple of 32 (not including multiple of 64 and 128) -0.6 -0.25 - - 45 - 55 % VDD=1.62 to 3.6 V -0.12 - 0.03 % TJ=-20 to 105 C -1(3) - 1(3) % TJ=-40 to TJmax C -2(3) - 1(3) - - 1.4 2 s at 1% of target frequency - - 4 s - - 300 400 A % 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization. 4 MHz low-power internal RC oscillator (CSI) Table 47. CSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fCSI CSI frequency VDD=3.3 V, TJ=30 C 3.96(2) 4 4.04(2) MHz TRIM Trimming step - - 0.35 - % Duty Cycle - 45 - 55 % TJ = 0 to 85 C - -3.7(3) 4.5(3) TJ = -40 to 125 C - -11(3) 7.5(3) VDD = 1.62 to 3.6 V - -0.06 0.06 % - - 1 2 s DuCy(CSI) TEMP (CSI) CSI oscillator frequency drift over temperature DVDD (CSI) CSI oscillator frequency drift over VDD tsu(CSI) CSI oscillator startup time DS12110 Rev 5 % 123/231 199 Electrical characteristics STM32H743xI Table 47. CSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit tstab(CSI) CSI oscillator stabilization time (to reach 3% of fCSI) - - - 4 cycle IDD(CSI) CSI oscillator power consumption - - 23 30 A Min Typ Max Unit VDD = 3.3 V, TJ = 25 C (after calibration) 31.4 32 32.6 TJ = -40 to 105 C, VDD = 1.62 to 3.6 V 29.76 - 33.60 1. Guaranteed by design. 2. Guaranteed by test in production. 3. Guaranteed by characterization. Low-speed internal (LSI) RC oscillator Table 48. LSI oscillator characteristics Symbol fLSI(1) Parameter Conditions LSI frequency kHz tsu(LSI)(2) LSI oscillator startup time - - 80 130 tstab(LSI)(2) LSI oscillator stabilization time (5% of final value) - - 120 170 IDD(LSI)(2) LSI oscillator power consumption - - 130 280 s nA 1. Guaranteed by characterization results. 2. Guaranteed by design. 6.3.10 PLL characteristics The parameters given in Table 49 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 49. PLL characteristics (wide VCO frequency range)(1) Symbol fPLL_IN fPLL_P_OUT fPLL_Q_OUT fVCO_OUT 124/231 Parameter Conditions Min Typ Max Unit PLL input clock - 2 - 16 MHz PLL input clock duty cycle - 10 - 90 % Voltage scaling range 1 1.5 - 400(2) Voltage scaling range 2 1.5 - 300 Voltage scaling range 3 1.5 - 200 Voltage scaling range 1 1.5 - 400(2) Voltage scaling range 2 1.5 - 300 Voltage scaling range 3 1.5 - 200 - 192 - 836 PLL multiplier output clock P PLL multiplier output clock Q/R PLL VCO output DS12110 Rev 5 MHz STM32H743xI Electrical characteristics Table 49. PLL characteristics (wide VCO frequency range)(1) (continued) Symbol tLOCK Parameter PLL lock time Cycle-to-cycle jitter Jitter Long term jitter IDD(PLL)(3) Conditions Typ Max (3) Unit (3) 150 Normal mode - 50 Sigma-delta mode (CKIN 8 MHz) - 58(3) 166(3) VCO = 192 MHz - 134 - VCO = 200 MHz - 134 - VCO = 400 MHz - 76 - VCO = 800 MHz - 39 - Normal mode - 0.7 - Sigma-delta mode (CKIN = 16 MHz) - 0.8 - VDDA - 590 1500 VCORE - 720 - VDDA - 180 600 VCORE - 280 - VCO freq = 836 MHz PLL power consumption on VDD Min VCO freq = 192 MHz s ps % A 1. Guaranteed by design unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation (400 MHz for VOS1, 300 MHz for VOS2, 200 MHz for VOS3). 3. Guaranteed by characterization results. Table 50. PLL characteristics (medium VCO frequency range)(1) Symbol fPLL_IN fPLL_OUT fVCO_OUT tLOCK Parameter Conditions Min Typ Max Unit PLL input clock - 1 - 2 MHz PLL input clock duty cycle - 10 - 90 % Voltage scaling Range 1 1.17 - 210 Voltage scaling Range 2 1.17 - 210 Voltage scaling Range 3 1.17 - 200 - 150 - 420 Normal mode - 60(2) Sigma-delta mode forbidden - PLL multiplier output clock P, Q, R PLL VCO output PLL lock time DS12110 Rev 5 (2) MHz MHz 100 s - s 125/231 199 Electrical characteristics STM32H743xI Table 50. PLL characteristics (medium VCO frequency range)(1) (continued) Symbol Parameter Cycle-to-cycle jitter(3) Jitter - fPLL_OUT = 50 MHz Period jitter Long term jitter I(PLL)(2) Conditions Normal mode VCO freq = 420MHz PLL power consumption on VDD VCO freq = 150MHz Min Typ Max VCO = 150 MHz - 145 - VCO = 300 MHz - 91 - VCO = 400 MHz - 64 - VCO = 420 MHz - 63 - VCO = 150 MHz - 55 - VCO = 400 MHz - 30 - VCO = 150 MHz - - - VCO = 300 MHz - - - VCO = 400 MHz - +/-0.3 - VDD - 440 1150 VCORE - 530 - VDD - 180 500 VCORE - 200 - Unit +/ps +/ps % A 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by characterization results. 3. Integer mode only. 6.3.11 Memory characteristics Flash memory The characteristics are given at TJ = -40 to 125 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 51. Flash memory characteristics Symbol IDD 126/231 Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode - 6.5 - Write / Erase 16-bit mode - 11.5 - Write / Erase 32-bit mode - 20 - Write / Erase 64-bit mode - 35 - DS12110 Rev 5 Unit mA STM32H743xI Electrical characteristics Table 52. Flash memory programming (single bank configuration nDBANK=1) Symbol tprog tERASE128KB tME Min(1) Typ Max(1) Program/erase parallelism x 8 - 290 580(2) Program/erase parallelism x 16 - 180 360 Program/erase parallelism x 32 - 130 260 Program/erase parallelism x 64 - 100 200 Program/erase parallelism x 8 - 2 4 Program/erase parallelism x 16 - 1.8 3.6 Program/erase parallelism x 32 - Program/erase parallelism x 8 - 13 26 Program/erase parallelism x 16 - 8 16 Program/erase parallelism x 32 - 6 12 Program/erase parallelism x 64 - 5 10 1.62 - 3.6 1.8 - 3.6 Parameter Word (266 bits) programming time Sector (128 KB) erase time Mass erase time Conditions Unit s s Program parallelism x 8 Vprog Programming voltage Program parallelism x 16 Program parallelism x 32 Program parallelism x 64 V 1. Guaranteed by characterization results. 2. The maximum programming time is measured after 10K erase operations. Table 53. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Conditions Min(1) Endurance TJ = -40 to +125 C (6 suffix versions) 10 Data retention 1 kcycle at TA = 85 C 30 10 kcycles at TA = 55 C 20 Unit kcycles Years 1. Guaranteed by characterization results. DS12110 Rev 5 127/231 199 Electrical characteristics 6.3.12 STM32H743xI EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 54. They are based on the EMS levels and classes defined in application note AN1709. Table 54. EMS characteristics Symbol VFESD VFTB Parameter Conditions Level/ Class Voltage limits to be applied on any I/O pin to induce VDD = 3.3 V, TA = +25 C, a functional disturbance UFBGA240, frcc_c_ck = Fast transient voltage burst limits to be applied 400 MHz, conforms to through 100 pF on VDD and VSS pins to induce a IEC 61000-4-2 functional disturbance 3B 4B As a consequence, it is recommended to add a serial resistor (1 k) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: 128/231 Corrupted program counter Unexpected reset Critical Data corruption (control registers...) DS12110 Rev 5 STM32H743xI Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 55. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 8/400 MHz SEMI 6.3.13 VDD = 3.6 V, TA = 25 C, UFBGA240 package, Peak level conforming to IEC61967-2 0.1 to 30 MHz 6 30 to 130 MHz 5 130 MHz to 1 GHz 13 1 GHz to 2 GHz 7 EMI Level 2.5 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards. Table 56. ESD absolute maximum ratings Conditions Packages Class Maximum value(1) Electrostatic discharge VESD(HBM) voltage (human body model) TA = +25 C conforming to ANSI/ESDA/JEDEC JS001 All 1C 1000 Electrostatic discharge VESD(CDM) voltage (charge device model) TA =+25 C conforming to ANSI/ESDA/JEDEC JS002 All Symbol Ratings Unit V C1 250 1. Guaranteed by characterization results. DS12110 Rev 5 129/231 199 Electrical characteristics STM32H743xI Static latchup Two complementary static tests are required on six parts to assess the latchup performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 57. Electrical sensitivities Symbol LU 6.3.14 Parameter Static latchup class Conditions Class TA =+25 C conforming to JESD78 II level A I/O current injection characteristics As a general rule, a current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). The following tables are the compilation of the SIC1/SIC2 and functional ESD results. NegativeinducedA negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. Table 58. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15, PJ12, PB4 5 0 PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11 0 NA PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4, PA5, PH4, PH5, BOOT0 0 0 All other I/Os 5 NA 1. Guaranteed by characterization. 130/231 DS12110 Rev 5 Unit mA STM32H743xI 6.3.15 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 59: I/O static characteristics are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0). Table 59. I/O static characteristics Symbol Parameter Condition Min Typ Max - - 0.3xVDD - - 0.4xVDD- 0.1 BOOT0 I/O input low level voltage - - 0.19xVDD +0.1 I/O input high level voltage except BOOT0 0.7xVDD - - 0.47xVDD+ 0.25 - - 0.17xVDD+ 0.6 - - - 250 - - 200 - 30 40 50 I/O input low level voltage except BOOT0 VIL(1) VIH(1) I/O input low level voltage except BOOT0 I/O input low level voltage except BOOT0 1.62 V<VDD<3.6 V 1.62 V<VDD<3.6 V BOOT0 I/O input high level voltage (1) VHYS TT_xx, FT_xxx and NRST I/O input hysteresis 1.62 V< VDD <3.6 V BOOT0 I/O input hysteresis RPU Weak pull-up equivalent resistor(2) RPD Weak pull-down equivalent resistor(2) CIO I/O pin capacitance VIN=VSS Unit V V mV k VIN=VDD (3) - 30 40 50 - 5 - pF 1. Guaranteed by design. 2. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). 3. Max(VDDXXX) is the maximum value of all the I/O supplies. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 21. DS12110 Rev 5 131/231 199 Electrical characteristics STM32H743xI Figure 21. VIL/VIH for all I/Os except BOOT0 9 ' LQ W9 ,+P HQ XLUHP 6UHT &02 9ROWDJH 7//UHTXLUHPHQW9,+PLQ 9 ' RQ9,+PLQ XODWL GRQVLP 9'' %DVH 9'' RQ9,/PD[ WL OD X QVLP 9'' %DVHGR PD[ PHQW9,/ H LU X T H U &026 7//UHTXLUHPHQW9,/PLQ 9 06Y9 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: 132/231 The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 21). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 21). DS12110 Rev 5 STM32H743xI Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 60 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS and TTL compliant. Table 60. Output voltage characteristics(1) Symbol Parameter Conditions(3) Min Max Unit port(2) Output low level voltage CMOS IIO=8 mA 2.7 V VDD 3.6 V Output high level voltage CMOS port(2) IIO=-8 mA 2.7 V VDD 3.6 V Output low level voltage TTL port(2) IIO=8 mA 2.7 V VDD 3.6 V Output high level voltage TTL port(2) IIO=-8 mA 2.7 V VDD 3.6 V VOL(3) Output low level voltage IIO=20 mA 2.7 V VDD 3.6 V VOH(3) Output high level voltage IIO=-20 mA 2.7 V VDD 3.6 V VOL(3) Output low level voltage IIO=4 mA 1.62 V VDD 3.6 V VOH (3) Output high level voltage IIO=-4 mA 1.62 VVDD<3.6 V VDD--0.4 IIO= 20 mA 2.3 V VDD3.6 V - 0.4 IIO= 10 mA 1.62 V VDD 3.6 V - 0.4 VOL VOH VOL (3) VOH (3) VOLFM+(3) Output low level voltage for an FTf IO pin in FM+ mode 0.4 VDD-0.4 0.4 2.4 V 1.3 VDD-1.3 0.4 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings IIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. DS12110 Rev 5 133/231 199 Electrical characteristics STM32H743xI Output buffer timing characteristics (HSLV option disabled) The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.5 V. Table 61. Output timing characteristics (HSLV OFF)(1) Speed Symbol Fmax(2) Parameter Maximum frequency 00 tr/tf(3) Fmax(2) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(3) 134/231 Output high to low level fall time and output low to high level rise time conditions Min Max C=50 pF, 2.7 V VDD3.6 V - 12 C=50 pF, 1.62 VVDD2.7 V - 3 C=30 pF, 2.7 VVDD3.6 V - 12 C=30 pF, 1.62 VVDD2.7 V - 3 C=10 pF, 2.7 VVDD3.6 V - 16 C=10 pF, 1.62 VVDD2.7 V - 4 C=50 pF, 2.7 V VDD3.6 V - 16.6 C=50 pF, 1.62 VVDD2.7 V - 33.3 C=30 pF, 2.7 VVDD3.6 V - 13.3 C=30 pF, 1.62 VVDD2.7 V - 25 C=10 pF, 2.7 VVDD3.6 V - 10 C=10 pF, 1.62 VVDD2.7 V - 20 C=50 pF, 2.7 V VDD3.6 V - 60 C=50 pF, 1.62 VVDD2.7 V - 15 C=30 pF, 2.7 VVDD3.6 V - 80 C=30 pF, 1.62 VVDD2.7 V - 15 C=10 pF, 2.7 VVDD3.6 V - 110 C=10 pF, 1.62 VVDD2.7 V - 20 C=50 pF, 2.7 V VDD3.6 V - 5.2 C=50 pF, 1.62 VVDD2.7 V - 10 C=30 pF, 2.7 VVDD3.6 V - 4.2 C=30 pF, 1.62 VVDD2.7 V - 7.5 C=10 pF, 2.7 VVDD3.6 V - 2.8 C=10 pF, 1.62 VVDD2.7 V - 5.2 DS12110 Rev 5 Unit MHz ns MHz ns STM32H743xI Electrical characteristics Table 61. Output timing characteristics (HSLV OFF)(1) (continued) Speed Symbol Parameter conditions Min Max C=50 pF, 2.7 VVDD3.6 V - 85 C=50 pF, 1.62 VVDD2.7 V(4) - 35 - 110 C=30 pF, 1.62 VVDD2.7 V - 40 C=10 pF, 2.7 VVDD3.6 V(4) - 166 C=10 pF, 1.62 VVDD2.7 V(4) - 100 - 3.8 (4) (4) Fmax(2) Maximum frequency 10 C=30 pF, 2.7 VVDD3.6 V (4) (4) C=50 pF, 2.7 VVDD3.6 V (4) C=50 pF, 1.62 VVDD2.7 V tr/tf(3) Output high to low level fall time and output low to high level rise time - 6.9 V(4) - 2.8 C=30 pF, 1.62 VVDD2.7 V(4) - 5.2 C=10 pF, 2.7 VVDD3.6 V(4) - 1.8 V(4) - 3.3 V(4) - 100 C=50 pF, 1.62 VVDD2.7 V(4) - 50 V(4) - 133 V(4) - 66 C=10 pF, 2.7 VVDD3.6 V(4) - 220 C=10 pF, 1.62 VVDD2.7 V(4) - 85 V(4) - 3.3 V(4) - 6.6 V(4) - 2.4 C=30 pF, 1.62 VVDD2.7 V(4) - 4.5 C=10 pF, 2.7 VVDD3.6 V(4) - 1.5 V(4) - 2.7 C=30 pF, 2.7 VVDD3.6 C=10 pF, 1.62 VVDD2.7 C=50 pF, 2.7 VVDD3.6 Fmax(2) Maximum frequency 11 C=30 pF, 2.7 VVDD3.6 C=30 pF, 1.62 VVDD2.7 C=50 pF, 2.7 VVDD3.6 C=50 pF, 1.62 VVDD2.7 tr/tf(3) Output high to low level fall time and output low to high level rise time C=30 pF, 2.7 VVDD3.6 C=10 pF, 1.62 VVDD2.7 Unit MHz ns MHz ns 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) 2/3 T Skew 1/20 T 45%<Duty cycle<55% 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. DS12110 Rev 5 135/231 199 Electrical characteristics STM32H743xI Output buffer timing characteristics (HSLV option enabled) Table 62. Output timing characteristics (HSLV ON)(1) Speed Symbol Fmax (2) Parameter Maximum frequency 00 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 10 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 11 tr/tf(3) Output high to low level fall time and output low to high level rise time conditions Min Max C=50 pF, 1.62 VVDD2.7 V - 10 C=30 pF, 1.62 VVDD2.7 V - 10 C=10 pF, 1.62 VVDD2.7 V - 10 C=50 pF, 1.62 VVDD2.7 V - 11 C=30 pF, 1.62 VVDD2.7 V - 9 C=10 pF, 1.62 VVDD2.7 V - 6.6 C=50 pF, 1.62 VVDD2.7 V - 50 C=30 pF, 1.62 VVDD2.7 V - 58 C=10 pF, 1.62 VVDD2.7 V - 66 C=50 pF, 1.62 VVDD2.7 V - 6.6 C=30 pF, 1.62 VVDD2.7 V - 4.8 C=10 pF, 1.62 VVDD2.7 V - 3 C=50 pF, 1.62 VVDD2.7 V(4) - 55 C=30 pF, 1.62 VVDD2.7 V(4) - 80 C=10 pF, 1.62 VVDD2.7 V(4) - 133 C=50 pF, 1.62 VVDD2.7 V(4) - 5.8 C=30 pF, 1.62 VVDD2.7 V(4) - 4 C=10 pF, 1.62 VVDD2.7 V(4) - 2.4 C=50 pF, 1.62 VVDD2.7 V(4) - 60 C=30 pF, 1.62 VVDD2.7 V(4) - 90 C=10 pF, 1.62 VVDD2.7 V(4) - 175 C=50 pF, 1.62 VVDD2.7 V(4) - 5.3 C=30 pF, 1.62 VVDD2.7 V(4) - 3.6 (4) - 1.9 C=10 pF, 1.62 VVDD2.7 V Unit MHz ns MHz ns MHz ns MHz ns 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) 2/3 T Skew 1/20 T 45%<Duty cycle<55% 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. 136/231 DS12110 Rev 5 STM32H743xI 6.3.16 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 59: I/O static characteristics). Unless otherwise specified, the parameters given in Table 63 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 63. NRST pin characteristics Symbol RPU(2) Parameter Conditions Min Typ Max Unit VIN = VSS 30 40 50 1.71 V < VDD < 3.6 V - - 50 1.71 V < VDD < 3.6 V 300 - - 1.62 V < VDD < 3.6 V 1000 - - Weak pull-up equivalent resistor(1) VF(NRST)(2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse ns 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 22. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW 1567 538 ,QWHUQDO5HVHW )LOWHU ) 670 DLG 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 63. Otherwise the reset is not taken into account by the device. DS12110 Rev 5 137/231 199 Electrical characteristics 6.3.17 STM32H743xI FMC characteristics Unless otherwise specified, the parameters given in Table 64 to Table 77 for the FMC interface are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 11 Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 23 through Figure 26 represent asynchronous waveforms and Table 64 through Table 71 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: AddressSetupTime = 0x1 AddressHoldTime = 0x1 DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5) BusTurnAroundDuration = 0x0 Capcitive load CL = 30 pF In all timing tables, the TKERCK is the fmc_ker_ck clock period. 138/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms WZ1( )0&B1( WY12(B1( W Z12( W K1(B12( )0&B12( )0&B1:( WY$B1( )0&B$>@ W K$B12( $GGUHVV WY%/B1( W K%/B12( )0&B1%/>@ W K'DWDB1( W VX'DWDB12( WK'DWDB12( W VX'DWDB1( 'DWD )0&B'>@ W Y1$'9B1( WZ1$'9 )0&B1$'9 )0&B1:$,7 WK1(B1:$,7 WVX1:$,7B1( 069 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. DS12110 Rev 5 139/231 199 Electrical characteristics STM32H743xI Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Min Max 2Tfmc_ker_ck - 1 2 Tfmc_ker_ck +1 0 0.5 2Tfmc_ker_ck - 1 2Tfmc_ker_ck + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - tsu(Data_NE) Data to FMC_NEx high setup time 11 - tsu(Data_NOE) Data to FMC_NOEx high setup time 11 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - Tfmc_ker_ck + 1 tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time Unit ns 1. Guaranteed by characterization results. Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)(2) Symbol Min Max FMC_NE low time 7Tfmc_ker_ck +1 7Tfmc_ker_ck +1 FMC_NWE low time 5Tfmc_ker_ck -1 5Tfmc_ker_ck +1 FMC_NWAIT low time Tfmc_ker_ck -0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4Tfmc_ker_ck +11 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 3Tfmc_ker_ck+11.5 - tw(NE) tw(NOE) tw(NWAIT) Parameter 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. 140/231 DS12110 Rev 5 Unit ns STM32H743xI Electrical characteristics Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ1( )0&B1([ )0&B12( WY1:(B1( W K1(B1:( WZ1:( )0&B1:( WY$B1( )0&B$>@ WK$B1:( $GGUHVV WY%/B1( )0&B1%/>@ WK%/B1:( 1%/ WY'DWDB1( WK'DWDB1:( 'DWD )0&B'>@ W Y1$'9B1( WZ1$'9 )0&B1$'9 )0&B1:$,7 WK1(B1:$,7 WVX1:$,7B1( 069 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NWE low Min Max 3Tfmc_ker_ck - 1 3Tfmc_ker_ck Tfmc_ker_ck Tfmc_ker_ck + 1 Tfmc_ker_ck - 0.5 Tfmc_ker_ck + 0.5 FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid Tfmc_ker_ck - - 2 Tfmc_ker_ck - 0.5 - - 0.5 Tfmc_ker_ck - 0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck + 2.5 th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck+0.5 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - Tfmc_ker_ck + 1 tw(NADV) Unit ns 1. Guaranteed by characterization results. DS12110 Rev 5 141/231 199 Electrical characteristics STM32H743xI Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2) Symbol Min Max 8Tfmc_ker_ck - 1 8Tfmc_ker_ck + 1 FMC_NWE low time 6Tfmc_ker_ck - 1.5 6Tfmc_ker_ck + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck + 13 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+ 13 - tw(NE) tw(NWE) Parameter FMC_NE low time Unit ns 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. Figure 25. Asynchronous multiplexed PSRAM/NOR read waveforms WZ1( )0&B 1( WY12(B1( W K1(B12( )0&B12( W Z12( )0&B1:( WK$B12( WY$B1( )0&B $>@ $GGUHVV WY%/B1( WK%/B12( )0&B 1%/>@ 1%/ WK'DWDB1( WVX'DWDB1( W Y$B1( )0&B $'>@ WVX'DWDB12( WK'DWDB12( 'DWD $GGUHVV WK$'B1$'9 W Y1$'9B1( WZ1$'9 )0&B1$'9 )0&B1:$,7 WK1(B1:$,7 WVX1:$,7B1( 069 142/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Table 68. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Min Max 3Tfmc_ker_ck - 1 3Tfmc_ker_ck + 1 2Tfmc_ker_ck 2Tfmc_ker_ck + 0.5 Tfmc_ker_ck - 1 Tfmc_ker_ck + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time Tfmc_ker_ck - 0.5 Tfmc_ker_ck+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck + 0.5 - th(A_NOE) Address hold time after FMC_NOE high Tfmc_ker_ck - 0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - FMC_NEx low to FMC_BL valid - 0.5 tw(NE) FMC_NE low time tv(NOE_NE) FMC_NEx low to FMC_NOE low FMC_NOE low time ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) tv(BL_NE) tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck - 2 - tsu(Data_NOE) Data to FMC_NOE high setup time Tfmc_ker_ck - 2 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Guaranteed by characterization results. Table 69. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol tw(NE) tw(NOE) Parameter FMC_NE low time FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid Min Max 8Tfmc_ker_ck - 1 8Tfmc_ker_ck 5Tfmc_ker_ck - 1.5 5Tfmc_ker_ck + 0.5 5Tfmc_ker_ck + 3 - 4Tfmc_ker_ck - Unit ns 1. Guaranteed by characterization results. DS12110 Rev 5 143/231 199 Electrical characteristics STM32H743xI Figure 26. Asynchronous multiplexed PSRAM/NOR write waveforms WZ1( )0&B 1([ )0&B12( WY1:(B1( W K1(B1:( WZ1:( )0&B1:( WK$B1:( WY$B1( )0&B $>@ $GGUHVV WY%/B1( WK%/B1:( )0&B 1%/>@ 1%/ W Y$B1( W Y'DWDB1$'9 'DWD $GGUHVV )0&B $'>@ WK'DWDB1:( WK$'B1$'9 W Y1$'9B1( WZ1$'9 )0&B1$'9 )0&B1:$,7 WK1(B1:$,7 WVX1:$,7B1( 069 Table 70. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max FMC_NE low time 4Tfmc_ker_c - 1 4Tfmc_ker_ck FMC_NEx low to FMC_NWE low Tfmc_ker_c - 1 Tfmc_ker_ck + 0.5 FMC_NWE low time 2Tfmc_ker_ck- 0.5 2Tfmc_ker_ck+ 0.5 FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck - 0.5 - FMC_NEx low to FMC_A valid - 0 FMC_NEx low to FMC_NADV low 0 0.5 Tfmc_ker_ck Tfmc_ker_ck+ 1 Tfmc_ker_ck+0.5 - FMC_NADV low time th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck+0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck - 0.5 - - 0.5 - Tfmc_ker_ck + 2 Tfmc_ker_ck+0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid tv(Data_NADV) FMC_NADV high to Data valid th(Data_NWE) Data hold time after FMC_NWE high 1. Guaranteed by characterization results. 144/231 DS12110 Rev 5 Unit ns STM32H743xI Electrical characteristics Table 71. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid Min Max 9Tfmc_ker_ck - 1 9Tfmc_ker_ck 7Tfmc_ker_ck - 0.5 7Tfmc_ker_ck + 0.5 6Tfmc_ker_ck + 3 - 4Tfmc_ker_ck - Unit ns 1. Guaranteed by characterization results. Synchronous waveforms and timings Figure 27 through Figure 30 represent synchronous waveforms and Table 72 through Table 75 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: BurstAccessMode = FMC_BurstAccessMode_Enable MemoryType = FMC_MemoryType_CRAM WriteBurst = FMC_WriteBurst_Enable CLKDivision = 1 DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum values: For 2.7 V<VDD<3.6 V, FMC_CLK =133 MHz at 20 pF For 1.8 V<VDD<1.9 V, FMC_CLK =100 MHz at 20 pF For 1.62 V<VDD<1.8 V, FMC_CLK =100 MHz at 15 pF DS12110 Rev 5 145/231 199 Electrical characteristics STM32H743xI Figure 27. Synchronous multiplexed NOR/PSRAM read timings %867851 WZ&/. WZ&/. )0&B&/. 'DWDODWHQF\ WG&/./1([/ )0&B1([ W G&/./1$'9/ WG&/.+1([+ WG&/./1$'9+ )0&B1$'9 WG&/./$9 WG&/.+$,9 )0&B$>@ WG&/./12(/ WG&/.+12(+ )0&B12( W G&/./$'9 )0&B$'>@ WG&/./$',9 WVX$'9&/.+ $'>@ WK&/.+$'9 WVX$'9&/.+ ' WVX1:$,79&/.+ )0&B1:$,7 :$,7&)* E :$,732/E )0&B1:$,7 :$,7&)* E :$,732/E WVX1:$,79&/.+ WVX1:$,79&/.+ WK&/.+$'9 ' WK&/.+1:$,79 WK&/.+1:$,79 WK&/.+1:$,79 069 146/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Table 72. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low td(CLKL-NADVH) FMC_CLK low to FMC_NADV high td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Min Max 2Tfmc_ker_ck - 1 - - 1 Tfmc_ker_ck + 0.5 - - 1. 0 - - 2.5 Tfmc_ker_ck - - 1.5 Tfmc_ker_ck - 0.5 - td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 2 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) 2 - FMC_NWAIT valid after FMC_CLK high Unit ns 1. Guaranteed by characterization results. DS12110 Rev 5 147/231 199 Electrical characteristics STM32H743xI Figure 28. Synchronous multiplexed PSRAM write timings %867851 WZ&/. WZ&/. )0&B&/. 'DWDODWHQF\ WG&/./1([/ WG&/.+1([+ )0&B1([ WG&/./1$'9/ WG&/./1$'9+ )0&B1$'9 WG&/.+$,9 WG&/./$9 )0&B$>@ WG&/.+1:(+ WG&/./1:(/ )0&B1:( WG&/./$',9 WG&/./$'9 )0&B$'>@ WG&/./'DWD WG&/./'DWD $'>@ ' ' )0&B1:$,7 :$,7&)* E :$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 WG&/.+1%/+ )0&B1%/ 069 148/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Table 73. Synchronous multiplexed PSRAM write timings(1) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2Tfmc_ker_ck - 1 - - 1 Tfmc_ker_ck + 0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 2 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Tfmc_ker_ck - - 1.5 Tfmc_ker_ck + 0.5 - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2.5 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 2.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck + 0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 - Unit ns 1. Guaranteed by characterization results. DS12110 Rev 5 149/231 199 Electrical characteristics STM32H743xI Figure 29. Synchronous non-multiplexed NOR/PSRAM read timings WZ&/. WZ&/. )0&B&/. WG&/./1([/ WG&/.+1([+ 'DWDODWHQF\ )0&B1([ WG&/./1$'9/ WG&/./1$'9+ )0&B1$'9 WG&/.+$,9 WG&/./$9 )0&B$>@ WG&/./12(/ WG&/.+12(+ )0&B12( WVX'9&/.+ WK&/.+'9 WVX'9&/.+ ' )0&B'>@ ' WVX1:$,79&/.+ )0&B1:$,7 :$,7&)* E :$,732/E WK&/.+1:$,79 WVX1:$,79&/.+ )0&B1:$,7 :$,7&)* E :$,732/E WVX1:$,79&/.+ WK&/.+'9 W K&/.+1:$,79 WK&/.+1:$,79 069 Table 74. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) t(CLKL-NExL) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) Min Max 2Tfmc_ker_ck - 1 - - 2 Tfmc_ker_ck + 0.5 - td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 2 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Tfmc_ker_ck - - 1.5 Tfmc_ker_ck + 0.5 - td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 2 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1 - t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 - 1. Guaranteed by characterization results. 150/231 DS12110 Rev 5 Unit ns STM32H743xI Electrical characteristics Figure 30. Synchronous non-multiplexed PSRAM write timings WZ&/. WZ&/. )0&B&/. WG&/./1([/ WG&/.+1([+ 'DWDODWHQF\ )0&B1([ WG&/./1$'9/ WG&/./1$'9+ )0&B1$'9 WG&/.+$,9 WG&/./$9 )0&B$>@ WG&/./1:(/ WG&/.+1:(+ )0&B1:( WG&/./'DWD )0&B'>@ WG&/./'DWD ' ' )0&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WG&/.+1%/+ WK&/.+1:$,79 )0&B1%/ 069 Table 75. Synchronous non-multiplexed PSRAM write timings(1) Symbol t(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) Min Max 2Tfmc_ker_ck - 1 - - 2 Tfmc_ker_ck + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 2 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Tfmc_ker_ck - - 1.5 Tfmc_ker_ck + 1 - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck + 1 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) 2 - FMC_NWAIT valid after FMC_CLK high Unit ns 1. Guaranteed by characterization results. DS12110 Rev 5 151/231 199 Electrical characteristics STM32H743xI NAND controller waveforms and timings Figure 31 through Figure 34 represent synchronous waveforms, and Table 76 and Table 77 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: COM.FMC_SetupTime = 0x01 COM.FMC_WaitSetupTime = 0x03 COM.FMC_HoldSetupTime = 0x02 COM.FMC_HiZSetupTime = 0x01 ATT.FMC_SetupTime = 0x01 ATT.FMC_WaitSetupTime = 0x03 ATT.FMC_HoldSetupTime = 0x02 ATT.FMC_HiZSetupTime = 0x01 Bank = FMC_Bank_NAND MemoryDataWidth = FMC_MemoryDataWidth_16b ECC = FMC_ECC_Enable ECCPageSize = FMC_ECCPageSize_512Bytes TCLRSetupTime = 0 TARSetupTime = 0 CL = 30 pF In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period. Figure 31. NAND controller waveforms for read access )0&B1&([ $/()0&B$ &/()0&B$ )0&B1:( WG$/(12( WK12($/( )0&B12(15( WVX'12( WK12(' )0&B'>@ 069 152/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Figure 32. NAND controller waveforms for write access )0&B1&([ $/()0&B$ &/()0&B$ WK1:($/( WG$/(1:( )0&B1:( )0&B12(15( WK1:(' WY1:(' )0&B'>@ 069 Figure 33. NAND controller waveforms for common memory read access )0&B1&([ $/()0&B$ &/()0&B$ WK12($/( WG$/(12( )0&B1:( WZ12( )0&B12( WVX'12( WK12(' )0&B'>@ 069 DS12110 Rev 5 153/231 199 Electrical characteristics STM32H743xI Figure 34. NAND controller waveforms for common memory write access )0&B1&([ $/()0&B$ &/()0&B$ WG$/(12( WZ1:( WK12($/( )0&B1:( )0&B1 2( WG'1:( WY1:(' WK1:(' )0&B'>@ 069 Table 76. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck + 0.5 tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 8 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck + 1 th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck - 2 - Unit ns 1. Guaranteed by characterization results. Table 77. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FMC_NWE low width tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid td(D-NWE) FMC_D[15-0] valid before FMC_NWE high td(ALE-NWE) FMC_ALE valid before FMC_NWE low th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 1. Guaranteed by characterization results. 154/231 DS12110 Rev 5 Min Max 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck + 0.5 0 - 2Tfmc_ker_ck - 0.5 - 5Tfmc_ker_ck - 1 - - 3Tfmc_ker_ck + 0.5 2Tfmc_ker_ck - 1 - Unit ns STM32H743xI Electrical characteristics SDRAM waveforms and timings In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values: For 1.8 V<VDD<3.6V: FMC_CLK =100 MHz at 20 pF For 1.62 V<DD<1.8 V, FMC_CLK =100 MHz at 30 pF Figure 35. SDRAM read access waveforms (CL = 1) )0&B6'&/. WG6'&/./B$GG& WK6'&/./B$GG5 WG6'&/./B$GG5 )0&B$>@ 5RZQ &RO &RO &ROL &ROQ WK6'&/./B$GG& WK6'&/./B61'( WG6'&/./B61'( )0&B6'1(>@ WK6'&/./B15$6 WG6'&/./B15$6 )0&B6'15$6 WK6'&/./B1&$6 WG6'&/./B1&$6 )0&B6'1&$6 )0&B6'1:( WVX6'&/.+B'DWD WK6'&/.+B'DWD 'DWD )0&B'>@ 'DWD 'DWDL 'DWDQ 069 Table 78. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 1 2Tfmc_ker_ck + 0.5 tsu(SDCLKH _Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 1 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. DS12110 Rev 5 155/231 199 Electrical characteristics STM32H743xI Table 79. LPSDR SDRAM read timings(1) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 1 2Tfmc_ker_ck + 0.5 tsu(SDCLKH_Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. Figure 36. SDRAM write access waveforms )0&B6'&/. WG6'&/./B$GG& WK6'&/./B$GG5 WG6'&/./B$GG5 )0&B$>@ 5RZQ &RO &RO &ROL &ROQ WK6'&/./B$GG& WK6'&/./B61'( WG6'&/./B61'( )0&B6'1(>@ WG6'&/./B15$6 WK6'&/./B15$6 )0&B6'15$6 WG6'&/./B1&$6 WK6'&/./B1&$6 WG6'&/./B1:( WK6'&/./B1:( )0&B6'1&$6 )0&B6'1:( WG6'&/./B'DWD )0&B'>@ 'DWD 'DWD 'DWDL 'DWDQ WK6'&/./B'DWD WG6'&/./B1%/ )0&B1%/>@ 069 156/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Table 80. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 1 2Tfmc_ker_ck + 0.5 td(SDCLKL _Data) Data output valid time - 3 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - Unit ns 1. Guaranteed by characterization results. Table 81. LPSDR SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 1 2Tfmc_ker_ck + 0.5 td(SDCLKL _Data) Data output valid time - 2.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL-SDNWE) SDNWE valid time - 2.5 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 3 th(SDCLKL- SDNE) Chip select hold time 0 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL-SDNRAS) SDNRAS hold time 0 - td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5 td(SDCLKL-SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. DS12110 Rev 5 157/231 199 Electrical characteristics 6.3.18 STM32H743xI Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 82 and Table 83 for Quad-SPI are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 11 Measurement points are done at CMOS levels: 0.5VDD I/O compensation cell enabled HSLV activated when VDD2.7 V Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics. Table 82. Quad-SPI characteristics in SDR mode(1) Symbol Fck1/t(CK) tw(CKH) tw(CKL) Parameter Quad-SPI clock frequency Quad-SPI clock high and low time Conditions Min Typ Max 2.7 V VDD<3.6 V CL=20 pF - - 133 1.62 V<VDD<3.6 V CL=15 pF - - 100 t(CK)/2 -0.5 - t(CK)/2 t(CK)/2 - t(CK)/2 + 0.5 1.5 - - 2 - - - MHz ts(IN) Data input setup time th(IN) Data input hold time tv(OUT) Data output valid time - - 1.5 2 th(OUT) Data output hold time - 0.5 - - - 1. Guaranteed by characterization results. 158/231 DS12110 Rev 5 Unit ns STM32H743xI Electrical characteristics Table 83. Quad SPI characteristics in DDR mode(1) Symbol Fck1/t(CK) tw(CKH) Parameter Quad-SPI clock frequency Conditions Min Typ Max 2.7 V<VDD<3.6 V CL=20 pF - - 100 1.62 V<VDD<3.6 V CL=15 pF - - 100 t(CK)/2 - 0.5 - t(CK)/2 t(CK)/2 - t(CK)/2+0.5 MHz Quad-SPI clock high and low time - tsr(IN), tsf(IN) Data input setup time - 2 - - thr(IN), thf(IN) Data input hold time - 2 - - DHHC=0 - 3.5 4 DHHC=1 Pres=1, 2... - t(CK)/4+3.5 t(CK)/4+4 DHHC=0 3 - - DHHC=1 Pres=1, 2... t(CK)/4+3 - - tw(CKL) tvr(OUT), tvf(OUT) Data output valid time thr(OUT), thf(OUT) Data output hold time Unit ns 1. Guaranteed by characterization results. Figure 37. Quad-SPI timing diagram - SDR mode WU&. &ORFN W&. WZ&.+ WY287 WZ&./ WI&. WK287 'DWDRXWSXW ' ' WV,1 'DWDLQSXW ' ' WK,1 ' ' 06Y9 Figure 38. Quad-SPI timing diagram - DDR mode WU&. &ORFN 'DWDRXWSXW W&. WYI287 WZ&.+ WKU287 ' WYU287 ' ' WZ&./ WKI287 ' WVI,1 WKI,1 'DWDLQSXW ' ' WI&. ' ' WVU,1 WKU,1 ' ' ' ' 06Y9 DS12110 Rev 5 159/231 199 Electrical characteristics 6.3.19 STM32H743xI Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 85 for the delay block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 23: General operating conditions. Table 84. Dynamics characteristics: Delay Block characteristics(1) Symbol Parameter Conditions Min Typ Max tinit Initial delay - 1400 2200 2400 t Unit Delay - 35 40 45 Unit ps 1. Guaranteed by characterization results. 6.3.20 16-bit ADC characteristics Unless otherwise specified, the parameters given in Table 85 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 23: General operating conditions. Table 85. ADC characteristics(1) Symbol Parameter VDDA Analog power supply VREF+ Positive reference voltage VREF- Negative reference voltage fADC ADC clock frequency Sampling rate for Fast channels, BOOST = 1, fADC = 36 MHz Conditions Min Typ Max - 1.62 - 3.6 VDDA 2 V 2 - VDDA VDDA< 2 V VDDA - VSSA BOOST = 1 - - 36 BOOST = 0 - - 20 16-bit resolution - - 3.60 14-bit resolution - - 4.00 12-bit resolution - - 4.50 10-bit resolution - - 5.00 2 V VDDA 3.3 V 8-bit resolution fS Sampling rate for Fast channels, BOOST = 0, fADC = 20 MHz 16-bit resolution - - 2.00 14-bit resolution - - 2.20 12-bit resolution - - 2.50 10-bit resolution - - 2.80 160/231 3.30 16-bit resolution - - 1.00 14-bit resolution - - 1.00 12-bit resolution - - 1.00 10-bit resolution - - 1.00 8-bit resolution DS12110 Rev 5 V MHz 6.00 8-bit resolution Sampling rate for Slow channels, BOOST = 0, fADC = 10 MHz Unit 1.00 MSPS STM32H743xI Electrical characteristics Table 85. ADC characteristics(1) (continued) Symbol Conditions Min Typ Max Unit fADC = 36 MHz - - 3.6 MHz 16-bit resolution - - 10 1/fADC Conversion voltage range - 0 - VREF+ Common mode input voltage - RAIN External input impedance - - - 50 CADC Internal sample and hold capacitor - - 4 - pF ADC LDO startup time - - 5 10 s fTRIG VAIN (2) VCMIV tADCREG_ STUP Parameter External trigger frequency V VREF/2- /2+ VREF/2 REF 10% 10% tSTAB ADC power-up time LDO already started 1 tCAL Offset and linearity calibration time - 16384 - 1280 tOFF_CAL Offset calibration time tLATR tLATRINJ tS tCONV Trigger conversion latency for regular and injected channels without aborting the conversion Trigger conversion latency for regular and injected channels when a regular conversion is aborted Sampling time Total conversion time (including sampling time) conversion cycle CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2 CKMODE = 10 2.25 CKMODE = 11 2.125 CKMODE = 00 2.5 3 3.5 CKMODE = 01 - - 3 CKMODE = 10 - - 3.25 CKMODE = 11 - - 3.125 - 1.5 - 640.5 N-bit resolution V 1/fADC tS + 0.5 + N/2 (9 to 648 cycles in 14-bit mode) 1. Guaranteed by design. 2. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA. DS12110 Rev 5 161/231 199 Electrical characteristics STM32H743xI Table 86. ADC accuracy(1)(2)(3) Symbol Parameter ET Total unadjusted error ED EL ENOB(5) SINAD(5) SNR(5) THD(5) Differential linearity error Integral linearity error Effective number of bits (2 MSPS) Signal-tonoise and distortion ratio (2 MSPS) Signal-tonoise ratio (2 MSPS) Total harmonic distortion Conditions(4) Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential Single ended Differential Min Typ Max BOOST = 1 - 6 - BOOST = 0 - 8 - BOOST = 1 - 10 - BOOST = 0 - 16 - BOOST = 1 - 2 - BOOST = 0 - 1 - BOOST = 1 - 8 - BOOST = 0 - 2 - BOOST = 1 - 6 - BOOST = 0 - 4 - BOOST = 1 - 6 - BOOST = 0 - 4 - BOOST = 1 - 11.6 - BOOST = 0 - 12 - BOOST = 1 - 13.3 - BOOST = 0 - 13.5 - BOOST = 1 - 71.6 - BOOST = 0 - 74 - BOOST = 1 - 81.83 - BOOST = 0 - 83 - BOOST = 1 - 72 - BOOST = 0 - 74 - BOOST = 1 - 82 - BOOST = 0 - 83 - BOOST = 1 - -78 - BOOST = 0 - -80 - BOOST = 1 - -90 - BOOST = 0 - -95 - Unit LSB bits dB 1. Guaranteed by characterization for BGA packages, the values for LQFP packages might differ. 2. ADC DC accuracy values are measured after internal calibration. 3. The above table gives the ADC performance in 16-bit mode. 4. ADC clock frequency 36 MHz, 2 V VDDA 3.3 V, 1.6 V VREF VDDA, BOOSTEN (for I/O) = 1. 5. ENOB, SINAD, SNR and THD are specified for VDDA = VREF = 3.3 V. Note: 162/231 ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion DS12110 Rev 5 STM32H743xI Electrical characteristics being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.15 does not affect the ADC accuracy. Figure 39. ADC accuracy characteristics (12-bit resolution) 9 ''$ 9 5() >/6% ,'($/ RUGHSHQGLQJRQSDFNDJH @ (* (7 (2 (/ (' / 6%,'($/ 9 66$ 9''$ DLF 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. DS12110 Rev 5 163/231 199 Electrical characteristics STM32H743xI Figure 40. Typical connection diagram using the ADC 670 9'' 5$,1 $,1[ 9$,1 &SDUDVLWLF 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& 97 9 ,/$ ELW FRQYHUWHU & $'& DLE 1. Refer to Table 85 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 164/231 DS12110 Rev 5 STM32H743xI Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 41 or Figure 42, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 95() )Q) 9''$ )Q) 966$95() 06Y9 1. VREF+ input is available on all package whereas the VREF- s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA. Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA) 670 95()9''$ )Q) 95()966$ 06Y9 1. VREF+ input is available on all package whereas the VREF- s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA. DS12110 Rev 5 165/231 199 Electrical characteristics 6.3.21 STM32H743xI DAC electrical characteristics Table 87. DAC characteristics(1) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage - 1.8 3.3 3.6 VREF+ Positive reference voltage - 1.80 - VDDA VREF- Negative reference voltage - - VSSA - connected to VSSA 5 - - connected to VDDA 25 - - 10.3 13 16 VDD = 2.7 V - - 1.6 VDD = 2.0 V - - 2.6 VDD = 2.7 V - - 17.8 RL Resistive Load DAC output buffer ON RO(2) Output Impedance RBON Output impedance sample and hold mode, output buffer ON DAC output buffer ON Output impedance sample and hold mode, output buffer OFF DAC output buffer OFF RBOFF DAC output buffer OFF Unit V VDD = 2.0 V - - 18.7 DAC output buffer OFF - - 50 pF Sample and Hold mode - 0.1 1 F DAC output buffer ON 0.2 - VREF+ -0.2 V DAC output buffer OFF 0 - VREF+ Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes Normal mode, DAC output buffer tSETTLING when DAC_OUT reaches OFF, 1LSB CL=10 pF the final value of 0.5LSB, 1LSB, 2LSB, 4LSB, 8LSB) - 1.7(2) 2(2) s Wakeup time from off state (setting the Enx bit in Normal mode, DAC output buffer the DAC Control register) ON, CL 50 pF, RL = 5 until the 1LSB final value - 5 7.5 s VREF+ = 3.6 V - 850 - VREF+ = 1.8 V - 425 - CL(2) CSH (2) VDAC_OUT tWAKEUP(3) Voffset(2) 166/231 Capacitive Load Voltage on DAC_OUT output Middle code offset for 1 trim code step DS12110 Rev 5 V STM32H743xI Electrical characteristics Table 87. DAC characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max No load, middle code (0x800) - 360 - No load, worst code (0xF1C) - 490 - No load, middle/worst code (0x800) - 20 - - 360*TON/ (TON+TOFF) - No load, middle code (0x800) - 170 - No load, worst code (0xF1C) - 170 - No load, middle/worst code (0x800) - 160 - Sample and Hold mode, Buffer ON, CSH=100 nF (worst code) - 170*TON/ (TON+TOFF) - Sample and Hold mode, Buffer OFF, CSH=100 nF (worst code) - 160*TON/ (TON+TOFF) - DAC output buffer ON DAC quiescent IDDA(DAC) consumption from VDDA DAC output buffer OFF Sample and Hold mode, CSH=100 nF DAC output buffer ON IDDV(DAC) DAC consumption from VREF+ DAC output buffer OFF Unit A 1. Guaranteed by characterization results. 2. Guaranteed by design. 3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value). Table 88. DAC accuracy(1) Symbol Parameter Conditions Min Typ Max DNL Differential non linearity(2) DAC output buffer ON - 2 - DAC output buffer OFF - 2 - DAC output buffer ON, CL 50 pF, RL 5 - 4 - DAC output buffer OFF, CL 50 pF, no RL - 4 - VREF+ = 3.6 V - - 12 VREF+ = 1.8 V - - 25 DAC output buffer OFF, CL 50 pF, no RL - - 8 DAC output buffer OFF, CL 50 pF, no RL - - 5 INL Offset Offset1 Integral non linearity (3) Offset error at code 0x800 (3) Offset error at code 0x001(4) DAC output buffer ON, CL 50 pF, RL 5 DS12110 Rev 5 Unit LSB LSB LSB LSB 167/231 199 Electrical characteristics STM32H743xI Table 88. DAC accuracy(1) (continued) Symbol Parameter OffsetCal Offset error at code 0x800 after factory calibration Gain Gain Conditions error(5) DAC output buffer ON, CL 50 pF, RL 5 VREF+ = 3.6 V Min Typ Max - - 5 Unit LSB VREF+ = 1.8 V - - 7 DAC output buffer ON,CL 50 pF, RL 5 - - 1 DAC output buffer OFF, CL 50 pF, no RL - - 1 % TUE Total unadjusted error DAC output buffer OFF, CL 50 pF, no RL - - 12 LSB SNR Signal-to-noise ratio(6) DAC output buffer ON,CL 50 pF, RL 5 , 1 kHz, BW = 500 KHz - 67.8 - dB SINAD Signal-to-noise and distortion ratio(6) DAC output buffer ON, CL 50 pF, RL 5 , 1 kHz - 67.5 - dB ENOB Effective number of bits DAC output buffer ON, CL 50 pF, RL 5 , 1 kHz - 10.9 - bits 1. Guaranteed by characterization. 2. Difference between two consecutive codes minus 1 LSB. 3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x001) and the ideal value. 5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON. 6. Signal is -0.5dBFS with Fsampling=1 MHz. Figure 43. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ DL9 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 168/231 DS12110 Rev 5 STM32H743xI 6.3.22 Electrical characteristics Voltage reference buffer characteristics Table 89. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA Analog supply voltage Degraded mode Normal mode VREFBUF _OUT Voltage Reference Buffer Output Degraded mode Min Typ Max VSCALE = 000 2.8 3.3 3.6 VSCALE = 001 2.4 - 3.6 VSCALE = 010 2.1 - 3.6 VSCALE = 011 1.8 - 3.6 VSCALE = 000 1.62 - 2.80 VSCALE = 001 1.62 - 2.40 VSCALE = 010 1.62 - 2.10 VSCALE = 011 1.62 - 1.80 VSCALE = 000 - 2.5 - VSCALE = 001 - 2.048 - VSCALE = 010 - 1.8 - VSCALE = 011 - 1.5 - VSCALE = 000 VDDA- 150 mV - VDDA VSCALE = 001 VDDA- 150 mV - VDDA VSCALE = 010 VDDA- 150 mV - VDDA VSCALE = 011 VDDA- 150 mV - VDDA (2) Unit V TRIM Trim step resolution - - - 0.05 0.2 % CL Load capacitor - - 0.5 1 1.50 uF esr Equivalent Serial Resistor of CL - - - - 2 Iload Static load current - - - - 4 mA Iline_reg Line regulation 2.8 V VDDA 3.6 V Iload = 500 A - 200 - Iload = 4 mA - 100 - Iload_reg Load regulation 500 A ILOAD 4 mA Normal Mode - 50 - ppm/ mA - - - Tcoeff xVREFINT + 75 ppm/ C DC - - 60 - 100KHz - - 40 - Tcoeff Temperature coefficient -40 C < TJ < +125 C PSRR Power supply rejection DS12110 Rev 5 ppm/V dB 169/231 199 Electrical characteristics STM32H743xI Table 89. VREFBUF characteristics(1) (continued) Symbol tSTART IINRUSH IDDA(VRE FBUF) Parameter Conditions Start-up time Typ Max CL=0.5 F - - 300 - CL=1 F - - 500 - CL=1.5 F - - 650 - - 8 - Control of maximum DC current drive on VREFBUF_OUT during startup phase(3) - VREFBUF consumption from VDDA Min Unit s mA ILOAD = 0 A - - 15 25 ILOAD = 500 A - - 16 30 ILOAD = 4 mA - - 32 50 A 1. Guaranteed by design. 2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA-drop voltage). 3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively. 6.3.23 Temperature sensor characteristics Table 90. Temperature sensor characteristics Symbol Parameter TL(1) (2) Avg_Slope V30(3) Typ Max Unit VSENSE linearity with temperature - - 3 C Average slope - 2 - mV/C V Voltage at 30C 5 C - 0.62 - (1) Startup time in Run mode (buffer startup) - - 25.2 (1) ADC sampling time when reading the temperature 9 - - Sensor consumption - 0.18 0.31 Sensor buffer consumption - 3.8 tstart_run tS_temp Min Isens(1) Isensbuf(1) 6.5 s A 1. Guaranteed by design. 2. Guaranteed by characterization. 3. Measured at VDDA = 3.3 V 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Table 91. Temperature sensor calibration values Symbol 170/231 Parameter Memory address TS_CAL1 Temperature sensor raw data acquired value at 30 C, VDDA=3.3 V 0x1FF1 E820 -0x1FF1 E821 TS_CAL2 Temperature sensor raw data acquired value at 110 C, VDDA=3.3 V 0x1FF1 E840 - 0x1FF1 E841 DS12110 Rev 5 STM32H743xI 6.3.24 Electrical characteristics VBAT monitoring characteristics Table 92. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 26 - K Q Ratio on VBAT measurement - 4 - - -10 - +10 % 9 - - s Unit (1) Error on Q Er tS_vbat(1) ADC sampling time when reading VBAT input 1. Guaranteed by design. Table 93. VBAT charging characteristics Symbol RBC 6.3.25 Parameter Battery charging resistor Condition Min Typ Max VBRS in PWR_CR3= 0 - 5 - 1.5 - VBRS in PWR_CR3= 1 K Voltage booster for analog switch Table 94. Voltage booster for analog switch characteristics(1) Symbol VDD Parameter Condition Min Typ Max Unit - 1.62 2-6 3.6 V - - - 50 s 1.62 V VDD 2.7 V - - 125 2.7 V < VDD < 3.6 V - - 250 Supply voltage tSU(BOOST) Booster startup time IDD(BOOST) Booster consumption A 1. Guaranteed by characterization results. DS12110 Rev 5 171/231 199 Electrical characteristics 6.3.26 STM32H743xI Comparator characteristics Table 95. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 3.3 3.6 Comparator input voltage range - 0 - VDDA VBG(2) Scaler input voltage - Refer to VREFINT VSC Scaler offset voltage - - 5 10 BRG_EN=0 (bridge disable) - 0.2 0.3 BRG_EN=1 (bridge enable) - 0.8 1 - - 140 250 High-speed mode - 2 5 Medium mode - 5 20 Ultra-low-power mode - 15 80 High-speed mode - 50 80 Medium mode - 0.5 1.2 Ultra-low-power mode - 2.5 7 High-speed mode - 50 120 Medium mode - 0.5 1.2 Ultra-low-power mode - 2.5 7 Full common mode range - 5 20 No hysteresis - 0 - Low hysteresis - 10 - Medium hysteresis - 20 - High hysteresis - 30 - Static - 400 600 With 50 kHz 100 mV overdrive square signal - 800 - Static - 5 7 - 6 - Static - 70 100 With 50 kHz 100 mV overdrive square signal - 75 - VDDA VIN IDDA(SCALER) Parameter Scaler static consumption from VDDA tSTART_SCALER Scaler startup time tSTART Comparator startup time to reach propagation delay specification Propagation delay for 200 mV step with 100 mV overdrive tD Voffset Vhys Propagation delay for step > 200 mV with 100 mV overdrive only on positive inputs Comparator offset error Comparator hysteresis Ultra-lowpower mode IDDA(COMP) Comparator consumption from VDDA Medium mode With 50 kHz 100 mV overdrive square signal High-speed mode 1. Guaranteed by design, unless otherwise specified. 2. Refer to Table 27: Embedded reference voltage. 172/231 DS12110 Rev 5 Unit V mV A s s ns s ns s mV mV nA A STM32H743xI 6.3.27 Electrical characteristics Operational amplifiers characteristics Table 96. OPAMP characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage Range - 2 3.3 3.6 CMIR Common Mode Input Range - 0 - VDDA 25C, no load on output - - 1.5 All voltages and temperature, no load - - 2.5 - - 3.0 - Offset trim step at low TRIMOFFSETP common input voltage TRIMLPOFFSETP (0.1*V DDA) - - 1.1 1.5 TRIMOFFSETN Offset trim step at high common input voltage TRIMLPOFFSETN (0.9*V DDA) - - 1.1 1.5 Drive current - - - 500 Drive current in PGA mode - - - 270 CLOAD Capacitive load - - - 50 pF CMRR Common mode rejection ratio - - 80 - dB PSRR Power supply rejection ratio CLOAD 50pf / RLOAD 4 k(2) at 1 kHz, Vcom=VDDA/2 50 66 - dB GBW Gain bandwidth for high supply range - 4 7.3 12.3 MHz SR Slew rate (from 10% and 90% of output voltage) Normal mode - 3 - High-speed mode - 30 - AO Open loop gain - 59 90 129 dB m Phase margin - - 55 - GM Gain margin - - 12 - dB VIOFFSET VIOFFSET ILOAD ILOAD_PGA Input offset voltage Input offset voltage drift V mV V/C mV DS12110 Rev 5 A V/s 173/231 199 Electrical characteristics STM32H743xI Table 96. OPAMP characteristics(1) (continued) Symbol VOHSAT VOLSAT tWAKEUP Parameter Conditions Min Typ Max High saturation voltage Iload=max or RLOAD=min(2), Input at VDDA VDDA -100 mV - - Low saturation voltage Iload=max or RLOAD=min(2), Input at 0 V - - 100 Normal mode CLOAD 50pf, RLOAD 4 k(2), follower configuration - 0.8 3.2 High speed CLOAD 50pf, RLOAD 4 k(2), follower configuration - 0.9 2.8 - - 2 - - - - 4 - - - - 8 - - - - 16 - - - - -1 - - - - -3 - - - - -7 - - - - -15 - - PGA Gain=2 - 10/10 - PGA Gain=4 - 30/10 - PGA Gain=8 - 70/10 - PGA Gain=16 - 150/10 - PGA Gain=-1 - 10/10 - PGA Gain=-3 - 30/10 - PGA Gain=-7 - 70/10 - PGA Gain=-15 - 150/10 - - -15 - 15 Gain=2 - GBW/2 - Gain=4 - GBW/4 - Gain=8 - GBW/8 - Gain=16 - GBW/16 - Wake up time from OFF state Non inverting gain value PGA gain Inverting gain value R2/R1 internal resistance values in non-inverting PGA mode(3) Rnetwork R2/R1 internal resistance values in inverting PGA mode(3) Delta R PGA BW 174/231 Resistance variation (R1 or R2) PGA bandwidth for different non inverting gain DS12110 Rev 5 Unit mV s k/ k % MHz STM32H743xI Electrical characteristics Table 96. OPAMP characteristics(1) (continued) Symbol en IDDA(OPAMP) Parameter Voltage noise density OPAMP consumption from VDDA Conditions at 1 KHz at 10 KHz Normal mode Highspeed mode output loaded with 4 k no Load, quiescent mode, follower Min Typ Max - 140 - - 55 - - 570 1000 Unit nV/ Hz A - 610 1200 1. Guaranteed by design, unless otherwise specified. 2. RLOAD is the resistive load connected to VSSA or to VDDA. 3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1. DS12110 Rev 5 175/231 199 Electrical characteristics 6.3.28 STM32H743xI Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 97 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for DFSDMx). Table 97. DFSDM measured timing 1.62-3.6 V(1) Symbol Parameter Conditions Min Typ Max fDFSDMCLK DFSDM clock 1.62 V < VDD < 3.6 V - - fSYSCLK SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 V < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 1.62 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 2.7 < VDD < 3.6 V - - 20 (fDFSDMCLK/4) fCKIN (1/TCKIN) Input clock frequency fCKOUT Output clock frequency 1.62 < VDD < 3.6 V - - 20 DuCyCKOUT Output clock frequency duty cycle 1.62 < VDD < 3.6 V 45 50 55 176/231 DS12110 Rev 5 Unit MHz % STM32H743xI Electrical characteristics Table 97. DFSDM measured timing 1.62-3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V TCKIN/2 - 0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V 4 - - Unit ns th Data input hold time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V 0.5 - - TManchester Manchester data period (recovered clock period) Manchester mode (SITP[1:0]=2,3), Internal clock mode (SPICKSEL[1:0]0), 1.62 < VDD < 3.6 V (CKOUTDIV+1) * TDFSDMCLK - (2*CKOUTDIV) * TDFSDMCLK 1. Guaranteed by characterization results. DS12110 Rev 5 177/231 199 Electrical characteristics STM32H743xI ')6'0B&.,1\ ')6'0B'$7,1\ ')6'0B&.287 63,&.6(/ WVX WK WZO WZK WU WI WU WI 6,73 WVX WK 6,73 63,&.6(/ 63,&.6(/ 63,&.6(/ WVX ')6'0B'$7,1\ 63,WLPLQJ63,&.6(/ 63,WLPLQJ63,&.6(/ Figure 44. Channel transceiver timing diagrams WK WZO WZK 6,73 WVX WK 6,73 ')6'0B'$7,1\ 0DQFKHVWHUWLPLQJ 6,73 6,73 UHFRYHUHGFORFN UHFRYHUHGGDWD 069 178/231 DS12110 Rev 5 STM32H743xI 6.3.29 Electrical characteristics Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 98 for DCMI are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: DCMI_PIXCLK polarity: falling DCMI_VSYNC and DCMI_HSYNC polarity: high Data formats: 14 bits Capacitive load C=30 pF Measurement points are done at CMOS levels: 0.5VDD Table 98. DCMI characteristics(1) Symbol Min Max Unit - 0.4 - - 80 MHz Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 1 - th(DATA) Data input hold time 1 - - Parameter Frequency ratio DCMI_PIXCLK/frcc_c_ck DCMI_PIXCLK Pixel clock input DPixel tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 1.5 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 1 - ns 1. Guaranteed by characterization results. Figure 45. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WVX+6<1& WK+6<1& '&0,B+6<1& WVX96<1& WK+6<1& '&0,B96<1& WVX'$7$ WK'$7$ '$7$>@ 069 DS12110 Rev 5 179/231 199 Electrical characteristics 6.3.30 STM32H743xI LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 99 for LCD-TFT are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: LCD_CLK polarity: high LCD_DE polarity: low LCD_VSYNC and LCD_HSYNC polarity: high Pixel formats: 24 bits Output speed is set to OSPEEDRy[1:0] = 11 Capacitive load C=30 pF Measurement points are done at CMOS levels: 0.5VDD I/O compensation cell enabled Table 99. LTDC characteristics (1) Symbol fCLK Parameter LTDC clock output frequency Conditions Min Max 2.7 V < VDD < 3.6 V, 20 pF - 150 2.7 V < VDD < 3.6 V - 133 1.62 V < VDD < 3.6 V - 90 - 45 55 DCLK LTDC clock output duty cycle tw(CLKH), tw(CLKL) Clock High time, low time tv(DATA) Data output valid time - 0.5 th(DATA) Data output hold time 0 - tv(HSYNC), tv(VSYNC), tv(DE) HSYNC/VSYNC/DE output valid time - 0.5 th(HSYNC), th(VSYNC), th(DE) HSYNC/VSYNC/DE output hold time 0.5 - MHz % tw(CLK)/2-0.5 tw(CLK)/2+0.5 ns 1. Guaranteed by characterization results. 180/231 Unit DS12110 Rev 5 STM32H743xI Electrical characteristics Figure 46. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY+6<1& WY+6<1& /&'B+6<1& WK'( WY'( /&'B'( WY'$7$ /&'B5>@ /&'B*>@ /&'B%>@ 1JYFM 1JYFM 1JYFM / WK'$7$ +6<1& +RUL]RQWDO ZLGWK EDFNSRUFK $FWLYHZLGWK +RUL]RQWDO EDFNSRUFK 2QHOLQH 069 Figure 47. LCD-TFT vertical timing diagram W&/. /&'B&/. WY96<1& WY96<1& /&'B96<1& /&'B5>@ /&'B*>@ /&'B%>@ 0OLQHVGDWD 96<1& 9HUWLFDO ZLGWK EDFNSRUFK $FWLYHZLGWK 9HUWLFDO EDFNSRUFK 2QHIUDPH 069 DS12110 Rev 5 181/231 199 Electrical characteristics 6.3.31 STM32H743xI Timer characteristics The parameters given in Table 100 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 100. TIMx characteristics(1)(2) Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 200 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 100 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 200 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit - 65536 x 65536 tTIMxCLK Parameter Timer resolution time Maximum possible count with 32-bit counter - 1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 200 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx_d2. 182/231 DS12110 Rev 5 STM32H743xI 6.3.32 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: Standard-mode (Sm): with a bit rate up to 100 kbit/s Fast-mode (Fm): with a bit rate up to 400 kbit/s. Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0433 reference manual) and when the i2c_ker_ck frequency is greater than the minimum shown in the table below: Table 101. Minimum i2c_ker_ck frequency in all I2C modes Symbol Parameter Condition Min Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Unit 2 Analog filter ON DNF=0 8 Analog filter OFF DNF=1 9 Analog filter ON DNF=0 17 Analog filter OFF DNF=1 16 MHz The SDA and SCL I/O requirements are met with the following restrictions: The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas: tr(SDA/SCL)=0.8473xRpxCload Rp(min)= (VDD-VOL(max))/IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 6.3.15: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 102 for the analog filter characteristics: Table 102. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by design. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered. DS12110 Rev 5 183/231 199 Electrical characteristics STM32H743xI SPI interface characteristics Unless otherwise specified, the parameters given in Table 103 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 11 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.5VDD I/O compensation cell enabled HSLV activated when VDD 2.7 V Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 103. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency tsu(NSS) NSS setup time th(NSS) NSS hold time tw(SCKH), tw(SCKL) SCK high and low time 184/231 Conditions Min Typ Max Master mode 1.62 VVDD3.6 V 90 Master mode 2.7 VVDD3.6 V SPI1,2,3 133 Master mode 2.7 VVDD3.6 V SPI4,5,6 100 Slave receiver mode 1.62 VVDD3.6 V SPI1,2,3 - - 150 Slave receiver mode 1.62 VVDD3.6 V SPI4,5,6 100 Slave mode transmitter/full duplex 2.7 VVDD3.6 V 31 Slave mode transmitter/full duplex 1.62 VVDD3.6 V 25 Slave mode Master mode DS12110 Rev 5 2 - - 1 - - TPLCK - 2 TPLCK TPLCK + 2 Unit MHz ns STM32H743xI Electrical characteristics Table 103. SPI dynamic characteristics(1) (continued) Symbol tsu(MI) tsu(SI) Parameter Data input setup time th(MI) Data input hold time th(SI) Conditions Min Typ Max Master mode 1 - - Slave mode 2 - - Master mode 2 - - Slave mode 1 - - ta(SO) Data output access time Slave mode 9 13 27 tdis(SO) Data output disable time Slave mode 0 1 5 Slave mode, 2.7 VVDD3.6 V - 11.5 16 Slave mode 1.62 VVDD3.6 V - 13 20 Master mode - 1 3 Slave mode, 1.62 VVDD3.6 V 9 - - Master mode 0 - - tv(SO) Data output valid time tv(MO) th(SO) th(MO) Data output hold time Unit ns 1. Guaranteed by characterization results. Figure 48. SPI timing diagram - slave mode and CPHA = 0 166LQSXW WF6&. 6&.LQSXW WVX166 WK166 WZ6&.+ WU6&. &3+$ &32/ &3+$ &32/ WD62 WZ6&./ 0,62RXWSXW WY62 )LUVWELW287 WK62 1H[WELWV287 WI6&. WGLV62 /DVWELW287 WK6, WVX6, 026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1 06Y9 DS12110 Rev 5 185/231 199 Electrical characteristics STM32H743xI Figure 49. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW WF6&. WVX166 WZ6&.+ WD62 WZ6&./ WI6&. WK166 6&.LQSXW &3+$ &32/ &3+$ &32/ 0,62RXWSXW WY62 WK62 )LUVWELW287 WVX6, WU6&. 1H[WELWV287 WGLV62 /DVWELW287 WK6, )LUVWELW,1 026,LQSXW 1H[WELWV,1 /DVWELW,1 06Y9 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 50. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX0, 0,62 ,13 87 WZ6&.+ WZ6&./ 06%,1 WU6&. WI6&. %,7,1 /6%,1 WK0, 026, 287387 06%287 WY02 % , 7287 /6%287 WK02 DLF 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. 186/231 DS12110 Rev 5 STM32H743xI Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 104 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.5VDD I/O compensation cell enabled Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 104. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256x8K 256xFs MHz fCK I2S clock frequency Master data - 64xFs Slave data - 64xFs tv(WS) WS valid time Master mode - 3.5 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 1 - Master receiver 1 - Slave receiver 1 - Master receiver 4 - Slave receiver 2 - Slave transmitter (after enable edge) - 20 Master transmitter (after enable edge) - 3 Slave transmitter (after enable edge) 9 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz ns 1. Guaranteed by characterization results. DS12110 Rev 5 187/231 199 Electrical characteristics STM32H743xI Figure 51. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 52. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 188/231 DS12110 Rev 5 STM32H743xI Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 105 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C=30 pF Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 105. SAI characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK SAI Main clock output - 256 x 8K 256xFs MHz Master data: 32 bits - 128xFs(3) Slave data: 32 bits - 128xFs Master mode 2.7VDD3.6V - 15 Master mode 1.71VDD3.6V - 20 Slave mode 7 - Master mode 1 - Slave mode 1 - Master receiver 0.5 - Slave receiver 1 - Master receiver 3.5 - Slave receiver 2 - Slave transmitter (after enable edge) 2.7VDD3.6V - 17 Slave transmitter (after enable edge) 1.62VDD3.6V - 20 Slave transmitter (after enable edge) 7 - Master transmitter (after enable edge) 2.7VDD3.6V - 17 Master transmitter (after enable edge) 1.62VDD3.6V - 20 Master transmitter (after enable edge) 7.55 - FCK SAI clock frequency(2) tv(FS) FS valid time tsu(FS) FS setup time th(FS) FS hold time tsu(SD_A_MR) tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Data input setup time Data input hold time Data output valid time Data output hold time Data output valid time Data output hold time MHz ns ns 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. 3. With FS=192 kHz. DS12110 Rev 5 189/231 199 Electrical characteristics STM32H743xI Figure 53. SAI master timing waveforms I6&. 6$,B6&.B; WK)6 6$,B)6B; RXWSXW WY)6 WY6'B07 6$,B6'B; WUDQVPLW WK6'B07 6ORWQ WVX6'B05 6ORWQ WK6'B05 6$,B6'B; UHFHLYH 6ORWQ 069 Figure 54. SAI slave timing waveforms I6&. 6$,B6&.B; WZ&.+B; 6$,B)6B; LQSXW WZ&./B; WK)6 WVX)6 WY6'B67 6$,B6'B; WUDQVPLW WK6'B67 6ORWQ WVX6'B65 6$,B6'B; UHFHLYH 6ORWQ WK6'B65 6ORWQ 069 MDIO characteristics Table 106. MDIO Slave timing parameters Symbol Min Typ Max Unit Management data clock - - 40 MHz td(MDIO) Management data input/output output valid time 7 8 20 tsu(MDIO) Management data input/output setup time 4 - - th(MDIO) Management data input/output hold time 1 - - FsDC Parameter ns The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at least 1.5 times the MDC frequency: FPCLK2 1.5 * FMDC. 190/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Figure 55. MDIO Slave timing diagram W0'& WG0',2 WVX0',2 WK0',2 06Y9 SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 107 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 11 Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.5VDD I/O compensation cell enabled HSLV activated when VDD 2.7 V Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics. Table 107. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 125 MHz tW(CKL) Clock low time 9.5 10.5 - tW(CKH) Clock high time 8.5 9.5 - 2 - - 1.5 - - 3 - - - 3.5 5 2 - - fPP =50 MHz ns CMD, D inputs (referenced to CK) in MMC and SD HS/SDR/DDR mode tISU Input setup time HS tIH Input hold time HS tIDW(3) Input valid window (variable window) fPP 50 MHz ns CMD, D outputs (referenced to CK) in MMC and SD HS/SDR/DDR mode tOV Output valid time HS tOH Output hold time HS fPP 50 MHz DS12110 Rev 5 ns 191/231 199 Electrical characteristics STM32H743xI Table 107. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2) Symbol Parameter Conditions Min Typ Max 2 - - 1.5 - - - 1 2 0 - - Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD tIHD Input hold time SD fPP =25 MHz ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD tOHD Output hold default time SD fPP =25 MHz ns 1. Guaranteed by characterization results. 2. Above 100 MHz, CL = 20 pF. 3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Table 108. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 120 MHz tW(CKL) Clock low time 9.5 10.5 - tW(CKH) Clock high time 8.5 9.5 - 1.5 - - 2 - - 3.5 - - - 5 7 3 - - fPP =50 MHz ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS tIH Input hold time HS tIDW(3) Input valid window (variable window) fPP 50 MHz ns CMD, D outputs (referenced to CK) in eMMC mode tOV Output valid time HS tOH Output hold time HS fPP 50 MHz 1. Guaranteed by characterization results. 2. CL = 20 pF. 3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. 192/231 DS12110 Rev 5 ns STM32H743xI Electrical characteristics Figure 56. SDIO high-speed mode Figure 57. SD default mode &. W29' W2+' '&0' RXWSXW DL Figure 58. DDR mode WU&. &ORFN 'DWDRXWSXW W&. WYI287 WZ&.+ WKU287 ' WYU287 ' ' WZ&./ WKI287 ' WVI,1 WKI,1 'DWDLQSXW ' ' WI&. ' ' WVU,1 WKU,1 ' ' ' ' 06Y9 CAN (controller area network) interface Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (FDCANx_TX and FDCANx_RX). DS12110 Rev 5 193/231 199 Electrical characteristics STM32H743xI USB OTG_FS characteristics The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 109. USB OTG_FS electrical characteristics Symbol Parameter Condition Min Typ Max Unit USB transceiver operating voltage - 3.0(1) - 3.6 V RPUI Embedded USB_DP pull-up value during idle - 900 1250 1600 RPUR Embedded USB_DP pull-up value during reception - 1400 2300 3200 ZDRV Output driver impedance(2) Driver high and low 28 36 44 VDD33USB 1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7 to 3.0 V voltage range. 2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver. USB OTG_HS characteristics Unless otherwise specified, the parameters given in Table 110 for ULPI are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 11 Capacitive load C = 20 pF Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics. Table 110. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min Typ Max tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 0.5 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 6.5 - - tSD Data in setup time - 2.5 - - tHD Data in hold time - 0 - - 2.7 V < VDD < 3.6 V, CL = 20 pF - 6.5 8.5 - - 1.7 V < VDD < 3.6 V, CL = 15 pF - 6.5 13 tDC/tDD Data/control output delay 1. Guaranteed by characterization results. 194/231 DS12110 Rev 5 Unit ns STM32H743xI Electrical characteristics Figure 59. ULPI timing diagram &ORFN &RQWURO,Q 8/3,B',5 8/3,B1;7 W6& W+& W6' W+' GDWD,Q ELW W'& W'& &RQWURORXW 8/3,B673 W'' GDWDRXW ELW DLF Ethernet characteristics Unless otherwise specified, the parameters given in Table 111, Table 112 and Table 113 for SMI, RMII and MII are derived from tests performed under the ambient temperature, frcc_c_ck frequency summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 10 Capacitive load C = 20 pF Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics. Table 111 gives the list of Ethernet MAC signals for the SMI and Figure 60 shows the corresponding timing diagram. Table 111. Dynamics characteristics: Ethernet MAC signals for SMI(1) Symbol tMDC Parameter Min Typ Max MDC cycle time(2.5 MHz) 400 400 403 Td(MDIO) Write data valid time 1 1.5 3 tsu(MDIO) Read data setup time 8 - - th(MDIO) Read data hold time 0 - - Unit ns 1. Guaranteed by characterization results. DS12110 Rev 5 195/231 199 Electrical characteristics STM32H743xI Figure 60. Ethernet SMI timing diagram W0'& (7+B0'& WG0',2 (7+B0',22 WVX0',2 WK0',2 (7+B0',2, 069 Table 112 gives the list of Ethernet MAC signals for the RMII and Figure 61 shows the corresponding timing diagram. Table 112. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 3 - - tsu(CRS) Carrier sense setup time 2.5 - - tih(CRS) Carrier sense hold time 2 - - td(TXEN) Transmit enable valid delay time 4 4.5 7 td(TXD) Transmit data valid delay time 7 7.5 11.5 Unit ns 1. Guaranteed by characterization results. Figure 61. Ethernet RMII timing diagram 50,,B5()B&/. WG7;(1 WG7;' 50,,B7;B(1 50,,B7;'>@ WVX5;' WVX&56 WLK5;' WLK&56 50,,B5;'>@ 50,,B&56B'9 DLE Table 113 gives the list of Ethernet MAC signals for MII and Figure 62 shows the corresponding timing diagram. 196/231 DS12110 Rev 5 STM32H743xI Electrical characteristics Table 113. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 3 - - tsu(DV) Data valid setup time 1.5 - - tih(DV) Data valid hold time 1 - - tsu(ER) Error setup time 1.5 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 4.5 6.5 11 td(TXD) Transmit data valid delay time 7 7.5 15 Unit ns 1. Guaranteed by characterization results. Figure 62. Ethernet MII timing diagram 0,,B5;B&/. WVX5;' WVX(5 WVX'9 WLK5;' WLK(5 WLK'9 0,,B5;'>@ 0,,B5;B'9 0,,B5;B(5 0,,B7;B&/. WG7;(1 WG7;' 0,,B7;B(1 0,,B7;'>@ DLE 6.3.33 JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 114 and Table 115 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: Output speed is set to OSPEEDRy[1:0] = 0x10 Capacitive load C=30 pF Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics. DS12110 Rev 5 197/231 199 Electrical characteristics STM32H743xI Table 114. Dynamics characteristics: JTAG characteristics(1) Symbol Parameter Fpp 1/tc(TCK) TCK clock frequency Conditions Min Typ Max 2.7 V <VDD< 3.6 V - - 37 MHz 1.62 V <VDD< 3.6 V - - 27.5 tisu(TMS) TMS input setup time - 2 - - tih(TMS) TMS input hold time - 1 - - tisu(TDI) TDI input setup time - 1.5 - - tih(TDI) TDI input hold time - 1 - - TDO output valid time 2.7 V <VDD< 3.6 V - 8 13.5 tov (TDO) 1.62 V <VDD< 3.6 V - 8 18 - 7 - - toh(TDO) Unit TDO output hold time ns 1. Guaranteed by characterization results. Table 115. Dynamics characteristics: SWD characteristics(1) Symbol Parameter Fpp Conditions Min Typ Max 2.7 V <VDD< 3.6 V - - 71 1.62 V <VDD< 3.6 V - - 55.5 1/tc(SWCLK) SWCLK clock frequency tisu(SWDIO) SWDIO input setup time - 2.5 - - tih(SWDIO) SWDIO input hold time - 1 - - 2.7 V <VDD< 3.6 V - 8.5 14 tov (SWDIO) SWDIO output valid time 1.62 V <VDD< 3.6 V - 8.5 18 - 8 - - toh(SWDIO) MHz SWDIO output hold time 1. Guaranteed by characterization results. 198/231 Unit DS12110 Rev 5 ns STM32H743xI Electrical characteristics Figure 63. JTAG timing diagram WF7&. 7&. WVX7067', WK7067', WZ7&./ WZ7&.+ 7',706 WRY7'2 WRK7'2 7'2 06Y9 Figure 64. SWD timing diagram WF6:&/. 6:&/. WVX6:',2 WK6:',2 WZ6:&/./ WZ6:&/.+ 6:',2 UHFHLYH WRY6:',2 WRK6:',2 6:',2 WUDQVPLW 06Y9 DS12110 Rev 5 199/231 199 Package information 7 STM32H743xI Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at www.st.com. ECOPACK(R) is an ST trademark. 7.1 LQFP100 package information Figure 65. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline PP F $ $ $ 6($7,1*3/$1( & *$8*(3/$1( ' / ' $ . FFF & / ' 3,1 ,'(17,),&$7,21 H 1. Drawing is not to scale. 200/231 ( ( ( E DS12110 Rev 5 /B0(B9 STM32H743xI Package information Table 116. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS12110 Rev 5 201/231 227 Package information STM32H743xI Figure 66. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint DLF 1. Dimensions are expressed in millimeters. 202/231 DS12110 Rev 5 STM32H743xI Package information Device marking for LQFP100 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 67. LQFP100 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ (6+9,7 5 5HYLVLRQFRGH 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12110 Rev 5 203/231 227 Package information 7.2 STM32H743xI TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information GGG & Figure 68. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package outline 6($7,1* 3/$1( % $EDOO LQGH[ $EDOO DUHD LGHQWLILHU ' H $ $ $ & ' ) ( ( * $ % & ' ( ) * + . H $ %277209,(: E %$//6 HHH & $ % III & 7239,(: $4B0(B9 1. Drawing is not to scale. Table 117. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol 204/231 Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 DS12110 Rev 5 STM32H743xI Package information Table 117. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 7.850 8.000 8.150 0.3091 0.3150 0.3209 D1 - 7.200 - 0.2835 - E 7.850 8.000 8.150 0.3091 0.3150 0.3209 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 0.400 - - 0.0157 - G - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 69. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint 'SDG 'VP 1. Dimensions are expressed in millimeters. DS12110 Rev 5 205/231 227 Package information STM32H743xI Device marking for TFBGA100 Table 118. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 70. TFBGA100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670+ 5HYLVLRQFRGH 9+, 5 'DWHFRGH %DOO $LGHQWLILHU < :: 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 206/231 DS12110 Rev 5 STM32H743xI LQFP144 package information Figure 71. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ & $ PP *$8*(3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E 7.3 Package information ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. DS12110 Rev 5 207/231 227 Package information STM32H743xI Table 119. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 208/231 DS12110 Rev 5 STM32H743xI Package information Figure 72. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DLH 1. Dimensions are expressed in millimeters. DS12110 Rev 5 209/231 227 Package information STM32H743xI Device marking for LQFP144 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 73. LQFP144 marking example (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 (6+=,7 'DWHFRGH < :: 3LQLGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 210/231 DS12110 Rev 5 STM32H743xI 7.4 Package information UFBGA169 package information Figure 74. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJSODQH $ $ GGG = $ $ $ E 6,'(9,(: $EDOO LGHQWLILHU $EDOO LQGH[DUHD ; ( ( H ) $ ) ' ' H < 1 %277209,(: 7239,(: EEDOOV HHH 0 = ; < III 0 = $<9B0(B9 1. Drawing is not in scale. Table 120. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 - 0.130 - - 0.0051 - A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.950 6.000 6.050 0.2343 0.2362 0.2382 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e - 0.500 - - 0.0197 - DS12110 Rev 5 211/231 227 Package information STM32H743xI Table 120. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. F 0.450 0.500 0.550 0.0177 0.0197 0.0217 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 7.5 LQFP176 package information Figure 75. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline F $ $ $ & 6HDWLQJSODQH PP JDXJHSODQH N $ / +' 3,1 ,'(17,),&$7,21 / ' =( ( +( H =' E 7B0(B9 1. Drawing is not to scale. 212/231 DS12110 Rev 5 STM32H743xI Package information Table 121. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data Dimensions Ref. Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 HD 25.900 - 26.100 1.0197 - 1.0276 ZD - 1.250 - - 0.0492 - E 23.900 - 24.100 0.9409 - 0.9488 HE 25.900 - 26.100 1.0197 - 1.0276 ZE - 1.250 - - 0.0492 - e - 0.500 - - 0.0197 - 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - k 0 - 7 0 - 7 ccc - - 0.080 - - 0.0031 L (2) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. L dimension is measured at gauge plane at 0.25 mm above the seating plane. DS12110 Rev 5 213/231 227 Package information STM32H743xI Figure 76. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package recommended footprint 7B)3B9 1. Dimensions are expressed in millimeters. 214/231 DS12110 Rev 5 STM32H743xI Package information Device marking for LQFP176 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 77. LQFP176 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ (6+,,7 5HYLVLRQFRGH < :: 'DWHFRGH 5 3LQLGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12110 Rev 5 215/231 227 Package information 7.6 STM32H743xI LQFP208 package information Figure 78. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & FFF & PP $ *$8*(3/$1( . / ' / ' ' 3,1 ,'(17,),&$7,21 ( ( ( E H 6)@.&@7 1. Drawing is not to scale. 216/231 DS12110 Rev 5 STM32H743xI Package information Table 122. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1811 1.1732 1.1890 D1 27.800 28.000 28.200 1.1024 1.0945 1.1102 D3 - 25.500 - - 1.0039 - E 29.800 30.000 30.200 1.1811 1.1732 1.1890 E1 27.800 28.000 28.200 1.1024 1.0945 1.1102 E3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS12110 Rev 5 217/231 227 Package information STM32H743xI Figure 79. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint 8+B)3B9 1. Dimensions are expressed in millimeters. 218/231 DS12110 Rev 5 STM32H743xI Package information Device marking for LQFP208 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 80. LQFP208 marking example (package top view) 5HYLVLRQFRGH 5 3URGXFWLGHQWLILFDWLRQ (6+%,7 < :: 'DWHFRGH 3LQLGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12110 Rev 5 219/231 227 Package information 7.7 STM32H743xI UFBGA176+25 package information Figure 81. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline & ^ $ $EDOO LGHQWLILHU ( $EDOO LQGH[ DUHD $ ' Z KddKDs/t EEDOOV dKWs/t HHH 0 & $ III 0 & $(B0(B9 1. Drawing is not to scale. Table 123. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol 220/231 Min. Typ. Max. Min. Typ. Max. A - - 0.600 - - 0.0236 A1 - - 0.110 - - 0.0043 A2 - 0.130 - - 0.0051 - A3 - 0.450 - - 0.0177 - A4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 9.100 - - 0.3583 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 9.100 - - 0.3583 - e - 0.650 - - 0.0256 - Z - 0.450 - - 0.0177 - ddd - - 0.080 - - 0.0031 DS12110 Rev 5 STM32H743xI Package information Table 123. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 82. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint 'SDG 'VP &Ws Table 124. UFBGA 176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DS12110 Rev 5 221/231 227 Package information STM32H743xI Device marking for UFBGA176+25 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 83. UFBGA176+25 marking example (package top view) 5HYLVLRQFRGH 5 3URGXFWLGHQWLILFDWLRQ (6+,, 'DWHFRGH %DOO $LGHQWLILHU < :: 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 222/231 DS12110 Rev 5 STM32H743xI TFBGA240+25 package information GGG& Figure 84. TFBGA - 240+25 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array package outline 6($7,1* 3/$1( $ $ & $ $EDOOLGHQWLILHU ' ' H ( * $ ( 7.8 Package information H 6 ) %277209,(: EEDOOV 7239,(: $8B0(B9 1. Dimensions are expressed in millimeters. DS12110 Rev 5 223/231 227 Package information STM32H743xI Table 125. TFBG - 240 +25 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 13.850 14.000 14.150 0.5453 0.5512 0.5571 D1 - 12.800 - - 0.5039 - E 13.850 14.000 14.150 0.5453 0.5512 0.5571 E1 - 12.800 - - 0.5039 - e - 0.800 - - 0.0315 - F - 0.600 - - 0.0236 - G - 0.600 - - 0.0236 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 85. TFBGA - 240+25 ball, 14x14 mm 0.8 mm pitch recommended footprint 'SDG 'VP h&Ws 1. Dimensions are expressed in millimeters. 224/231 DS12110 Rev 5 STM32H743xI Package information Table 126. TFBGA - 240+25ball recommended PCB design rules (0.8 mm pitch) Dimension Recommended values Pitch 0.8 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking for TFBGA240+25 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 86. TFBGA240+25 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670+;,+ 5HYLVLRQFRGH 5 'DWHFRGH %DOO $LGHQWLILHU < :: 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12110 Rev 5 225/231 227 Package information 7.9 STM32H743xI Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 127. Thermal characteristics Symbol JA 7.9.1 Parameter Value Thermal resistance junction-ambient LQFP100 - 14 x 14 mm /0.5 mm pitch 45.0 Thermal resistance junction-ambient TFBGA100 - 8 x 8 mm /0.8 mm pitch 39.3 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm /0.5 mm pitch 43.7 Thermal resistance junction-ambient UFBGA169 - 7 x 7 mm /0.5 mm pitch 37.7 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm /0.5 mm pitch 43.0 Thermal resistance junction-ambient LQFP208 - 28 x 28 mm /0.5 mm pitch 42.4 Thermal resistance junction-ambient UFBGA176+25 - 10 x 10 mm /0.65 mm pitch 37.4 Thermal resistance junction-ambient TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch 36.6 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 226/231 DS12110 Rev 5 STM32H743xI 8 Ordering information Ordering information Table 128. STM32H743xI ordering information scheme Example: STM32 H 743 V I T 6 TR Device family STM32 = Arm-based 32-bit microcontroller Product type H = High performance Device subfamily 743 = STM32H7x3 line Pin count V = 100 pins Z = 144 pins A = 169 pins I = 176 pins/balls B = 208 pins X = 240 balls Flash memory size I = 2 Mbytes Package T = LQFP K = UFBGA pitch 0.65 mm I = UFBGA pitch 0.5 mm H = TFBGA Temperature range 6 = Industrial temperature range, -40 to 85 C Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. DS12110 Rev 5 227/231 227 Revision history 9 STM32H743xI Revision history Table 129. Document revision history Date Revision 22-Jun-2017 1 Initial release. 2 Updated list of features. Changed datasheet status to "production data". Added UFBGA169 and TFBGA100 packages and well as notes related their status on cover page and in Table 2: STM32H743xI features and peripheral counts. Differentiated number of GPIOs for each package in Table 2: STM32H743xI features and peripheral counts. Updated Error code correction (ECC) in Section 3.3.2: Embedded SRAM. Change PWR_CR3 into PWR_D3CR in Section 3.5.1: Power supply scheme. Updated Section 3.12: Nested vectored interrupt controller (NVIC). Added ADC sampling rate values in Section 3.17: Analog-todigital converters (ADCs). Added Table 4: DFSDM implementation in Section 3.23: Digital filter for sigma-delta modulators (DFSDM) Changed PC2/3 to PC2/3_C and VDD33USB to VDD in Figure 4: LQFP100 pinout. Changed PC2/3 to PC2/3_C in Figure 6: LQFP144 pinout. Changed PC2/3 to PC2/3_C in Figure 8: LQFP176 pinout. Changed PC2/3 to PC2/3_C in Figure 10: LQFP208 pinout. Table 8: STM32H743xI pin/ball definition: - Modified PA7, PC4, PC5, PB1, PG1, PE7, PE8 and PE9 I/O structure - TFBGA240 +25: removed duplicate occurrence of F1, F2 and P17 pin; added notes related to F1, F2, G2 pin connection; added note on E1, L16, L17, M16, M17, K16, K17, N17. - UFBGA176+25: changed G10 pin name to VSS. - Added note to VREF+ pin. Added current consumption corresponding to 125 C ambient temperature in Section 6.3.6: Supply current characteristics. Removed CRYP peripheral from Table 38: Peripheral current consumption in Run mode. Replaced FMC_CLK by FMC_SDCLK in Section : SDRAM waveforms and timings. Changed description of the last five fS values and updated tLATRINJin Table 85: ADC characteristics. For TFBGA100, TFBGA240+25 and UFBGA169, updated thermal resistance power-junction in Table 127: Thermal characteristics as well as power dissipation in Table 23: General operating conditions. 27-Sep-2017 228/231 Changes DS12110 Rev 5 STM32H743xI Revision history Table 129. Document revision history Date 23-Oct-2017 18-May-2018 Revision Changes 3 Features: - Removed secure firmware upgrade support. - Total current consumption changed to 4 A minimum. Updated Figure 7: UFBGA169 ballout. Updated dpad and dsm in Table 126: TFBGA - 240+25ball recommended PCB design rules (0.8 mm pitch). 4 Updated LSI clock frequency and ADC on cover page. Removed note related to UFBGA169 package. Updated USB OTG interfaces to add crystal-less capability. Updated ADC features on cover page and in Table 2: STM32H743xI features and peripheral counts. Added Arm trademark notice in Section 1: Introduction. Updated Figure 1: STM32H743xI block diagram. Updated GPIO default mode in Section 3.8: General-purpose input/outputs (GPIOs). Added ADC sampling rate values in Section 3.17: Analog-todigital converters (ADCs). Updated Section 3.18: Temperature sensor. Updated LCD-TFT FIFO Size in Section 3.25: LCD-TFT controller. Section 3.33: Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S): changed maximum SPI frequency to 150 Mbits/s. Modified number of bidirectional endpoints in Section 3.40: Universal serial bus on-the-go high-speed (OTG_HS). Table 8: STM32H743xI pin/ball definition: - Updated PC14 and PC15 function after reset. - Changed CAN1_TX/RX to FDCAN1_TX/RX and CAN1_TXFD/RXFD to FDCAN1_TXFD_MODE/RXFD_MODE - Changed CAN2_TX/RX to FDCAN2_TX/RX and CAN2_TXFD/RXFD to FDCAN2_TXFD_MODE/RXFD_MODE Replaced VCAP1/2/3 and VDDLDO1/2/3 by VCAP and VDDLDO, respectively. Updated PA0, PA13, PA14, PC14 and PC15 pin/ball signals in pinout/ballout schematics. Replaced fACLK by frcc_c_ck in Section : Typical and maximum current consumption. Replaced system clock by CPU clock and fACLK by frcc_c_ck in Section : On-chip peripheral current consumption. Updated Note 2. in Table 26: Reset and power control block characteristics. Updated Table 27: Embedded reference voltage, Table 29: Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator ON, Table 30: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON, regulator ON and Table 35: Typical and maximum current consumption in Stop mode, regulator ON. DS12110 Rev 5 229/231 230 Revision history STM32H743xI Table 129. Document revision history Date 18-May-2018 13-Jul-2018 230/231 Revision Changes 4 (continued) Updated typical and maximum current consumption in Table 36: Typical and maximum current consumption in Standby mode and Table 37: Typical and maximum current consumption in VBAT mode. Added note to fLSI in Table 48: LSI oscillator characteristics. Updated Figure 21: VIL/VIH for all I/Os except BOOT0. Added note in Table 82: Quad-SPI characteristics in SDR mode, Table 83: Quad SPI characteristics in DDR mode and Table 84: Dynamics characteristics: Delay Block characteristics. Section 6.3.20: 16-bit ADC characteristics: updated THD conditions in Table 86: ADC accuracy; removed formula to compute RAIN. Changed decoupling capacitor value to 100 nF in Section : General PCB design guidelines.* Added note in Table 87: DAC characteristics, Table 94: Voltage booster for analog switch characteristics, Table 97: DFSDM measured timing 1.62-3.6 V, Table 114: Dynamics characteristics: JTAG characteristics and Table 115: Dynamics characteristics: SWD characteristics. Updated Figure 73: LQFP144 marking example (package top view), Figure 77: LQFP176 marking example (package top view) and Figure 80: LQFP208 marking example (package top view). Updated TFBGA240+25 package information to final mechanical data. 5 Added description of power-up and power-down phases in Section 3.5.1: Power supply scheme. Removed ETH_TX_ER from Table 8: STM32H743xI pin/ball definition and Table 9: Port A alternate functions to Table 19: Port K alternate functions. Added note related to decoupling capacitor tolerance below Figure 14: Power supply scheme. Added note 2. related to CEXT in Table 24: VCAP operating conditions. Updated Table 45: HSI48 oscillator characteristics, Table 46: HSI oscillator characteristics and Table 47: CSI oscillator characteristics. Renamed Table 49 into "PLL characteristics (wide VCO frequency range)" and updated note 2.. Added Table 50: PLL characteristics (medium VCO frequency range). Updated Tcoeff in Table 89: VREFBUF characteristics. Updated tS_vbat in Table 92: VBAT monitoring characteristics. Updated Table 96: OPAMP characteristics. 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