AT24C512SC Preliminary - Atmel Corporation

Features

•Low-voltage and Standard-voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)

– 2.7 (VCC = 2.7V to 5.5V)

•Internally Organized 65,536 x 8

•2-wire Serial Interface

•Schmitt Triggers, Filtered Inputs for Noise Suppression

•Bi-directional Data Transfer Protocol

•1 MHz (5V) and 400 kHz (2.7V) Compatibility

•128-byte Page Write Mode (Partial Page Writes Allowed)

•Self-timed Write Cycle (5 ms Typical)

•High Reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 40 Years

– ESD Protection: >4000V

Description

The AT24C512SC provides 524,288 bits of serial electrically erasable and

programmable read only memory (EEPROM) organized as 65,536 words of 8 bits

each. This device is optimized for use in smart card applications where low-power and

low-voltage operation may be essential. This device is available in a standard ISO

7816 smart card module (see Ordering Information). The entire family is available in

both high-voltage (4.5V to 5.5V) and low-voltage (2.7V to 5.5V) versions. All devices

are functionally equivalent to Atmel Serial EEPROM products offered in standard IC

packages (PDIP, SOIC, EIAJ, LAP), with the exception of the slave address and write

protect functions which are not required for smart card applications.

Pin Configurations

Card Module Contact

Pad Name Description ISO Module Contact

VCC Power Supply Voltage C1

GND Ground C5

SCL Serial Clock Input C3

SDA Serial Data Input/Output C7

NC No Connect C2, C4, C6, C8

VCC

Rev. 1933A–10/00

2-wire Serial

EEPROM Smart

Card Module

512K (65,536 x 8)

AT24C512SC

Preliminary

2-Wire Serial

EEPROM 512K

(65,536 x 8)

AT24C512SC

Block Diagram

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive

edge clock data into each EEPROM device and negative

edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for

serial data transfer. This pin is open-drain driven and may

be wire-ORed with any number of other open-drain or open

collector devices.

Memory Organization

AT24C512SC, 512K SERIAL EEPROM: The 512K is inter-

nally organized as 512 pages of 128 bytes each. Random

word addressing requires a 16-bit data word address.

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

AT24C512SC

Note: 1. This parameter is characterized and is not 100% tested.

Note: 1. VIL min and VIH max are reference only and are not tested.

Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V.

Symbol Test Condition Max Units Conditions

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (SCL) 6 pF VIN = 0V

DC Characteristics

Applicable over recommended operating range from: TAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 2.7 5.5 V

VCC2 Supply Voltage 4.5 5.5 V

ICC1 Supply Current VCC = 5.0V Read at 400 kHz 1.0 2.0 mA

ICC2 Supply Current VCC = 5.0V Write at 400 kHz 2.0 3.0 mA

ISB1

Standby Current

(2.7V option)

VCC = 2.7V VIN = VCC or GND 0.6 µA

VCC = 5.5V 6.0

ISB2

Standby Current

(5.0V option)

VCC = 4.5 - 5.5V VIN = VCC or GND 6.0 µA

ILI Input Leakage Current VIN = VCC or GND 0.10 3.0 µA

ILO

Output Leakage

Current VOUT = VCC or GND 0.05 3.0 µA

VIL Input Low Level(1) -0.6 VCC x 0.3 V

VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V

VOL Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

AT24C512SC

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:

RL (connects to VCC): 1.3 kΩ (2.7V, 5V)

Input pulse voltages: 0.3VCC to 0.7VCC

Input rise and fall times: ≤ 50ns

Input and output timing reference voltages: 0.5VCC

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is nor-

mally pulled high with an external device. Data on the SDA

pin may change only during SCL low time periods (refer to

Data Validity timing diagram). Data changes during SCL

high periods will indicate a start or stop condition as defined

below.

START CONDITION: A high-to-low transition of SDA with

SCL high is a start condition which must precede any other

command (refer to Start and Stop Definition timing dia-

gram).

STOP CONDITION: A low-to-high transition of SDA with

SCL high is a stop condition. After a read sequence, the

stop command will place the EEPROM in a standby power

mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are seri-

ally transmitted to and from the EEPROM in 8-bit words.

The EEPROM sends a zero during the ninth clock cycle to

acknowledge that it has received each word.

STANDBY MODE: The AT24C512SC features a low power

standby mode which is enabled: a) upon power-up and b)

after the receipt of the STOP bit and the completion of any

internal operations.

MEMORY RESET: After an interruption in protocol, power

loss or system reset, any 2-wire part can be reset by follow-

ing these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition as SDA is high.

AC Characteristics

Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 100 pF (unless other-

wise noted). Test conditions are listed in Note 2.

Symbol Parameter

2.7-volt 5.0-volt

UnitsMin Max Min Max

fSCL Clock Frequency, SCL 400 1000 kHz

tLOW Clock Pulse Width Low 1.3 0.6 µs

tHIGH Clock Pulse Width High 1.0 0.4 µs

tAA Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs

tBUF

Time the bus must be free before a new

transmission can start(1) 1.3 0.5 µs

tHD.STA Start Hold Time 0.6 0.25 µs

tSU.STA Start Set-up Time 0.6 0.25 µs

tHD.DAT Data In Hold Time 0 0 µs

tSU.DAT Data In Set-up Time 100 100 ns

tRInputs Rise Time(1) 0.3 0.3 µs

tFInputs Fall Time(1) 300 100 ns

tSU.STO Stop Set-up Time 0.6 0.25 µs

tDH Data Out Hold Time 50 50 ns

tWR Write Cycle Time 10 10 ms

Endurance(1) 5.0V, 25°C, Page Mode 100K 100K Write Cycles

AT24C512SC

Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write

cycle.

(1)

AT24C512SC

Data Validity

Start and Stop Definition

Output Acknowledge

AT24C512SC

Device Addressing

The 512K EEPROM requires an 8-bit device address word

following a start condition to enable the chip for a read or

write operation (refer to Figure 1). The device address word

consists of a mandatory one, zero sequence for the first

four most significant bits as shown. This is common to all 2-

wire EEPROM devices.

The next three bits of the device address word are unused.

These three unused bits should be set to “0”.

The eighth bit of the device address is the read/write opera-

tion select bit. A read operation is initiated if this bit is high

and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will

output a zero. If a compare is not made, the device will

return to a standby state.

Write Operations

BYTE WRITE: A write operation requires two 8-bit data

word addresses following the device address word and

acknowledgment. Upon receipt of this address, the

EEPROM will again respond with a zero and then clock in

the first 8-bit data word. Following receipt of the 8-bit data

word, the EEPROM will output a zero. The addressing

device, such as a microcontroller, then must terminate the

write sequence with a stop condition. At this time the

EEPROM enters an internally-timed write cycle, tWR, to the

nonvolatile memory. All inputs are disabled during this write

cycle and the EEPROM will not respond until the write is

complete (refer to Figure 2).

PAG E WRITE: The 512K EEPROM is capable of 128-byte

page writes.

A page write is initiated the same way as a byte write, but

the microcontroller does not send a stop condition after the

first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcon-

troller can transmit up to 127 more data words. The

EEPROM will respond with a zero after each data word

received. The microcontroller must terminate the page

write sequence with a stop condition (refer to Figure 3).

The data word address lower seven bits are internally

incremented following the receipt of each data word. The

higher data word address bits are not incremented, retain-

ing the memory page row location. When the word

address, internally generated, reaches the page boundary,

the following byte is placed at the beginning of the same

page. If more than 128 data words are transmitted to the

EEPROM, the data word address will “roll over” and previ-

ous data will be overwritten. The address “roll over” during

write is from the last byte of the current page to the first

byte of the same page.

ACKNOWLEDGE POLLING: Once the internally-timed

write cycle has started and the EEPROM inputs are dis-

abled, acknowledge polling can be initiated. This involves

sending a start condition followed by the device address

word. The read/write bit is representative of the operation

desired. Only if the internal write cycle has completed will

the EEPROM respond with a zero, allowing the read or

write sequence to continue.

Read Operations

Read operations are initiated the same way as write opera-

tions with the exception that the read/write select bit in the

device address word is set to one. There are three read

operations: current address read, random address read

and sequential read.

CURRENT ADDRESS READ: The internal data word

address counter maintains the last address accessed dur-

ing the last read or write operation, incremented by one.

This address stays valid between operations as long as the

chip power is maintained. The address “roll over” during

read is from the last byte of the last memory page, to the

first byte of the first page.

Once the device address with the read/write select bit set

to one is clocked in and acknowledged by the EEPROM,

the current address data word is serially clocked out. The

microcontroller does not respond with an input zero but

does generate a following stop condition (refer to Figure 4).

RANDOM READ: A random read requires a “dummy” byte

write sequence to load in the data word address. Once the

device address word and data word address are clocked in

and acknowledged by the EEPROM, the microcontroller

must generate another start condition. The microcontroller

now initiates a current address read by sending a device

address with the read/write select bit high. The EEPROM

acknowledges the device address and serially clocks out

the data word. The microcontroller does not respond with a

zero but does generate a following stop condition (refer to

Figure 5).

SEQUENTIAL READ: Sequential reads are initiated by

either a current address read or a random address read.

After the microcontroller receives a data word, it responds

with an acknowledge. As long as the EEPROM receives an

acknowledge, it will continue to increment the data word

address and serially clock out sequential data words. When

the memory address limit is reached, the data word

address will “roll over” and the sequential read will con-

tinue. The sequential read operation is terminated when

the microcontroller does not respond with a zero but does

generate a following stop condition (refer to Figure 6).

AT24C512SC

Figure 1. Device Address

Figure 2. Byte Write

Figure 3. Page Write

AT24C512SC

Figure 4. Current Address Read

Figure 5. Random Read

Figure 6. Sequential Read

AT24C512SC

AT24C32SC Ordering Information

Notes: 1. Formal drawings may be obtained from an Atmel Sales Office.

2. Atmel currently offers this device in the “L” module only.

Ordering Code Package(1) Voltage Range Temperature Range

AT24C512SC - 09AT - 2.7 M2 - L Module 2.7V to 5.5V Commercial

(0°C to 70°C)

AT24C512SC - 09AT M2 - L Module 4.5V to 5.5V Commercial

(0°C to 70°C)

Package Type(1)

M2 - L Module M2 ISO 7816 Smart Card Module

AT24C512SC

Smart Card Module

M2 - L Module - Ordering code: 09LT

Module Size: M2

Dimension(1): 12.6 x 11.4 [mm]

Glob Top: Square: 8.6 x 8.6 [mm]

Thickness: 0.58 [mm] max.

Pitch: 14.25 mm

Note: 1. The module dimensions listed refer to the

dimensions of the exposed metal contact area.

The actual dimensions of the module after excise or

punching from the carrier tape are generally 0.4 mm

greater in both directions (i.e. a punched M2 module

will yield 13.0 x 11.8 mm).

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notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

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not authorized for use as critical components in life support devices or systems.

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1933A–10/00/xM

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