MM74HC373SJX - FAIRCHILD SEMICONDUCTOR

September 1983

Revised May 2005

MM74HC373 3-STATE Octal D-Type Latch

MM74HC373

3-STATE Octal D-Type Latch

General Descript ion

The MM74HC373 high speed octal D-type latches utilize

advanced silicon-gate CMOS technology. They possess

the high noise immunity and low power consumption of

standard CMOS integrat ed cir cuits, as w ell a s the a bility to

drive 15 LS -TTL loa ds. Du e to the larg e outpu t drive capa-

bility and the 3-STATE feature, these devices are ideally

suited for interfacing with bus lines in a bus organized sys-

tem.

When the LATCH ENABLE input is HIGH, the Q outputs

will follow the D inputs. When the LATCH ENABLE goes

LOW, data at the D inputs will be retained at the outputs

until LATCH ENABLE returns HIGH again. When a high

logic level is applied to the OUTPUT CONTROL input, all

outputs go to a high impedance state, regardless of what

signals are present at th e other inputs and the state of the

storage elements.

The 74H C log i c fam ily i s sp ee d, fu ncti o n, a nd pin- ou t com -

patible with the standard 74LS logic family. All inputs are

protect ed from damage due to static di scharge by in ternal

diode clamps to VCC and ground.

Features

■Typical propagation delay: 18 ns

■Wide operat i ng voltage ran ge : 2 to 6 volts

■Low input current: 1

A maximum

■Low quiescent current: 80

A maximum ( 74 Series)

■Output drive capability: 15 LS-TTL loads

Ordering Code:

Devices also available in Tape and Reel. Specify by ap pending th e s uffix let t er “X” to the or dering code.

Connection Diagram

Pin Assignments for DIP, SOIC, SOP a nd TSSOP

Top View

Truth Table

HIGH Level

LOW Le vel

Level of output bef ore stea dy -s ta te input cond it ions were es tab lis hed.

High Impedance

Order Number Package Number Package Description

MM74HC373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Output Latch Data 373

Control Enable Output

LHHH

LHLL

LLXQ

HXXZ

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MM74HC373

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute Maximum Ratings a re those va lues beyon d which d am-

age to the device may occur.

Note 2: Unless ot herw ise sp ec ified all vo lt ages are referenced to ground.

Note 3: Power Dis sipation temp erature de rating — plastic “N” package:



12 mW/

C from 65

C to 85

DC Electrical Characteristi cs

Note 4: For a power supply of 5V

10% t he wor st case ou tput vo ltages (V OH, and VOL) occur for HC a t 4.5V. Thus t he 4.5V values s hould be used w hen

designing with this supply. Worst case VIH and VIL occur at VCC

5.5V a nd 4.5V res pectively. (T he VIH value at 5. 5V is 3.8 5V.) Th e w orst cas e leakage cur-

rent (IIN, ICC, and IOZ) occur for CMOS at the hi gher voltage and so the 6.0V valu es s hould be u s ed.

Supply Voltage (VCC)



0.5 to



7.0V

DC Input Voltage (VIN)



1.5 to VCC



1.5V

DC Output Voltage (VOUT)



0.5 to VCC



0.5V

Clamp Diode Current (IIK, IOK)

20 mA

DC Output Current, per pin (IOUT)

35 mA

DC VCC or GND Current, per pin (ICC)

70 mA

Storage Temper ature Range (TSTG)



C to



150

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 second s) 260

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage

(VIN,VOUT)0V

CC V

Operating Temperature Range (TA)





Input Rise or Fall Times

(tr, tf) V

2.0V 1000 ns

VCC

4.5V 500 ns

VCC

6.0V 400 ns

Symbol Parameter Conditions VCC TA



40 to 85



55 to 125

CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HIGH Level VIN

VIH or VIL

Output Voltage |IOUT|

A 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN

VIH or VIL

|IOUT|

6.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT|

7.8 mA 6.0V 5.7 5.48 5.34 5.2 V

VOL Maximum LOW Lev el VIN

VIH or VIL

Output Voltage |IOUT|

A 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN

VIH or VIL

|IOUT|

6.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT|

7.8 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maxim um In put VIN

VCC or GND 6.0V

0.1

1.0

Current

IOZ Maxim um 3-STAT E VIN

VIH or VIL, OC

VIH 6.0V

0.5

Output Leakage VOUT

VCC or GND

Current

ICC Maximum Quiescent VIN

VCC or GND 6.0V 8.0 80 160

Supply Current IOUT

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MM74HC373

AC Electrical Characteristics

VCC

5V, TA

C, tr

6 ns

AC Electrical Characteristics

VCC

2.0



6.0V, CL

50 pF, tr

6 ns (unless otherwise specified)

Symbol Parameter Conditions Typ Guaranteed Units

Limit

tPHL, tPLH Maximum Propagation Delay, Data to Q CL

45 pF 18 25 ns

tPHL, tPLH Maximum Propagation Delay, LE to Q CL

45 pF 21 30 ns

tPZH, tPZL Maximum Output Enable Time RL

1 k

20 28 ns

45 pF

tPHZ, tPLZ Maximum Output Disable Time RL

1 k

18 25 ns

5 pF

tSMinimum Set Up Time 5ns

tHMinimum Hold Time 10 ns

tWMinimum Pulse Width 9 16 ns

Symbol Parameter Conditions VCC TA



40 to 85



55 to 125

CUnits

Typ Guaranteed Limits

tPHL, tPLH Maximum Propagation CL

50 pF 2.0V 50 150 188 225 ns

Delay, Data to Q CL

150 pF 2.0V 80 200 250 300 ns

50 pF 4.5V 22 30 37 45 ns

150 pF 4.5V 30 40 50 60 ns

50 pF 6.0V 19 26 31 39 ns

150 pF 6.0V 26 35 44 53 ns

tPHL, tPLH Maximum Propagation CL

50 pF 2.0V 63 175 220 263 ns

Delay, LE to Q CL

150 pF 2.0V 110 225 280 338 ns

50 pF 4.5V 25 35 44 52 ns

150 pF 4.5V 35 45 56 68 ns

50 pF 6.0V 21 30 37 45 ns

150 pF 6.0V 28 39 49 59 ns

tPZH, tPZL Maximum Output RL

1 k

Enable Time CL

50 pF 2.0V 50 150 188 225 ns

150 pF 2.0V 80 200 250 300 ns

50 pF 4.5V 21 30 37 45 ns

150 pF 4.5V 30 40 50 60 ns

50 pF 6.0V 19 26 31 39 ns

150 pF 6.0V 26 35 44 53 ns

tPHZ, tPLZ Maximum Output Disable RL

1 k

2.0V 50 150 188 225 ns

Disable Time CL

50 pF 4.5V 21 30 37 45 ns

6.0V 19 26 31 39 ns

tSMinimum Set Up Time 2.0V 50 60 75 ns

4.5V 9 13 15 ns

6.0V 9 11 13 ns

tHMinimum Hold Time 2.0V 5 5 5 ns

4.5V 5 5 5 ns

6.0V 5 5 5 ns

tWMinimum Pulse Width 2.0V 30 80 100 120 ns

4.5V 10 16 20 24 ns

6.0V 9 14 18 20 ns

tTHL, tTLH Maximum Output Rise CL

50 pF 2.0V 25 60 75 90 ns

and Fall Time 4.5V 7 12 15 18 ns

6.0V 6 10 13 15 ns

CPD Power Dissipation (per latch)

Capacitance (Note 5) OC

VCC 30 pF

GND 50 pF

CIN Maximum Input Capacitance 5 10 10 10 pF

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MM74HC373

AC Electrical Characteristics (Continued)

Note 5: CPD determines t he no load d y namic pow er consu m pt ion, PD

CPD VCC2 f



ICC VCC, and the no load dynamic current consumption,

CPD VCC f



ICC.

Symbol Parameter Conditions VCC TA



40 to 85



55 to 125

CUnits

Typ Gu ar ant eed Li mi ts

COUT Maximum Output 15 20 20 20 pF

Capacitance

5 www.fairchildsemi.com

MM74HC373

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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MM74HC373

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ T YPE II, 5.3mm Wide

Package Number M20D

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MM74HC373

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

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MM74HC373 3-STATE Octal D-Type Latch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices o r syste ms a re device s or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical com ponent in any compon ent of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.