TEMIC Semiconductors e5551 Standard R/W Identification IC with Anticollision Description The e5551 is a contactless R/W-IDentification IC (IDIC for general-purpose applications in the 125 kHz range. A single coil, connected to the chip, serves as the ICs power supply and bidirectional communication interface. Coil and chip together form a transponder. The on-chip 264-bit EEPROM (8 blocks 33 bits each) can be read and written blockwise from a base station. The blocks can be protected against overwriting. One block is Features Low-power, low-voltage operation Contactless power supply Contactless read/write data transmission Radio Frequency (RF): 100 kHz to 150 kHz 264 bit EEPROM memory in 8 blocks of 33 bits 224 bits in 7 blocks of 32 bits are free for user data Block write protection Extensive protection against contactless malpro- gramming of the EEPROM Power Base station Data reserved for setting the operation modes of the IC. Another block can contain a password to prevent unauthorized writing. Reading occurs by damping the coil by an internal load. There are different bitrates and encoding schemes possible. Writing occurs by interrupting the RF field in a special way. @ Anticollision using Answer-On-Request (AOR) @ Typical < 50 ms to write and verify a block @ Other options set by EEPROM: Bitrate [bit/s]: RF/8, RF/16, RF/32, RF/40 RF/50, RF/64, RF/100, RF/128 BIN, FSK, PSK, Manchester, Biphase Terminator mode, Password mode Modulation: Other: Transponder oO 9 3 So h> S be = 5 Memory 45 z 5 oO e555 1 Figure 1. RFID system using e5551 tag * IDIC stands for IDentification Integrated Circuit and is a trademark of TEMIC Semiconductors Rev. A2, 11-Oct-99 1 (20)e5551 TEMIC Semiconductors e5551 Building Blocks Analog Front End (AFE) The AFE includes all circuits which are directly connected to the coil. It generates the ICs power supply and handles the bidirectional data communication with the reader unit. It consists of the following blocks: Rectifier to generate a dc supply voltage from the ac coil voltage @ Clock extractor @ Switchable load between Coill/ Coil2 for data trans- mission from the IC to the reader unit (read) @ Field gap detector for data transmission from the reader unit into the IC (write) Controller The main controller has following functions: @ Load mode register with configuration data from EEPROM block 0 after power-on and also during reading @ Control memory access (read, write) @ Handle write data transmission and the write error modes @ The first two bits of the write data stream are the OP- code. There are two valid OP-codes (standard and stop) which are decoded by the controller. @ In password mode, the 32 bits received after the OP- code are compared with the stored password in block 7. Bitrate Generator The bitrate generator can deliver the following bitrates: RF/8 - RE/16 - RF/32 - RF/40 - RF/50 - RE/64 - RF/100 - RF/128 Write Decoder Decode the detected gaps during writing. Check if write data stream is valid. Test Logic Test circuitry allows rapid programming and verification of the IC during test. HV Generator Voltage pump which generates ~18 V for programming of the EEPROM. POR eat Modulator Coil 1 oe +} Mode register Reena San 5 o C : = z 3 Y Y Y Y Y Memory a . = 2 oO oS ws g eet hs ial se 20 (264 bit EEPROM) & = gs 8 3 Ba Seo : a Controller Sessstlal } Coil 2 Lo = S Lp Het Input register a 8 5 me 5 4 Test logic HV generator Vpp Yss Lt Lt LJ Test pads Figure 2. Block diagram e5551 2 (20) Rev. A2, 11-Oct-99TEMIC Semiconductors e5551 Power-On Reset (POR) The power-on reset is a delay reset which is triggered when supply voltage is applied. Mode Register The mode register stores the mode data from EEPROM block 0. It is continually refreshed at the start of every block. This increases the reliability of the device (Gf the originally loaded mode information is false, it will be corrected by subsequent refresh cycles). Modulator The modulator consists of several data encoders in two stages, which may be freely combined to obtain the desired modulation. The basic types of modulation are: @ PSK: phase shift: 1) every change; 2) every 1; 3) every rising edge (carrier: fc/2, fc/4 or fc/8) @ FSK: 1) fl =rf/8 f2 =rf/5; 2) fl =rf/8, f2 = rf/10 @ Manchester: rising edge = H; falling edge = L @ Biphase: every bit creates a change, a data H creates an additional mid-bit change Note: The following modulation type combinations will not work: @ Stagel Manchester or Biphase, stage2 PSK2, at any PSK carrier frequency (because the first stage output frequency is higher than the second stage strobe frequency) @ Stagel Manchester or Biphase and stage2 PSK with bitrate = rf/8 and PSK carrier frequency = rf/8 (for the same reason as above) @ Any stagel option with any PSK for bitrates rf/50 or rf/100 if the PSK carrier frequency is not an integer multiple of the bitrate (e.g., br = rf/50, PSKef = rf/4, because 50/4 = 12.5). This is because the PSK carrier frequency must maintain constant phase with respect to the bit clock. Memory The memory of the e5551 is a 264 bit EEPROM, which is arranged in 8 blocks of 33 bits each. All 33 bits of a block, including the lock bit, are programmed. simulta- neously. The programming voltage is generated on-chip. Block 0 contains the mode data, which are not normally transmitted (see figure 5). Block 1 to 6 are freely programmable. Block 7 may be used as a password. If password protection is not required, it may be used for user data. Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lockbit itself) cannot be field-reprogrammed. Data from the memory is transmitted serially, starting with block 1, bit 1, up to block MAXBLK, bit 32. MAXBLK is a mode parameter set by the user to a value between 0 and 7 Gf maxblk=0, only block 0 will be trans- mitted). 01 32 L User data or password Block 7 L, User data Block 6 L User data Block 5 L User data Block 4 L User data Block 3 L User data Block 2 L User data Block 1 L Configuration data Block 0 | | 32 bits [ | Not transmitted Figure 3. Memory map Carrier frequency 4 Manchester Biphase From memory mux PSK1 PSK2 vy PSK3 FSK1, la re mUX}__$ to load FSK2, 2a a Figure 4. Modulator block diagram Rev. A2, 11-Oct-99 3 (20)TEMIC Semiconductors 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 reserved lock bit (never transmitted) Key: AOR BT ST PWD STOP BR MS1 MS2 PSKCF MAXBLK reserved Anwer-On-Request use Block Terminator use Sequence Terminator use Password obey stop header (active low!) Bit Rate Modulator Stage 1 Modulator Stage 2 PSK Clock Frequency see Maxblock feature do not use * Bit 15 and 24 must always be at 0, otherwise malfunction will appear. [2] [1] [0] Ree OOCe BR Ree COOrFF CSC rPOrOrOFro Figure 5. MSI MS2_ PSKCF MAXBLK | U1) (0) 2) U1 101 (4) fol} fs 21 C4 10] resd Q Q *yseSTOP useBT AOR useST usePWD send blocks: 0 0 0 0 0 0 1 1 0 1 =O 1to2 0 1 1 1to3 1 0 0 1to4 1 0 1 I1to5 1 1 O 1to6 1 1 1 = I1to7 0 O RF2 0 1 RF4 1 O RFS 1 1. reserved 0 O O. direct 0 O 1 psk1 (phase change when input changes) 0 1 O- psk2 (phase change on bitclk if input high) 0 1 1 psk3 (phase change on rising edge of input) o/p freq. DATA=1 DATA=0 1 O O. fsk1 rf/8 rf/5 1 O 1 fsk2 rf/8 rf/10 1 1 #O. fskla rf/5 rf/8 1 1 #1 fsk2a rf/10 rf/8 0 O. direct 0 1 Manchester 1 O Biphase 1 1. reserved RF/8 bitrate_8cpb RF/16 bitrate_16cpb RF/32 bitrate_32cpb RF/40 bitrate_40cpb RF/50 bitrate_50cpb RF/64 bitrate_64cpb RF/100 bitrate_100cpb RF/128 bitrate_128cpb Memory map of block 0 4 (20) Rev. A2, 11-Oct-99TEMIC Semiconductors e5551 Operating the e5551 General The basic functions of the e5551 are: supply IC from the coil, read data from the EEPROM to the reader, write data into the IC and program these data into the EEPROM. Several errors can be detected to protect the memory from being written with the wrong data (see figure 20). Supply The e5551 is supplied via a tuned LC circuit which is con- nected to the Coill and Coil2 pads. The incoming RF (actually a magnetic field) induces a current into the coil. The on-chip rectifier generates the dc supply voltage (Vad, Vss pads). Overvoltage protection prevents the IC from damage due to high-field strengths. Depending on the coil, the open-circuit voltage across the LC circuit can reach more than 100 V. The first occurrence of RF trig- gers a power-on reset pulse, ensuring a defined start-up state. Reader coil IAC Energy \_ 125 kHz <.\__ Data Read Reading is the default mode after power-on reset. It is done by switching a load between the coil pads on and off. This changes the current through the IC coil, which can be detected from the reader unit. Start-Up The many different modes of the e5551 are activated after the first readout of block 0. The modulation is off while block 0 is read. After this set-up time of 256 field clock periods, modulation with the selected mode starts. Any field gap during this initialization will restart the complete sequence. Read Datastream The first block transmitted is block 1. When the last block is reached, reading restarts with block 1. Block 0, which contains mode data, is normally never transmitted. How- ever, the mode register is continuously refreshed with the contents of EEPROM block 0. Tuned LC e5551 Na oO oo oa PN | Figure 6. Application circuit Vooil 1 Coil 2 <2 ms Damping on Damping off x ping -| . Power-on reset Loading block 0 (256 FC=2 ms) Read data with configured modulation and bitrate * FC > Field clocks Figure 7. Voltage at Coill/Coil2 after power-on Rev. A2, 11-Oct-99 5 (20)e5551 TEMIC Semiconductors ~sLeee See | Bit period Block terminator ______ | Data bit 1 Block ( | Last bit First bit Sequence terminator ~~ Data bit 1 Data bit 1 - Sequence ( | Last bit First bit | ) } Vcoill-Coil2 First bit 0 or 71 Waveforms for different t modulations Manchester FSK PSK Terminator not suitable for Biphase modulation Figure 8. Terminators ST BT [ ote | ott | | o] Block | Block 2 | Block7 | Block 1 | Block 2 | Loading block 0 Sequence terminator I | | on | off | | oY Block 1 | Block 2 II Block 7 VA Block 1 | Block 2 | Loading block 0 Block terminator | off | on | | 0 y Block 1 YJ Block 2 I| Block 7 4 Block 1 (J Block 2 (J Loading block 0 - | on | on | | of 4] Block 1 YJ Block 2 i Block 7 (4 Block 1 4 Block 2 Y Loading block 0 Figure 9. Read data streams and terminators MAXBLK =5 | 0 | Block 1 | | Block 4 | Block 5 | Block 1 | Block 2 | Loading block 0 MAXBLK =2 | 0 | Block 1 | Block 2 | Block 1 | Block 2 | Block 1 | Loading block 0 MAXBLK =0 | 0 | Block 0 | Block 0 | Block 0 | Block 0 | Block 0 | Loading block 0 Figure 10. MAXBLK examples 6 (20) Rev. A2, 11-Oct-99TEMIC Semiconductors e5551 Maxblock Feature If it is not necessary to read all user data blocks; the MAXBLK field in block 0 can be used to limit the number of blocks read. For example, if MAXBLK = 5, the e5551 repeatedly reads and transmits only blocks 1 to 5 (see figure 10). If MAXBLK is set to 0, block 0 which is normally not transmitted can be read. Terminators The terminators are (optionally selectable) special damping patterns, which may be used to synchronize the reader. There are two types available; a block terminator which precedes every block, and a sequence terminator which always follows the last block. The sequence terminator consists of two consecutive block terminators. The terminators may be individually enabled with the mode bits ST (sequence terminator enable) or BT (block terminator enable). Note: It is not possible to include a sequence terminator in a transmission where MAXBLK = 0. Table 4. e5551 modes of operation Direct Access The direct access command allows the reading of an indi- vidual block by sending the OP-code (10), the lock-bit and the 3-bit address. Note: PWD has to be 0. Modulation and Bitrate There are two modulator stages in the e5551 (see figure 4) whose mode can be selected using the appropriate bits in block 0 (MS1[1:0] and MS[2:0]). Also the bitrate can be selected using BR[2:0] in block 0. These options are described in detail in figures 21 through 26. Anticollision Mode When the AOR bit is set, the IC does not start modulation after loading configuration block 0. It waits for a valid AOR data stream (wake-up command) from the reader before modulation is enabled. The wake-up command consists of the OP-code ( 10) folowing by a valid password. The IC will remain active until the RF field is turned off or a stop OP-code is received. Anticollision mode: @ Modulation starts after wake-up with a matching PWD @ Programming needs valid PWD @ AOR allows programing with read protection (no read after write) STOP OP-code (' 11) defeats modu- lation until RF field is turned off Password mode: @ Modulation starts after reset @ Programming needs valid PWD 0 1 0 e command possible Modulation starts after wake-up @ Programming with modulation defeat without previous wake-up @ AOR allows programing with read protection (no read after write) 0 e Modulation starts after reset @ Direct access command @ Programming without password See corresponding modes above STOP OP-code ignored, modulation continues until RF field is turned off Rev. A2, 11-Oct-99 7 (20)5551 TEMIC Modulation on Vooil 1 Coil 2 \ Loading block 0 No modulation OP-code ( 10) followed by valid password POR (STOP = 0, AOR = 1) Figure 11. Answer-on-request (AOR) mode BASE station TAG init tags with AOR =1, PWD =1, Stop =0" Field OFF > ON POWER ON RESET read configuration wait for t w> 2.5ms v wait for OPCODE + PWD (== wake up command) write damping select single tag send OPCODE + PWD ) (== wake up command) PWD correct ? v send block 1..MAXBLK| [aevoiedae] (Ta MANE y send stop command ) enter AOR mode v internal reset sequence all tags read ? EXIT Figure 12. Anticollision procedure 8 (20) Rev. A2, 11-Oct-99TEMIC Semiconductors e5551 >64 FCs = stop write RF Field Gap Write mode Data Clock f& ! nn Field clock fF Read mode, Writing Programming Read mode Figure 13. Signals during writing 1 16 32 48 64 Write data decoder Figure 14. Write data decoding schemes OP Standard write {10/1 Data bits 32 |2 Addr 0 OP Password mode [10] 1 Password 32|L [1 Data bits 32 |2 Addr 0 OP AOR (wake-up command)| 10] 1 Password 32 | Direct access OP OP Stop command Figure 15. e5551 OP-code formats Write Writing data into the IC occurs via the TEMIC write method. It is based on interrupting the RF field with short gaps. The time between two gaps encodes the 0/1 information to be transmitted. Start Gap The first gap is the start gap which triggers write mode. In write mode, the damping is permanently enabled which eases gap detection. The start gap may need to be longer than subsequent gaps in order to be detected reliably. A start gap will be detected at any time after block 0 has been read (field-on plus approximately 2 ms). Rev. A2, 11-Oct-99 9 (20)e5551 TEMIC Semiconductors Read mode Write mode ~ Start of writing (start gap) Figure 16. Start of writing Decoder The duration of the gaps is usually 50 to 150 us. The time between two gaps is nominally 24 field clocks for a 0 and 56 field clocks for a 1. When there is no gap for more than 64 field clocks after previous gap, the IDIC exits write mode; it starts with programming if the correct number of valid bits were received. If there is a gap fail i.e., one or more of the intervals did represent not a valid O or 1 the IC does not program, but enters read mode beginning with block 1, bit 1. Writing Data into the e5551 The e5551 expects a two bit OP-code first. There are two valid OP-codes ( 10 and 11). If the OP-code is invalid, the e5551 starts read mode beginning with block 1 after the last gap. The OP-code ( 10) is followed by different information (see figure 15): @ Standard writing needs the OP-code, the lock bit, the 32 data bits and the 3-bit block address. @ Writing with usePWD set requires a valid password between OP-code and address/data bits. @ In AOR mode with usePWD, OP-code and a valid password are necessary to enable modulation. @ The STOP OP-code is used to silence the e5551 (dis- able damping until power is cycled). Note: The data bits are read in the same order as written. STOP OP-Code The STOP OP-code (11) is used to stop modulation until a power-on reset occurs. This feature can be used to have a steady RF field where single transponders are collected one by one. Each IC is read and than disabled, so that it does not interfere with the next IC. Note: The STOP OP-code should contain only the two OP-code bits to disable the IC. Any additional data sent will not be ignored, and the IC will not stop modulation. Standard OP-code Start gap Q A Stop OP-code Read mode Write mode Figure 17. OP-code transmission Password When password mode is on (usePWD = 1), the first 32 bits after the OP-Code are regarded as the password. They are compared bit-by-bit with the contents of block 7, starting at bit 1. If the comparison fails, the IC will not program the memory, but restart in read mode at block 1 once writing has completed. Notes: @ If PWD is not set, but the IC receives a write datastream containing any 32 bits in place of a pass- word, the IC will enter programming mode. @ The first 4 bits of the password have to be 0. @ In password mode, MAXBLK should be set to a value below 7 to prevent the password from being trans- mitted by the e5551. @ Every transmission of 2 OP-code bits, 32 password bits, one lock bit, 32 data bits and 3 address bits (= 70 bits) needs about 35 ms. Testing all 232 possible combinations (about 4.3 billion) takes about 40,000 h, or over four years. This is a sufficient password protection for a general-purpose IDIC. 10 (20) Rev. A2, 11-Oct-99TEMIC Semiconductors e5551 -_ Writing done (> 64 clocks since last gap) Write mode Programming ends Check V pp 16 ms pla a 0.12ms_ Programming starts (HV at EEPROMs) HV on lw \a~ [ HV on for testing if Vpp is ok Reading starts Modulation | No modulation Operation | Write | Vpp/Lock ok? Program EEPROM READ Figure 18. Programming Vcoil 1 Coil 2 16 ms Read programming block Read next block rogramming Write data into the IC (= block 0) with updated modes (e.g., new bitrate) Figure 19. Coil voltage after programming of block 0 Programming When all necessary information has been written to the e5551, programming may proceed. There is a 32-clock delay between the end of writing and the start of pro- gramming. During this time, Vpp the EEPROM programming voltage is measured and the lock bit for the block to be programmed is examined. Further, Vpp is continually monitored throughout the programming cycle. If at any time Vpp is too low, the chip enters read mode immediately. The programming time is 16 ms. After programming is done, the e5551 enters read mode, starting with the block just programmed. If either block or sequence terminators are enabled, the block is pre- ceded by a block terminator. If the mode register (block 0) has been reprogrammed, the new mode will be activated after the just-programmed block has been transmitted using the previous mode. Error Handling Several error conditions can be detected to ensure that only valid bits are programmed into the EEPROM. There are two error types which lead to different actions. Errors During Writing There are four detectable errors which could occur during writing data into the e5551: @ Wrong number of field clocks between two gaps @ The OP-code is neither the standard OP-code (10) nor the stop OP-code ( 11) @ Password mode is active but the password does not match the contents of block 7 @ The number of bits received is incorrect; valid bit counts are @ Standard write 38 bits (PWD not set) @ Password write 70 bits (PWD set) @ AOR wake-up 34 bits @ Stop command 2 bits If any of these four conditions are detected, the IC starts read mode immediately after leaving write mode. Reading starts with block 1. Rev. A2, 11-Oct-99 11 (20)5551 TEMIC Errors During Programming If writing was successful, the following errors could Vpp is too low prevent programming: In these cases, programming stops immediately. The IC reverts to read mode, starting with the currently addressed @ The lock bit of the addressed block is set block. Loading block 0 READ _ k A . | addr= 1 | addr = current | Write mode fail Stop fog | OP-code | Figure 20. Functional diagram of the e5551 12 (20) Rey. A2, 11-Oct-99TEMIC e5551 Semiconductors 91 91 91 pT 6 Pleyel popos oseydig yeusis JOye[NPOU! payJoAuy oT. ST. Ulvaljs Bye > | +> Od 8 O48 OEE aE GP==-S eS eTe TESTED (OD SYOTD PIP OS = oe1 eG I ST. 6 Pleyel _ | _> Od 8 O48 > OD SOD PIP OS = ae BR I pspos JoysoyouryA[ yeusis JOJe[NPOU! PoLISAUT Ulvaljs Bye Figure 22. Example of Biphase coding with data rate RF/16 Figure 21. Example of Manchester coding with data rate RF/16 13 (20) Rev. A2, 11-Oct-99TEMIC e5551 _'+_ O48 O48 ony EE G=EE=gISSEEDUEUEESESTEEEEL a! (OD SYOTD PPL 91 = a]e1 BG I Te (OD S30[D PIS OF =o]el Bled I Pleyel T/T Jortwogns yeusis JO}e[NPOU! psyJoAuyT Ulvaljs Bye Pleyel srra aly grt =97 yeusis JOJP[NPOUL PoVISAUy] Ulvaljs Bye Figure 24. Example of PSK1 coding with data rate RF/16 Figure 23. Example of FSK coding with data rate RF/40, sub- RF/5 carrier fy = RF/8, fy Rev. A2, 11-Oct-99 14 (20)TEMIC Semiconductors e5551 5 SS 91. OT OT. oT. = 1 OT. OT OT. IL | = | 5 O48 O48 + (OD SYOTD PIPL 91 = a]e1 eG nnng.annr IL O48 O48 DOE IEEE p-TEnpUeS SEDNENTEUEESUEEEEELed (OD SYOTD PIPL 91 = a]e1 eG I Pleyel dda Jettes qns Jeusis Joye[npour Ppoveauy Ulvaljs Bye Pleyel dda Jetreoqns Jeusis Joye[Npour PoveAuy Uieval]s seyecy Figure 26. Example of PSK3 coding with data rate RF/16 Figure 25. Example of PSK2 coding with data rate RF/16 15 (20) Rev. A2, 11-Oct-995551 TEMIC Ipp 100 Vop Coil 1 v Coil 2 Vsg Vpp Coil= 1.5 V Figure 27. Measurement setup for Ipp Figure 28. Simplified damping circuit Application Example I Input capacitance From AC 740 wH 4.2mH 360 pF 5 pF static, 25 pF dynamic oscillator 125 kHz Energy Coil 1 (Pin 8) DIA | { ( 5551 HULU <__Y Coil 2 (Pin 1) To read Data amplifier 1 fres = = 125 kHz 2n LC 2.2 nF Figure 29. Typical application circuit 16 (20) Rey. A2, 11-Oct-99TEMIC Semiconductors e5551 Absolute Maximum Ratings Maximum DC current into COIL 1/ COIL 2 Teoil 10 mA Maximum AC current into COIL 1/ COIL 2, f = 125 kHz Icoil pp 20 mA Power dissipation (dice) )) Prot 100 mw Electro-static discharge maximum to Vmax 2000 Vv MIL-Standard 883 C method 3015 Operating ambient temperature range Tamb 40 to +85 C Storage temperature range 2) Tsto 40 to +125 C Maximum assembly temperature for less than 5 min >) Tsla +150 C Notes: 1) Free-air condition, time of application: 1 s 2) Data retention reduced 3) Assembly temperature of 150C for less than 5 minutes does not affect the data retention. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Operating Characteristics Tamb = 25C; frp = 125 kHz, reference terminal is Vss RF frequency range fRr 100 125 150 kHz Supply current Read and write over the full (see figure 27) temperature range Ipp 5 75 vA Programming over the full Ipp 100 200 pA temperature range Clamp voltage 10 mA current into Coil1/2 Vel 9.5 11.5 Vv Programming voltage From on-chip HV- Vopp 16 20 Vv Generator Programming time tp 18 ms Startup time tstartup 4 ms Data retention 1) tretention 10 Years Programming cycles 1) Neycle 100 000 Supply voltage Read and write Vpp 1.6 Vv Supply voltage Read-mode, T = 30C Vpp 2.0 Vv Coil voltage Read and write Veoil pp 6.0 Vv Coil voltage Programming, Veoil pp 10 Vv RF field not damped Damping resistor Rp 300 Q Note 1) parameters for dow (= die-on-wafer) and ICs assembled in standard package. Ordering Information Since EEPROM performance may be influenced by assembly and packaging, we can confirm the e5551A-DOW e5551A-DIT DOW Dice in tray Default programming: Manchester modulation, RF/32, MAXBLK = 2 Rev. A2, 11-Oct-99 17 20)5551 TEMIC Chip Dimensions (um) 18 (20) Rey. A2, 11-Oct-99TEMIC 5551 Chip Dimensions (um) Rev. A2, 11-Oct-99 19 (20)