CY7C1392CV18-200BZC - Cypress Semiconductor

18-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-07162 Rev. *C Revised May 22, 2008

Features

■18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■300 MHz clock for high bandwidth

■2-word burst for reducing address bus frequency

■Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■Two input clocks (K and K) for precise DDR timing

❐SRAM uses rising edges only

■Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■Synchronous internally self-timed writes

■DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

■Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■1.8V core power supply with HSTL inputs and outputs

■Variable drive HSTL output buffers

■Expanded HSTL output voltage (1.4V–VDD)

■Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■Offered in both Pb-free and non Pb-free packages

■JTAG 1149.1 compatible test access port

■Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1392CV18 – 2M x 8

CY7C1992CV18 – 2M x 9

CY7C1393CV18 – 1M x 18

CY7C1394CV18 – 512K x 36

Functional Description

The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and

CY7C1394CV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with Double Data Rate Separate IO (DDR-II SIO)

architecture. The DDR-II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR-II

SIO has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common IO devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K if C/C are not provided. Each address

location is associated with two 8-bit words in the case of

CY7C1392CV18, two 9-bit words in the case of

CY7C1992CV18, two 18-bit words in the case of

CY7C1393CV18, and two 36-bit words in the case of

CY7C1394CV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to ca pture

data separately from each individual DDR-II SIO SRAM in the

system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 820 770 700 575 485 mA

x9 825 775 700 575 490

x18 865 800 725 600 500

x36 935 850 770 630 540

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 2 of 30

Logic Block Diagram (CY7C1392CV18)

Logic Block Diagram (CY7C1992CV18)

1M x 8 Array

CLK

A(19:0)

Gen.

Control

Logic

Address

D[7:0]

Read Add. Decode

Read Data Reg.

LD Q[7:0]

Reg.

NWS[1:0]

VREF

Write Add. Decode

Write

Data Reg

R/W

DOFF

1M x 8 Array

Write

Data Reg

Control

Logic

1M x 9 Array

CLK

A(19:0)

Gen.

Control

Logic

Address

D[8:0]

Read Add. Decode

Read Data Reg.

LD Q[8:0]

Reg.

BWS[0]

VREF

Write Add. Decode

Write

Data Reg

R/W

DOFF

1M x 9 Array

Write

Data Reg

Control

Logic

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 3 of 30

Logic Block Diagram (CY7C1393CV18)

Logic Block Diagram (CY7C1394CV18)

512K x 18 Array

CLK

A(18:0)

Gen.

Control

Logic

Address

D[17:0]

Read Add. Decode

Read Data Reg.

LD Q[17:0]

Reg.

BWS[1:0]

VREF

Write Add. Decode

Write

Data Reg

18 18

R/W

DOFF

512K x 18 Array

Write

Data Reg

Control

Logic

256K x 18 Array

CLK

A(17:0)

Gen.

Control

Logic

Address

D[35:0]

Read Add. Decode

Read Data Reg.

LD Q[35:0]

Reg.

BWS[3:0]

VREF

Write Add. Decode

Write

Data Reg

36 36

R/W

DOFF

256K x 18 Array

Write

Data Reg

Control

Logic

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 4 of 30

Pin Configuration

The Pin Configuration for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows . [1]

165-Ball FBGA (13 x 15 x 1 .4 mm) Pinout

CY7C1392CV18 (2M x 8)

12345678910 11

ACQ NC/72M A R/W NWS1KNC/144M LD A NC/36M CQ

BNC NC NC A NC/288M K NWS0ANCNCQ3

CNC NC NC VSS AAAV

SS NC NC D3

DNC D4 NC VSS VSS VSS VSS VSS NC NC NC

ENC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2

FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

GNC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC

HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JNC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1

KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

LNC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0

MNC NC NC VSS VSS VSS VSS VSS NC NC D0

NNC D7 NC VSS AAAV

SS NC NC NC

PNC NC Q7 A A C A A NC NC NC

RTDO TCK A A A C AAATMSTDI

CY7C1992CV18 (2M x 9)

12345678910 11

ACQ NC/72M A R/W NC K NC/144M LD A NC/36M CQ

BNC NC NC A NC/288M K BWS0ANCNCQ4

CNC NC NC VSS AAAV

SS NC NC D4

DNC D5 NC VSS VSS VSS VSS VSS NC NC NC

ENC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3

FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

GNC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC

HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JNC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2

KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

LNC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1

MNC NC NC VSS VSS VSS VSS VSS NC NC D1

NNC D8 NC VSS AAAV

SS NC NC NC

PNC NC Q8 A A C A A NC D0 Q0

RTDO TCK A A A C AAATMSTDI

Note

1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 5 of 30

CY7C1393CV18 (1M x 18)

12345678910 11

ACQ NC/144M NC/36M R/W BWS1KNC/288M LD A NC/72M CQ

BNC Q9 D9 A NC K BWS0ANCNCQ8

CNC NC D10 VSS AAAV

SS NC Q7 D8

DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7

ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6

FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5

GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5

HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4

KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3

LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2

MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2

NNC D17 Q16 VSS AAAV

SS NC NC D1

PNC NC Q17 A A C A A NC D0 Q0

RTDO TCK A A A C AAATMSTDI

CY7C1394CV18 (512K x 36)

12345678910 11

ACQ NC/288M NC/72M R/W BWS2KBWS1LD NC/36M NC/144M CQ

BQ27 Q18 D18 A BWS3KBWS

0AD17Q17Q8

CD27 Q28 D19 VSS AAAV

SS D16 Q7 D8

DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7

EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6

FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5

GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5

HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4

KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3

LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2

MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2

ND34 D26 Q25 VSS AAAV

SS Q10 D9 D1

PQ35 D35 Q26 A A C A A Q9 D0 Q0

RTDO TCK A A A C AAATMSTDI

Pin Configuration (continued)

The Pin Configuration for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows . [1]

165-Ball FBGA (13 x 15 x 1 .4 mm) Pinout

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 6 of 30

Pin Definitions

Pin Name IO Pin Descripti on

D[x:0] Input-

Synchronous Data input signals. Sampled on the rising edge of K and K clocks during valid write operations.

CY7C1392CV18 - D[7:0]

CY7C1992CV18 - D[8:0]

CY7C1393CV18 - D[17:0]

CY7C1394CV18 - D[35:0]

LD Input-

Synchronous Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition

includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period

of bus activity).

NWS0,

NWS1Nibble Write Select 0, 1 − Active LOW (CY7C1392CV18 On ly). Sampled on the rising edge of the K

and K clocks during Write operations. Used to select which nibble is written into the device during the

current portion of the Write operations.Nibbles not written remain unaltered.

NWS0 contro ls D [3:0] and NWS1 controls D[7:4].

All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device.

BWS0,

BWS1,

BWS2,

BWS3

Input-

Synchronous Byte Write Select 0, 1, 2 and 3 − Active LOW . Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the write

operations. Bytes not written remain unaltered .

CY7C1992CV18 − BWS0 controls D[8:0]

CY7C1393CV18 − BWS0 controls D[8:0], BWS1 controls D[17:9].

CY7C1394CV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls

D[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device.

A Input-

Synchronous Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These

address inputs are multiplexed for both read and write operations. Internally, the device is organized as

2M x 8 (2 arrays each of 1M x 8) for CY7C1392CV18, 2M x 9 (2 arrays each of 1M x 9) for CY7C1992CV18,

1M x 18 (2 arrays each of 512K x 18) for CY7C1393CV18 and 512K x 36 (2 arrays each of 256K x 36)

for CY7C1394CV18. Therefore, only 20 address inputs are needed to access the entire memory array of

CY7C1392CV18 and CY7C1992CV18, 19 address inputs for CY7C1393CV18 and 18 address inputs for

CY7C1394CV18. These inputs are ignored when the app ropriate port is deselected.

Q[x:0] Outputs-

Synchronous Data output signals. These pins drive out the requested data during a read operation. Valid data is driven

out on the rising edge of both the C and C clocks during read operations, or K and K when in single clock

mode. When the read port is deselected, Q[x:0] are automatically tri-stated.

CY7C1392CV18 − Q[7:0]

CY7C1992CV18 − Q[8:0]

CY7C1393CV18 − Q[17:0]

CY7C1394CV18 − Q[35:0]

R/W Input-

Synchronous Synchronous Read/Write input. When LD is LOW, this input designates the access type (read when

R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times

around the edge of K.

C Input Clock Positive input cl ock for output data . C is used in conjunction with C to clock out the read data from the

device. C and C can be used together to deskew the flight times of various devices on the board back to

the controller. See Application Example on page 9 for further details.

CInput Clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 9 for further details.

K Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and

to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K.

KInput Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and

to drive out data through Q[x:0] when in single clock mode.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 7 of 30

CQ Echo Clock CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings

for the echo clocks is shown in the Switchin g Characteristics on page 23.

CQ Echo Clock CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings

for the echo clocks is shown in the Switchin g Characteristics on page 23.

ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data

bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor

connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which

enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-

nected.

DOFF Input DLL turn off − Active LOW . Connecting this pin to ground turns off the DLL inside the device. The timing

in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves in DDR-I

mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167

MHz with DDR-I timing.

TDO Output TDO for JTAG.

TCK Input TCK pin for JTAG.

TDI Input TDI pin for JTAG.

TMS Input TMS pin for JTAG.

NC N/A Not connected to the die. Can be tied to any voltage level.

NC/36M N/A Not connected to the die. Can be tied to any voltage level.

NC/72M N/A Not connected to the die. Can be tied to any voltage level.

NC/144M N/A Not connected to the die. Can be tied to any voltage level.

NC/288M N/A Not connected to the die. Can be tied to any voltage level.

VREF Input-

Reference Reference Voltage in put. Static input used to set the reference level for HSTL inputs, Outputs, and AC

measurement points.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the device.

VDDQ Power Supply Power supply inputs for the outputs of the device.

Pin Definitions (continued)

Pin Name IO Pin Descripti on

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 8 of 30

Functional Overview

The CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and

CY7C1394CV18 are synchronous pipelined Burst SRAMs

equipped with a DDR-II Separate IO interface, which operates

with a read latency of one and half cycles when DOFF pin is tied

HIGH. When DOFF pin is set LOW or connected to VSS the

device behaves in DDR-I mode with a read latency of one clock

cycle.

Accesses are initiated on the rising edge of the positive input

clock (K). All synchronous input timing is referenced from the

rising edge of the input clocks (K and K) and all output timing is

referenced to the rising edge of the output clocks (C/C, or K/K

when in single clock mode).

All synchronous data inputs (D[x:0]) pass through input registers

controlled by the rising edge of the input clocks (K and K). All

synchronous data outputs (Q[x:0]) pass through output registers

controlled by the rising edge of the output clocks (C/C, or K/K

when in single-clock mode).

All synchronous control (R/W , LD, BWS[0:X]) inputs p ass through

input registers controlled by the rising edge of the input clock (K).

CY7C1393CV18 is described in the following sections. The

same basic descriptions apply to CY7C1392CV18,

CY7C1992CV18, and CY7C1394CV18.

Read Operations

The CY7C1393CV18 is organized internally as two arrays of

512K x 18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

R/W HIGH and LD LOW at the rising edge of the positive input

clock (K). The address presented to address inputs is stored i n

the read address register. Following the next K clock rise the

corresponding lowest order 18-bit word of data is driven onto the

Q[17:0] using C as the output timing reference. On the subse-

quent rising edge of C, the next 18-bit data word is driven onto

the Q[17:0]. The requested data is valid 0.45 ns from the rising

edge of the output clock (C or C, or K and K when in single clock

mode, for 200 MHz and 250 MHz devi ce). Read accesses can

be initiated on every rising edge of the positive input clock (K).

This pipelines the data flow such that d ata is transferred out of

the device on every rising edge of the output clocks, C/C (or K/K

when in single clock mode).

The CY7C1393CV18 first comp letes the pending read transac-

tions, when read access is deselected. Synchronous internal

circuitry automatically tri-states the output following the next

rising edge of the positive output clock (C).

Write Operations

Write operations are initiated by asserting R/W LOW and LD

LOW at the rising edge of the positive input clock (K). The

address presented to address inputs is stored in the write

address register. On the following K clock rise the data presented

to D[17:0] is latched and stored into the 18-bit write data register,

provided BWS[1:0] are both a sserted active. On the su bsequent

rising edge of the negative input clock (K) the information

presented to D[17:0] is also stored into the write data register,

provided BWS[1:0] are both asserted active. The 36 bits of data

are then written into the memory array at the spe cified locati on.

Write accesses can be initiated on every rising edge of the

positive input clock (K). This pipelines the data flow such that 18

bits of data can be transferred into the device on every rising

edge of the input clocks (K and K).

When Write access is deselected, the device i gnores all inputs

after the pending write operations are completed.

Byte Write Operations

Byte write operati ons are supported by the CY7C1 393CV18. A

write operation is initiated as described in the Write Operations

section. The bytes that are written are determined by BWS0 and

BWS1, which are sampled with each set of 18-bit data words.

Asserting the appropriate Byte Write Select input during the data

portion of a write latches the d ata being presented and writes it

into the device. Deasserting the Byte Write Select input during

the data portion of a write enables the data stored in the d evice

for that byte to remain unaltered. This feature can be used to

simplify read/modify/write operations to a byte write operation.

Single Clock Mode

The CY7C1393CV18 can be used with a single clock that

controls both the input and output registers. In this mode the

device recognizes only a single pair of input clocks (K and K) that

control both the input and output registers. This operation is

identical to the operation if the device had zero skew between

the K/K and C/C clocks. All timing parameters remain the same

in this mode. To use this mode of operation, tie C and C HIGH at

power on. This function is a strap option and not alterable during

device operation.

DDR Operation

The CY7C1393CV18 enables high-performance operation

through high clock frequencies (achieved through pipelining) and

double data rate mode of operation.

If a read occurs after a write cycle, address and data for the write

are stored in registers. The write information must be stored

because the SRAM cannot perform the last word write to the

array without conflicting with the read. The data stays in this

after th e read(s), the stored data from the earlier write is written

into the SRAM array. This is called a posted wri te .

Depth Expansion

Depth expansion requires replicating the LD control signal for

each bank. All other control signals can be common between

banks as appropriate.

Programmable Impedance

An external resistor , RQ, must be connected between the ZQ pin

on the SRAM and VSS to enable the SRAM to adjust its output

driver impedance. The value of RQ must be 5x the value of the

intended line impedance driven by the SRAM. The allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15% is between 175Ω and 350Ω, with VDDQ =1.5V. The

output impedance is adjusted every 1024 cycles at power up to

account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the DDR-II to simplify data capture

on high-speed systems. Two echo clocks are generated by the

DDR-II. CQ is referenced with respect to C and CQ is referenced

with respect to C. These are free-running clocks and are

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 9 of 30

synchronized to the output clock of the DDR-II. In the single clock

mode, CQ is generated with respect to K and CQ is g enerated

with respect to K. The timing for the echo clocks is shown in

Switching Characteristics on page 23.

DLL

These chips use a Delay Lock Loop (DLL) that is designed to

function between 120 MHz and the specified maximum clock

frequency. During power up, when the DOFF is tied HIGH, the

DLL is locked after 1024 cycles of stable clock. The DLL can also

be reset by slowing or stopping the input clocks K and K for a

minimum of 30 ns. However , it is not necessary to reset the DLL

to lock it to the desired frequency. The DLL automatically locks

1024 clock cycles after a stable clock is presented. The DLL may

be disabled by applying ground to the DOFF pin. When the DLL

is turned off, the device behaves in DDR-I mode (with one cycle

latency and a longer access time). For information refer to the

application note DLL Considerati ons in QDRII™/DDRII.

Application Example

Figure 1 shows four DDR-II SIO used in an application.

Figure 1. Application Example

R/W

Vt = V

REF

CC#

CQ#

CC#K

BUS

MASTER

(CPU

ASIC)

SRAM 1

SRAM 4

DATA IN

DATA OUT

Address

LD#

R/W#

BWS#

SRAM 1 Input CQ

SRAM 1 Input CQ#

SRAM 4 Input CQ

SRAM 4 Input CQ#

Source K

Source K#

Delayed K

Delayed K#

R=50

Ohms

R = 250Ohms CQ

CQ#

R/W

R = 250Ohms

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 10 of 30

Truth Table

The truth table for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows. [2, 3, 4, 5, 6, 7]

Operation KLD R/W DQ DQ

Write Cycle:

Load address; wait one cycle;

input write data on consecutive K and K rising edges.

L-H L L D(A + 0) at K(t + 1)↑D(A + 1) at K(t + 1)↑

Read Cycle:

Load address; wait one and a half cycle;

read data on consecutive C and C rising edges.

L-H L H Q(A + 0) at C(t + 1)↑Q(A + 1) at C(t + 2)↑

NOP: No Operation L-H H X High-Z High-Z

Standby: Clock Sto pped Stopped X X Previous State Previous State

Write Cycle Descriptions

The write cycle description table for CY7C1392CV18 and CY7C1393CV18 follows. [2, 8]

BWS0/

NWS0

BWS1/

NWS1KKComments

L L L–H – During the data portion of a write sequence :

CY7C1392CV18 − b oth nibb les (D[7:0]) are written into the device,

CY7C1393CV18 − both bytes (D[17:0]) are written into the device.

L L – L-H During the data portion of a write sequence :

CY7C1392CV18 − b oth nibb les (D[7:0]) are written into the device,

CY7C1393CV18 − both bytes (D[17:0]) are written into the device.

L H L–H – During the data portion of a write sequence :

CY7C1392CV18 − o nly the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.

CY7C1393CV18 − o nly the lowe r byte (D[8:0]) is written into th e device, D[17:9] remains unaltered.

L H – L–H During the data portion of a write sequence :

CY7C1392CV18 − o nly the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.

CY7C1393CV18 − o nly the lowe r byte (D[8:0]) is written into th e device, D[17:9] remains unaltered.

H L L–H – During the data portion of a write sequence :

CY7C1392CV18 − o nly the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.

CY7C1393CV18 − o nly the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.

H L – L–H During the data portion of a write sequence :

CY7C1392CV18 − o nly the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.

CY7C1393CV18 − o nly the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.

H H L–H – No data is written into the devices during this portion of a write operati on.

H H – L–H No data is written into the devices during this portion of a write operation.

Notes

2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.

3. Device powers up deselected with the outputs in a tri-state condition.

4. “A” represents address location latched by the device s when transaction was initiated. A + 0, A + 1 represents the internal address sequence in t he burst.

5. “t” represents the cycle at which a Read/W rite operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.

6. Data input s are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permit s most rapid resta rt by overcoming transmission line charging

symmetrically.

8. Is based on a write cycle that was initiated in accordance with the Wri te Cycle Descrip tions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on

differen t portions of a write cycle, as long as the setup and hold requirements are achieved.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 11 of 30

Write Cycle Descriptions

The write cycle description table for CY7C1992CV18 follows. [2, 8]

BWS0K K Comments

L L–H – During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L – L –H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H L–H – No data is written into the device during this portion of a write operation.

H – L–H No data is written into the device during this portion of a write operation.

Write Cycle Descriptions

The write cycle description table for CY7C1394CV18 follows. [2, 8]

BWS0BWS1BWS2BWS3K K Comments

LLLLL–H–During the data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

LLLL–L–HDuring the data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

L H H H L–H – During the data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

L H H H – L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

H L H H L–H – Du ring the data portion of a write sequence, only the byte (D[17:9]) is written into

the device. D[8:0] and D[35:18] remains unaltered.

H L H H – L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into

the device. D[8:0] and D[35:18] remains unaltered.

H H L H L–H – During the data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains una ltered.

H H L H – L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains una ltered.

H H H L L–H – During the data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

H H H L – L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

HHHHL–H–No data is written into the device during this portion of a write operation.

HHHH–L–HNo data is written into the device during this portion of a write operation.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 12 of 30

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan Test Access

Port (T AP) in the FBGA p ackage. This part is fully compliant with

IEEE Standard #1149.1-2001. The TAP operates using JEDEC

standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternatively

be connected to VDD through a pull up resistor . TDO must be left

unconnected. Upon power up, the device comes up in a reset

state, which does not interfere with the operation of the device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller . All inputs are

captured on the rising edge of TC K. All outputs are driven from

the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. This pin may be le ft

unconnected if the TAP is not used. The pin is pulled up inter-

nally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers

and can be connected to the input of any of the registers. The

is loaded into the TAP instruction register. For information on

loading the instruction register, see the TAP Controller State

Diagram on page 14. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the most significan t bit (MSB) on any register.

Test Data-Out (T DO)

The TDO output pin is used to serially clock data out from the

registers. The output is active, depending upon the current state

of the TAP state machine (see Instruction Codes on page 17).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing T MS HIGH (VDD) for five rising

edges of TCK. This Reset does not affect the operation of the

SRAM and can be performed while the SRAM is operating. At

power up, the TAP is reset internally to ensure that TDO comes

up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins to scan

the data in and out of the SRAM test circuitry. Only one re gister

can be selected at a time through the instruction registers. Data

is serially loaded into the TDI pin on the rising edge of TCK. Data

is output on the TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be seriall y loaded into the instru ction

and TDO pins, as shown in TAP Controller Block Diagram on

page 15. Upon power up , the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state, as described

in the previous section.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a bin ary “01” pattern to allow for

fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

and TDO pins. This enables shifting of data through th e SRAM

with minimal delay. The bypass register is set LOW (V SS) when

the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register i s connected to all of the input and

output pins on the SRAM. Several No Connect (NC) pins are also

included in the scan register to reserve pins for higher density

devices.

The boundary scan register is loaded with the contents of the

RAM input and output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

pins when the controller is moved to the Shift-DR state. The

EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can

be used to capture the contents of the input and output ring.

The Boundar y Scan Orde r on page 18 shows the order in which

the bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected to

TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in Identification Register Definitions on

page 17.

TAP Instruction Set

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in Instruction

Codes on page 17. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions

are described in this section in detail.

Instructions are loaded into the T AP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO pins. To execute

the instruction after it is shifted in, the TAP controller must be

moved into the Update-IR state.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 13 of 30

IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into

the instruction register. It also places the instruction register

between the TDI and TDO pins and shifts the IDCODE out of the

device when the TAP controller enters the Shift-DR state. The

IDCODE instruction is loaded into the instruction register at

power up or whenever the TAP controller is supplied a

Test-Logic-Reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register

between the TDI and TDO pins when the TAP controller is in a

Shift-DR state. The SAMPLE Z command puts the output bus

into a High-Z state until the next command is supplied during the

Update IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Captu re-DR

state, a snapshot of data on the input and output pins is captured

in the boundary scan register.

The user must be aware that the TAP controller clock can o nly

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster . Because there

is a large difference in the clock frequencies, it is possible that

during the Capture-DR state, an input or output undergoes a

transition. The TAP may then try to capture a signal while in

transition (metastable state). This does not harm the device, but

there is no guarantee as to the value that is captured.

Repeatable results may not be possible.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the T AP controller's capture setup plus hold

times (tCS and tCH). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by

putting the T AP into the Shif t-DR state. This places the boundary

scan register between the TDI and TDO pin s .

PRELOAD places an initial data pattern at the latched parallel

outputs of the boundary scan register cells be fore the selection

of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required, that is, while the data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYP ASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through

the system output pins. This instruction also connects the

boundary scan register for serial access between the TDI and

TDO in the Shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE S t andard 1149.1 mandates that the TAP controller be able

to put the output bus into a tri-state mode.

The boundary scan registe r has a special bit located a t bit #47.

When this scan cell, called the “extest output bus tri-state,” is

latched into the preload register during the Update-DR state in

the TAP controller, it directly controls the state of the output

(Q-bus) pins, when the EXTEST is entered as the current

instruction. When HIGH, it enables the output buffers to drive the

output bus. When LOW, this bit places the output bus into a

High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that cell,

during the Shift-DR state. During Update-DR, the value l oaded

into that shift-register cell latches into the preload register . When

the EXTEST instruction is entered, this bit directly controls the

output Q-bus pins. Note that this bit is pre-set LOW to enable the

output when the device is powered up, and also when the TAP

controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 14 of 30

TAP Controller State Diagram

The state diagram for the TAP controller follows. [9]

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 15 of 30

TAP Controller Block Diagram

TAP Electrical Characteristics

Over the Operating Range [10, 11, 12]

Parameter Description Test Conditions Min Max Unit

VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V

VOH2 Output HIGH Voltage IOH = −100 μA1.6 V

VOL1 Output LOW Voltage IOL = 2.0 mA 0.4 V

VOL2 Output LOW Voltage IOL = 100 μA0.2V

VIH Input HIGH Voltage 0.65VDD VDD + 0.3 V

VIL Input LOW Voltage –0.3 0.35VDD V

IXInput and Output Load Current GND ≤ VI ≤ VDD –5 5 μA

012..29

3031

Boundary Scan Registe r

Identification Register

012..

.106

012

Instruction Register

Bypass Register

Selection

Circuitry Selection

Circuitry

TAP Controller

TDI TDO

TCK

TMS

Notes

10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).

12.All Voltage referenced to Ground.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 16 of 30

TAP AC Switching Characteristics

Over the Operating Range [13, 14]

Parameter Description Min Max Unit

tTCYC TCK Clock Cycle Time 50 ns

tTF TCK Clock Frequency 20 MHz

tTH TCK Clock HIGH 20 ns

tTL TCK Clock LOW 20 ns

Setup Times

tTMSS TMS Setup to TCK Clock Rise 5 ns

tTDIS TDI Setup to TCK Clock Rise 5 ns

tCS Capture Setup to TCK Rise 5 ns

Hold Times

tTMSH TMS Hold after TCK Clock Rise 5 ns

tTDIH TDI Hold after Clock Rise 5 ns

tCH Capture Hold after Clock Rise 5 ns

Output Times

tTDOV TCK Clock LOW to TDO Valid 10 ns

tTDOX TCK Clock LOW to TDO Invalid 0 ns

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test condi tions. [14]

Figure 2. TAP Timing and Test Conditions

(a)

TDO

= 20 pF

= 50

GND

0.9V

1.8V

ALL INPUT PULSES

0.9V

Test Clock

Test Mode Select

TCK

TMS

Test Data In

TDI

Test Data Out

TCYC

TMSH

TMSS

TDIS

TDIH

TDOV

TDOX

TDO

Notes

13.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

14.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 17 of 30

Identification Register Definitions

Instruction Field Value Description

CY7C1392CV18 CY7C1992CV18 CY7C1393CV18 CY7C1394CV18

Revision Numb er

(31:29) 000 000 000 000 Version number.

Cypress Device ID

(28:12) 11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type of

SRAM.

Cypress JEDEC ID

(11:1) 00000110100 00000110100 00000110100 00000110100 Allows unique

identification of

SRAM vendor.

ID Register

Presence (0) 1111Indicates the

presence of an ID

Scan Register Sizes

Instruction 3

Bypass 1

ID 32

Boundary Scan 107

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the input and output ring contents.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM outpu t drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI

and TDO. Does not affect the SRAM operation.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 18 of 30

Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 28 10G 56 6A 84 2J

16P299G575B853K

2 6N 30 11F 58 5A 86 3J

3 7P 31 11G 59 4A 87 2K

47N329F605C881K

5 7R 33 10F 61 4B 89 2L

6 8R 34 11E 62 3A 90 3L

7 8P 35 10E 63 1H 91 1M

8 9R 36 10D 64 1A 92 1L

9 11P 37 9E 65 2B 93 3N

10 10P 38 10C 66 3B 94 3M

11 10N 39 11D 67 1C 95 1N

12 9P 40 9C 68 1B 96 2M

13 10M 41 9D 69 3D 97 3P

14 11N 42 11B 70 3C 98 2N

15 9M 43 11C 71 1D 99 2P

16 9N 44 9B 72 2C 100 1P

17 11L 45 10B 73 3E 101 3R

18 11M 46 11A 74 2D 102 4R

19 9L 47 Internal 75 2E 103 4P

20 10L 48 9A 76 1E 104 5P

21 11K 49 8B 77 2F 105 5N

22 10K 50 7C 78 3F 106 5R

23 9J 51 6C 79 1G

24 9K 52 8A 80 1F

25 10J 53 7A 81 3G

26 11J 54 7B 82 2G

27 11H 55 6B 83 1J

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 19 of 30

Power Up Sequence in DDR-II SRAM

DDR-II SRAMs must be powered up and initialized in a

predefined manner to prevent undefined operations.

Power Up Sequence

■Apply power and drive DO FF either HIGH or LOW (all other

inputs can be HIGH or LOW).

❐Apply VDD before VDDQ.

❐Apply VDDQ before VREF or at the same time as VREF.

❐Drive DO FF HIGH.

■Provide stable DOFF (HIGH), power, and clock (K, K) for 1024

cycles to lock the DLL.

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencie s down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the

DLL may lock onto an incorrect frequency, causing unstable

SRAM behavior. T o avoid this, provide1024 cycles stable clock

to relock to the desired clock frequency.

Figure 3. Power Up Waveforms

> 1024 Stable clock

Start Normal

Operation

DOFF

Stable(< +/- 0.1V DC per 50ns )

Fix High (or tie to VDDQ)

DDQDD

/DDQDD

Clock Start (Clock Starts after Stable)

DDQ

Unstable Clock

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 20 of 30

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Tempe r at ure with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND........–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD

DC Applied to Outputs in High-Z ........–0.5V to VDDQ + 0.3V

DC Input Voltage [11]..............................–0.5V to VDD + 0.3V

Current into Outputs (LOW) ........................ ... .. ...........20 mA

Static Discharge Voltage (MIL-ST D-883, M. 3015).. > 2001V

Latch-up Current ................................................... > 200 mA

Operating Range

Range Ambient

Temperature (TA) VDD [15] VDDQ [15]

Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to

VDD

Industrial –40°C to +85°C

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range [12]

Parameter Description Test Conditio ns Min Typ Max Unit

VDD Power Supply Voltage 1.7 1.8 1.9 V

VDDQ IO Supply Voltage 1.4 1.5 VDD V

VOH Output HIGH Voltage Note 16 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V

VOL Output LOW Voltage Note 17 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V

VOH(LOW) Output HIGH Voltage IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V

VOL(LOW) Output LOW Voltage IOL = 0.1 mA, Nominal Impedance VSS 0.2 V

VIH Input HIGH Voltage VREF + 0.1 VDDQ + 0.3 V

VIL Input LOW Voltage –0.3 VREF – 0.1 V

IXInput Leakage Current GND ≤ VI ≤ VDDQ −5 5 μA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled −5 5 μA

VREF Input Reference Voltage [18] Typical Value = 0.75V 0.68 0.75 0.95 V

IDD [19] VDD Operating Supply VDD = Max,

IOUT = 0 mA,

f = fMAX = 1/tCYC

300 MHz (x8) 820 mA

(x9) 825

(x18) 865

(x36) 935

278 MHz (x8) 770 mA

(x9) 775

(x18) 800

(x36) 850

250 MHz (x8) 700 mA

(x9) 700

(x18) 725

(x36) 770

Notes

15.Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

16.Outputs are impeda nce controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17.Outputs are impeda nce controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18.VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54VDDQ, whichever is smaller.

19.The operation current is calculated with 50% read cycle and 50% write cycle.

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 21 of 30

IDD [19] VDD Operating Supply VDD = Max,

IOUT = 0 mA,

f = fMAX = 1/tCYC

200 MHz (x8) 575 mA

(x9) 575

(x18) 600

(x36) 630

167 MHz (x8) 485 mA

(x9) 490

(x18) 500

(x36) 540

ISB1 Automatic Power Down

Current Max VDD,

Both Ports Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC,

Inputs Static

300 MHz (x8) 275 mA

(x9) 275

(x18) 285

(x36) 300

278 MHz (x8) 265 mA

(x9) 265

(x18) 275

(x36) 290

250 MHz (x8) 255 mA

(x9) 255

(x18) 260

(x36) 275

200 MHz (x8) 245 mA

(x9) 245

(x18) 250

(x36) 260

167 MHz (x8) 240 mA

(x9) 240

(x18) 245

(x36) 255

AC Electrical Characteristics

Over the Operating Range [11]

Parameter Description Test Conditio ns Min Typ Max Unit

VIH Input HIGH Voltage VREF + 0.2 – – V

VIL Input LOW Voltage – – VREF – 0.2 V

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [12]

Parameter Description Test Conditio ns Min Typ Max Unit

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CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 22 of 30

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V 5 pF

CCLK Clock Input Capacitance 6 pF

COOutput Capacitance 7pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions 165 FBGA

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient) Test conditions follow standard test methods and

procedures for measuring the r mal impedance, in

accordance with EIA/JESD51.

18.7 °C/W

ΘJC Thermal Resistance

(Junction to Case) 4.5 °C/W

Figure 4. AC Test Loads and Waveforms

1.25V

0.25V

R = 50Ω

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device RL= 50Ω

Z0= 50Ω

VREF = 0.75V

[20]

0.75V

Under

Test

0.75V

Device

Under

Test

OUTPUT

0.75V

VREF

OUTPUT

(a)

Slew Rate = 2 V/ns

RQ =

250

(b)

RQ =

250

Note

20.Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input

pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.

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Document #: 001-07162 Rev. *C Page 23 of 30

Switching Characteristics

Over the Operating Range [20, 21]

Cypress

Parameter Consortium

Parameter Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Min Max Min Max Min Max Min Max Min Max

tPOWER VDD(Typical) to the First Access [22] 11111ms

tCYC tKHKH K Clock and C Clock Cycle Time 3.3 8.4 3.6 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns

tKH tKHKL Input Clock (K/K; C/C) HIGH 1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns

tKL tKLKH Input Clock (K/K; C/C) LOW 1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns

tKHKHtKHKHK Clock Rise to K Clock Rise and C

to C Rise (rising edge to rising edge) 1.49 – 1.6 – 1.8 – 2.2 – 2.7 – ns

tKHCH tKHCH K/K Clock Rise to C/C Clock Rise

(rising edge to rising edge) 01.4501.5501.802.202.7ns

Setup Times

tSA tAVKH Address Setup to K Clock Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

tSC tIVKH Control Setup to K Clock Rise

(LD, R/W)0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

tSCDDR tIVKH Double Data Rate Control Setup to

Clock (K/K) Rise

(BWS0, BWS1, BWS2, BWS3)

0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

tSD [23] tDVKH D[X:0] Set up to Clock (K/K) Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

Hold Times

tHA tKHAX Address Hold after K Clock Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

tHC tKHIX Control Hold after K Clock Rise

(LD, R/W)0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

tHCDDR tKHIX Double Data Rate Control Hold after

Clock (K/K) Rise

(BWS0, BWS1, BWS2, BWS3)

0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

Notes

21.When a part with a maximum fre quency above 167 MHz is operating at a lower clock frequency, it requires th e input timings of the freque ncy range in which it is being

operated and outputs data with the output timings of that frequency range.

22.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be

initiated.

23.For D2 data signal on CY7C1992CV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz, and 300 MHz frequencies.

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CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 24 of 30

Output Times

tCO tCHQV C/C Clock Rise (or K/K in single

clock mode) to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

tDOH tCHQX Data Output Hold after Output C/C

Clock Rise (Active to Active) –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

tCQOH tCHCQX Echo Clock Hold after C/C Clock

Rise –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

tCQD tCQHQV Echo Clock High to Data Valid 0.27 0.27 0.30 0.35 0.40 ns

tCQDOH tCQHQX Echo Clock High to Data Invalid –0.27 – –0.27 – –0.30 – –0.35 – –0.40 – ns

tCQH tCQHCQL Output Clock (CQ/CQ) HIGH [24] 1.24–1.35–1.55–1.95–2.45– ns

tCQHCQHtCQHCQHCQ Clock Rise to CQ Clock Rise

(rising edge to rising edge) [24] 1.24–1.35–1.55–1.95–2.45– ns

tCHZ tCHQZ Clock (C/C) Rise to High-Z

(Active to High-Z) [25, 26] – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

tCLZ tCHQX1 Clock (C/C) Rise to Low-Z [25, 26] –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

DLL T im i n g

tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns

tKC lock tKC lock DLL Lock Time (K, C) 1024 – 1024 – 1024 – 1024 – 1024 – Cycles

tKC Reset tKC Reset K Static to DLL Reset 30 30 30 30 30 ns

Switching Characteristics (continued)

Over the Operating Range [20, 21]

Cypress

Parameter Consortium

Parameter Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Min Max Min Max Min Max Min Max Min Max

Notes

24.These parameter s are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already

included in the tKHKH). These parameters are only guarante ed by design and are not tested in production

25.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.

26.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

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CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 25 of 30

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29]

1234567

R/W

READ

(burst of 2)

READ

(burst of 2)

READ

(burst of 2)

WRITE

(burst of 2)

WRITE

(burst of 2)

tKHCH

NOP NOP

CQ#

tKH tKHKH

tCO

tKL tCYC

ttHC

tSA tHA

tSD

tHD

tSD

tHD

tCLZ tDOH

tKH tKHKH

tKL tCYC

tCQD

tCCQO

tCQOH

tCCQO

tCQOH

DON’T CARE UNDEFINED

A0 A1 A2 A3 A4

D20 D21 D30 D31

Q40

Q11Q10 Q41

Q00 Q01

tCQDOH

CQH

CQHCQH

tCHZ

Notes

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

28.Outputs are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A4 = A3, then dat a Q40 = D30 and Q41 = D31. W rite dat a is forwarded imme diately as read resu lts. This note applies to t he whole diagram.

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Document #: 001-07162 Rev. *C Page 26 of 30

Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

300 CY7C1392CV18-300BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1992CV18-300BZC

CY7C1393CV18-300BZC

CY7C1394CV18-300BZC

CY7C1392CV18-300BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-300BZXC

CY7C1393CV18-300BZXC

CY7C1394CV18-300BZXC

CY7C1392CV18-300BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1992CV18-300BZI

CY7C1393CV18-300BZI

CY7C1394CV18-300BZI

CY7C1392CV18-300BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-300BZXI

CY7C1393CV18-300BZXI

CY7C1394CV18-300BZXI

278 CY7C1392CV18-278BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1992CV18-278BZC

CY7C1393CV18-278BZC

CY7C1394CV18-278BZC

CY7C1392CV18-278BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-278BZXC

CY7C1393CV18-278BZXC

CY7C1394CV18-278BZXC

CY7C1392CV18-278BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1992CV18-278BZI

CY7C1393CV18-278BZI

CY7C1394CV18-278BZI

CY7C1392CV18-278BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-278BZXI

CY7C1393CV18-278BZXI

CY7C1394CV18-278BZXI

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CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 27 of 30

250 CY7C1392CV18-250BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1992CV18-250BZC

CY7C1393CV18-250BZC

CY7C1394CV18-250BZC

CY7C1392CV18-250BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-250BZXC

CY7C1393CV18-250BZXC

CY7C1394CV18-250BZXC

CY7C1392CV18-250BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1992CV18-250BZI

CY7C1393CV18-250BZI

CY7C1394CV18-250BZI

CY7C1392CV18-250BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-250BZXI

CY7C1393CV18-250BZXI

CY7C1394CV18-250BZXI

200 CY7C1392CV18-200BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1992CV18-200BZC

CY7C1393CV18-200BZC

CY7C1394CV18-200BZC

CY7C1392CV18-200BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-200BZXC

CY7C1393CV18-200BZXC

CY7C1394CV18-200BZXC

CY7C1392CV18-200BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1992CV18-200BZI

CY7C1393CV18-200BZI

CY7C1394CV18-200BZI

CY7C1392CV18-200BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-200BZXI

CY7C1393CV18-200BZXI

CY7C1394CV18-200BZXI

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 28 of 30

167 CY7C1392CV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1992CV18-167BZC

CY7C1393CV18-167BZC

CY7C1394CV18-167BZC

CY7C1392CV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-167BZXC

CY7C1393CV18-167BZXC

CY7C1394CV18-167BZXC

CY7C1392CV18-167BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1992CV18-167BZI

CY7C1393CV18-167BZI

CY7C1394CV18-167BZI

CY7C1392CV18-167BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992CV18-167BZXI

CY7C1393CV18-167BZXI

CY7C1394CV18-167BZXI

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

[+] Feedback

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Document #: 001-07162 Rev. *C Page 29 of 30

Package Diagram

Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

PIN 1 CORNER

15.00±0.10

13.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25MCAB

Ø0.05 M C

0.15(4X)

0.35±0.06

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

PIN 1 CORNER

TOP VIEW

BOTTOM VIEW

2345678910

10.00

14.00

1110986754321

15.00±0.10

13.00±0.10

1.00

5.00

0.36

-0.06

+0.14

1.40 MAX.

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

NOTES :

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

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Document #: 001-07162 Rev. *C Revised May 22, 2008 Page 30 of 30

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document

are the tr ademarks of their respective holders.

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used

for medical, li fe support, life saving, crit ica l con tr ol or safety applica ti ons, unless pursuant to an express written agreement with Cypress. Furthermore, Cyp r ess d oe s no t a uth or iz e its products for use

as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support

systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright law s and i ntern atio nal t reaty p rovi sions. Cyp ress he reby gr ant s to licensee a per son al, non- exclu siv e, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Co de and derivative works for the sole p urpose of creating custo m software and or firmware in support of l icensee product to be used only in conjun ction with a Cypress

integrated ci rcuit as speci fied in the app licable agreem ent. Any reprod uction, modifi cation, transla tion, compila tion, or represent ation of th is Source Code exce pt as specified above is prohibited without

the express written perm i ssion of Cypr ess.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypre ss reserves the right to make ch anges without further notice to the materials described herein. Cypress does not

assume any liabili ty ar ising ou t of the ap plicati on or u se o f any prod uct or c ircuit descri bed h erein. Cypress d oes not aut horize its pro duct s for use a s critical compo nent s in life-support systems whe re

a malfunctio n or failure may reasonab ly be expected to result in significant injury t o the user. Th e inclusion of Cypress ’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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Document History Page

Document Title: CY7C1392CV18/CY7C1992CV18/CY7C1393CV18/C Y7C139 4CV18, 18-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

Document Number: 001-07162

Rev. ECN No. Submission

Date Orig. of

Change Description of Change

** 433284 See ECN NXR New data sheet

*A 462615 See ECN NXR Changed tCYC from 100 ns to 50 ns, changed tTH and tTL from 40 ns to 20 ns, changed

tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns

to 10 ns in TAP AC Switching Characteristics table

Modified Power-Up waveform

*B 1523386 See ECN VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated IDD/ISB

specs, Changed DLL minimum operating frequency from 80MHz to 120MHz, Changed

tCYC max spec to 8.4ns for all speed bins, Modified footnotes 20 and 28.

*C 2507766 05/23/08 VKN/PYRS Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C

to +125°C” in the “Maximum Ratings“ on page 20, Updated power up sequence

waveform and its description, Added footnote #19 related to IDD, Changed ΘJA spec

from 28.51 to 18.7, Changed ΘJC spec from 5.91 to 4.5, Changed JTAG ID [31:29]

from 001 to 000.

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