IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 1
DR036-0D 02/04/2005
Document Title
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Revision History
Revision No History Draft Date Remark
0A Initial Draft September 26,2002
0B Obselete partial refresh function September 05,2003
Obselete 5ns speed grade
Change ICC3P from 3mA to 5mA
0C Revise typo April 27,2004
0D Revise p.20,p.22 data and p.28 typo February 04,2005
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC42S32200
IC42S32200L
2Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
512K Words x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
· Concurrent auto precharge
· Clock rate:166/143/125 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (512K x 32bit x 4bank)
· Programmable Mode
-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
-Burst-Read-Single-Write
· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· Single +3.3V ±0.3V power supply
· Interface:LVTTL
· Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin
Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm
· Pb-free package is available.
DESCRIPTION
The ICSI IC42S32200 and IC42S32200L is a high-speed
CMOS configured as a quad 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).
Each of the 512K x 32 bit banks is organized as 2048 rows
by 256 columns by 32 bits.Read and write accesses start
at a selected locations in a programmed sequence.
Accesses begin with the registration of a BankActive
command which is then followed by a Read or Write
command
The ICSI IC42S32200 and IC42S32200L provides for
programmable Read or Write burst lengths of 1,2,4,8,or
full page, with a burst termination operation. An auto
precharge function may be enable to provide a self-timed
row precharge that is initiated at the end of the burst
sequence.The refresh functions,either Auto or Self
Refresh are easy to use.
By having a programmable mode register,the system
can choose the most suitable modes to maximize its
performance.
These devices are well suited for applications requiring
high memory bandwidth.
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 3
DR036-0D 02/04/2005
FUNCTIONAL BLOCK DIAGRAM
COLUMN
COUNTER
ADDRESS
BUFFER
A0
A9
BS0
BS1
DQM0~3
CLOCK
BUFFER
COMMAND
DECODER
Sense Amplifier
Row Decoder
Row Decoder
CLK
CKE
CS#
RAS#
CAS#
WE#
DQ0
DQ31
Row Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #2)
DQ
BUFFER
A
10/AP
REFRESH
COUNTER
MODE
REGISTER
CONTROL
SIGNAL
GENERATOR
Column Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #0)
2048 X 256 X 32
CELL ARRAY
(BANK #1)
2048 X 256 X 32
CELL ARRAY
(BANK #3)
Row Decoder
Column Decoder
Column Decoder
Sense Amplifier
Sense Amplifier
Sense Amplifier
Column Decoder
IC42S32200
IC42S32200L
4Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
PIN DESCRIPTIONS
Table 1.Pin Details of IC42S32200 and IC42S32200L
Symbol Type Description
CLK Input Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge
of CLK.CLK also increments the internal burst counter and controls the output registers.
CKE Input Clock Enable:CKE activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low syn-
chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE
remains low.When all banks are in the idle state,deactivating the clock controls the entry to the
Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power
Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode.
The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing
low standby power.
BS0,BS1
Input Bank Select:BS0 and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge
command is being applied.
A0-A10 Input Address Inputs:A0-A10 are sampled during the BankActivate command (row address A0-A10)and
Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one
location out of the 256K available in the respective bank.During a Precharge command,A10 is
sampled to determine if all banks are to be precharged (A10 =HIGH).
The address inputs also provide the op-code during a Mode Register Set .
CS# Input Chip Select:CS#enables (sampled LOW)and disables (sampled HIGH)the command decoder.All
commands are masked when CS#is sampled HIGH.CS#provides for external bank selection on
systems with multiple banks.It is considered part of the command code.
RAS# Input Row Address Strobe:The RAS#signal defines the operation commands in conjunction with the
CAS#and WE#signals and is latched at the positive edges of CLK.When RAS# and CS#are as-
serted “LOW”and CAS#is asserted “HIGH,”either the BankActivate command or the Precharge
command is selected by the WE#signal.When the WE#is asserted “HIGH,”the BankActivate com-
mand is selected and the bank designated by BS is turned on to the active state.When the WE#is
asserted “LOW,”the Precharge command is selected and the bank designated by BS is switched to
the idle state after the precharge operation.
CAS# Input Column Address Strobe:The CAS#signal defines the operation commands in conjunction with the
RAS#and WE#signals and is latched at the positive edges of CLK. When RAS#is held “HIGH”and
CS#is asserted “LOW,”the column access is started by asserting CAS#”LOW.”Then,the Read or
Write command is selected by asserting WE# “LOW”or “HIGH.”
WE# Input Write Enable:The WE#signal defines the operation commands in conjunction with the RAS#and
CAS#signals and is latched at the positive edges of CLK.The WE#input is used to select the
BankActivate or Precharge command and Read or Write command.
DQM0-3 Input Data Input/Output Mask:DQM0-DQM3 are byte specific,nonpersistent I/O buffer controls. The I/O
buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM
is sampled HIGH during a write cycle.Output data is masked (two-clock latency)when DQM is
sampled HIGH during a read cycle.DQM3 masks DQ31-DQ24,DQM2 masks DQ23-DQ16,DQM1
masks DQ15-DQ8,and DQM0 masks DQ7-DQ0.
DQ0-31 Input/Output Data I/O:The DQ0-31 input and output data are synchronized with the positive edges of
CLK.The I/Os are byte-maskable during Reads and Writes.
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 5
DR036-0D 02/04/2005
PIN FUNCTION
NC - No Connect:These pins should be left unconnected.
VDDQ Supply DQ Power:Provide isolated power to DQs for improved noise immunity.
VSSQ Supply DQ Ground:Provide isolated ground to DQs for improved noise immunity.
VDD Supply Power Supply:+3.3V ± 0.3V
VSS Supply Ground
Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN CONFIGURATIONS
86-Pin TSOP 2 90-Ball FBGA
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
(Top View)
DQ26 DQ24 Vss
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3A3
A4 A5 A6
A7 A8 NC
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2VDD
A10 A0 A1
NC
BA1
NC
CLK CKE A9
DQM1 NC NC
VDDQ DQ8VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
BA0 CS RAS
CAS WE DQM0
VDD DQ7VSSQ
DQ6DQ5VDDQ
DQ1DQ3VDDQ
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDDQ VSSQ DQ4
VDD DQ0DQ2
IC42S32200
IC42S32200L
6Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth
table for the operation commands.
Table 2.Truth Table (Note (1),(2))
Note:
1. V =Valid,X =Don ’t care,L =Logic low,H =Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1,2,4,8,and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle,device state is clock suspend mode.
6. DQM0-3
Command State CKEn-1 CKE DQM(6) BS0,1 A10 A9-0 CS# RAS# CAS# WE#
BankActivate Idle (3) H X X V Row address L L H H
BankPrecharge Any H X X V L X L L H L
PrechargeAll Any H X X X H X L L H L
Write Active (3) HXXVL LHLL
Write and Auto Precharge Active (3) HXXVH LHLL
Read Active (3) HXXVL LHLH
Read and Autoprecharge Active (3) HXXVH LHLH
Mode Register Set Idle H X X OP code L L L L
No-Operation Any H X X X X X L H H H
Burst Stop Active(4) HXXXXX LHHL
Device Deselect Any H X X X X X H X X X
AutoRefresh Idle H H X X X X L L L H
SelfRefresh Entry Idle H L X X X X L L L H
SelfRefresh Exit Idle L H X X X X H X X X
(SelfRefresh) L H H H
Clock Suspend Mode Entry Active H L X X X X X X X X
Power Down Mode Entry Any(5) HLXXXX HXXX
LH H H
Clock Suspend Mode Exit Active L H X X X X X X X X
Power Down Mode Exit Any L H X X X X H X X X
(PowerDown) L H H H
Data Write/Output Enable Active H X L X X X X X X X
Data Mask/Output Disable Active H X H X X X X X X X
Column
address
(A0 ~A7)
Column
address
(A0 ~A7)
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 7
DR036-0D 02/04/2005
Commands
1 BankActivate
(RAS#=”L”,CAS#=”H”,WE#=”H”,BS =Bank,A0-A10 =Row Address)
The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the
row address on A0 to A10 at the time of this command,the selected row access is initiated.The read or write
operation in the same bank can occur after a time delay of tRCD(min.)from the time of bank activation.A
subsequent BankActivate command to a different row in the same bank can only be issued after the previous
active row has been precharged (refer to the following figure).The minimum time interval between successive
BankActivate commands to the same bank is defined by tRC(min.).The SDRAM has four internal banks on the
same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back
activation of the four banks.tRRD(min.)specifies the minimum time required between activating different banks.
After this command is used,the Write command and the Block Write command perform the no mask write
operation.
CLK
ADDRESS
T0 T1 T2 T3 Tn+3 Tn+4 Tn+5 Tn+6
..............
COMMAND
..............
..............
NOP NOP NOP NOP
RAS# - CAS# delay (t
RCD
)RAS#- RAS# delay time (t
RRD
)
RAS# Cycle time (t
RC
)
Bank A
Row Addr. Bank A
Col Addr. Bank B
Row Addr. Bank A
Row Addr.
Bank A
Activate
R/W A with
AutoPrecharge
Bank B
Activate Bank A
Activate
Auto Precharge
Begin
:"H" or "L"
Bank
2 BankPrecharge command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Bank,A10 =”L”,A0-A9 =Don ’t care)
The BankPrecharge command precharges the bank disignated by BS0,1 signal.The
precharged bank is switched from the active state to the idle state.This command can be asserted anytime after
tRAS(min.)is satisfied from the BankActivate command in the desired bank.The maximum time any bank can be
active is specified by tRAS(max.).Therefore,the precharge function must be performed in any active bank within
tRAS(max.).At the end of precharge,the precharged bank is still in the idle state and is ready to be activated again.
IC42S32200
IC42S32200L
8Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
3 PrechargeAll command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Don t care,A10 =”H”,A0-A9 =Don ’t care)
The PrechargeAll command precharges all the four banks simultaneously and can be issued even if all banks are
not in the active state.All banks are then switched to the idle state.
4 Read command
(RAS#=”H”,CAS#=”L”,WE#=”H”,BS =Bank,A10 =”L”,A0-A7 =Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.)before the Read command is issued.During read
bursts,the valid data-out element from the starting column address will be available following the CAS#latency
after the issue of the Read command.Each subsequent data- out element will be valid by the next positive clock
edge (refer to the following figure).The DQs go into high-impedance at the end of the burst unless other com-
mand is initiated.The burst length,burst sequence,and CAS#latency are determined by the mode register which
is already programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 9
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T0 T2T1 T3 T4 T5 T6 T7 T8
READ A NOP NOP NOP NOP NOP NOP NOP NOP
DOUT A0DOUT A1DOUT A2DOUT A3
DOUT A0DOUT A1DOUT A2DOUT A3
CLK
COMMAND
CAS# latency=2
tCK2, DQs
CAS# latency=3
tCK3, DQs
READ A READ B NOP NOP NOP NOP NOP NOP NOP
DOUT A0DOUT B0DOUT B1DOUT B2DOUT B3
DOUT A0DOUT B0DOUT B1DOUT B3
2
DOUT B
CLK
COMMAND
CAS# latency=2
tCK2, DQs
CAS# latency=3
tCK3, DQs
T0 T2T1 T3 T4 T5 T6 T7 T8
Burst Read Operation(Burst Length =4,CAS#Latency =2,3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks
for output buffers).A read burst without the auto precharge function may be interrupted by a subsequent Read or Write
command to the same bank or the other active bank before the end of the burst length.It may be interrupted by a
BankPrecharge/PrechargeAll command to the same bank too.The interrupt coming from the Read command can occur on
any clock cycle following a previous Read command (refer to the following figure).
Read Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command.The
DQMs must be asserted (HIGH)at least two clocks prior to the Write command to suppress data-out on the DQ pins.To
guarantee the DQ pins against I/O contention,a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write command (refer to the following three figures).If the data output of the burst read occurs at the
second clock of the burst write,the DQMs must be asserted (HIGH)at least one clock prior to the Write command to avoid
internal bus contention.
IC42S32200
IC42S32200L
10 Integrated Circuit Solution Inc.
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READ A NOP NOP NOP NOP
WRITE B
NOP NOP
DQM
COMMAND
DQ’s
NOP
DOUT A
DINB2
DINB1
DINB0
Must be Hi-Z before
the Write Command
: "H" or "L"
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8
CLK
DQM
COMMAND
NOP NOP NOP NOP NOP
BANKA
ACTIVAT E
DIN A
0DIN A
1DIN A
2DIN A
3
1 Clk Interval
CAS# latency=2
READ A WRITEA
: "H" or "L"
NOP
T0 T2T1 T3 T4 T5 T6 T7 T8
tCK2, DQs
CLK
DQM
COMMAND
NOP READ A NOP NOP NOP NOP
DIN B0DIN B1DIN B
2DIN B3
CAS# latency=2
NOP NOP
: "H" or "L"
tCK2, DQ’s
T0 T2T1 T3 T4 T5 T6 T7 T8
WRITEB
tCK2, DQs
Read to Write Interval (Burst Length = 4,CAS#Latency =3)
Read to Write Interval (Burst Length = 4,CAS#Latency =2)
Read to Write Interval (Burst Length = 4,CAS#Latency =2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank.The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS#latency.
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 11
DR036-0D 02/04/2005
Read to Precharge (CAS#Latency =2,3)
5 Write command
(RAS#=”H”,CAS#=”L”,WE#=”L”,BS =Bank,A10 =”L”,A0-A7 =Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.)before the Write command is issued.During write bursts,
the first valid data-in element will be registered coincident with the Write command.Subsequent data elements
will be registered on each successive positive clock edge (refer to the following figure).The DQs remain with high-
impedance at the end of the burst unless another command is initiated.The burst length and burst sequence are
determined by the mode register,which is already programmed.A full-page burst will continue until terminated (at
the end of the page it will wrap to column 0 and continue).
CLK
COMMAND
READ A NOP NOP NOP NOP Activate NOP
NOP Precharge
DOUT A0DOUT A1DOUT A2DOUT A3
DOUT A0DOUT A1DOUT A2DOUT A3
ADDRESS
t
RP
Bank,
Col A Bank(s)
CAS# latency=2
tCK2, DQs
CAS# latency=3
tCK3, DQs
T0 T2T1 T3 T4 T5 T6 T7 T8
Bank,
Row
CLK
COMMAND
DIN A 3
NOP
WRITEA
INOP NOP NOP NOP NOP
NOP NOP
DIN A 0DIN A
1DIN A 2
DQ0 - DQ3
The first data element and the write
are registered on the same clock edge.
Extra data is masked.
don’t care
T0 T2T1 T3 T4 T5 T6 T7 T8
Burst Write Operation (Burst Length =4,CAS#Latency =2,3)
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/
PrechargeAll,or Read command before the end of the burst length.An interrupt coming from Write command can
occur on any clock cycle following the previous Write command (refer to the following figure).
IC42S32200
IC42S32200L
12 Integrated Circuit Solution Inc.
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CLK
COMMAND
DIN B2
NOP
WRITEA WRITEB
NOP NOP NOP NOP NOP
NOP
DIN A0DIN B0DIN B1
DQ’s DIN B3
1 Clk Interval
T0 T2T1 T3 T4 T5 T6 T7 T8
CLK
COMMAND
T0T 1 T2T3 T4T5 T6T7 T8
NOP WRITEA NOP NOP NOP NOP NOP
READ B NOP
DIN A0don’t care DOUT B2
DOUT B0DOUT B1DOUT B3
DIN A0don’t care don’t care DOUT B2
DOUT B0DOUT B1DOUT B3
DI N
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Input data for the write is masked.
CAS# latency=2
tCK2, DQ’s
CAS# latency=3
tCK3 , DQ’s
CLK
WRITE
COMMAND
BANK (S) ROW
NOP NOPPrecharge NOP NOP Activate
BANK
COL n
DIN
nn + 1
DQM
ADDRESS
DQ
tWR
tRP
: dont care
T0 T2T1 T3 T4 T5 T6
Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3)
The Read command that interrupts a write burst without auto precharge function should be issued one cycle after
the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must
be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the
following figure).Once the Read command is registered,the data inputs will be ignored and writes will not be
executed.
Write Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
should be issued m cycles after the clock edge in which the last data-in element is registered,where m equals tWR/
tCK rounded up to the next whole number.In addition,the DQM signals must be used to mask input data,starting
with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/
PrechargeAll command is entered (refer to the following figure).
Note:The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
IC42S32200
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DON T CARE
CLK
DQ
D
OUT
a
T2T1 T4T3 T6T5T0
COMMAND
READ - AP
BANK n NOP NOPNOPNOP
D
OUT
a + 1 D
OUT
dD
OUT
d + 1
NOP
T7
BANK n
CAS Latency = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
NOTE: DQM is LOW.
BANK n,
COL a BANK m,
COL d
READ - AP
BANK m
Internal
States t
Page Active READ with Burst of 4 Interrupt Burst, Precharge
Page Active READ with Burst of 4 Precharge
RP - BANK
ntRP - BANK m
CAS Latency = 3 (BANK n)
6 Concurrent Auto Precharge
An access command (READ or WRITE) to another bank while an access command with auto precharge enabled
is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE.
ICSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n,
CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is regis-tered.
READ With Auto Precharge Interrupted by a READ
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
READ With Auto Precharge Interrupted by a WRITE
CLK
DQ
D
OUT
a
T2T1 T4T3 T6T5T0
COMMAND
NOPNOPNOPNOP
D
IN
d + 1
D
IN
dD
IN
d + 2 D
IN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
Idle
NOP
DQM
NOTE: 1. DQM is HIGH at T2 to prevent D
OUT
-a+1 from contending with D
IN
-d at T4.
BANK n,
COL a BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page
Active READ with Burst of 4 Interrupt Burst, Precharge
Page Active WRITE with Burst of 4 Write-Back
RP -
BANK
ntWR -
BANK
m
CAS Latency = 3 (BANK n)
READ - AP
BANK n
1
DON’T CARE
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WRITE with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n
when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after
t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will
be data-in registered one clock prior to the READ to bank m.
WRITE With Auto Precharge Interrupted by a READ
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank
n when registered. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the WRITE
to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE
to bank m.
WRITE With Auto Precharge Interrupted by a WRITE
D
IN
aD
IN
d + 2 D
IN
d + 3
DON’T CARE
T2T1 T4T3 T6T5T0
COMMAND
T7
BANK n
NOP
D
IN
d + 1
WRITE - AP
BANK n NOPNOPNOP
NOTE: 1. DQM is LOW.
BANK n,
COL a BANK m,
COL d
WRITE - AP
BANK m NOP
D
IN
a + 1 D
IN
a + 2 D
IN
d
Page Active WRITE with Burst of 4 Write-Back
WR - BANK n tRP - BANK n tWR - BANK m
BANK m
ADDRESS
Internal
States
t
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
T2T1 T4T3 T6T5T0
COMMAND
WRITE - AP
BANK n
NOP NOPNOPNOP
NOTE: 1. DQM is LOW.
BANK n,
COL a BANK m,
COL d
READ - AP
BANK m NOP
NOP
Page Active READ with Burst of 4
Internal
States
t
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
WR - BANK n RP - BANK n
t
tRP - BANK
m
T7
BANK n
BANK m
ADDRESS
CLK
DQ
D
IN
aD
IN
a + 1 D
OUT
dD
OUT
d + 1
CAS Latency = 3 (BANK m)
DON’T CAR
E
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7 Mode Register Set command
(RAS#=”L”,CAS#=”L”,WE#=”L”,BS0,1 and A10-A0 =Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM.The Mode Regis-
ter Set command programs the values of CAS#latency,Addressing Mode and Burst Length in the Mode register
to make SDRAM useful for a variety of different applications.The default values of the Mode Register after power-
up are undefined;therefore this command must be issued at the power-up sequence.The state of pins BS0,1 and
A10~A0 in the same cycle is the data written to the mode register.One clock cycle is required to complete the write
in the mode register (refer to the following figure).The contents of the mode register can be changed using the
same command and the clock cycle requirements during operation as long as all banks are in the idle state.
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Mode Register Set Cycle
The mode register is divided into various fields depending on functionality.
*Note:RFU (Reserved for future use)should stay 0 during MRS cycle.
• Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2,
4,8,or full page.
RAS#
CLK
CKE
CS#
CAS#
WE#
ADDR.
DQM
DQ
tCK2
Clock min.
Address Key
t
RP
Hi-Z
Precharge All Mode Register
Set Command
Any
Command
T0 T2T1 T3 T4 T5 T6 T7 T8 T9 T10
A2 A1 A0 Burst Length
0001
0012
0104
0118
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Full Page
Address BS0,1 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function RFU* RFU* WBL Test Mode CAS Latency BT Burst Length
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Data n 0 1234567 -255256257-
Column Address
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -
2 words:
Burst Length 4 words:
8 words:
Full Page: Column address is repeated until terminated.
Data n Column Address Burst Length
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0# 4
words
Data 2 A7 A6 A5 A4 A3 A2 A1#
A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0# 8 words
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1#
A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#
• Burst Type Field (A3)
The Burst Type can be one of two modes,Interleave Mode or Sequential Mode.
—Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column address which is input to the
device.The internal column address is varied by the Burst Length as shown in the following table.When the value
of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective.
• Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address
bits in the sequence shown in the following table.
• CAS#Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data.The minimum whole value of CAS#Latency depends on the frequency of CLK.The
minimum whole value satisfying the following formula must be programmed into this field.
tCAC(min)<=CAS#Latency X tCK
A6 A5 A4 CAS#Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2 clocks
0 1 1 3 clocks
1 X X Reserved
A3 Burst Type
0 Sequential
1 Interleave
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• Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to “00”in normal operation.
• Write Burst Length (A9)
This bit is used to select the burst write length.
8 No-Operation command
(RAS#=”H”,CAS#=”H”,WE#=”H”)
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low).This prevents unwanted commands from being registered during idle or wait states.
9 Burst Stop command
(RAS#=”H”,CAS#=”H”,WE#=”L”)
The Burst Stop command is used to terminate either fixed-length or full-page bursts.This
command is only effective in a read/write burst without the auto precharge function.The terminated
read burst ends after a delay equal to the CAS#latency (refer to the following figure).The
termination of a write burst is shown in the following figure.
Termination of a Burst Read Operation (Burst Length > 4,CAS#Latency =2,3)
Termination of a Burst Write Operation (Burst Length =X)
CLK
COMMAND
T0T 1T2T3 T4T5 T6T7 T
8
READ A NOP NOP NOP NOP NOP NOP
NOP
CAS# latency =2
tCK2,DQ’s
DOUT A0DOUT A1DOUT A2DOUT A3
DOUT A0DOUT A1DOUT A2DOUT A3
CAS# latency =3
tCK3,DQ’s
The Burst ends after a delay equal to the CAS# latency.
Burst Stop
CL K
COMMAN D
T0T 1T2T3T4T5T6T7T
8
NOP WRITE A NOP NOP NOP NOP NOP
NOP Burst Stop
CAS# latenc y=2,3
DQ’s DIN A0DIN A1DIN A2don’t care
Input Data for the Write is masked.
A8 A7 Test Mode
0 0 normal mode
0 1 Vendor Use Only
1 X Vendor Use Only
A9 Write Burst Length
0 Burst
1 Single Bit
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10 Device Deselect command (CS#=”H”)
The Device Deselect command disables the command decoder so that the RAS#,CAS#,WE# and Address inputs
are ignored,regardless of whether the CLK is enabled.This command is similar to the No Operation command.
11 AutoRefresh command
(RAS#=”L”,CAS#=”L”,WE#=”H”,CKE =”H”,BS0,1 =Don t care,A0-A10 =Don ’t care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before-
RAS#(CBR)Refresh in conventional DRAMs.This command is non-persistent,so it must be issued each time a
refresh is required.The addressing is generated by the internal refresh controller.This makes the address bits a
“don ’t care”during an AutoRefresh command.The internal refresh counter increments automatically on every
auto refresh cycle to all of the rows.The refresh operation must be performed 4096 times within 64ms.The time
required to complete the auto refresh operation is specified by tRC(min.).To provide the AutoRefresh command,
all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle).This command must be followed by NOPs until the auto refresh operation is completed.The precharge time
requirement,tRP(min),must be met before successive auto refresh operations are performed.
12 SelfRefresh Entry command
(RAS#=”L”,CAS#=”L”,WE#=”H”,CKE =”L”,A0-A10 =Don ’t care)
The SelfRefresh is another refresh mode available in the SDRAM.It is the preferred refresh mode for data retention
and low power operation.Once the SelfRefresh command is registered,all the inputs to the SDRAM become “don
’t care”with the exception of CKE,which must remain LOW.The refresh addressing and timing is internally
generated to reduce power consumption.The SDRAM may remain in SelfRefresh mode for an indefinite period.
The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh
Exit command).
13 SelfRefresh Exit command
(CKE =”H”,CS#=”H”or CKE =”H”,RAS#=”H”,CAS#=”H”,WE#=”H”)
This command is used to exit from the SelfRefresh mode.Once this command is registered, NOP or Device
Deselect commands must be issued for tRC(min.)because time is required for the completion of any bank
currently being internally refreshed.If auto refresh cycles in bursts are performed during normal operation,a burst
of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode.
14 Clock Suspend Mode Entry /PowerDown Mode Entry command (CKE =”L”)
When the SDRAM is operating the burst cycle,the internal CLK is suspended(masked)from the subsequent cycle
by issuing this command (asserting CKE “LOW”).The device operation is held intact while CLK is suspended.On
the other hand,when all banks are in the idle state,this command performs entry into the PowerDown mode.All
input and output buffers (except the CKE buffer)are turned off in the PowerDown mode.The device may not remain
in the Clock Suspend or PowerDown state longer than the refresh period (64ms)since the command does not
perform any refresh operations.
15 Clock Suspend Mode Exit /PowerDown Mode Exit command
When the internal CLK has been suspended,the operation of the internal CLK is einitiated from the subsequent
cycle by providing this command (asserting CKE “HIGH”).When the device is in the PowerDown mode,the device
exits this mode and all disabled buffers are turned on to the active state.tPDE(min.)is required when the device
exits from the PowerDown mode.Any subsequent commands can be issued after one clock cycle from the end
of this command.
16 Data Write /Output Enable,Data Mask /Output Disable command (DQM =”L”,”H”)
During a write cycle,the DQM signal functions as a Data Mask and can control every word of
the input data.During a read cycle,the DQM functions as the controller of output buffers.DQM is also used for
device selection,byte selection and bus control in a memory system.
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Absolute Maximum Rating
Symbol Item Rating Unit Note
VIN,VOUT Input,Output Voltage -0.3~VDD +0.3 V 1
VDD,VDDQ Power Supply -0.3~4.6 V 1
TOPR Operating Temperature 0~70 C 1
TSTG Storage Temperature -55~150 C 1
TSOLDER Soldering Temperature (10s) 260 C 1
PD Power Dissipation 1 W 1
IOUT Short Circuit Output Current 50 mA 1
Recommended D.C.Operating Conditions (Ta =0~70 C)
Symbol Parameter Min. Typ. Max. Unit Note
VDD Power Supply Voltage 3.0 3.3 3.6 V 2
VDDQ Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2
VIH LVTTL Input High Voltage 2.0 VDDQ +1.2 V 2
VIL LVTTL Input Low Voltage -1.2 0.8 V 2
Capacitance (VDD =3.3V,f =1MHz,Ta =25 C)
Symbol Parameter Min. Max. Unit
CI Input Capacitance 4.5 pF
CI/O Input/Output Capacitance 6.5 pF
Note:
1. These parameters are periodically sampled and are not 100% tested.
2. V
IH
(max) for pulse width with ≤ 3ns of duration
V
IL
(min) for pulse width with ≤ 3ns of duration
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Description/Test condition Symbol Max. Unit Note
Operating Current
t
RC
≥ t
RC
(min), Outputs Open, Input
signal one transition per one cycle
1 bank
operation
I
CC1
140/130/130 3
Precharge Standby Current in power down mode
t
CK
= 15ns, CKE ≤ V
IL
(max) I
CC2P
2
Precharge Standby Current in power down mode
t
CK
= ∞, CKE ≤ V
IL
(max)
I
CC2PS
2
Precharge Standby Current in non-power down mode
t
CK
= 15ns, CS#
≥ V
IH
(min), CKE
≥ V
IH
nput signals are changed once during 30ns.
I
CC2N
20 3
Precharge Standby Current in non-power down mode
t
CK
= ∞, CLK ≤ V
IL
(max), CKE
≥ V
IH
I
CC2NS
10
Active Standby Current in power down mode
CKE ≤ V
IL
(max), t
CK
= 15ns I
CC3P
5mA3
Active Standby Current in power down mode
CKE& CLK ≤ V
IL
(max), t
CK
= ∞ I
CC3PS
5
Active Standby Current in non-power down mode
CKE
≥ V
IH
(min), CS#
≥ V
IH
(min), t
CK
= 15ns I
CC3N
30
Active Standby Current in non-power down mode
CKE
≥ V
IH
(min), CLK ≤ V
IL
(max), t
CK
= ∞ I
CC3NS
20
Operating Current (Burst mode)
t
CK
=t
CK
(min), Outputs Open, Multi-bank interleave I
CC4
200/180/150 3, 4
Refresh Current
t
RC
≥ T
rC
(min) I
CC5
200/180/160 3
Self Refresh Current
CKE ≤ 0.2V I
CC6
0.4 (L-Version)
1
Parameter Description Min. Max. Unit Note
I
IL
Input Leakage Current
(0V VIN VDD, All other pins not under test = 0V ) - 5 + 5 µA
V
OH
LVTTL Output "H" Level Voltage
( I
OUT
= -2mA ) 2.4 V
V
OL
LVTTL Output "L" Level Voltage
( I
OUT
= 2mA ) 0.4 V
3
3
Recommended D.C.Operating Conditions (VDD =3.3V ± 0.3V,Ta =0~70 C)
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Symbol A.C. Parameter Min. Max. Unit Note
t
RC
Row cycle time
(same bank) 60/70/80 9
t
RRD
Row activate to row activate delay
(different banks) 12/14/16 9
t
RCD
RAS# to CAS# delay
(same bank) 18/21/24 9
t
RP
Precharge to refresh/row activate command
(same bank) 18/21/24 9
t
RAS
Row activate to precharge time
(same bank) 42/49/56 100,000 9
t
CK2
Clock cycle time CL* = 2 - / - /10
t
CK3
CL* = 3 6/7/8 ns
t
AC2
Access time from CLK CL* = 2 - / - /8 9
t
AC3
(positive edge) CL* = 3 5.5/5.5/6
t
OH
Data output hold time 2/2.5/2.5 9
t
CH
Clock high time 2/3/3 10
t
CL
Clock low time 2/3/3 10
t
IS
Data/Address/Control Input set-up time 1.5/1.75/2 10
t
IH
Data/Address/Control Input hold time 110
t
LZ
Data output low impedance 19
t
HZ
Data output high impedance 5.5/5.5/6 8
* CL is CAS# Latency.
t
DAL
Input data to active/refresh command 2CLK+t
RP
delay time (During Auto-precharge)
t
SRX
Exit self refresh and active command 70
t
RFC
Auto refresh Period
t
REF
Refresh cycle time(4096) 64
60/70/80
ms
t
WR
Write Recovery Time 2
t
CCD
CAS# to CAS# Delay time CLK
t
MRS
Mode Register Set cycle time 2
t
PDE
CKE to clock enable or power down exit
setup mode
1
1
Electrical Characteristics and Recommended A.C.Operating Conditions
(VDD =3.3V ± 0.3V,Ta =0~70 C)(Note:5,6,7,8)
Note:
1. Stress greater than those listed under “Absolute Maximum Ratings”may cause permanent damage to the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of
tCK and tRC.Input signals are changed one time during tCK.
4. These parameters depend on the output loading.Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
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6.A.C.Test Conditions
LVTTL Interface
Reference Level of Output Signals 1.4V /1.4V
Output Load Reference to the Under Output Load (B)
Input Signal Levels 2.4V /0.4V
Transition Time (Rise and Fall)of Input Signals 1ns
Reference Level of Input Signals 1.4V
3.3V
1.2kΩ
870Ω
30pF
Output
LVTTL D.C. Test Load (A)
1.4V
50Ω
Output
30pF
Z0=
50Ω
LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope
(1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns,(tR /2 -0.5)ns should be added to the parameter.
10. Assumed input rise and fall time tT (tR &tF )=1 ns
If tR or tF is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously)when all input signals are held “NOP”state and both
CKE =”H”and DQM =”H.”The CLK signals must be started at the same time.
2) After power-up,a pause of 200µ seconds minimum is required.Then,it is recommended that DQM is held
“HIGH”(VDD levels)to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
5) Mode Register Set command must be asserted to initialize the Mode register.
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Timing Waveforms
Figure 1.AC Parameters for Write Timing (Burst Length=4,CAS#Latency=2)
-5 , , -7 , x x
BS0,1
t
CH
t
CL
t
CK2
t
IS
t
IS
t
IH
Begin Auto Precharge
Bank A
Begin Auto Precharge
Bank B
t
IS
t
IH
t
IS
RBx CAx RBx CBx RAy CAy RAz RBy
t
RCD
t
DAL
t
RC
t
IS
t
IH
t
WR
t
RP
t
RRD
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Activate
Command
Bank A
Write with
Auto Precharge
Command
Bank A
Activate
Command
Bank B
Write with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
CLK
CKE
CS#
RAS#
CAS#
WE#
A
DDR.
DQM
DQ
Hi-Z
T0 T2T1 T3 T4 T5 T6 T7 T9T8 T12T11T10 T14
T13 T15 T16 T17 T18 T19 T21T20 T22
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Figure 2.AC Parameters for Read Timing (Burst Length=2,CAS#Latency=2)
A10
A0-A9
DQ
t
CH tCL tCK2
tIS
tIS
tIH
Begin AutoPrecharge
Bank B
tIH
tIH
tIS
RAx
RAx CAx RBx
RBx
CBx
RAy
RAy
tRRD
tRAS
tRC
tRCD tAC2
tLZ
tOH
tHZ
Ax0 Ax1 Bx0 Bx1
tRP
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Hi-Z t
AC2
tHZ
T0 T2T1 T3 T4 T5 T6 T7 T9T8 T12T11T10 T13
BS0,1
CLK
CKE
CS#
RAS#
CAS#
WE#
DQM
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A10
A
0-A9
DQM
DQ
t
CK2
RAx
RAx CAx
t
RP
t
RC
Ax0 Ax1 Ax2 Ax3
Precharge All
Command
Auto Refresh
Command
Auto Refresh
Command
Activate
Command
Bank A
Read
Command
Bank A
t
RC
T0 T2T1 T3 T4 T5 T6 T7 T9T8 T12T11T10 T14
T13 T15 T16 T17 T18 T19 T21T20 T22
BS0,1
CLK
CKE
CS#
RAS#
CAS#
WE#
DQ
Figure 3.Auto Refresh (CBR)(Burst Length=4,CAS#Latency=2)
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Figure 4.Power on Sequene and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS
RAS
CAS
WE
A10
ADD
D
QM
DQ
High level
is required Minimum of 2 Refresh Cycles are required tMRS
tRP
High Level is Necessary
tRC
Address Key
Inputs
be stable
for 200us
Precharge
All Banks
must Command 1st Auto
Command
Refresh 2nd Auto
Refresh
Command
Mode
Set Command Command
Register
Hi-Z
B
S0, 1
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Figure 5.Self Refresh Entry &Exit Cycle
Note:To Enter SelfRefresh Mode
1. CS#,RAS#&CAS#with CKE should be low at the same clock cycle.
2. After 1 clock cycle,all the inputs including the system clock can be don ’t care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays “low”.
Once the device enters SelfRefresh mode,minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
4. System clock restart and be stable before returning CKE high.
5. Enable CKE and CKE should be set high for minimum time of tSRX.
6. CS#starts from high.
7. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
8. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh.
CLK
CKE
CS#
RAS#
CAS#
BS0,1
A
0-A9
WE#
DQM
DQ
*Note 1
*Note 2
tIS
*Note 3
*Note 4 tRC(min) *Note 7
*Note 5
*Note 6
*Note 8
*Note 8
Hi-Z Hi-Z
SelfRefresh Enter SelfRefresh Exit Auto Refresh
tSRX
tPDE
T0 T2T1 T3 T4 T5 T6 T7 T9T8 T12T11T10 T14
T13 T15 T16 T17 T18 T19
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Figure 6.2.Clock Suspension During Burst Read (Using CKE)
(Burst Length=4,CAS#Latency=2)
T0 T 1 T 2 T3 T4 T 5 T6 T 7 T8 T 9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
RAx
RAx CAx
Hi-Z Ax0 Ax1 Ax2 Ax3
Activate
Command
Bank A
Rea d
Command
Bank A
Clock Suspend
1 Cycle
t
HZ
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Clock Suspend
2 Cycle Clock Suspend
3 Cycle
Note:CKE to CLK disable/enable =1 clock
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Figure 6.3.Clock Suspension During Burst Read (Using CKE)
(Burst Length=4,CAS#Latency=3)
Note:CKE to CLK disable/enable =1 clock
T0T 1 T3T4T5T6T7T8T9T10T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
RAx
RAx CAx
Hi-Z Ax0 Ax1 Ax2 Ax3
tHZ
T 2
Clock Suspend
1 Cycle Clock Suspend
2 Cycle
Clock Suspend
3 Cycle
Activate
Command
Bank A
Rea d
Command
Bank A
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
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T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21
T22
t
CK2
RAx
RAx CAx
DAx0 DAx1 DAx2 DAx3
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Write
Command
Bank A
Clock Suspend
1 Cycle Clock Suspend
2 Cycle
Clock Suspend
3 Cycle
Figure 7.2.Clock Suspension During Burst Write (Using CKE)
(Burst Length=4,CAS#Latency=2)
Note:CKE to CLK disable/enable =1 clock
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Figure 7.3.Clock Suspension During Burst Write (Using CKE)
(Burst Length=4,CAS#Latency=3)
Note:CKE to CLK disable/enable =1 clock
T0 T 1 T2 T3 T 4 T 5 T6 T 7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
DAx0 DAx1 DAx2 DAx3
t
CK3
RAx
RAx CAx
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Clock Suspend
1 Cycle
Clock Suspend
2 Cycle Clock Suspend
3 Cycle
Write
Command
Bank A
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T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
t
CK2
t
IS
t
PDE
RAx
RAx CAx
t
HZ
Ax3
Ax2
Ax1
Ax0
Power Down
Mode Entry Power Down
Mode Entry
Mode Exit
Clock Mask
Start
STANDBY
Any
Valid
ACTIVE
STANDBY
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Rea d
Command
Bank A
Power Down
Mode Exit
Power Down
Clock Mask
End
Precharge
Command
Bank A
PRECHARGE
Command
Figure 8.Power Down Mode and Clock Mask (Burst Lenght=4,
CAS#Latency=2)
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Figure 9.2.Random Column Read (Page within same Bank)
(Burst Length=4,CAS#Latency=2)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
t
CK2
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
RAw
RAw CAw CAx CAy CAz
Az0 Az1 Az2 Az3
Activate
RAz
RAz
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Rea d
Command
Bank A
Precharge
Command
Bank A
Rea d
Command
Bank A
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
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Figure 9.3.Random Column Read (Page within same Bank)
(Burst Length=4,CAS#Latency=3)
T0T 1T2T3T4T5T6T7T8T9T10T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
RAw
RAw CAw CAx CAy CAz
RAz
RAz
Az0
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Activate
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
Precharge
Command
Bank A
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Figure 10.2.Random Column Write (Page within same Bank)
(Burst Length=4,CAS#Latency=2)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
tCK2
DBw0 DBx0 DBx1 DBy0
RBw
CBw CBx CByCBz
RBz
RBz
RBw
DBw1 DBw2 DBw3 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank B
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Figure 10.3.Random Column Write (Page within same Bank)
(Burst Length=4,CAS#Latency=3)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
t
CK3
DBw0 DBx0 DBx1
RBw CBw CBx CBy CBz
DBz0
RBz
RBz
RBw
DBz1 DBz2DBw1 DBw2 DBw3 DBy0 DBy1 DBy2 DBy3
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A
0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank B
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Figure 11.3.Random Row Read (Interleaving Banks)
(Burst Length=8,CAS#Latency=3)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
t
CK3
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1
RBx
RBx RBy CBy
High
RAx
Ax7 By0
Ax2 Ax3 Ax4 Ax5 Ax6
CBx CAx
RAx
RBy
t
RCD
t
AC3
t
RP
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Rea d
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Rea d
Command
Bank B
Rea d
Command
Bank B
Precharge
Command
Bank B
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Figure 12.1.Random Row Write (Interleaving Banks)
(Burst Length=8,CAS#Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK1
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1
RAx
RAx RAy CAy
RBx
DBx7 DAy3
DBx2 DBx3 DBx4 DBx5 DBx6
CAx RBx
RAy
t
RCD
CBx
DAy0 DAy1 DAy2
t
RP
t
WR
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
High
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T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1
RAx
RAx RAy CAy
RBx
DBx7
DBx2 DBx3 DBx4 DBx5 DBx6
CAx CBx
RBx
RAy
t
RCD
DAy3
DAy0 DAy1 DAy2 DAy4
t
WR*
t
RP
t
WR*
* tWR > tWR(min.)
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
High
Figure 12.2.Random Row Write (Interleaving Banks)
(Burst Length=8,CAS#Latency=2)
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Figure 12.3.Random Row Write (Interleaving Banks)
(Burst Length=8,CAS#Latency=3)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
t
CK3
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1
RAx
RAx RAy CAy
RBx
DBx7
DBx2 DBx3 DBx4 DBx5 DBx6
CAx CBx
RBx
RAy
t
RCD
DAy3
DAy0 DAy1 DAy2
t
WR*
t
RP
t
WR*
* t
WR
> t
WR
(min.)
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
High
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T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
t
CK2
Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 Az3
DAy3 Az0 Az1
RAx
RAx CAx CAy CAz
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Activate
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
The Write Data
is Masked with a
Zero Clock
Latency
The Read Data
is Masked with a
Two Clock
Latency
Figure 13.2.Read and Write Cycle (Burst Length=4,CAS#Latency=2)
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Figure 13.3.Read and Write Cycle (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 Az3
DAy3 Az0 Az1
RAx
RAx CAx CAy CAz
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A
0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Activate
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
The Write Data
is Masked with a
Zero Clock
Latency
The Read Data
is Masked with a
Two Clock
Latency
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T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Bw0 Bw1 Bx0 Bx1 By1 Ay0 Bz0
RAx
RAx
Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1 Bz2 Bz3
t
RCD
t
AC2
CAy RAx
RAx
CBw CBx CBy CAy CBz
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A
0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank B
Rea d
Command
Bank B
Rea d
Command
Bank B
Rea d
Command
Bank B
Rea d
Command
Bank B
Precharge
Command
Bank B
Figure 14.2.Interleaving Column Read Cycle (Burst Length=4,CAS#Latency=2)
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T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
Bx0 Bx1 By0 By1 Bz1 Ay0 Ay2
RAx
RAx
Ax0 Ax1 Ax2 Ax3 Bz0 Ay1 Ay3
t
RCD
t
AC3
CAx RBx
RBx
CBx CBy CBz CAy
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank B
Rea d
Command
Bank B
Rea d
Command
Bank B
Rea d
Command
Bank B
Precharge
Command
Bank B
Figure 14.3.Interleaved Column Read Cycle (Burst Length=4,CAS#Latency=3)
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T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
DBx0 DBx1 DAy0
RAx
RAx
DAx0 DAx1 DAx2 DAx3 DAy1
t
RCD
CAx RBw
RBw
CBw CBx CBy CAy
t
RRD
t
RP
t
WR
t
RP
CBz
DBz0 DBz1 DBz2 DBz3
DBy0 DBy1
DBw0 DBw1
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A
0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
Figure 15.2.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency=2)
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Figure 15.3.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T 6 T 7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
DBw0 DBw1 DBx0 DBx1 DBy1 DAy0
RAx
RAx
DAx0 DAx1 DAx2 DAx3 DBy0 DAy1
t
RCD
CAx RBw
RBw
CBw CBx CBy CAy
t
RRD
>
t
RRD(min)
t
RP
t
WR
t
WR(min)
CBz
DBz0 DBz1 DBz2 DBz3
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A
0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
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Figure 16.2.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Bx0 Bx1 Bx2 Bx3 Ay1 Ay2
RAx
RAx
RBx
Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0
RBx CBx RBy
RAy CBy
By1 By2 By3 Az0 Az1 Az2
CAx
RBy RAz
CAz
RAz
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A
0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Activate
Command
Bank A
Rea d
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
High
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Read with
Auto Precharge
Command
Bank A
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Figure 16.3.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
Bx0 Bx1 Bx2 Bx3 Ay1 Ay2
RAx
RAx
RBx
Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0
RBx CBx
By1 By2 By3
CAx
RBy
CBy
RBy
CAy
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A
0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Rea d
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
High
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
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Figure 17.2.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency=2)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
t
CK2
DBx0 DBx1 DBx2 DBx3 DAy1 DAy2
RAx
RAx
RBx
DAx0 DAx1 DAx2 DAx3 DAy0 DAy3
CBx CAy
RBy
CBy
RBy
DAz0 DAz1 DAz2 DAz3
CAx RBx CAz
RAz
RAz
DBy0 DBy1 DBy2 DBy3
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A
0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
High
Write
with
Auto Precharge
Command
Bank B
Write
with
Auto Precharge
Command
Bank B
Write
with
Auto Precharge
Command
Bank A
Write
with
Auto Precharge
Command
Bank A
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Figure 17.3.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
DBx0 DBx1 DBx2 DBx3 DAy1 DAy2
RAx
RAx
RBx
DAx0 DAx1 DAx2 DAx3 DAy0 DAy3
CBx CAyCAx RBx CBy
RBy
RBy
‘
DBy0 DBy1 DBy2 DBy3
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A9
A0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
High
Write
with
Auto Precharge
Command
Bank B
Write
with
Auto Precharge
Command
Bank B
Write
with
Auto Precharge
Command
Bank A
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Figure 18.2.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency=2)
T0 T 1T2T3T4T5T6T7T8T9T10T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Ax Ax+1 Bx Bx+1 Bx+3 Bx+4
RAx
RAx
Ax+1 Ax+2 Ax-2 Ax-1 B x+2 Bx+5
CBx
RBx
CAx RBy
RBy
Ax Bx+6
t
CK2
t
RP
RBx
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
High
Burst Stop
Command
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Rea d
Command
Bank A
Rea d
Command
Bank B
Full Page burst operation does not
term in ate when the burst length is sat is fied;
the burst counter increments and continues
bursting beginning with the starting address.
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Figure 18.3.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency=3)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
Bx Bx+1
RAx
RAx
Ax+1 Ax-2 Ax-1
CBx
RBxCAx RBy
RBy
Ax
t
CK3
t
RP
RBx
Ax+2 Ax Ax+1 Bx+2 Bx+3 Bx+4 Bx+5
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
High
Burst Stop
Command
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Rea d
Command
Bank A
Rea d
Command
Bank B
Full Page burst operation does not
terminate when the burst length is
satisfied; the burst counter
increments and continues
bursting beginning with the
starting address.
IC42S32200
IC42S32200L
54 Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
Figure 19.2.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAx
RAx CBx
RBx
CAx RBy
RBy
t
CK2
5
RBx
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
High
Burst Stop
Command
Data is ignored
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
The burst counter wraps
from the highest order
page address back to zero
during this time interval
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 55
DR036-0D 02/04/2005
Figure 19.3.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=3)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
RAx
RAx CBx
RBx
CAx RBy
RBy
t
CK3
RBx
Data is ignored
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+3 DBx+4 DBx+5
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
High
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Activate
Command
Bank B
Precharge
Command
Bank B
Burst Stop
Command
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
IC42S32200
IC42S32200L
56 Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
Figure 20.Byte Write Operation (Burst Length=4,CAS#Latency=2)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
RAx
RAx CAy
CAx
tCK2
CAz
Ax0 Ax1 Ax2
Ax1 Ax2 Ax3
DAy1 DAy2
DAy0 DAy1 DAy3
Az1 Az2
Az1 Az2
Az3
Write
Command
Bank A
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
High
Activate
Command
Bank A
Command
Bank A
DQM0
DQM1,2,3
DQ0 - DQ7
DQ8 - DQ15
Read
Command
Bank A
Read
are masked
Upper 3 Bytes
are masked
Upper 3 Bytes
Lower Byte
is masked Lower Byte
is masked Lower Byte
is masked
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 57
DR036-0D 02/04/2005
Figure 22.Full Page Random Column Read (Burst Length=Full Page,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2
t
RP
t
RRD
t
RCD
RAx
RAx
RBx
RBx CAx CBx CAy CBy CAz CBz
RBw
RBw
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Command
Bank B
Activate
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Rea d
Command
Bank B
Rea d
Command
Bank B
Rea d
Command
Bank A
Rea d
Command
Bank A
Rea d
Command
Bank A
Rea d Precharge
Command Bank B
(Precharge Temination)
IC42S32200
IC42S32200L
58 Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
Figure 23.Full Page Random Column Write (Burst Length=Full Page,CAS#Latency=2)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
tCK2
DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0
tRP
tRRD tRCD
RAx
RAx
RBx
RBx CAx CBx CAy CBy CAz CBz
RBw
RBw
tWR
DBz1 DBz2
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Write
Command
Bank A
Write
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
Write Data
is masked
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 59
DR036-0D 02/04/2005
Figure 24.2.Precharge Termination of a Burst
(Burst Length=8 or Full Page,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK2
DAx0 DAx1 DAx2 DAx3 Ay2Ay0 Ay1
RAx
RAx
RAy
CAx RAy CAy
Az0 Az1 Az2
tWR tRP tRP
RAz
CAz
tRP
RAz
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
High
Write
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Command
Bank A
Precharge
Command
Bank A
Precharge
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Read
Precharge Termination
of a Write Burst. Precharge Termination
of a Read Burst.
Write data is masked.
IC42S32200
IC42S32200L
60 Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
Figure 24.3.Precharge Termination of a Burst
(Burst Length=4,8 or Full Page,CAS#Latency=3)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
t
CK3
DAx0 Ay0 Ay1 Ay2
RAx
RAx
RAy
CAx RAy CAy
tWR tRP tRP
RAz
RAz
DAx1
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
High
Write
Command
Bank A
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Precharge
Command
Bank A
Write Data
is masked Precharge Termination
of a Write Burst
Precharge Termination
of a Read Burst
Read
IC42S32200
IC42S32200L
Integrated Circuit Solution Inc. 61
DR036-0D 02/04/2005
ORDERING INFORMATION
Commercial Range: 0οο
οο
οC to 70οο
οο
οC
Frequency Speed (ns) Order Part No. Package
166MHz 6 IC42S32200/L-6T 400mil TSOP-2
166MHz 6 IC42S32200/L-6B 11*13mm BGA
143MHz 7 IC42S32200/L-7T 400mil TSOP-2
143MHz 7 IC42S32200/L-7B 11*13mm BGA
125MHz 8 IC42S32200/L-8T 400mil TSOP-2
125MHz 8 IC42S32200/L-8B 11*13mm BGA
ORDERING INFORMATION
Industrial Temperature Range: -40οο
οο
οC to 85οο
οο
οC
Frequency Speed (ns) Order Part No. Package
166MHz 6 IC42S32200/L-6TI 400mil TSOP-2
166MHz 6 IC42S32200/L-6BI 11*13mm BGA
143MHz 7 IC42S32200/L-7TI 400mil TSOP-2
143MHz 7 IC42S32200/L-7BI 11*13mm BGA
125MHz 8 IC42S32200/L-8TI 400mil TSOP-2
125MHz 8 IC42S32200/L-8BI 11*13mm BGA
IC42S32200
IC42S32200L
62 Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
ORDERING INFORMATION (Pb-free Package)
Commercial Range: 0οο
οο
οC to 70οο
οο
οC
Frequency Speed (ns) Order Part No. Package
166MHz 6 IC42S32200/L-6TG 400mil TSOP-2
166MHz 6 IC42S32200/L-6BG 11*13mm BGA
143MHz 7 IC42S32200/L-7TG 400mil TSOP-2
143MHz 7 IC42S32200/L-7BG 11*13mm BGA
125MHz 8 IC42S32200/L-8TG 400mil TSOP-2
125MHz 8 IC42S32200/L-8BG 11*13mm BGA
ORDERING INFORMATION (Pb-free Package)
Industrial Temperature Range: -40οο
οο
οC to 85οο
οο
οC
Frequency Speed (ns) Order Part No. Package
166MHz 6 IC42S32200/L-6TIG 400mil TSOP-2
166MHz 6 IC42S32200/L-6BIG 11*13mm BGA
143MHz 7 IC42S32200/L-7TIG 400mil TSOP-2
143MHz 7 IC42S32200/L-7BIG 11*13mm BGA
125MHz 8 IC42S32200/L-8TIG 400mil TSOP-2
125MHz 8 IC42S32200/L-8BIG 11*13mm BGA