DS2502 DALLAS SEMICONDUCTOR DS2502 1Kbit AddOnly Memory FEATURES 1024 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground Unique, factorylasered and tested 64-bit registra- tion number (8-bit family code + 48-bit serial number + &-bit CRC tester) assures absolute traceability because no two parts are alike Builtjn multidrop controller ensures compatibility with other MicroLAN products @ EPROM partitioned into four 256bit pages for ran- domly accessing packetized data records * Each memory page can be pennanently write-pro- tected to prevent tampering Device is an add only memory where additional data can be programmed into EPROM without disturbing existing data Architecture allows software to patch data by super- seding an old page in favor of a newly programmed page @ Reduces control, address, data, power, and program- ming signals to a single data pin * Directly connects toa single port pin of amicroproces- sor and communicates at up to 16.3k bits per second * 8-bit family code specifies DS2502 communications requirements to reader @ Presence detector acknowledges when reader first applies voltage Low cost TO-92 or 8pin SOIC and TSOC surface mount packages @ Reads over a wide voltage range of 2.8V to 6.0V from 40C to +85C; programs at 11.5V to 12.0V from 40C to +50C PIN ASSIGNMENT TO-92 Penta] eee Ne O14) 1 &HU nc No O44] 2 7 HO ne aTdan) pee ee DATA LIL]| 3 6H Ne Pe GND C1) 4 5 Ne 8-PIN SCIC (150 MIL) TSOG PACKAGE (a ~ GND g|1 =e |O NG DATA 0 2 5/0 NG NC O|3 4|0NC oa ay TOP VIEW 3.7X4.0X1.5mm See Mech. Drawings Section BOTTOM VIEW ORDERING INFORMATION DS2502 TO-92 package DS25028 8-pin SOIC package DS2502P 6-pin TSOC package DS2502T Tape & Reel version of DS2502 DS2502Y Tape & Reel version of DS825028 DS2502V Tape & Reel version of DS2502P SILICON LABEL DESCRIPTION The DS2502 1K-bit AddOnly Memory identifies and stores relevant information about the product to which it is associated. This lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. The DS2502 con- sists of a factorytasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8bit Family Code (09h) plus 1Kbit of EPROM which is user-programmable. The power to program and read the DS2502 is derived entirely from the 1-Wire Copyright 1995 by Dallas Semiconductor Corporation All Rights Reserved For important information regarding atents and other intellectual property rights please refer to allas Semiconductor data books 111797 1/21DS2502 communication line. Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. The entire device can be pro- grammed and then write-protected if desired. Alterna- tively, the part may be programmed multiple times with new data being appended to, but not overwriting, exist- ing data with each subsequent programming of the device. Note: Individual bits can be changed only froma logical 1 to a logical 0, never from a logical 0 toa logical 1. A provision is also included for indicating that a cer- tain page or pages of data are no longer valid and have been replaced with new or updated data that is now residing at an alternate page address. This page address redirection allows software to patch data and enhance the flexibility of the device as a standalone database. The 48-bit serial number that is factory lasered into each DS2502 provides a guaranteed unique identity which allows for absolute traceability. The familiar TO-92 or SOIC or TSOC package provides a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printed circuit boards or wiring. Typical applications include storage of calibration constants, maintenance records, asset tracking, product revision status, and access codes. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2502. The DS2502 has three main data compo- nents: 1) 64bit lasered ROM, 2) 1024-bit EPROM, and 3) EPROM Status Bytes. The device derives its power for read operations entirely from the 1-Wire commu- nication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off of this parasite power source during the low times of the 1Wire line until it returns high tc replenish the parasite (capacitor) supply. During programming, 1Wire communication occurs at normal voltage levels and thenis pulsed momentarily to the pro- gramming voltage to cause the selected EPROM bits to be programmed. The 1Wire line must be able to pro- vide 12 volts and 10 milliamperes to adequately pro- gram the EPROM portions of the part. Whenever pro- gramming voltages are present on the 1Wire line a special high voltage detect circuit within the DS2502 generates an internal logic signal to indicate this condi- tion. The hierarchical structure of the 1Wire protocol is shown in Figure 2. The bus master must first provide one of the four ROM Function Gommands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on the 64-bit lasered ROM portion of each device and can singulate a specific device if many are present on the 1Wire line as well as indicate to the bus master how many and what types of devices are present. The protocol required for these ROM Function Commands is described in Figure 9. After a ROM Function Command is successtully executed, the memory functions that operate on the EPROM portions of the DS2502 become accessible and the bus master may issue any one of the five Memory Function Commands specific to the DS2502 to read or program the various data fields. The protocol for these Memory Function Commands is described in Fig- ure 6. All datais read and written least significant bit first. 64BIT LASERED ROM Each 082502 contains a unique ROM code that is 64 bits long. The first eight bits are a 1Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3). The 64-bit ROM and ROM Function Control section allow the DS2502 to operate as a 1Wire device and fol- low the 1Wire protocol detailed in the section 1-Wire Bus System. The memory functions required to read and program the EPROM sections of the DS2502 are not accessible until the ROM function protocol has been satisfied. This protocol is described in the ROM func- tions flow chart (Figure 9). The 1-Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been suc- cessfully executed, the bus master may then provide any one of the memory function commands specific to the DS2502 (Figure 6). The 1-Wire CRC of the lasered ROMis generated using the polynomial X8 + X54 X44 1. Figure 4 shows a hard- ware implementation of this CRC generator. Additional information about the Dallas Semiconductor 1Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register acting as the GRG accumulator is initialized tozero. Then starting with the least significant bit of the family code, one bit at atimeis shifted in. After the eighth bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeroes. 111 797 2/21DS2502 DS2502 BLOCK DIAGRAM Figure 1 PARASITE POWER Ha! Vv 1-WIRE DATA BUS aoe w| 1-WIREFUNCTION |g______|___ 64-BITLASERED ROL ROM PROGRAM MEMORY VOLTAGE *| FUNCTION [* + 8-BIT DETECT CONTROL SCRATCHPAD 8-BIT CRC GENERATOR 1024-BIT EPROM - (4 PAGES OF 32 BYTES) a 2 ' EPROM STATUS BYTES 111797 3/21DS2502 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 BUS MASTER y 1-WIRE BUS OTHER DEVICES DS2502 commanp = AVAILABLE DATA FIELD LEVEL: COMMANDS: AFEECTED: ' READ ROM 64-BIT ROM {-WIRE ROM FUNCTION MATCH ROM 64BIT ROM COMMANDS (SEE FIGURE 9) SEARCH ROM 64-BIT ROM SKIP ROM NA a 4 WRITE MEMORY {024-BIT EPROM D&2502-SPECIFIC WRITE STATUS BYTE EPROM STATUS BYTES MEMORY FUNCTION READ MEMORY {024-BIT EPROM (SEE FIGURE 6) READ STATUS BYTE EPROM STATUS BYTES READ DATA/GENERATE {024-BIT EPROM &-BIT CRC 64BIT LASERED ROM Figure 3 v &-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (09h) MSB LSB MSB 1-WIRE CRC GENERATOR Figure 4 <r . (MSB} LSB MS8B s of; > (ron) LSB INPUT. e(ion) of | {LSB} 111 797 4/21DS2502 1024-BIT EPROM The memory map in Figure 5 shows the 1024bit EPROM section of the D32502 which is configured as four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when program- ming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit CRC from the DS2502 that confirms proper receipt of the data. If the buffer contents are correct, a programming voltage shouldbe applied and the byte of data will be written into the selected address in memory. This process insures data integrity when programming the memory. The details for reading and programming the 1024bit EPROM portion of the DS2502 are given in the Memory Function Gommands section. EPROM STATUS BYTES In addition to the 1024 bits of data memory the DS2502 provides 64 bits of Status Memory accessible with sep- arate commands. The EPROM Status Bytes can be read or programmed to indicate various conditions to the software interrogat- ing the DS2502. The first byte of the EPROM Status Memory contains the Write Protect Page bits which inhibit programming of the corresponding page in the 1024-bit main memory area if the appropriate write protection bit is programmed. Once a bit has been pro- grammed in the Write Protect Page byte, the entire 32 byte page that corresponds to that bit can no longer be altered but may still be read. The next four bytes of the EPROM Status Memory con- tain the Page Address Redirection Bytes which indicate if one or more of the pages of data in the 1024-bit EPROM section have been invalidated and redirected to the page address contained in the appropriate redirection byte. The hardware of the DS2502 makes no decisions based on the contents of the Page Address Redirection Bytes. These additional bytes of Status EPROM allow for the redirection of an entire page to another page address, indicating that the data in the original page is no longer considered relevant or valid. With EPROM technology, bits within a page can be changed from a logical 1 to alogical 0 by programming, but cannot be changed back. Therefore, it is not pos- sible to simply rewrite a page if the data requires chang- ing or updating, but with space permitting, an entire page of data can be redirected to another page within the DS2502 by writing the ones complement of the new page address into the Page Address Redirection Byte that corresponds to the original (replaced) page. This architecture allows the user's software to make a data patch to the EPROM by indicating that a particu- lar page or pages should be replaced with those indi- cated in the Page Address Redirection Bytes. Ifa Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to that page is valid. Ifa Page Address Redirection Byte has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the ones complement of the page address indicated by the hex value stored in the associated Page Address Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that the updated data is now in page 2. The details for reading and programming the EPROM status memories portion of the DS2502 is given in the Memory Function Commands section. MEMORY FUNCTION COMMANDS The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the various data fields within the DS82502. The Memory Function Control section, 8bit scratchpad, and the Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create the correct control signals within the device. A three-pyte protocol is issued by the bus master. Itis comprised of a command byte to determine the type of operation and two address bytes to determine the specific starting byte location within a data field. The command byte indicates if the device is to be read or written. Writing data involves not only issuing the correct command sequence but also providing a 12 volt programming voltage at the appropri- ate times. To execute a write sequence, a byte of datais first loaded into the scratchpad and then programmed into the selected address. Write sequences always occur a byte at a time. To execute a read sequence, the starting address is issued by the bus master and datais read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. All bits transferred to the DS2502 and received back by the bus master are sent least significant bit first. 111797 5'21DS2502 DS2502 MEMORY MAP Figure 5 8-BIT SCRATCHPAD STARTING ADDRESS o000h PAGE 0 32 BYTES 0020h PAGE 1 32 BYTES eRoM S 0040n PAGE 2 32 BYTES 0060h PAGE 3 32 BYTES EPROM STATUS BYTES ADDRESS: 0007h o00Bh o005h 04h 0003h a0o2h 000th 000h (MSB} (LSB) 7 6 5 4 3 2 1 0 FACTORY RESERVED FOR PAGE ADDRESS f PAGE ADDRESS # PAGE ADDRESS / PAGE ADDRESS PROGRAMMED FUTURE EXPANSION REDIRECTION REDIRECTION REDIRECTION REDIRECTION ooh BYTE FOR BYTE FOR BYTE FOR BYTE FOR PAGE 3 PAGE 2 PAGE + PAGE 0 BIT WRITE PROTECT PAGE O BIT 1 WRITE PROTECT PAGE 1 BIT 2 WRITE PROTECT PAGE 2 BIT 3 WRITE PROTECT PAGE 3 BIT 47 BITMAP OF USED PAGES (RESERVED FOR TMEX} 111797 6/21DS2502 MEMORY FUNCTION FLOW CHART BUS MASTER Ry DATA FROM DATA MEMORY DS2502 INCREMENTS ADDRESS GOUNTER BUS MASTER Ty RESET BUS MASTER Ty RESET BUS MASTER Ri BIT CRC OF DAIA BUS MASTER Ty RESET BUS MASTER Ay 1S DS2502 Ty PRESENCE PULSE Figure 6 MASTER Ty MEMORY FUNCTION COMMAND Foh READ MEMORY BUS MASTER Ty BUS MASTER Ty TAT (T7 To) TAt (17 TO} BUS MASTER Ty BUS MASTER Ty TAZ (T15 T8} TAZ (T15 T8} BUS MASTER Ry 8-BIT GRC BUS MASTER Ry 8-BIT CRG OF COMMAND AND ADDRESS OF COMMAND AND ADDRESS CRC N cRC CORRECT MASTER Tx CORRECT mY Yl BUS MASTER Ry DATA FROM STATUS MEMORY BUS MASTER Ty RESET DS2502 INCREMENTS ADDRESS COUNTER BUS MASTER BUS MASTER Ry 8-BIT GRO OF STATUS DATA i" N BUS MASTER Ty RESET BUS MASTER Ry 1S 111797 7/21DS2502 MEMORY FUNCTION FLOW CHART (contc) Figure 6 G3h READ DATA N al GENERATE cal & 8-BIT CRG, - bail TO WRITE COMMANDS BUS MASTER Ty TAT (Tz TO} BUS MASTER Tx TA2 (115 18} ! BUS MASTER Ry 8-BIT CRC. OF GOMMAND AND ADDRESS BUS MASTER Ty RESET BUS MASTER Ry DATA FROM DATA MEMORY BUS MASTER Sy_ ~ Ty RESET DS2802 INCREMENTS ADDRESS COUNTER i BUS MASTER Ry 8-BIT CRG OF PRECEDING PAGE OF DATA BUS MASTER - LEGEND: Ty RESET DECISION MADE BY THE MASTER CS t BUS MASTER 082502 T; DECISION MADE BY DS2502 Ty RESET PRESENCE PULSE BUS MASTER Ry 1'S 111 797 38/21MEMORY FUNCTION FLOW CHART (cont'd) Figure 6 FROM READ COMMANDS BUS MASTER Ty TAT (T7 TO) BUS MASTER Tx Taz (715 TB} BUS MASTER Tx DATA BYTE (07 Do} ~ BUS MASTER Ry 8-BIT CRC OF COMMAND ADDRESS DATA (187 PASS} CRC OF ADDRESS DATA (SUBSEQUENT PASSES) CRG CORRECT BUS MASTER Ty PROGRAM PULSE t DS2502 COPIES SGRATGHPAD TO DATA EPROM ' BUS MASTER Rx BYTE FROM EPROM EPROM BYTE = DATA BYTE DS2602 NCREMENTS ADDRESS COLNTER Y DS2502 LOADS LSB OF; MASTER Tx RESET NEW ADDRESS INTO CRC GENERATOR Ld BUS MASTER Ty TAI (17 TO} BUS MASTER Tx TA? (T15 Ta) BUS MASTER Tx DATA BYTE (D7 Do} Y CRG OF COMMAND ADDRESS BUS MASTER Ry 8-8IT DATA (187 PASS} CRC OF ADDRESS DATA (SUBSEQUENT PASSES} Lye) MASTER T RESET CRG CORRECT BUS MASTER Ty PROGRAM PULSE Yy DS2602 COPIES SCRATCHPAD TO STATUS EPROM BUS MASTER Ry BYTE FROM EPROM EPROM BYTE = DATA BYTE, 052502 INCREMENTS ADDRESS COUNTER Y DS 2802 LOADS LSB OF NEW ADDRESS INTO GRC GENERATOR DS2502 , BUS MASTER Ty RESET Ld DS2502 Ty PRESENCE PULSE 111797 921DS2502 READ MEMORY [FOH] The Read Memory command is used to read data from the 1024bit EPROM data field. The bus master follows the command byte with a two-byte address (TA1=(T7:TO), TAZ=(T15:T8)) that indicates a starting byte location within the data field. An 8bit CRC of the command byte and address bytes is computed by the DS2502 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC read by the bus masteris incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus mas- teris correct, the bus master issues read time slots and receives data from the DS2502 starting at the initial address and continuing until the end of the 1024bit data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may issue eight additional read time slots and the DS2502 will respond with an 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 8-bit CRC available. Typically a 16-bit CRC would be stored with each page of data to insure rapid, error-free data transfers that eliminate having to read a page multiple times to deter- mine if the received data is correct or not. (See Book of DS19xx iButton Standards, Ghapter 7 for the recom- mended file structure to be used with the 1Wire envi- ronment). lf CRC values are imbedded within the data, a Reset Pulse may be issued at the endof memory space during a Read Memory command. READ STATUS [AAH] The Read Status command is used to read data from the EPROM Status data field. The bus master follows the command byte with a two-byte address (TA1=(T7:TO), TAZ=(T15:T8)) that indicates a starting byte location within the data field. An 8bit CRC of the command byte and address bytes is computed by the DS2502 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC read by the bus masteris incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus mas- teris correct, the bus master issues read time slots and receives data from the DS2502 starting at the supplied address and continuing until the end of the EPROM Sta- tus data field is reached. At that point the bus master will receive an 8-bit CRC thatis the result of shifting into the CRC generator all of the data bytes from the initial start- ing byte through the final factoryprogrammed byte that contains the 00h value. This feature is provided since the EPROM Status information may change over time making it impossible to program the data once and include an accompanying CRC that will always be valid. Therefore, the Read Sta- tus command supplies an 8-bit CRC that is based on and is always consistent with the current data stored in the EPROM Status data field. After the 8-bit CRC is read, the bus master will receive logical 1s from the DS 2502 until a Reset Pulseis issued. The Read Status command sequence can be exited at any point by issuing a Reset Pulse. READ DATA/GENERATE 8-BIT CRC [C3H] The Read Data/Generate 8-bit CRC command is used to read data from the 1024bit EPROM data field. The bus master follows the command byte with a two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by the DS2502 and read back by the bus master to confirm that the correct command word and starting address were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the GRG received by the bus master is correct, the bus master issues read time slots and receives data from the DS2502 starting at the initial address and continuing until the end of a 32byte page is reached. At that point the bus master will send eight additional read time slots and receive an 8-bit CRC thatis the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the 8-bit GRC has been received, data is again read from the 1024bit EPROM data field starting at the next page. This sequence will continue until the final page and its accompanying CRC are read by the bus master. Thus each page of data can be considered to be 33 bytes long, the 32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the end of each page. This type of read differs from the Read Memory com- mand which simply reads each page until the end of address space is reached. The Read Memory com- 111 797 10/21DS2502 mand only generates an 8-bit CRC at the end of memory space that often might be ignored, since in many applications the user would store a 16-bit CRC with the data itself in each page of the 1024-bit EPROM data field at the time the page was programmed. The Read Data/Generate 8-bit CRC command pro- vides an alternate read capability for applications that are bit-oriented rather than pageoriented where the 1024bit EPROM information may change over time within a page boundary making itimpossible to program the page once and include an accompanying GRC that will always be valid. Therefore, the Read Data/Generate 8-Bit CRC command concludes each page with the DS2502 generating and supplying an 8-bit CRC that is based on and therefore is always consistent with the current data stored in each page of the 1024bit EPROM data field. After the @bit CRC of the last page is read, the bus master will receive logical 1s from the DS2502 until a Reset Pulse is issued. The Read Data/ Generate 8-Bit CRC command sequence can be exited at any point by issuing a Reset Pulse. WRITE MEMORY [OFH] The Write Memory command is used to program the 1024-bit EPROM data field. The bus master will follow the command byte with a two-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of data (D7:D0). An 8bit CRC of the command byte, address bytes, and data byte is computed by the DS2502 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. lf the CRC read by the bus masteris incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is cor- rect, a programming pulse (12 volts on the 1Wire bus for 480 1s) is issued by the bus master. Prior to program- ming, the entire unprogrammed 1024-bit EPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus master thatis set to alogical 0, the corresponding bit in the selected byte of the 1024bit EPROM will be programmed toa logical 0 after the programming pulse has been applied at that byte location. After the 480 pts programming pulse is applied and the data line returns to a5 volt level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2502 responds with the data from the selected EPROM address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in bit positions where the byte issued by the master contains Os, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS2502 EPROM databyte contains Qs in the same bit positions as the data byte, the programming was successful and the DS2502 will automatically increment its address counter to select the next byte in the 1024bit EPROM data field. The least significant byte of the new two-byte address will also be loaded into the 8-bit CRC generator as a start- ing value. The bus master will issue the next byte of data using eight write time slots. As the DS2502 receives this byte of data into the scratchpad, it also shifts the data into the CRC genera- tor that has been preloaded with the LSB of the current address and the result is an 8bit CRC of the new data byte and the LSB of the new address. After supplying the data byte, the bus master will read this 8-bit CRC from the DS2502 with eight read time slots to confirm thatthe addressincremented propery and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Memory command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Memory flow chart will generate an 8-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS82502 automatically increment- ing its address counter will generate an 8-bit CRC that is the result of loading (not shifting) the LSB of the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS2502) is made entirely by the bus master, since the DS2502 will not be able to determine if the 8-bit CRC calculated by the bus master agrees with the 8-bit CRC calculated by the DS2502. If an incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS2502. Also note that the DS2502 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the 111797 11/21DS2502 programming of the selected EPROM byte. The deci- sion to continue is again made entirely by the bus mas- ter, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Memory command, incorrect programming could occur within the DS2502. The Write Memory command sequence can be exited at any point by issuing a Reset Pulse. WRITE STATUS [55H] The Write Status command is used to program the EPROM Status data field. The bus master will follow the command byte with a two-byte starting address (TA1=(T7:TG), TA2=(T15:T8)) and a byte of status data (D7:DO). An 8-bit CRC of the command byte, address bytes, and data byte is computed by the DS2502 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is cor- rect, a programming pulse (12 volts on the 1Wire bus for 480 ps} is issued by the bus master. Prior to program- ming, the first seven bytes of the EPROM Status data field will appear as logical 1s. For each bit in the data byte provided by the bus master thatis set to a logical 0, the corresponding bitin the selected byte of the EPROM Status data field will be programmed to a logical 0 after the programming pulse has been applied at that byte location. The eighth byte of the EPROM Status Byte data field is factory-programmed to contain 00h. After the 480 ws programming pulse is applied and the data line returns toa 5 volt level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2502 responds with the data from the selected EPROM Status address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM Status Byte address. If the EPROM Status Byte contains 1s in bit positions where the byte issued by the master contained Os, a Reset Pulse should be issued and the currentbyte address should be programmed again. If the DS2502 EPROM Status Byte contains Os in the same bit posi- tions as the data byte, the programming was successful and the 082502 will automatically incrementits address counter to select the next byte in the EPROM Status data field. The least significant byte of the new twobyte address will also be loaded into the 8-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS2502 receives this byte of data into the scratchpad, it also shifts the data into the CRC genera- tor that has been preloaded with the LSB of the current address and the result is an 8bit CRC of the new data byte and the LSB of the new address. After supplying the data byte, the bus master will read this 8-bit CRC from the DS2502 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Status flow chart will generate an 8bit CRC value thatis the result of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the data byte. Subsequent passes through the Write Status flow chart due to the DS2502 automatically incrementing its address counter will generate an 8bit CRC that is the result of loading (net shifting) the LSB of the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS2502) is made entirely by the bus master, since the DS2502 will not be able to determine if the 8-bit CRC calculated by the bus master agrees with the 8-bit CRC calculated by the D32502. If an incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS2502. Also note that the DS2502 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The deci- sion to continue is again made entirely by the bus mas- ter, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Status command, incorrect programming could occur within the DS2502. The Write Status command sequence can be ended at any point by issuing a Reset Pulse. 111797 12/21DS2502 1-WIRE BUS SYSTEM The 1Wire bus is a system which has a single bus mas- ter and oneormore slaves. Inallinstances, the DS2502 is a slave device. The bus master is typically a micro- controller. The discussion of this bus system is broken down into three topics: hardware configuration, transac- tion sequence, and 1Wire signaling (signal type and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. Hardware Configuration The 1Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain connection or 3state outputs. The DS2502 is an open drain part with an internal circuit equivalent to that shown in Figure 7. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together. The bus master requires a pull-up resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figures 8a and &b. The value of the pull-up resistor should be approximately 5 kQ for short line lengths. A multidrop bus consists of a 1Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second. If the bus master is also required to perform programming of the EPROM por- tions of the DS2502, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 ps is required. The idle state for the 1Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus MUST be leftin the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 ws, one or more of the devices on the bus may be reset. TRANSACTION SEQUENCE The sequence foraccessing the DS2502 via the 1-Wire portis as follows: Initialization # ROM Function Command Memory Function Command Read/Write Memory/Status INITIALIZATION All transactions on the 1Wire bus begin with an initial- ization sequence. The initialization sequence consists ofa reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS$2502 is on the bus and is ready to operate. For more details, see the 1Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four RGM function commands. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 9): Read ROM [33H] This command allows the bus master to read the DS2502's 8-bit family code, unique 48-bit serial num- ber, and 8bit CRC. This command can be used only if there is a single DS2502 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wiredAND result). Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2502 on a multidrop bus. Only the DS2502 that exactly matches the 64bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64bit ROM sequence will wait for areset pulse. This command canbe used witha single or multiple devices on the bus. 111797 13/21DS2502 DS$2502 EQUIVALENT CIRCUIT Figure 7 R OT Data 5 uA Tx Typ. programming signal switching 1008 MOSFET Vo Ground BUS MASTER CIRCUIT Figure & \ 12V A) Open Drain BUS MASTER 10kQ DSs000 OR 8051 EQUIVALENT VPO300L 5kQ TOKO | 5 vpoipeNs ees) Open Drain _[ BSS110 ort Pin R 5 D _p- Jodata connection >N7000 . of DS2502 T D | 470 pF PGM 8 y Capacitor added to reduce L 2N7000 coupling on data line due to 2N7000 B) Standard TTL dD | BUS MASTER 12 Vop (10 mA min.} 5kQ PROGRAMMING PULSE TTL-Equivalent on Ss To data connection of DS2502 v 111797 14/21DS2502 ROM FUNCTIONS FLOW CHART Figure 9 33h READ ROM COMMAND MASTER Tx RESET PULSE Y DS2502 Ty PRESENCE PULSE ' MASTER Tx ROM FUNCTION COMMAND 55h MATCH ROM COMMAND FOh SEARCH ROM COMMAND CCh SKIP ROM COMMAND DS2502 Ty BIT O DS2502 Ty FAMILY MASTER Tx BIT 0 DS2502 Tx BIT oO 1 BYTE MASTER Tx BITO BITO N BITO MATCH? MATGH? Y DS2502 Ty BIT 1 DS2502 Tx SERIAL NUMBER MASTER Tx BIT 1 DS2502 Tx BIT 1 6 BYTES MASTER Ty BIT 1 N N DS2502 Ty CRC BYTE AY ~Y DS2502 Ty BIT 63 MASTER Tx BIT 63 Dspso? Ty BIT 63 MASTER Tx BIT 63 N BIT 63 BIT 63 MATCH? MATCH? ~ . MASTER Tx MEMORY FUNCTION COMMAND (SEE FIGURE 6} 111797 15/21DS2502 Skip ROM [CCH] This command can save time ina single drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wiredAND result). Search ROM [FOH] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM com- mand allows the bus master to use a process ofelimina- tion toidentify the 64bit ROM codes of all slave devices onthe bus. The ROM search process is the repetition of asimple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards fora comprehensive discussion of a ROM search, including an actual example. 1-Wire Signaling The DS2502 requires strict protocols to insure data integrity. The protoccl consists of five types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data and Pro- gram Pulse. All these signals except presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2502 is shown in Figure 10. A reset pulse followed by a Pres- ence Pulse indicates the DS2502 is ready to accept a ROM command. The bus master transmits (TX) a reset pulse (tagq7_, minimum 480 js). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pull-up resis- tor. After detecting the rising edge on the 1Wire line, the DS2502 waits (tppy, 15-60 ws) and then transmits the presence pulse (tpp,_, 60-240 ps). Read/Write Time Slots The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS2502 to the master by triggering a delay circuit in the DS2502. During write time slots, the delay circuit determines when the DS2502 will sample the data line. For a read data time slot, if a O is to be transmitted, the delay circuit determines how long the DS2502 will hold the data line low overriding the 1 gen- erated by the master. If the data bit is a 1, the device will leave the read data time slot unchanged. PROGRAM PULSE To copy data from the 8-bit scratchpad to the 1024bit EPROM Memory or Status Memory, a program pulse of 12 volts is applied to the data line after the bus master has confirmed that the CRC for the current byte is cor- rect. During programming, the bus master controls the transition from a state where the data line is idling high via the pull-up resistor to a state where the data line is actively driven to a programming voltage of 12 volts pro- viding a minimum of 10 mA of current to the DS2502. This programming voltage (Figure 12) should be applied for 480 ws, after which the bus master returns the data line to an idle high state controlled by the pull-up resistor. Note that due to the high voltage pro- gramming requirements for any 1-Wire EPROM device, it is not possible to multi-drop non-EPROM based 1-Wire devices with the DS2502 during pro- gramming. An intemal diode within the non-EPROM based 1-Wire devices will attempt to clamp the data line at approximately 8 volts and could potentially damage these devices. CRC GENERATION The DS2502 has an 8-bit GRC stored in the most signif- icant byte of the 64-bit ROM. The bus master can com- pute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the 032502 to determine if the ROM data has been received errorfree by the bus master. The equivalent polynomial function of this CRC is: X84 X54 X44 1. Under certain conditions, the DS2502 also generates an 8-bit CRC value using the same polynomial function shown above and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the DS2502. The Memory Function Flow Chart of Figure 6 indicates that the DS2502 computes an 8-bit CRC for the command, address, and data bytes received for the Write Memory and the Write Status commands and then outputs this value to the bus master to confirm proper transfer. Simi- larly the DS2502 computes an 8-bit CRC for the com- 111797 16/21DS2502 mand and address bytes received from the bus master for the Read Memory, Read Status, and Read Data/ Generate 8-Bit CRC commands to confirm that these bytes have been received correctly. The CRC generator on the DS2502 is also used to provide verification of error-free data transfer as each page of data from the 1024-bit EPROM is sent to the bus master during a Read Data/Generate 8-Bit CRC command, and for the eight bytes of information in the status memory field. In each case where a CRC is used for data transfer val- idation, the bus master must calculate a CRC value using the polynomial function given above and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the DS2502 (for ROM reads) or the 8-bit CRC value computed within the DS2502. The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. There is no circuitry on the DS2502 that prevents a command sequence from proceeding if the CRC stored in or calculated by the DS2502 does not match the value generated by the bus master. Proper use of the CRC as outlined in the flow chart of Figure 6 can result in a communication channel with a very high level of integrity. For more details on generating CRC values including example implementationsin both hard- ware and software, see the Book of DS19xx iButton Standards. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES Figure 10 MASTER Ty RESET PULSE MASTER Ry PRESENCE PULSE 1 ! ! VeULLUP VeULLUP MIN IH MIN VIL MAX ov tasTL 480 Ls < tasty < ce (includes recovery time) RESISTOR 480 us <tastl <7o* MASTER eccenees pS2502 15 Us <tppy < 60 pus 60 us <tpp, < 240 us * In order not to mask interrupt signaling by other devices on the 1Wire bus, tay. + tp should always be less than 960 us. 111797 17/21DS2502 READ/WRITE TIMING DIAGRAM Figure 11 Writeone Time Slot tsLor VeULLUP VPULLUP MIN ViIH MIN VIL MAX ov DS2s502 SAMPLING WINDOW 60 us 60 us <tsLo7r < 120 us 1 us < tlow: < 15 us 1 Us <tRec < co Writezero Time Slot trec VeULLUP VeULLUP MIN ViH MIN VILMAX ov 60 Us tLowo 60 us < tLowo < tgLor < 120 us 1us<tpec < co Read-data Time Slot tsLor rat tRec VPULLUP 6 VeULLUP MIN ra 2: IH MIN VILMAX L \ ov f 4 - TRELEASE 60 us <ts_oT < 120 Ls _ RESISTOR 1 us <tiowa <15us MASTER O<treLease < 45 us - DS2502 THs <tacc < ce troy = 15 us 111797 18/21DS2502 PROGRAM PULSE TIMING DIAGRAM Figure 12 VeuLLUP NORMAL 1-Wire COMMUNICATION RESUMES NORMAL 1-Wire COMMUNICATION ENDS LINE TYPE LEGEND: =_ean ap Bus master active high (12V @ 10 mA) Resistor pull-up 111797 19/21DS2502 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature 0.5V to 412.0V 40C to +85C 55C to 4125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is notimplied. Exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (Vpyp=2.8V to 6.0V; 40C to +85C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 Vin 2.2 Veco +0.3 Vv 1,6 Logic 0 ViL 0.3 +0.8 Vv 1 Output Logic Low @4 mA VoL 0.4 Vv 1 Qutput Logic High Vou Vpup 6.0 Vv 1,2 Input Load Current IL 5 pA 3 Operating Charge Qop 30 nG 7,8 Programming Voltage @ 10 mA Vpp 11.5 12.0 Vv CAPACITANCE (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Data (1-Wire) Cinout 800 pF g AC ELECTRICAL CHARACTERISTICS (Vpyp=2.8V to 6.0V; -40C to +85C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Time Slot te_ot 60 120 ps Write 1 Low Time tLow1 1 15 ps Write 0 Low Time tLowo 60 120 us Read Data Valid trpy exactly 15 us Release Time tRELEASE 0 15 45 us Read Data Setup tsu 1 us 5 Recovery Time tREc 1 ps Reset Time High trsTH 480 us 4 Reset Time Low tRstL 480 ps Presence Detect High tppHIGH 15 60 us Presence Detect Low tppLow 60 240 us Belay to Program top 5 ps 10 Delay to Verify toy 5 ps 10 Program Pulse Width tpp 480 Us 10 Program Voltage Rise Time trp 0.5 5.0 us 10 Program Voltage Fall Time trp 0.5 5.0 us 10 111 797 20/21DS2502 NOTES: 1. All voltages are referenced to ground. 2. Vpup = external pull-up voltage. 3. Inputload is to ground. 4. An additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data setup time refers to the time the host must pull the 1Wire bus low to read a bit. Data is guaranteed to be valid within 1 1s of this falling edge and will remain valid for 14 us minimum. (15 ps total from falling edge on 1Wire bus.) 6. ViyH is a function of the external pull-up resistor and the Ver supply. 7. 30 nanocoulombs per 72 time slots @ 5.0V. 8. At Vec=5.0V with a5 k pullup to Vee and a maximum time slot of 120 us. 9. Capacitance on the data pin could be 800 pF when power is first applied. If a5 kQ resistor is used to pull up the data line to Voc, 5 ws after power has been applied the parasite capacitance will not affect normal communica- tions. 10. Maximum 1Wire voltage for programming parameters is 11.5V + 0.5V; temperature range is -40C to +85C. 111797 21/21