1
FEATURES
DESCRIPTION
APPLICATIONS
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs
•Maximum Sample Rate: 250 MSPS•14-Bit Resolution – ADS614X
ADS614X (ADS612X) is a family of 14-bit (12-bit) A/Dconverters with sampling rates up to 250 MSPS. It•12-Bit Resolution – ADS612X
combines high dynamic performance and low power•687 mW Total Power Dissipation at 250 MSPS
consumption in a compact 48 QFN package. This•Double Data Rate (DDR) LVDS and Parallel
makes it well-suited for multicarrier, wide band-widthCMOS Output Options communications applications.•Programmable Fine Gain up to 6dB for
ADS614X/2X has fine gain options that can be usedSNR/SFDR Trade-Off
to improve SFDR performance at lower full-scaleinput ranges. It includes a dc offset correction loop•DC Offset Correction
that can be used to cancel the ADC offset. Both DDR•Supports Input Clock Amplitude Down to 400
LVDS (Double Data Rate) and parallel CMOS digitalmV
PP
Differential
output interfaces are available. At lower sampling•Internal and External Reference Support
rates, the ADC automatically operates at scaled downpower with no loss in performance.•48-QFN Package (7mm × 7mm)•Pin Compatible with ADS5547 Family
It includes internal references while the traditionalreference pins and associated decoupling capacitorshave been eliminated. Nevertheless, the device canalso be driven with an external reference. The device•Multicarrier, Wide Band-Width
is specified over the industrial temperature rangeCommunications
( – 40 ° C to 85 ° C).•Wireless Multi-carrier Communications
250 MSPS 210 MSPSInfrastructure
ADS614X•Software Defined Radio
ADS6149 ADS614814-Bit Family•Power Amplifier Linearization
ADS612X
ADS6129 ADS6128•802.16d/e
12-Bit Family•Test and Measurement Instrumentation•High Definition Video•Medical Imaging•Radar Systems
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ADS614X BLOCK DIAGRAM
B0095-06
Sample
and
Hold
14-Bit ADC
CLOCKGEN
Reference
DDR
Serializer
Control
Interface
INP
INM
CLKP
CLKM
VCM
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D4_D5_P
D6_D7_P
D8_D9_P
D10_D11_P
D12_D13_P
D2_D3_M
D4_D5_M
D6_D7_M
D8_D9_M
D10_D11_M
D12_D13_M
OVR_SDOUT
ADS6149/48
RESET
SCLK
SEN
SDATA
DFS
MODE
DDRLVDSInterface
AVDD
AGND
DRVDD
DRGND
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
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ADS612X BLOCK DIAGRAM
B0095-07
Sample
and
Hold
12-Bit ADC
CLOCKGEN
Reference
DDR
Serializer
Control
Interface
INP
INM
CLKP
CLKM
VCM
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D4_D5_P
D6_D7_P
D8_D9_P
D10_D11_P
D2_D3_M
D4_D5_M
D6_D7_M
D8_D9_M
D10_D11_M
OVR_SDOUT
ADS6129/28
RESET
SCLK
SEN
SDATA
DFS
MODE
AVDD
AGND
DRVDD
DRGND
DDRLVDSInterface
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
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ABSOLUTE MAXIMUM RATINGS
(1)
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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PACKAGE/ORDERING INFORMATION
(1) (2)
SPECIFIEDPACKAGE LEAD/BALL PACKAGE ORDERING TRANSPORTPRODUCT PACKAGE-LEAD TEMPERATUREDESIGNATOR FINISH MARKING NUMBER MEDIA, QUANTITYRANGE
ADS614x
ADS6149IRGZRADS6149 AZ6149
ADS6149IRGZTQFN-48 RGZ – 40 ° C to 85 ° C Cu NiPdAu Tape and reelADS6148IRGZRADS6148 AZ6148
ADS6148IRGZT
ADS612x
ADS6129IRGZRADS6129 AZ6129
ADS6129IRGZTQFN-48 RGZ – 40 ° C to 85 ° C Cu NiPdAu Tape and reelADS6128IRGZRADS6128 AZ6128
ADS6128IRGZT
(1) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θ
JA
= 25.41 ° C/W (0LFM air flow),θ
JC
= 16.5 ° C/W when used with 2oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in (7.62 cm x 7.62cm) PCB.(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.
VALUE UNIT
Supply voltage range, AVDD – 0.3 V to 3.9 VSupply voltage range, DRVDD – 0.3 V to 2.2 VVoltage between AGND and DRGND – 0.3 to 0.3 VVoltage between AVDD to DRVDD (when AVDD leads DRVDD) 0 to 3.3 VVoltage between DRVDD to AVDD (when DRVDD leads AVDD) – 1.5 to 1.8 VV
I
Voltage applied to external pin, VCM (in external reference mode) – 0.3 to 2.0 VVoltage applied to analog input pins - INP, INM – 0.3V to minimum V( 3.6, AVDD + 0.3V )Voltage applied to input pins - CLKP, CLKM
(2)
, RESET, SCLK, SDATA, SEN, DFS and – 0.3V to AVDD + 0.3V VMODET
A
Operating free-air temperature range – 40 to 85 ° CT
J
Operating junction temperature range 125 ° CT
stg
Storage temperature range – 65 to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is < |0.3V|. Thisprevents the ESD protection diodes at the clock input pins from turning on.
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RECOMMENDED OPERATING CONDITIONS
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
SUPPLIES
AVDD Analog supply voltage 3 3.3 3.6 VDRVDD Digital supply voltage 1.7 1.8 1.9 V
ANALOG INPUTS
Differential input voltage range 2 V
pp
Input common-mode voltage 1.5 ± 0.1 VVoltage applied on CM in external reference mode 1.5 ± 0.05 VMaximum analog input frequency with 2 V
PP
input amplitude
(1)
500 MHzMaximum analog input frequency with 1 V
PP
input amplitude
(1)
800 MHz
CLOCK INPUT
ADS6149 / ADS6129 1 250Input clock sample rate MSPSADS6148 / ADS6128 1 210Sine wave, ac-coupled 0.3 1.5LVPECL, ac-coupled 1.6 V
ppInput Clock amplitude differential(V
CLKP
– V
CLKM
)
LVDS, ac-coupled 0.7LVCMOS, single-ended, ac-coupled 3.3 VInput clock duty cycle 40% 50% 60%
DIGITAL OUTPUTS
C
L
Maximum external load capacitance from each output pin to DRGND 5 pFR
L
Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω
T
A
Operating free-air temperature – 40 85 ° C
(1) See the Theory of Operation in the application section.
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ELECTRICAL CHARACTERISTICS – ADS614X and ADS612X
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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Typical values are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, – 1dBFS differential analog input, internalreference mode unless otherwise noted.Min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = 3.3 V, DRVDD = 1.8 V
ADS6149/ADS6129 ADS6148/ADS6128250 MSPS 210 MSPSPARAMETER UNITMIN TYP MAX MIN TYP MAX
ANALOG INPUT
Differential input voltage range 2 2 V
PP
Differential input resistance (at dc), See Figure 97 > 1 > 1 M Ω
Differential input capacitance, See Figure 98 3.5 3.5 pFAnalog Input Bandwidth 700 700 MHzAnalog Input common mode current (per input pin) 2 2 µA/MSPSVCM Common mode output voltage 1.5 1.5 VVCM output current capability ± 4 ± 4 mA
DC ACCURACY
Offset error – 15 ± 2 15 – 15 ± 2 15 mVTemperature coefficient of offset error 0.005 0.005 mV/ ° CVariation of offset error with supply 0.3 0.3 mV/VE
GREF
Gain error due to internal reference inaccuracy alone – 1.25 ± 0.2 1.25 – 1.25 ± 0.2 1.25 %FSE
GCHAN
Gain error of channel alone 0.2 0.2 %FSTemperature coefficient of E
GCHAN
.001 .001 Δ%/ ° C
POWER SUPPLY
I
AVDD
Analog supply current 170 155 mAOutput buffer supply current, LVDS interface with 100 Ωexternal
70 65 mAterminationI
DRVDD
Output buffer supply current, CMOS interface Fin = 3 MHz
(1)
,
56 48 mA10-pF external load capacitanceAnalog power 561 630 510 570 mWDigital power LVDS interface 126 160 118 153 mWDigital power CMOS interface, Fin = 3 MHz
(2)
, 10-pF external
101 87 mWload capacitance
Global power down 20 50 20 50 mWStandby 120 120 mW
(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and thesupply voltage (see Figure 91 and CMOS interface power dissipation in application section).(2) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that themaximum recommended load capacitance on each digital output line is 10 pF.
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ELECTRICAL CHARACTERISTICS – ADS6149 and ADS6148
ELECTRICAL CHARACTERISTICS – ADS6129 and ADS6128
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Typical values are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, – 1dBFS differential analog input, internalreference mode unless otherwise noted.Min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = 3.3 V, DRVDD = 1.8 V
ADS6149 ADS6148
210 MSPS250 MSPSPARAMETER UNITMIN TYP MAX MIN TYP MAX
Fin = 20 MHz 73.4 73.4Fin = 80 MHz 72.7 72.7SNR
Fin = 100 MHz 72.3 72.3 dBFSSignal to noise ratio, LVDS
Fin = 170 MHz 69 71.3 69.7 71.2Fin = 300 MHz 69 69Fin = 20 MHz 73.2 73.3Fin = 80 MHz 72.4 72.4SINAD
Fin = 100 MHz 71.9 71.8 dBFSSignal to noise and distortion ratio, LVDS
Fin = 170 MHz 68 70.6 68.7 70.9Fin = 300 MHz 68 68.2
ENOB
Fin = 170 MHz 11 11.4 11.1 11.5 LSBEffective number of bits
DNL
– 0.95 ± 0.4 2 – 0.95 ± 0.4 2 LSBDifferential non-linearity
INL
– 5 ± 2 5 – 5 ± 2 5 LSBIntegrated non-linearity
Typical values are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, – 1dBFS differential analog input, internalreference mode unless otherwise noted.Min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = 3.3 V, DRVDD = 1.8 V
ADS6129 ADS6128
210 MSPS250 MSPSPARAMETER UNITMIN TYP MAX MIN TYP MAX
Fin = 20 MHz 70.7 70.9Fin = 80 MHz 70.5 70.5SNR,
Fin = 100 MHz 70.1 70.1 dBFSSignal to noise ratio, LVDS
Fin = 170 MHz 67.5 69.5 67.7 69.5Fin = 300 MHz 67.8 67.9Fin = 20 MHz 70.6 70.8Fin = 80 MHz 70.4 70.4SINAD
Fin = 100 MHz 69.8 69.8 dBFSSignal to noise and distortion ratio, LVDS
Fin = 170 MHz 66.5 69.2 66.7 69.3Fin = 300 MHz 67.2 67.3
ENOB,
Fin = 170 MHz 10.8 11.2 10.8 11.2 LSBEffective number of bits
DNL
– 0.5 ± 0.2 1 – 0.5 ± 0.2 1.0 LSBDifferential non-linearity
INL
– 2.5 ± 1 2.5 – 2.5 ± 1 2.5 LSBIntegrated non-linearity
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ELECTRICAL CHARACTERISTICS – ADS614x and ADS612x
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
Typical values are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, – 1dBFS differential analog input, internalreference mode unless otherwise noted.Min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = 3.3 V, DRVDD = 1.8 V
ADS6149/ADS6129 ADS6148/ADS6128
210 MSPS250 MSPSPARAMETER UNITMIN TYP MAX MIN TYP MAX
Fin = 20 MHz 92 92Fin = 80 MHz 86 82SFDR
Fin = 100 MHz 85 81 dBcSpurious Free Dynamic Range
Fin = 170 MHz 74 82 74 83Fin = 300 MHz 76 76Fin = 10 MHz 89 88.5Fin = 20 MHz 83 80THD
Fin = 80 MHz 82 79 dBcTotal Harmonic Distortion
Fin = 170 MHz 71 79 71 80Fin = 300 MHz 73 73Fin = 20 MHz 94 94Fin = 80 MHz 90 88HD2,
Fin = 100 MHz 88 88 dBcSecond Harmonic Distortion
Fin = 170 MHz 74 84 74 84Fin = 300 MHz 76 76Fin = 20 MHz 93 92Fin = 80 MHz 86 82HD3
Fin = 100 MHz 85 81 dBcThird Harmonic Distortion
Fin = 170 MHz 74 82 74 83Fin = 300 MHz 76 76Fin = 20 MHz 96 96Fin = 80 MHz 94 94Worst Spur
Fin = 100 MHz 94 94 dBcOther than second, third harmonics
Fin = 170 MHz 92 92Fin = 300 MHz 90 90F1 = 46 MHz, F2 = 50 MHz,
94 95Each tone at – 7 dBFSIMD
dBFS2-Tone inter-modulation distortion
F1 = 185 MHz, F2 = 190 MHz,
90 90Each tone at – 7 dBFSRecovery to within 1% (of final value) for clockInput overload recovery 1 16-dB overload with sine wave input cycles
PSRR
For 100 mV
PP
signal on AVDD supply 25 25 dBAC power supply rejection ratio
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DIGITAL CHARACTERISTICS – ADS614x and ADS612x
Dn_Dn+1_P
Dn_Dn+1_P
Dn_Dn+1_M
Dn_Dn+1_M
GND
GND
V
OCM
VOCM
Logic0
V = –350mV
ODL
(1)
Logic1
V =350mV
ODH
(1)
T0399-01
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logiclevel 0 or 1. AVDD = 3.3 V, DRVDD = 1.8 V
ADS6149/ADS6148/
ADS6129/ADS6128PARAMETER TEST CONDITIONS UNITMIN TYP MAX
DIGITAL INPUTS – RESET, SCLK, SDATA, SEN
(1)
High-level input voltage 1.3 VAll digital inputs support 1.8V and 3.3V CMOS logiclevelsLow-level input voltage 0.4 VSDATA, SCLK
(2)
VHIGH = 3.3V 16High-level input current µASEN
(3)
VHIGH = 3.3V 10SDATA, SCLK VLOW = 0V 0Low-level input current µASEN VLOW = 0V – 20Input capacitance 4 pF
DIGITAL OUTPUTS – CMOS INTERFACE (Pins D0 to D13 and OVR_SDOUT)
High-level output voltage DRVDD VLow-level output voltage 0 VOutput capacitance (internal to device) 2 pF
DIGITAL OUTPUTS – LVDS INTERFACE (Pins D0_D1_P/M to D12_D13_P/M)
(4)
V
ODH
, High-level output voltage
(5)
275 350 425 mVV
ODL
, Low-level output voltage
(5)
– 425 – 350 – 275 mVV
OCM
, Output common-mode voltage 1 1.2 1.3 VCapacitance inside the device, from either output toOutput capacitance 2 pFground
(1) SCLK, SDATA, SEN function as digital input pins in serial configuration mode.(2) SDATA, SCLK have internal 200 k Ωpull-down resistor(3) SEN has internal 100 k Ωpull-up resistor to AVDD. Since the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS buffers.(4) OVR_SDOUT has CMOS output logic levels, determined by DRVDD voltage.(5) With external 100 Ωtermination
Figure 1. LVDS Voltage Levels
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TIMING REQUIREMENTS – LVDS AND CMOS MODES
(1)
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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Typical values are at 25 ° C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock,C
LOAD
= 5pF
(2)
, R
LOAD
= 100 Ω
(3)
, LOW SPEED mode disabled, unless otherwise noted.Min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = 3.3V, DRVDD = 1.7V to1.9V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
The delay in time between the rising edge of the input sampling clock andt
a
Aperture delay 0.7 1.2 1.7 nsthe actual time at which the sampling occurs
t
j
Aperture jitter 170 fs rms
Time to valid data after coming out of STANDBY mode 0.3 1
µsTime to valid data after coming out of PDN GLOBAL mode 25 100Wake-up time
clockTime to valid data after stopping and restarting the input clock 10
cycles
clockADC Latency
(4)
Default, after reset 18
cycles
DDR LVDS MODE
(5)
t
su
Data setup time Data valid
(6)
to zero-crossing of CLKOUTP 0.8 1.2 ns
t
h
Data hold time Zero-crossing of CLKOUT to data becoming invalid
(6)
0.25 0.6 ns
t
PDI
Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 0.2 × t
s
+ t
delay
ns100 MSPS ≤Sampling frequency ≤250 MSPSt
delay
5.0 6.2 7.5 ns
Duty cycle of differential clock, (CLKOUTP – CLKOUTM)LVDS bit clock duty cycle 52%100 MSPS ≤Sampling frequency ≤250 MSPS
Rise time measured from – 100 mV to 100 mVt
RISE
, Data rise time,
Fall time measured from 100 mV to – 100 mV 0.08 0.14 0.2 nst
FALL
Data fall time
1 MSPS ≤Sampling frequency ≤250 MSPS
Rise time measured from – 100 mV to 100 mVt
CLKRISE
, Output clock rise time,
Fall time measured from 100 mV to – 100 mV 0.08 0.14 0.2 nst
CLKFALL
Output clock fall time
1 MSPS ≤Sampling frequency ≤250 MSPS
t
OE
Output enable (OE) to data delay Time to valid data after OE becomes active 40 ns
PARALLEL CMOS MODE
(7)
t
START
Input clock to data delay Input clock rising edge cross-over to start of data valid
(8)
3.2 ns
t
DV
Data valid time Time interval of valid data
(8)
0.7 1.5 ns
t
PDI
Clock propagation delay Input clock rising edge cross-over to output clock rising edge cross-over 0.78 × t
s
+ t
delay100 MSPS ≤Sampling frequency ≤150 MSPSt
delay
5 6.5 8 ns
Duty cycle of differential clock, (CLKOUT)Output clock duty cycle 50%100 MSPS ≤Sampling frequency ≤150 MSPS
t
RISE
, Data rise time, Rise time measured from 20% to 80% of DRVDD,Fall time measured from 80% to 20% of DRVDD, 0.7 1.2 2 nst
FALL
Data fall time
1 MSPS ≤Sampling frequency ≤250 MSPS
Rise time measured from 20% to 80% of DRVDD,t
CLKRISE
, Output clock rise time,
Fall time measured from 80% to 20% of DRVDD, 0.5 1 1.5 nst
CLKFALL
Output clock fall time
1 MSPS ≤Sampling frequency ≤150 MSPS
t
OE
Output enable (OE) to data delay Time to valid data after OE becomes active 20 ns
(1) Timing parameters are specified by design and characterization and not tested in production.(2) C
LOAD
is the effective external single-ended load capacitance between each output pin and ground(3) R
LOAD
is the differential load resistance between the LVDS output pair.(4) At higher frequencies, t
PDI
is greater than one clock period and overall latency = ADC latency + 1.(5) Measurements are done with a transmission line of 100 Ωcharacteristic impedance between the device and the load. Setup and holdtime specifications take into account the effect of jitter on the output data and clock.(6) Data valid refers to LOGIC HIGH of +100mV and LOGIC LOW of – 100mV.(7) For Fs > 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT).(8) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V.
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
LVDS Timings at Lower Sampling Frequencies
SETUP TIME, ns HOLD TIME, nsSAMPLING FREQUENCY, MSPS
MIN TYP MAX MIN TYP MAX
210 1.0 1.4 0.4 0.8190 1.1 1.5 0.5 0.9170 1.3 1.7 0.7 1.1150 1.6 1.9 0.9 1.2125 1.9 2.2 1.1 1.4< 100
2.5 2.0Enable LOW SPEED mode
t
PDI
, ns
(1)
1≤Fs ≤100,
MIN TYP MAXEnable LOW SPEED mode
8.2
(1) Ts = 1/Sampling frequency
CMOS Timings at Lower Sampling Frequencies
Timings specified with respect to input clock
SAMPLING FREQUENCY, MSPS t
START
, ns DATA VALID TIME, ns
MIN TYP MAX MIN TYP MAX
210 1.7 1.6 2.4190 0.4 2.2 3.0170 5.1 2.4 3.6150 4.8 3.0 4.3
Timings specified with respect to CLKOUT
SAMPLING FREQUENCY, MSPS SETUP TIME, ns HOLD TIME, ns
MIN TYP MAX MIN TYP MAX
150 2.0 3.2 1.5 2.2125 2.9 4 2.2 2.7< 100
5.0 3.8Enable LOW SPEED mode
t
PDI
, ns
(1)
1≤Fs ≤100
MIN TYP MAXEnable LOW SPEED mode
14
(1) Ts = 1/Sampling frequency
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18ClockCycles*
T0105-09
E E E E E E E EE E
O O O O O O O OO O
Input
Clock
CLKOUTM
CLKOUTP
OutputData
DXP,DXM
DDR
LVDS
N–18 N–17 N–16 N–15 N–14 N–1 NN+1 N+2
N–18 N–17 N–16 N–15 N N+2
18ClockCycles*
CLKOUT
OutputData
Parallel
CMOS
Input
Signal
Sample
N
N+1
N+2 N+3 N+4
th
tPDI
ta
tsu
th
tPDI
CLKP
CLKM
N+18
N+19 N+20
tsu
E – Even Bits D0,D2,D4,...
O – Odd Bits D1,D3,D5, ...
N+1
Then,overalllatency= ADClatency+1.
ADClatencyis14clockcyclesinlow-latencymode.
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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Figure 2. Latency Diagram
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T0106-07
Input
Clock
Output
Clock
Output
DataPair
CLKP
CLKOUTP
Dn_Dn+1_P,
Dn_Dn+1_M
CLKM
tPDI
tsu th
thtsu
CLKOUTM
(1)Dn – BitsD0,D2,D4,...
(2)Dn+1 – BitsD1,D3,D5,...
Dn(1) Dn+1(2)
T0107-05
Output
Data Dn
tSTART
*Dn – BitsD0,D1,D2,...
Dn*
Input
Clock
CLKM
CLKP
Input
Clock
Output
Clock
Output
Data
CLKM
Dn
CLKP
tsu
th
CLKOUT
Dn*
tPDI
tDV
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Figure 3. LVDS Mode Timing
Figure 4. CMOS Mode Timing
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DEVICE CONFIGURATION
PARALLEL CONFIGURATION ONLY
SERIAL INTERFACE CONFIGURATION ONLY
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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ADS614X/2X can be configured independently using either parallel interface control or serial interfaceprogramming.
To put the device in parallel configuration mode, keep RESET tied to HIGH (DRVDD).
Now, pins DFS, MODE, SEN and SDATA can be used to directly control certain modes of the ADC. The devicecan be easily configured by connecting the parallel pins to the correct voltage levels (as described in Table 3 toTable 6 . There is no need to apply reset.
In this mode, SEN and SDATA function as parallel interface control pins. Frequently used functions can becontrolled in this mode – standby, selection between LVDS/CMOS output format, internal/external reference,two ’ s complement/straight binary output format and position of the output clock edge.
Table 1 briefly describes the modes controlled by the parallel pins.
Table 1. Parallel Pin Functions
TYPE OFPIN CONTROLS MODESCONTROL
DFS Analog Data format and LVDS/CMOS output interface.MODE
(1)
Analog Internal or external reference, low speed mode enableSEN Analog CLKOUT edge programmability.
Global power-down (ADC, internal references and output buffers areSDATA Digital
powered down)
(1) In the next generation pin-compatible ADC family, MODE will be converted to a digital control pin forcertain reserved functions. So, the selection of internal or external reference and low speed functionswill not be supported using MODE. In the system board using ADS61x9/x8, the MODE pin can berouted to a digital controller. This will avoid board modification while migrating to the next generationADC.
To exercise this mode, first the serial registers have to be reset to their default values and RESET pin has to bekept LOW.
SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internalregisters of the ADC.
The registers can be reset either by applying a pulse on RESET pin or by setting HIGH the < RESET> bit (D7 inregister 0x00). The serial interface section describes the register programming and register reset in more detail.
Since the parallel pins DFS and MODE are not to be used in this mode, they have to be tied to ground.
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CONFIGURATION USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
DESCRIPTION OF PARALLEL PINS
ADS6149/ADS6129
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
For increased flexibility, an additional configuration mode is supported wherein a combination of serial interfaceregisters and parallel pin controls (DFS, MODE) can be used to configure the device.
To exercise this mode, the serial registers have to be reset to their default values and RESET pin has to be keptLOW.
SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internalregisters of ADC. The registers can be reset either by applying a pulse on RESET pin or by setting HIGH the< RESET> bit (D7 in register 0x00). The serial interface section describes the register programming and registerreset in more detail.
The parallel interface control pins DFS and MODE can be used and their function is determined by theappropriate voltage levels as described in Table 3 . The voltage levels can be easily derived, by using a resistorstring as illustrated with an example as shown in Figure 5 .
Since some functions can be controlled using both the parallel pins and serial registers, the priority between thetwo is determined by a Priority Table as shown in Table 2 .
Table 2. Priority Between Parallel Pins and Serial Registers
FUNCTION PRIORITY
MODE pin controls this selection ONLY if the register bits < REF > = 00, otherwise < REF > controls theInternal/External reference
selection
DFS pin controls this selection ONLY if the register bits < DATA FORMAT > = 00, otherwise < DATAData format selection
FORMAT > controls the selectionDFS pin controls this selection ONLY if the register bits < LVDS CMOS > = 00, otherwise < LVDSLVDS or CMOS interface selection
CMOS > controls the selection
Table 3. SDATA – DIGITAL CONTROL PIN
SDATA DESCRIPTION
0 Normal operation (default)AVDD Global power-down. ADC, internal references and the output buffers are powered down.
Table 4. SEN – ANALOG CONTROL PIN
(1)
SEN DESCRIPTION – Output Clock Edge Programmability
LVDS: Data and output clock transitions are aligned0
CMOS: Setup time increases by (6xTs/26), Hold time reduces by (6xTs/26)
LVDS: Setup time decreases by (4xTs/26), Hold time increases by (4xTs/26)(3/8)AVDD
CMOS: Setup time increases by (9xTs/26), Hold time reduces by (9xTs/26)
LVDS: Setup time increases by (4xTs/26), Hold time reduces by (4xTs/26)(5/8)AVDD
CMOS: Setup time increases by (3xTs/26), Hold time reduces by (3xTs/26)Default output clock position (Setup/hold timings of output data with respect to this clock position is specified in theAVDD
timing characteristics table).
(1) Ts = 1/Sampling frequency
Table 5. DFS – ANALOG CONTROL PIN
DFS DESCRIPTION
0 2s complement data and DDR LVDS output(3/8)AVDD 2s complement data and parallel CMOS output(5/8)AVDD Offset binary data and parallel CMOS outputAVDD Offset binary data and DDR LVDS output
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ToParallelPin
GND
GND
AVDD
AVDD
(5/8) AVDD
(5/8) AVDD
3R
2R
3R
(3/8) AVDD
(3/8) AVDD
S0321-01
SERIAL INTERFACE
Register Initialization
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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Table 6. MODE – ANALOG CONTROL PIN
MODE DESCRIPTION
0 Internal reference, LOW SPEED mode disabled (for Fs > 100 MSPS)(3/8)AVDD External reference, LOW SPEED mode disabled (for Fs > 100 MSPS)(5/8)AVDD External reference, LOW SPEED mode enabled (for Fs ≤100 MSPS)AVDD Internal reference, LOW SPEED mode enabled (for Fs ≤100 MSPS)
Figure 5. Simple Scheme to Configure Parallel Pins SEN and SCLK
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edgeof SCLK when SEN is active (low). The serial data is loaded into the register at every 16
th
SCLK falling edgewhen SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can beloaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can workwith SCLK frequency from 20 MHz down to low speeds (few Hertz) and also with non-50% SCLK duty cycle.
After power-up, the internal registers MUST be initialized to their default values. This can be done in one of twoways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) asshown in Figure 6 .
OR2. By applying software reset. Using the serial interface, set the < RESET> bit (D7 in register 0x00) to HIGH.This initializes internal registers to their default values and then self-resets the < RESET> bit to LOW. In thiscase the RESET pin is kept LOW.
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T0109-01
Register Address RegisterData
t(SCLK) t(DSU)
t(DH)
t(SLOADS)
D7A7 D3A3 D5A5 D1A1 D6A6 D2A2 D4A4 D0A0
SDATA
SCLK
SEN
RESET
t(SLOADH)
SERIAL INTERFACE TIMING CHARACTERISTICS
SERIAL REGISTER READOUT
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Figure 6. Serial Interface Timing
Typical values at 25 ° C, min and max values across the full temperature rangeT
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD = 3.3V, DRVDD = 1.8V, unless otherwise noted.PARAMETER MIN TYP MAX UNIT
f
SCLK
SCLK frequency (= 1/ tSCLK) > DC 20 MHzt
SLOADS
SEN to SCLK setup time 25 nst
SLOADH
SCLK to SEN hold time 25 nst
DS
SDATA setup time 25 nst
DH
SDATA hold time 25 ns
The device includes an option where the contents of the internal registers can be read back. This may be usefulas a diagnostic check to verify the serial interface communication between the external controller and the ADC.a. First, set register bit < SERIAL READOUT> = 1. This also disables any further writes into the registers(EXCEPT register bit < SERIAL READOUT> itself).b. Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read.c. The device outputs the contents (D7-D0) of the selected register on OVR_SDOUT pin.d. The external controller can latch the contents at the falling edge of SCLK.e. To enable register writes, reset register bit < SERIAL READOUT> = 0.
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T0386-01
D7A7 D3A3 D5A5 D1A1 D6
1000000 0
A6 D2A2 D4A4 D0A0
SDATA
SCLK
SEN
OVR_SDOUT
Register Address(A7:A0)=0x3F RegisterData(D7:D0)=XX(Don'tCare)
B)Readcontentsofregister0x3F. Thisregisterhasbeeninitializedwith0x04(deviceisputinglobalpowerdownmode)
PinOVR_SDOUT functionsasserialreadout(<SERIAL READOUT>=1)
D70 D30 D50 D10 D60 D20 D40 D00
SDATA
SCLK
SEN
OVR_SDOUT
Register Address(A7:A0)=0x00 RegisterData(D7:D0)=0x01
A)Enableserialreadout(<SERIAL READOUT>=1)
PinOVR_SDOUT functionsasOVR(<SERIAL READOUT>=0)
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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Figure 7. Serial Readout
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RESET TIMING
SERIAL REGISTER MAP
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Typical values at 25 ° C, min and max values across the full temperature rangeT
MIN
= – 40 ° C to T
MAX
= 85 ° C, unless otherwise noted.PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active 1 ms10 nst
2
Reset pulse width Pulse width of active RESET signal that will reset the serial registers
1µst
3
Delay from RESET disable to SEN active 100 ns
Figure 8. Reset Timing Diagram
Table 7. Summary of Functions Supported by Serial Interface
(1)
REGISTER ADDRESS REGISTER FUNCTIONS
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
< RESET >
< SERIAL00 0 0 0 0 0 0Software
READOUT >Reset
< ENABLE20 0 0 0 0 0 LOW SPEED 0 0MODE >REF >
< PDN < PDN3F 0 0 0 < STANDBY >GLOBAL > OBUF >Internal or external reference< LVDS CMOS >41 0 0 0 0 0 0Output interface
< CLKOUT POSN >44 0 0Output clock position control
< DATA FORMAT >50 0 0 0 0 0 02s complement or offsetbinary51 < CUSTOM PATTERN LOW >52 0 0 CUSTOM PATTERN HIGH >53 0 ENABLE OFFSET CORR > 0 0 0 0 0 0< OFFSET CORR TIME CONSTANT >55 < FINE GAIN >
Offset correction time constant62 0 0 0 0 0 TEST PATTERNS >63 0 0 PROGRAM OFFSET PEDESTAL >
(1) Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
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SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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A)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
< SERIA< RESET >
L00 0 0 0 0 0 0
READOSoftware Reset
UT >
D7 < RESET >
1 Software reset applied – resets all internal registers and self-clears to 0.
D0 < SERIAL READOUT >
0 Serial readout disabled1 Serial readout enabled, Pin OVR_SDOUT functions as serial data readout.
A)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
< ENABLE20 0 0 0 0 0 LOW SPEED 0 0MODE >
D2 < ENABLE LOW SPEED MODE >
0 LOW SPEED mode disabled. Use for sampling frequency > 100 MSPS1 Enable LOW SPEED mode for sampling frequencies ≤100 MSPS.
B)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
< PDN < PDN3F 0 < REF > 0 0 < STANDBY >GLOBAL > OBUF >
D0 < PDN OBUF > Power down output buffer
0 Output buffer enabled1 Output buffer powered down
D1 < STANDBY >
0 Normal operation1 ADC alone powered down. Internal references, output buffers are active. Quick wake-up time
D2 < PDN GLOBAL >
0 Normal operation1 Total power down – ADC, internal references and output buffers are powered down. Slow wake-up time.
D6,D5 < REF > Internal or external reference selection
00 MODE pin controls reference selection01 Internal reference enabled11 External reference enabled
C)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
41 < LVDS CMOS > 0 0 0 0 0 0
D7,D6 < LVDS CMOS >
00 DFS pin controls LVDS or CMOS interface selection10 DDR LVDS interface11 Parallel CMOS interface
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
D)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
44 < CLKOUT POSN > Output clock position control 0 0
LVDS Interface
D7-D5 < CLKOUT POSN > Output clock rising edge position
000 Default output clock position (refer to timing specification table)100 Default output clock position (refer to timing specification table)101 Rising edge shifted by + (4/26)Ts110 Rising edge aligned with data transition111 Rising edge shifted by - (4/26)Ts
D4-D2 < CLKOUT POSN > Output clock falling edge position
000 Default output clock position (refer to timing specification table)100 Default output clock position (refer to timing specification table)101 Falling edge shifted by + (4/26)Ts110 Falling edge aligned with data transition111 Falling edge shifted by - (4/26)Ts
CMOS Interface
D7-D5 < CLKOUT POSN > Output clock rising edge position
000 Default output clock position (refer to timing specification table)100 Default output clock position (refer to timing specification table)101 Rising edge shifted by + (4/26)Ts110 Rising edge shifted by + (6/26)Ts111 Rising edge aligned with data transition
D4-D2 < CLKOUT POSN > Output clock falling edge position
000 Default output clock position (refer to timing specification table)100 Default output clock position (refer to timing specification table)101 Falling edge shifted by + (4/26)Ts110 Falling edge shifted by + (6/26)Ts111 Falling edge aligned with data transition
T
s
= 1/Sampling Frequency
E)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
50 0 0 0 0 0 < DATA FORMAT > 2s complement or offset binary 0
D2,D1 < DATA FORMAT >
00 DFS pin controls data format selection10 2's complement11 Offset binary
F)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
51 < Custom Pattern >52 0 0 < Custom Pattern >
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D7 – D0 < CUSTOM LOW >
8 lower bits of custom pattern available at the output instead of ADC data.
D5 – D0 < CUSTOM HIGH >
6 upper bits of custom pattern available at the output instead of ADC data
G)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
< ENABLE OFFSET CORR >53 0 0 0 0 0 0 0Offset correction enable
D6 < ENABLE OFFSET CORR >
0 Offset correction disabled1 Offset correction enabled
H)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
< OFFSET CORR TC > Offset correction time55 < FINE GAIN >
constant
< OFFSET CORR TC > Time constant of correction loop in number of clock cycles. See "Offset Correction" in applicationD3 – D0
section.0000 256 k0001 512 k0010 1 M0011 2 M0100 4 M0101 8 M0110 16 M0111 32 M1000 64 M1001 128 M1010 256 M1011 512 M1100 to 1111 RESERVED
D7 – D4 < FINE GAIN > Gain programmability in 0.5 dB steps0000 0 dB gain, default after reset0001 0.5 dB gain0010 1.0 dB gain0011 1.5 dB gain0100 2.0 dB gain0101 2.5 dB gain0110 3.0 dB gain0111 3.5 dB gain1000 4.0 dB gain1001 4.5 dB gain1010 5.0 dB gain1011 5.5 dB gain1100 6.0 dB gain
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
I)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
62 0 0 0 0 0 < TEST PATTERNS >
D2 – D0 < TEST PATTERNS > Test Patterns to verify data capture000 Normal operation001 Outputs all zeros010 Outputs all ones011 Outputs toggle patternADS6149/8: Output data < D13:D0 > alternates between 10101010101010 and 01010101010101 every clock cycle.ADS6129/8: Output data < D11:D0 > alternates between 101010101010 and 010101010101 every clock cycle.100 Outputs digital rampADS6149/8: Output data increments by one LSB (14-bit) every clock cycle from code 0 to code 16383ADS6129/8: Output data increments by one LSB (124-bit) every 4
th
clock cycle from code 0 to code 4095101 Outputs custom pattern as specified in registers 0x51 and 0x52.110 Unused111 Unused
J)
A7 – A0 IN HEX D7 D6 D5 D4 D3 D2 D1 D0
63 < OFFSET PEDESTAL >
< OFFSET PEDESTAL > When the offset correction is enabled, the final converged value after the offset is corrected will beD5 – D0
the ADC mid-code value.A pedestal can be added to the final converged value by programming these bits. For example, See "Offset Correction" inapplication section.011111 Mid-code + 31 LSB011110 Mid-code + 30 LSB011101 Mid-code + 29 LSB....000000 Mid-code111111 Mid-code - 1 LSB111110 Mid-code - 2 LSB....100000 Mid-code - 32 LSB
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DEVICE INFORMATION
P0023-12
DRGND
VCM
DRVDD
AGND
OVR_SDOUT
INP
CLKOUTM
INM
CLKOUTP
AGND
DFS
AVDD
OE
AGND
AVDD
AVDD
AGND
NC
CLKP
AVDD
CLKM
MODE
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DRGND
D12_D13_P
DRVDD
D12_D13_M
D0_D1_P
D10_D11_P
D0_D1_M
D10_D11_M
NC
D8_D9_P
NC
D8_D9_M
RESET
D6_D7_P
SCLK
D6_D7_M
SDATA
D4_D5_P
SEN
D4_D5_M
AVDD
D2_D3_P
AGND
D2_D3_M
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
ThermalPad
PadisconnectedtoDRGND
P0023-13
DRGND
VCM
DRVDD
AGND
OVR_SDOUT
INP
CLKOUTM
INM
CLKOUTP
AGND
DFS
AVDD
OE
AGND
AVDD
AVDD
AGND
NC
CLKP
AVDD
CLKM
MODE
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DRGND
D10_D11_P
DRVDD
D10_D11_M
NC
D8_D9_P
NC
D8_D9_M
NC
D6_D7_P
NC
D6_D7_M
RESET
D4_D5_P
SCLK
D4_D5_M
SDATA
D2_D3_P
SEN
D2_D3_M
AVDD
D0_D1_P
AGND
D0_D1_M
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
ThermalPad
PadisconnectedtoDRGND
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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Figure 9. PIN CONFIGURATION (LVDS MODE) — ADS6149/48
Figure 10. PIN CONFIGURATION (LVDS MODE) — ADS6129/28
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Table 8. PIN ASSIGNMENTS (LVDS MODE) — ADS6149/48 and ADS6129/28PIN NO.I/O of DESCRIPTIONNAME NO.
PINS
8, 18, 20,AVDD I 6 3.3-V Analog power supply22, 24, 26
9, 12, 14,AGND I 6 Analog ground17, 19, 25
CLKP, CLKM 10, 11 I 2 Differential clock input
INP, INM 15, 16 I 2 Differential analog input
Internal reference mode – Common-mode voltage output.VCM 13 IO 1
External reference mode – Reference input. The voltage forced on this pin sets the internalreferences
Serial interface RESET input.When using the serial interface mode, the user MUST initialize internal registers through hardwareRESET by applying a high-going pulse on this pin or by using software reset option. Refer toSERIAL INTERFACE section.RESET 30 I 1
In parallel interface mode, the user has to tie RESET pin permanently HIGH. (SDATA and SENare used as parallel pin controls in this mode)The pin has an internal 100 k Ωpull-down resistor.SCLK 29 I 1 Serial interface clock input. The pin has an internal 100 k Ωpull-down resistor.
This pin functions as serial interface data input when RESET is LOW. It functions as power down control pinwhen RESET is tied high.SDATA 28 I 1
See Table 3 for detailed information.The pin has an internal 100 k Ωpull-down resistor.This pin functions as serial interface enable input when RESET is low.It functions as output clock edge control when RESET is tied high. See Table 4 for detailedSEN 27 I 1
information.
The pin has an internal 100 k Ωpull-up resistor to AVDD.OE 7 I 1 Output buffer enable input, active high. The pin has an internal 100 k Ωpull-up resistor to AVDD.
Data Format Select input. This pin sets the DATA FORMAT (2s complement or Offset binary) and theLVDS/CMOS output interface type.DFS 6 I 1
See Table 5 for detailed information.Internal or external reference selection and low speed mode control. control. See Table 6 for detailedMODE
(1)
23 I 1
information.
CLKOUTP 5 O 1 Differential output clock, true
CLKOUTM 4 O 1 Differential output clock, complement
D0_D1_P O 1 Differential output data D0 and D1 multiplexed, true
D0_D1_M O 1 Differential output data D0 and D1 multiplexed, complement
D2_D3_P O 1 Differential output data D2 and D3 multiplexed, true
D2_D3_M O 1 Differential output data D2 and D3 multiplexed, complement
D4_D5_P O 1 Differential output data D4 and D5 multiplexed, true
D4_D5_M O 1 Differential output data D4 and D5 multiplexed, complementSeeD6_D7_P O 1 Differential output data D6 and D7 multiplexed, trueFigure 9andD6_D7_M O 1 Differential output data D6 and D7 multiplexed, complementFigure 10D8_D9_P O 1 Differential output data D8 and D9 multiplexed, true
D8_D9_M O 1 Differential output data D8 and D9 multiplexed, complement
D10_D11_P O 1 Differential output data D10 and D11 multiplexed, true
D10_D11_M O 1 Differential output data D10 and D11 multiplexed, complement
D12_D13_P O 1 Differential output data D12 and D13 multiplexed, true
D12_D13_M O 1 Differential output data D12 and D13 multiplexed, complement
It is a CMOS output with logic levels determined by DRVDD supply. It functions as out-of-range indicator afterOVR_SDOUT 3 O 1 reset and when register bit < SERIAL READOUT > = 0. It functions as serial register readout pin when register bit< SERIAL READOUT > = 1.
(1) In the next generation pin-compatible ADC family, MODE will be converted to a digital control pin for certain reserved functions. So, theselection of internal or external reference and low speed functions will not be supported using MODE. In the system board usingADS61x9/x8, the MODE pin can be routed to a digital controller. This will avoid board modification while migrating to the next generationADC.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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Table 8. PIN ASSIGNMENTS (LVDS MODE) — ADS6149/48 and ADS6129/28 (continued)PIN NO.I/O of DESCRIPTIONNAME NO.
PINS
DRVDD 2, 35 I 2 1.8 V Digital and output buffer supply
DRGND 1, 36, PAD I 2 Digital and output buffer ground
See
Figure 9NC Do not connectand
Figure 10
26 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
P0023-14
DRGND
VCM
DRVDD
AGND
OVR_SDOUT
INP
UNUSED
INM
CLKOUT
AGND
DFS
AVDD
OE
AGND
AVDD
AVDD
AGND
NC
CLKP
AVDD
CLKM
MODE
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DRGND
D13
DRVDD
D12
D1
D11
D0
D10
NC
D9
NC
D8
RESET
D7
SCLK
D6
SDATA
D5
SEN
D4
AVDD
D3
AGND
D2
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
ThermalPad
PadisconnectedtoDRGND
P0023-15
DRGND
VCM
DRVDD
AGND
OVR_SDOUT
INP
UNUSED
INM
CLKOUT
AGND
DFS
AVDD
OE
AGND
AVDD
AVDD
AGND
NC
CLKP
AVDD
CLKM
MODE
AGND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DRGND
D11
DRVDD
D10
NC
D9
NC
D8
NC
D7
NC
D6
RESET
D5
SCLK
D4
SDATA
D3
SEN
D2
AVDD
D1
AGND
D0
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
ThermalPad
PadisconnectedtoDRGND
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Figure 11. PIN CONFIGURATION (CMOS MODE) – ADS6149/48
Figure 12. PIN CONFIGURATION (CMOS MODE) – ADS6129/28
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
PIN ASSIGNMENTS (CMOS MODE) – ADS6149/48 and ADS6129/28
PIN
NO. ofI/O DESCRIPTIONPINSNAME NO.
8, 18, 20, 3.3-V Analog power supplyAVDD I 622, 24, 269, 12, 14, Analog groundAGND I 617, 19, 25CLKP, CLKM 10, 11 I 2 Differential clock inputINP, INM 15, 16 I 2 Differential analog inputInternal reference mode – Common-mode voltage output.VCM 13 IO 1
External reference mode – Reference input. The voltage forced on this pin sets the internalreferences
Serial interface RESET input.When using the serial interface mode, the user MUST initialize internal registers throughhardware RESET by applying a high-going pulse on this pin or by using software reset option.Refer to SERIAL INTERFACE section.RESET 30 I 1
In parallel interface mode, the user has to tie RESET pin permanently HIGH. (SDATA and SENare used as parallel pin controls in this mode)The pin has an internal 100 k Ωpull-down resistor.SCLK 29 I 1 Serial interface clock input. The pin has an internal 100 k Ωpull-down resistor.This pin functions as serial interface data input when RESET is LOW. It functions as power downcontrol pin when RESET is tied high.SDATA 28 I 1
See Table 3 for detailed information.The pin has an internal 100 k Ωpull-down resistor.This pin functions as serial interface enable input when RESET is low.It functions as output clock edge control when RESET is tied high. See Table 4 for detailedSEN 27 I 1
information.
The pin has an internal 100 k Ωpull-up resistor to AVDD.Data Format Select input. This pin sets the DATA FORMAT (2s complement or Offset binary)and the LVDS/CMOS output interface type.DFS 6 I 1
See Table 5 for detailed information.Internal or external reference selection control and low speed mode control. See Table 6 forMODE 23 I 1
detailed information.CLKOUT 5 O 1 CMOS output clockOE 7 I 1 Output buffer enable input, active high. The pin has an internal 100 k Ωpull-up resistor to AVDD.CLKOUTM 4 O 1 Differential output clock, complementSee
Figure 11D0 – D13 O 14/12 14 bit/12 bit CMOS output dataand
Figure 12
It is a CMOS output with logic levels determined by DRVDD supply. It functions as out-of-rangeOVR_SDOUT 3 O 1 indicator after reset and when register bit < SERIAL READOUT > = 0. It functions as serialregister readout pin when < SERIAL READOUT > = 1.DRVDD 2, 35 I 2 1.8 V Digital and output buffer supplyDRGND 1, 36, PAD I 2 Digital and output buffer groundUNUSED 4 1 Unused pin in CMOS modeSee
Figure 11NC Do not connectand
Figure 12
28 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS - ADS6149
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G001
SFDR = 94.6 dBc
SINAD = 73.3 dBFS
SNR = 73.4 dBFS
THD = 90.2 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G002
SFDR = 87.7 dBc
SINAD = 72.7 dBFS
SNR = 73 dBFS
THD = 84 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G003
SFDR = 81.8 dBc
SINAD = 70.8 dBFS
SNR = 71.3 dBFS
THD = 79.7 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G004
SFDR = 76.3 dBc
SINAD = 68.1 dBFS
SNR = 69.1 dBFS
THD = 73.8 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G005
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –90.6 dBFS
SFDR = –91 dBFS
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G006
fIN1 = 185.1 MHz, –36 dBFS
fIN2 = 190.1 MHz, –36 dBFS
2-Tone IMD = –105 dBFS
SFDR = –103 dBFS
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface, 32K point FFT (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL FFT for 60 MHz INPUT SIGNAL
Figure 13. Figure 14.
FFT for 170 MHz INPUT SIGNAL FFT for 300 MHz INPUT SIGNAL
Figure 15. Figure 16.
FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD)
Figure 17. Figure 18.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
fIN − Input Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G007
CMOS
LVDS
fIN − Input Frequency − MHz
64
65
66
67
68
69
70
71
72
73
74
0 50 100 150 200 250 300 350 400 450 500
SNR − dBFS
G008
CMOS
LVDS
fIN − Input Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G009
Input adjusted to get −1dBFS input
1 dB 0 dB
5 dB
6 dB
3 dB
2 dB
4 dB
fIN − Input Frequency − MHz
55
57
59
61
63
65
67
69
71
73
75
0 50 100 150 200 250 300 350 400 450 500
SINAD − dBFS
G010
1 dB
3 dB 4 dB 6 dB
2 dB
0 dB
5 dB
Input adjusted to get −1dBFS input
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS - ADS6149 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface, 32K point FFT (unless otherwise noted)
SFDR SNRvs vsINPUT FREQUENCY INPUT FREQUENCY
Figure 19. Figure 20.
SFDR SINADvs vsGAIN GAIN
Figure 21. Figure 22.
30 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
SNR − dBFS
71
72
73
74
75
76
VCM − Common-Mode Voltage of Analog Inputs − V
80
82
84
86
88
90
1.35 1.40 1.45 1.50 1.55 1.60 1.65
fIN = 60 MHz
SFDR − dBc
G012
SNR
SFDR
70
71
72
73
74
75
76
77
78
SNR − dBFS
Input Amplitude − dBFS
30
40
50
60
70
80
90
100
110
−60 −50 −40 −30 −20 −10 0
SFDR − dBc, dBFS
G011
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
fIN = 60 MHz
SNR − dBFS
70
71
72
73
74
75
76
77
78
AVDD − Supply Voltage − V G013
80
82
84
86
88
90
92
94
96
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
SFDR − dBc
SNR
SFDR
fIN = 60.1 MHz
DRVDD = 1.8 V
SNR − dBFS
70
71
72
73
74
75
76
77
78
DRVDD − Supply Voltage − V G014
76
78
80
82
84
86
88
90
92
1.6 1.7 1.8 1.9 2.0
SFDR − dBc
SNR
SFDR
fIN = 60.1 MHz
AVDD = 3.3 V
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS - ADS6149 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface, 32K point FFT (unless otherwise noted)
PERFORMANCE PERFORMANCEvs vsINPUT AMPLITUDE INPUT COMMON-MODE VOLTAGE
Figure 23. Figure 24.
PERFORMANCE PERFORMANCEvs vsAVDD SUPPLY DRVDD SUPPLY
Figure 25. Figure 26.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
71
72
73
74
75
76
77
T − Temperature − °CG015
SNR − dBFS
80
82
84
86
88
90
92
−40 −20 0 20 40 60 80
SFDR − dBc
SFDR
SNR
fIN = 60 MHz
SNR − dBFS
70
71
72
73
74
75
76
77
78
78
80
82
84
86
88
90
92
94
0.20 0.70 1.20 1.70 2.20 2.70
SFDR − dBc
Input Clock Amplitude − VPP G016
SNR
SFDR
fIN = 60 MHz
SNR − dBFS
71
72
73
74
75
76
VVCM − VCM Voltage − V
80
82
84
86
88
90
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
fIN = 60 MHz
External Reference Mode
SFDR − dBc
G018
SNR
SFDR
SNR − dBFS
71
72
73
74
75
76
77
Input Clock Duty Cycle − % G017
72
76
80
84
88
92
96
30 35 40 45 50 55 60 65 70
SFDR − dBc
SNR
SFDR
fIN = 5 MHz
0
5
10
15
20
25
30
35
40
8203 8204 8205 8206 8207 8208 8209 8210 8211 8212
Occurence − %
RMS (LSB) = 0.995
Output Code G019
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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TYPICAL CHARACTERISTICS - ADS6149 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface, 32K point FFT (unless otherwise noted)
PERFORMANCE PERFORMANCEvs vsTEMPERATURE INPUT CLOCK AMPLITUDE
Figure 27. Figure 28.
PERFORMANCE PERFORMANCEvs vsINPUT CLOCK DUTY CYCLE VCM VOLTAGE
Figure 29. Figure 30.
OUTPUT NOISE HISTOGRAM
Figure 31.
32 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS - ADS6148
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G020
SFDR = 90.75 dBc
SINAD = 73.13 dBFS
SNR = 73.25 dBFS
THD = 87.76 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G021
SFDR = 92.3 dBc
SINAD = 72.9 dBFS
SNR = 73 dBFS
THD = 89 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G022
SFDR = 82.44 dBc
SINAD = 70.81 dBFS
SNR = 71.17 dBFS
THD = 80.89 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G023
SFDR = 76.3 dBc
SINAD = 68.5 dBFS
SNR = 69.3 dBFS
THD = 75.1 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G024
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –90 dBFS
SFDR = –88 dBFS
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G025
fIN1 = 185.1 MHz, –36 dBFS
fIN2 = 190.1 MHz, –36 dBFS
2-Tone IMD = –101 dBFS
SFDR = –97 dBFS
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL FFT for 60 MHz INPUT SIGNAL
Figure 32. Figure 33.
FFT for 170 MHz INPUT SIGNAL FFT for 300 MHz INPUT SIGNAL
Figure 34. Figure 35.
FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD)
Figure 36. Figure 37.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
fIN − Input Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G026
CMOS
LVDS
fIN − Input Frequency − MHz
64
65
66
67
68
69
70
71
72
73
74
0 50 100 150 200 250 300 350 400 450 500
SNR − dBFS
G027
CMOS
LVDS
fIN − Input Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G028
Input adjusted to get −1dBFS input
1 dB 0 dB
5 dB
3 dB
2 dB
4 dB
6 dB
fIN − Input Frequency − MHz
55
57
59
61
63
65
67
69
71
73
75
0 50 100 150 200 250 300 350 400 450 500
SINAD − dBFS
G029
3 dB
4 dB
2 dB
0 dB
5 dB
1 dB
Input adjusted to get −1dBFS input
6 dB
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS - ADS6148 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
SFDR SNRvs vsINPUT FREQUENCY INPUT FREQUENCY
Figure 38. Figure 39.
SFDR SINADvs vsGAIN GAIN
Figure 40. Figure 41.
34 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
70
71
72
73
74
75
76
77
78
SNR − dBFS
Input Amplitude − dBFS
30
40
50
60
70
80
90
100
110
−60 −50 −40 −30 −20 −10 0
SFDR − dBc, dBFS
G030
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
fIN = 60 MHz
SNR − dBFS
71
72
73
74
75
76
VCM − Common-Mode Voltage of Analog Inputs − V
86
88
90
92
94
96
1.35 1.40 1.45 1.50 1.55 1.60 1.65
fIN = 60.1 MHz
SFDR − dBc
G031
SNR
SFDR
SNR − dBFS
70
71
72
73
74
75
76
77
78
AVDD − Supply Voltage − V G032
80
82
84
86
88
90
92
94
96
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
SFDR − dBc
SNR
SFDR
fIN = 60.1 MHz
DRVDD = 1.8 V
SNR − dBFS
70
71
72
73
74
75
76
77
78
DRVDD − Supply Voltage − V G033
80
82
84
86
88
90
92
94
96
1.6 1.7 1.8 1.9 2.0
SFDR − dBc
SNR
SFDR
fIN = 60.1 MHz
AVDD = 3.3 V
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS - ADS6148 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
PERFORMANCE PERFORMANCEvs vsINPUT AMPLITUDE INPUT COMMON-MODE VOLTAGE
Figure 42. Figure 43.
PERFORMANCE PERFORMANCEvs vsAVDD SUPPLY DRVDD SUPPLY
Figure 44. Figure 45.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
71
72
73
74
75
76
77
T − Temperature − °CG034
SNR − dBFS
80
82
84
86
88
90
92
−40 −20 0 20 40 60 80
SFDR − dBc
SFDR
SNR
fIN = 60.1 MHz
SNR − dBFS
70
71
72
73
74
75
76
77
78
80
82
84
86
88
90
92
94
96
0.20 0.70 1.20 1.70 2.20
SFDR − dBc
Input Clock Amplitude − VPP G035
SNR
SFDR
fIN = 60 MHz
SNR − dBFS
71
72
73
74
75
76
77
Input Clock Duty Cycle − % G036
72
76
80
84
88
92
96
30 35 40 45 50 55 60 65 70
SFDR − dBc
SNR
SFDR
fIN = 5 MHz
SNR − dBFS
71
72
73
74
75
76
VVCM − VCM Voltage − V
86
88
90
92
94
96
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
fIN = 60.1 MHz
External Reference Mode
SFDR − dBc
G037
SNR
SFDR
0
5
10
15
20
25
30
35
40
8203 8204 8205 8206 8207 8208 8209 8210 8211 8212
Occurence − %
RMS (LSB) = 1
Output Code G038
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS - ADS6148 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
PERFORMANCE PERFORMANCEvs vsTEMPERATURE INPUT CLOCK AMPLITUDE
Figure 46. Figure 47.
PERFORMANCE PERFORMANCEvs vsINPUT CLOCK DUTY CYCLE VCM VOLTAGE
Figure 48. Figure 49.
OUTPUT NOISE HISTOGRAM
Figure 50.
36 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS - ADS6129
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G039
SFDR = 94.87 dBc
SINAD = 70.73 dBFS
SNR = 70.77 dBFS
THD = 89.9 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G040
SFDR = 87.8 dBc
SINAD = 70.5 dBFS
SNR = 70.6 dBFS
THD = 84 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G041
SFDR = 81.9 dBc
SINAD = 69.2 dBFS
SNR = 69.5 dBFS
THD = 79.7 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G042
SFDR = 76.09 dBc
SINAD = 67.13 dBFS
SNR = 67.95 dBFS
THD = 73.72 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G043
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –90.5 dBFS
SFDR = –91 dBFS
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 25 50 75 100 125
Amplitude − dB
G044
fIN1 = 185.1 MHz, –36 dBFS
fIN2 = 190.1 MHz, –36 dBFS
2-Tone IMD = –103 dBFS
SFDR = –97 dBFS
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL FFT for 60 MHz INPUT SIGNAL
Figure 51. Figure 52.
FFT for 170 MHz INPUT SIGNAL FFT for 300 MHz INPUT SIGNAL
Figure 53. Figure 54.
FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD)
Figure 55. Figure 56.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
fIN − Input Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G045
CMOS
LVDS
fIN − Input Frequency − MHz
64
65
66
67
68
69
70
71
72
73
74
0 50 100 150 200 250 300 350 400 450 500
SNR − dBFS
G046
CMOS
LVDS
fIN − Input Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G047
Input adjusted to get −1dBFS input
1 dB 0 dB
5 dB
3 dB
2 dB
4 dB
6 dB
fIN − Input Frequency − MHz
55
57
59
61
63
65
67
69
71
73
75
0 50 100 150 200 250 300 350 400 450 500
SINAD − dBFS
G048
3 dB 4 dB
Input adjusted to get −1dBFS input
0 dB 1 dB 2 dB
5 dB 6 dB
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS - ADS6129 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
SFDR SNRvs vsINPUT FREQUENCY INPUT FREQUENCY
Figure 57. Figure 58.
SFDR SINADvs vsGAIN GAIN
Figure 59. Figure 60.
38 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
68
69
70
71
72
73
74
75
76
SNR − dBFS
Input Amplitude − dBFS
30
40
50
60
70
80
90
100
110
−60 −50 −40 −30 −20 −10 0
SFDR − dBc, dBFS
G049
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
fIN = 60 MHz
SNR − dBFS
69
70
71
72
73
74
VCM − Common-Mode Voltage of Analog Inputs − V
82
84
86
88
90
92
1.35 1.40 1.45 1.50 1.55 1.60 1.65
fIN = 60 MHz
SFDR − dBc
G050
SNR
SFDR
SNR − dBFS
68
69
70
71
72
73
74
75
76
DRVDD − Supply Voltage − V G052
80
82
84
86
88
90
92
94
96
1.6 1.7 1.8 1.9 2.0
SFDR − dBc
SNR
SFDR
fIN = 60.1 MHz
AVDD = 3.3 V
SNR − dBFS
68
69
70
71
72
73
74
75
76
AVDD − Supply Voltage − V G051
80
82
84
86
88
90
92
94
96
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
SFDR − dBc
SNR
SFDR
fIN = 60.1 MHz
DRVDD = 1.8 V
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS - ADS6129 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
PERFORMANCE PERFORMANCEvs vsINPUT AMPLITUDE INPUT COMMON-MODE VOLTAGE
Figure 61. Figure 62.
PERFORMANCE PERFORMANCEvs vsAVDD SUPPLY DRVDD SUPPLY
Figure 63. Figure 64.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
68
69
70
71
72
73
74
T − Temperature − °CG053
SNR − dBFS
80
82
84
86
88
90
92
−40 −20 0 20 40 60 80
SFDR − dBc
SFDR
SNR
fIN = 60 MHz
SNR − dBFS
68
69
70
71
72
73
74
75
76
78
80
82
84
86
88
90
92
94
0.20 0.70 1.20 1.70 2.20 2.70
SFDR − dBc
Input Clock Amplitude − VPP G054
SNR
SFDR
fIN = 60 MHz
SNR − dBFS
69
70
71
72
73
74
75
Input Clock Duty Cycle − % G055
72
76
80
84
88
92
96
30 35 40 45 50 55 60 65 70
SFDR − dBc
SNR
SFDR
fIN = 5 MHz
SNR − dBFS
69
70
71
72
73
74
VVCM − VCM Voltage − V
80
82
84
86
88
90
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
fIN = 60.1 MHz
External Reference Mode
SFDR − dBc
G056
SNR
SFDR
0
10
20
30
40
50
60
2047 2048 2049 2050 2051 2052 2053 2054 2055 2056
Occurence − %
Output Code G057
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS - ADS6129 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
PERFORMANCE PERFORMANCEvs vsTEMPERATURE INPUT CLOCK AMPLITUDE
Figure 65. Figure 66.
PERFORMANCE PERFORMANCEvs vsINPUT CLOCK DUTY CYCLE VCM VOLTAGE
Figure 67. Figure 68.
OUTPUT NOISE HISTOGRAM
Figure 69.
40 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS - ADS6128
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G058
SFDR = 90.8 dBc
SINAD = 70.6 dBFS
SNR = 70.7 dBFS
THD = 87.8 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G059
SFDR = 92.5 dBc
SINAD = 70.5 dBFS
SNR = 70.6 dBFS
THD = 88.9 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G060
SFDR = 82.59 dBc
SINAD = 69.18 dBFS
SNR = 69.42 dBFS
THD = 80.99 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G061
SFDR = 76.3 dBc
SINAD = 67.5 dBFS
SNR = 68.1 dBFS
THD = 75.1 dBc
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G062
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –90 dBFS
SFDR = –88 dBFS
f − Frequency − MHz
−160
−140
−120
−100
−80
−60
−40
−20
0
0 20 40 60 80 100
Amplitude − dB
G063
fIN1 = 185.1 MHz, –36 dBFS
fIN2 = 190.1 MHz, –36 dBFS
2-Tone IMD = –101 dBFS
SFDR = –96 dBFS
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL FFT for 60 MHz INPUT SIGNAL
Figure 70. Figure 71.
FFT for 170 MHz INPUT SIGNAL FFT for 300 MHz INPUT SIGNAL
Figure 72. Figure 73.
FFT for 2-TONE INPUT SIGNAL (IMD) FFT for 2-TONE INPUT SIGNAL (IMD)
Figure 74. Figure 75.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 41
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
fIN − Input Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G064
CMOS
LVDS
fIN − Input Frequency − MHz
64
65
66
67
68
69
70
71
72
73
74
0 50 100 150 200 250 300 350 400 450 500
SNR − dBFS
G065
CMOS
LVDS
fIN − Input Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300 350 400 450 500
SFDR − dBc
G066
Input adjusted to get −1dBFS input
1 dB 0 dB
5 dB
3 dB
2 dB
4 dB
6 dB
fIN − Input Frequency − MHz
55
57
59
61
63
65
67
69
71
73
75
0 50 100 150 200 250 300 350 400 450 500
SINAD − dBFS
G067
3 dB 4 dB
Input adjusted to get −1dBFS input
0 dB 1 dB 2 dB
5 dB 6 dB
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS - ADS6128 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
SFDR SNRvs vsINPUT FREQUENCY INPUT FREQUENCY
Figure 76. Figure 77.
SFDR SINADvs vsGAIN GAIN
Figure 78. Figure 79.
42 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
68
69
70
71
72
73
74
75
76
SNR − dBFS
Input Amplitude − dBFS
30
40
50
60
70
80
90
100
110
−60 −50 −40 −30 −20 −10 0
SFDR − dBc, dBFS
G068
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
fIN = 60 MHz
SNR − dBFS
69
70
71
72
73
74
VCM − Common-Mode Voltage of Analog Inputs − V
86
88
90
92
94
96
1.35 1.40 1.45 1.50 1.55 1.60 1.65
fIN = 60 MHz
SFDR − dBc
G069
SNR
SFDR
SNR − dBFS
68
69
70
71
72
73
74
75
76
AVDD − Supply Voltage − V G070
80
82
84
86
88
90
92
94
96
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
SFDR − dBc
SNR
SFDR
fIN = 60.1 MHz
DRVDD = 1.8 V
SNR − dBFS
68
69
70
71
72
73
74
75
76
DRVDD − Supply Voltage − V G071
80
82
84
86
88
90
92
94
96
1.6 1.7 1.8 1.9 2.0
SFDR − dBc
SNR
SFDR
fIN = 60.1 MHz
AVDD = 3.3 V
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS - ADS6128 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
PERFORMANCE PERFORMANCEvs vsINPUT AMPLITUDE INPUT COMMON-MODE VOLTAGE
Figure 80. Figure 81.
PERFORMANCE PERFORMANCEvs vsAVDD SUPPLY DRVDD SUPPLY
Figure 82. Figure 83.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
69
70
71
72
73
74
75
T − Temperature − °CG072
SNR − dBFS
82
84
86
88
90
92
94
−40 −20 0 20 40 60 80
SFDR − dBc
SFDR
SNR
fIN = 60.1 MHz
SNR − dBFS
68
69
70
71
72
73
74
75
76
80
82
84
86
88
90
92
94
96
0.20 0.70 1.20 1.70 2.20
SFDR − dBc
Input Clock Amplitude − VPP G073
SNR
SFDR
fIN = 60 MHz
SNR − dBFS
69
70
71
72
73
74
75
Input Clock Duty Cycle − % G074
72
76
80
84
88
92
96
30 35 40 45 50 55 60 65 70
SFDR − dBc
SNR
SFDR
fIN = 5 MHz
SNR − dBFS
69
70
71
72
73
74
VVCM − VCM Voltage − V
86
88
90
92
94
96
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
fIN = 60.1 MHz
External Reference Mode
SFDR − dBc
G075
SNR
SFDR
0
10
20
30
40
50
60
2048 2049 2050 2051 2052 2053 2054 2055 2056
Occurence − %
Output Code G076
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS - ADS6128 (continued)All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
PERFORMANCE PERFORMANCEvs vsTEMPERATURE INPUT CLOCK AMPLITUDE
Figure 84. Figure 85.
PERFORMANCE PERFORMANCEvs vsINPUT CLOCK DUTY CYCLE VCM VOLTAGE
Figure 86. Figure 87.
OUTPUT NOISE HISTOGRAM
Figure 88.
44 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
TYPICAL CHARACTERISTICS - COMMON PLOTS
fIN − Input Frequency − MHz
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 20 40 60 80 100
CMRR − dB
G079
fS − Sampling Frequency − MSPS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 50 100 150 200 250
P − Total Power − W
G077
CMOS
LVDS
CL = 10 pF
fS − Sampling Frequency − MSPS
0
10
20
30
40
50
60
70
80
90
100
0 50 100 150 200 250
IDRVDD − DRVDD Current − mA
G078
CMOS
LVDS
fIN = 3 MHz
CL = 10 pF
OE Disabled
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
All plots are at 25 ° C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V
PPdifferential clock amplitude, 50% clock duty cycle, – 1 DBFS differential analog input, internal reference mode, 0 dB gain,LVDS output interface (unless otherwise noted)
CMRR TOTAL POWERvs vsINPUT FREQUENCY SAMPLING FREQUENCY
Figure 89. Figure 90.
DRVDD CURRENT
vsSAMPLING FREQUENCY
Figure 91.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
CONTOUR PLOTS - ADS6149/ADS6148/ADS6129/ADS6128
20 50 150 200
f -InputFrequency-MHz
IN
f -SamplingFrequency-MSPS
S
SFDR-dBc
250 350 500
80
100
200
120
140
160
180
220
240
250
65 70 75
M0049-17
68
68
68
72
76
76
76
76
72
72
84
84
84
84
84
84
84
84
80
80
80
80
88
60
64
64
64
60
60
60
80 85
100 300
90 95
450400
88
88
88
92
92
92
88
20 200 300
f -InputFrequency-MHz
IN
f -SamplingFrequency-MSPS
S
SFDR-dBc
400 800
80
100
200
120
140
160
180
220
240
250
65 70
M0049-18
68
68
68
72
72
76
76
76
72
72
84
84
84
84
84
84 84
84
84 84
80
80
80
88
60
64
64
64
60
60
60
80 85
100 500
90 95
700600
88
88
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
Plots are at 25 ° C, AVDD = 3.3V, DRVDD = 1.8 V, sine wave input clock, 1.5 V
PP
differential clock amplitude, 50% clock dutycycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted)
Figure 92. SFDR Contour Plot (0 dB gain)
Figure 93. SFDR Contour Plot (6 dB gain)
46 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
CONTOUR PLOTS - ADS6149/ADS6148
20 50 150 200
f -InputFrequency-MHz
IN
f -SamplingFrequency-MSPS
S
SNR-dBFS
250 350 500
80
100
200
120
140
160
180
220
240
250
66 67 68
M0048-19
67
67
67
68
68
68
69
69
69
72
72
72
73
73
73
74
70
70
70
71
71
71
64
65
66
66
66
69 70
100 300
71 74
450400
65 7572 73
20 200 300
f -InputFrequency-MHz
IN
f -SamplingFrequency-MSPS
S
SNR-dBFS
400 800
80
100
200
120
140
160
180
220
240
250
61 63
M0048-20
60
64
65
65
65
66
66
66
67
68
68
67
67
63
63
63
64
64
62
62
62
61
64 65
100 500
67 69
700600
62 66 68
ADS6149/ADS6129
ADS6148/ADS6128
www.ti.com
..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Plots are at 25 ° C, AVDD = 3.3V, DRVDD = 1.8 V, sine wave input clock, 1.5 V
PP
differential clock amplitude, 50% clock dutycycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, LVDS output interface (unless otherwise noted)
Figure 94. SNR Contour Plot (0 dB gain)
Figure 95. SNR Contour Plot (6 dB gain)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 47
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
APPLICATION INFORMATION
THEORY OF OPERATION
ANALOG INPUT
INP
INM
Cbond
~ 1 pF Csamp
2 pF
RCRFilter
Sampling
Capacitor
Sampling
Switch
Sampling
Switch
Ron
15 W
Ron
15 W
Csamp
2pF
10 W
10 W
100 W
100 W
3 pF
Cpar1
0.25 pF
Lpkg~1 nH
Cbond
~ 1 pF
Resr
200 W
Resr
200 W
Cpar2
0.5 pF
Cpar2
0.5 pF
Sampling
Capacitor
Ron
10 W
Lpkg~1 nH
3 pF
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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ADS6149/48 and ADS6129/28 is a family of high performance, low power 14-bit and 12-bit pipeline A/Dconverters with maximum sampling rate up to 250 MSPS.
At every rising edge of the input clock, the analog input signal is sampled and sequentially converted by apipeline of low resolution stages. In each stage, the sampled and held signal is converted by a high speed, lowresolution flash sub-ADC. The difference (residue) between the stage input and its quantized equivalent isgained and propagates to the next stage. At every clock, each succeeding stage resolves the sampled input withgreater accuracy. The digital outputs from all stages are combined in a digital correction logic block to create thefinal 14 or 12 bit code, after a data latency of 18 clock cycles.
The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary orbinary 2s complement format.
The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with2V
PP
amplitude) and about 800MHz (with 1V
PP
amplitude).
The analog input consists of a switched-capacitor based differential sample and hold architecture.
This differential topology results in a good AC performance even for high input frequencies at high samplingrates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available onVCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM +0.5V and VCM – 0.5V, resulting in a 2Vpp differential input swing.
Figure 96. Analog Input Equivalent Circuit
The input sampling circuit has a high 3-dB bandwidth that extends up to 700 MHz (measured from the input pinsto the sampled voltage).
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Drive Circuit Requirements
0.01
0.1
1
10
100
0 100 200 300 400 500 600 700 800 900 1000
f-Frequency-MHz
Resistance-kW
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
For optimum performance, the analog inputs must be driven differentially. This improves the common-modenoise immunity and even order harmonic rejection. A 5 Ωto 15 Ωresistor in series with each input pin isrecommended to damp out ringing caused by package parasitics. It is also necessary to present low impedance( < 50 Ω) for the common mode switching currents. This can be achieved by using two resistors from each inputterminated to the common mode voltage (VCM).
Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is toabsorb the glitches caused by the opening and closing of the sampling capacitors. The cut-off frequency of theR-C filter involves a trade-off. A lower cut-off frequency (larger C) absorbs glitches better, but also reduces theinput bandwidth and the maximum input frequency that can be supported. On the other hand, with no internalR-C filter, high input frequency can be supported, but now the sampling glitches need to be supplied by theexternal driving circuit. This has limitations due to the presence of the package bond-wire inductance.
In ADS61x9/x8, the R-C component values have been optimized while supporting high input bandwidth (up to750 MHz). However, in applications where high input frequency support is not required, the filtering of theglitches can be improved further using an external R-C-R filter (as shown in Figure 99 and Figure 100 ).
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over thedesired frequency range and matched impedance to the source. While doing this, the ADC input impedancemust be considered. Figure 97 and Figure 98 show the impedance (Zin = Rin || Cin) looking into the ADC inputpins.
Figure 97. ADC Analog Input Resistance (Rin) Across Frequency
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1
1.5
2
2.5
3
3.5
4
4.5
0 100 200 300 400 500 600 700 800 900 1000
f-Frequency-MHz
Capacitance-pF
Driving Circuit
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
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Figure 98. ADC Analog Input Capacitance (Cin) Across Frequency
Two example driving circuit configurations are shown in Figure 99 and Figure 100 – one optimized for lowbandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies.
In Figure 99 , an external R-C-R filter using 22pF has been used. Together with the series inductor (39nH), thiscombination forms a filter and absorbs the sampling glitches. Due to the large capacitor (22pF) in the R-C-R andthe 15 Ωresistors in series with each input pin, the drive circuit has low bandwidth, and supports low inputfrequencies ( < 100MHz)..
To support high input frequencies (up to about 300MHz, see Figure 100 ), the capacitance used in the R-C-R isreduced to 3.3pF and the series inductors are shorted out. Together with the lower series resistors (5 Ω), thisdrive circuit provides high bandwidth and supports high input frequencies.
A transformer such as ADT1-1WT or ETC1-1-13 can be used up to 300MHz.
In Figure 100 , by dropping the external R-C-R filter, the drive circuit has high bandwidth and can support highinput frequencies (> 300MHz). For example, a transformer such as the ADTL2-18 can be used.
Note that both the drive circuits have been terminated by 50 Ωnear the ADC side. The termination isaccomplished using a 25 Ωresistor from each input to the 1.5V common-mode (VCM) from the device. Thisbiases the analog inputs around the required common-mode voltage.
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INP
INM
VCM
1:1 1:1
22 pF
50 W
0.1 Fm0.1 Fm
0.1 Fm
39nH
50 W
39nH
0.1 Fm25 W
25 W
50 W
50 W
15 W
15 W
INP
INM
VCM
1:1 1:1
25 W
3.3 pF
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
25 W
5W
5W
50 W
50 W
Input Common-Mode
500 A Fs
250 MSPS
m ´
(1)
REFERENCE
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Figure 99. Drive Circuit with Low Bandwidth (for low input frequencies)
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-orderharmonic performance. Connecting two identical RF transformers back to back helps minimize this mismatch andgood performance is obtained for high frequency input signals. An additional termination resistor pair may berequired between the two transformers as shown in the figures. The center point of this termination is connectedto ground to improve the balance between the P and M sides. The values of the terminations between thetransformers and on the secondary side have to be chosen to get an effective 50 Ω(in the case of 50 Ωsourceimpedance).
Figure 100. Drive Circuit with High Bandwidth (for high input frequencies)
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1 µF low-inductance capacitorconnected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADCsinks a common-mode current in the order of 500 µA (per input pin, at 250 MSPS). Equation 1 describes thedependency of the common-mode current and the sampling frequency.
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
ADS614X/2X has built-in internal references REFP and REFM, requiring no external components. Designschemes are used to linearize the converter load seen by the references; this and the on-chip integration of therequisite reference capacitors eliminates the need for external decoupling. The full-scale input range of theconverter can be controlled in the external reference mode as explained below. The internal or external referencemodes can be selected by programming the serial interface register bit < REF>.
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S0165-09
VCM
REFM
REFP
INTREF
INTREF
EXTREF
Internal
Reference
Internal Reference
External Reference
CLOCK INPUT
ADS6149/ADS6129
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Figure 101. Reference Section
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.Common-mode voltage (1.5V nominal) is output on VCM pin, which can be used to externally bias the analoginput pins.
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on theVCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differentialinput voltage corresponding to full-scale is given by Equation 2 .Full-scale differential input pp = (Voltage forced on VCM) × 1.33 (2)
In this mode, the 1.5V common-mode voltage to bias the input pins has to be generated externally.
ADS614X/2X clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS), withlittle or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCMusing internal 5-k Ωresistors. This allows using transformer-coupled drive circuits for sine wave clock orac-coupling for LVPECL, LVDS clock sources.
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CLKP
5kW
VCM
5kW
2 pF
20 W
Lpkg
Cbond
~1pF
Lpkg
~1nH
Cbond
~1pF
Resr
~100 W
Resr
CLKM
Clockbuffer
Ceq Ceq
20 W
~1nH
~100 W
Ceq~1to3pF,equivalentinputcapacitanceofclockbuffer
S0168-14
CLKP
CLKM
CMOSClockInput
0.1 Fm
0.1 Fm
VCM
S0167-10
CLKP
CLKM
DifferentialSine-Wave
orPECL orLVDSClockInput
0.1 Fm
0.1 Fm
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Figure 102. Internal Clock Buffer
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1- µFcapacitor, as shown in Figure 104 . For best performance, the clock inputs have to be driven differentially,reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use aclock source with low jitter. Band-pass filtering of the clock source can help reduce the effect of jitter. There is nochange in performance with a non-50% duty cycle clock input.
Figure 103. Differential Clock Driving Circuit Figure 104. Single-Ended Clock Driving Circuit
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FINE GAIN CONTROL
OFFSET CORRECTION
ADS6149/ADS6129
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ADS614X/2X includes gain settings that can be used to get improved SFDR performance (compared to no gain).The gain is programmable from 0dB to 6dB (in 0.5 dB steps). For each gain setting, the analog input full-scalerange scales proportionally, as shown in Table 9 .
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades about0.5 – 1dB. The SNR degradation is less at high input frequencies. As a result, the gain is useful at high inputfrequencies as the SFDR improvement is significant with marginal degradation in SNR.
So, the gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB.
Table 9. Full-Scale Range Across Gains
Gain, dB Type Full-Scale, V
PP
0 Default after reset 2V1 1.782 1.593 1.42Fine, programmable4 1.265 1.126 1.00
ADS61x9/x8 has an internal offset correction algorithm that estimates and corrects the dc offset up to ± 10mV.The correction can be enabled using the serial register bit < ENABLE OFFSET CORR>. Once enabled, thealgorithm estimates the channel offset and applies the correction every clock cycle. The time constant of thecorrection loop is a function of the sampling clock frequency. The time constant can be controlled using registerbits < OFFSET CORR TIME CONSTANT> as described inTable 10 .
After the offset is estimated, the correction can be locked in by setting < OFFSET CORR TIME CONSTANT> = 0.Once locked, the last estimated value is used for offset correction every clock cycle. Note that offset correction isdisabled by default after reset.
Figure 105 shows the time response of the offset correction algorithm, after it is enabled.
Table 10. Time Constant of Offset Correction Algorithm
Time constant (TCCLK), number of clock< OFFSET CORR TIME CONSTANT > D3-D0 Time constant, sec (=TCCLK x 1/Fs) (1)cycles
0000 256 k 1 ms0001 512 k 2 ms0010 1 M 4 ms0011 2 M 8 ms0100 4 M 17 ms0101 8 M 33 ms0110 16 M 67 ms0111 32 M 134 ms1000 64 M 268 ms1001 128 M 536 ms1010 256 M 1.1 s1011 512 M 2.2 s1100 RESERVED –1101 RESERVED –1110 RESERVED –1111 RESERVED –
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t − Time − µs
8148
8152
8156
8160
8164
8168
8172
8176
8180
8184
8188
8192
8196
8200
8204
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56
Code − LSB
G080
Offset Correction Disabled Offset Correction Enabled
Output Data With
36 LSB Offset
Output Data With
Offset Corrected
POWER DOWN
Power Down Global
Standby
Output Buffer Disable
Input Clock Stop
POWER SUPPLY SEQUENCE
DIGITAL OUTPUT INFORMATION
ADS6149/ADS6129
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Figure 105. Output Code Time Response With Offset Correction Enabled
ADS614X/2X has three power down modes – power down global, standby and output buffer disable.
In this mode, the entire chip including the A/D converter, internal reference and the output buffers are powereddown resulting in reduced total power dissipation of about 20 mW. The output buffers are in high impedancestate. The wake-up time from global power down to data becoming valid in normal mode is typically 25 µs.
This can be controlled using register bit < PDN GLOBAL> or using SDATA pin (in parallel configuration mode).
Here, only the A/D converter is powered down and internal references are active, resulting in fast wake-up timeof 300 ns. The total power dissipation in standby is about 120 mW.
This can be controlled using register bit < STANDBY>.
The output buffers can be disabled and put in high impedance state – wakeup time from this mode is fast, about40 ns. This can be controlled using register bit < PDN OBUF>.
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The power dissipation is about 120 mW.
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies areseparated in the device. Externally, they can be driven from separate supplies or from a single supply.
ADS614X/2X provides 14-bit/12-bit data and an output clock synchronized with the data.
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Output Interface
DDR LVDS Outputs
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
OutputClock
DatabitsD0, D1
DatabitsD2, D3
DatabitsD4, D5
DatabitsD6, D7
DatabitsD8, D9
DatabitsD10, D11
ADS612X
Pins
12bit ADCdata
LVDSBuffers
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10
_D11_M
OutputClock
DatabitsD0,D1
DatabitsD2,D3
DatabitsD4,D5
DatabitsD6,D7
DatabitsD8,D9
DatabitsD10, D11
ADS 614 X
Pins
D12_D13_P
D12_D13_M DatabitsD12, D13
14bit ADCdata
LVDSBuffers
ADS6149/ADS6129
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Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can beselected using the serial interface register bit < ODI> or using DFS pin in parallel configuration mode.
In this mode, the data bits and clock are output using LVDS (Low Voltage Differential Signal) levels. Two databits are multiplexed and output on each LVDS differential pair.
Figure 106. 14-Bit ADC LVDS Outputs Figure 107. 12-Bit ADC LVDS Outputs
Even data bits D0, D2, D4 … are output at the falling edge of CLKOUTP and the odd data bits D1, D3, D5 … areoutput at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to captureall of the data bits (see Figure 108 ).
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T0110-01
CLKOUTP
D0_D1_P,
D0_D1_M
D2_D3_P,
D2_D3_M
D4_D5_P,
D4_D5_M
D6_D7_P,
D6_D7_M
D8_D9_P,
D8_D9_M
D10_D11_P,
D10_D11_M
D12_D13_P,
D12_D13_M
D0
D2
D4
D6
D8
D10
D12
SampleN+1SampleN
D0
D2
D4
D6
D8
D10
D12
D1
D3
D5
D7
D9
D11
D13
D1
D3
D5
D7
D9
D11
D13
CLKOUTM
LVDS Buffer
ADS6149/ADS6129
ADS6148/ADS6128
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Figure 108. DDR LVDS Interface
The equivalent circuit of each LVDS output buffer is shown in Figure 109 . The buffer is designed to present anoutput impedance of 100 Ω(Rout). The differential outputs can be terminated at the receive end by a 100 Ωtermination. The buffer output impedance behaves like a source-side series termination. By absorbing reflectionsfrom the receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabledand its value cannot be changed.
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OUTP
OUTM
High
HighLow
Low
ADS6149/48/29/28
Rout
–0.35V
1.2V
0.35V +
+
+
–
–
–
External
100- LoadW
Switchimpedanceis
nominally50 ( 10%)W ±
WhentheHighswitchesareclosed,OUTP =1.375V,OUTM=1.025V
WhentheLowswitchesareclosed,OUTP =1.025V,OUTM=1.375V
WhentheHigh(orLow)switchesareclosed,Rout=100 W
S0374-01
Parallel CMOS Interface
ADS6149/ADS6129
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Figure 109. LVDS Buffer Equivalent Circuit
In the CMOS mode, each data bit is output on separate pin as CMOS voltage level, every clock cycle. The risingedge of the output clock CLKOUT can be used to latch data in the receiver (for sampling frequencies up to150 MSPS).
Up to 150 MSPS, the setup and hold timings of the output data with respect to CLKOUT are specified. It isrecommended to minimize the load capacitance seen by data and clock output pins by using short traces to thereceiver. Also, match the output data and clock traces to minimize the skew between them.
For sampling frequencies > 150 MSPS, it is recommended to use an external clock to capture data. The delayfrom input clock to output data and the data valid times are specified for the higher sampling frequencies. Thesetimings can be used to delay the input clock appropriately and use it to capture the data (see Figure 4 ).
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D13
D12
D11
•
•
•
ADS614x
Pins
14-Bit ADCData
CMOS
OutputBuffers
D2
D1
D0
CLKOUT
OVR_SDOUT
Output Buffer Strength Programmability
CMOS Interface Power Dissipation
Output Data Format
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Figure 110. CMOS Output Interface
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant ofsampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is madestronger. To minimize this, the CMOS output buffers are designed with controlled drive strength to get best SNR.The default drive strength also ensures wide data stable window for load capacitances up to 5 pF.
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on everyoutput pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clockcycle. In an actual application, the DRVDD current would be determined by the average number of output bitsswitching, which is a function of the sampling frequency and the nature of the analog input signal.
Digital current due to CMOS output switching = C
L
× DRVDD × (N × F
AVG
),
where
C
L
= load capacitance,
N x F
AVG
= average number of output bits switching.
Figure 91 shows the current across sampling frequencies at 2 MHz analog input frequency.
Two output data formats are supported – 2s complement and offset binary. They can be selected using the serialinterface register bit < DATA FORMAT> or controlling the DFS pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positiveoverdrive, the output code is 0x3FFF in offset binary output format, and 0x1FFF in 2s complement output format.For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2scomplement output format.
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BOARD DESIGN CONSIDERATIONS
Grounding
Supply Decoupling
Exposed Pad
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A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections ofthe board are cleanly partitioned. See the EVM User Guide (SLWU061 ) for details on layout and grounding.
As the ADS61x9/x8 already includes internal decoupling, minimal external decoupling can be used without lossin performance. Note that decoupling capacitors can help filter external power supply noise, so the optimumnumber of capacitors would depend on the actual application. The decoupling capacitors should be placed closeto the converter supply pins.
In addition to providing a path for heat dissipation, the pad is also electrically connected to digital groundinternally. So, it is necessary to solder the exposed pad to the ground plane for best thermal and electricalperformance.
For detailed information, see the application notes for QFN Layout Guidelines (SLOA122 ) and QFN/SON PCBAttachment (SLUA271 ).
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DEFINITION OF SPECIFICATIONS
10 S
N
P
SNR = 10Log P
(3)
10 S
N D
P
SINAD = 10Log P + P
(4)
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..................................................................................................................................................... SLWS211B – JULY 2008 – REVISED OCTOBER 2008
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB withrespect to the low frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time atwhich the sampling occurs. This delay will be different across channels. The maximum variation is specified asaperture delay variation (channel-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remainsat a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as apercentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametrictesting is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit linedetermined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gainerror is given as a percentage of the ideal input full-scale range. Gain error has two components: error due toreference inaccuracy and error due to the channel. Both these errors are specified independently as E
GREF
andE
GCHAN
.
To a first order approximation, the total gain error will be E
TOTAL
~ E
GREF
+ E
GCHAN
.
For example, if E
TOTAL
= ± 0.5%, the full-scale input varies from (1-0.5/100) x FS
ideal
to (1 + 0.5/100) x FS
ideal
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual averageidle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies thechange per degree Celsius of the parameter from T
MIN
to T
MAX
. It is calculated by dividing the maximum deviationof the parameter across the T
MIN
to T
MAX
range by the difference T
MAX
– T
MIN
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),excluding the power at DC and the first nine harmonics.
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter ’ sfull-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (P
S
) to the powerof all the other spectral components including noise (P
N
) and distortion (P
D
), but excluding dc.
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter'sfull-scale range.
Effective Number of Bits (ENOB) – The ENOB is a measure of the converter performance as compared to thetheoretical limit based on quantization noise.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 61
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
SINAD 1.76
ENOB =
6.02
-
(5)
10 S
N
P
THD = 10Log P
(6)
(ExpressedindBc)
DVSUP
DVOUT
10
PSRR=20Log
(7)
(ExpressedindBc)
DVCM
DVOUT
10
CMRR=20Log
(8)
ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 .....................................................................................................................................................
www.ti.com
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (P
S
) to the power of thefirst nine harmonics (PD).
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest otherspectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given inunits of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB tofull scale) when the power of the fundamental is extrapolated to the converter ’ s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to achange in analog supply voltage. The DC PSRR is typically given in units of mV/V.
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in thesupply voltage by the ADC. If ΔV
SUP
is the change in supply voltage and ΔVout is the resultant change of theADC output code (referred to the input), then
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after anoverload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive andnegative overload. The deviation of the first few samples after the overload (from their expected values) is noted.
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog inputcommon-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔV
OUTis the resultant change of the ADC output code (referred to the input), then
Cross-Talk (only for multi-channel ADC) – This is a measure of the internal coupling of a signal from adjacentchannel into the channel of interest. It is specified separately for coupling from the immediate neighboringchannel (near-channel) and for coupling from channel across the package (far-channel). It is usually measuredby applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channelinput. It is typically expressed in dBc.
62 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6149/ADS6129 ADS6148/ADS6128
PACKAGE OPTION ADDENDUM
www.ti.com 4-Dec-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS6128IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6128IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6128IRGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6128IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
ADS6128IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
ADS6129IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6129IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6129IRGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6129IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
ADS6129IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
ADS6148IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6148IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6148IRGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6148IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
ADS6148IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
ADS6149IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6149IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
PACKAGE OPTION ADDENDUM
www.ti.com 4-Dec-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS6149IRGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples
ADS6149IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
ADS6149IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS6128IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS6128IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS6129IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS6129IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS6148IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS6148IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS6149IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
ADS6149IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS6128IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6
ADS6128IRGZT VQFN RGZ 48 250 336.6 336.6 28.6
ADS6129IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6
ADS6129IRGZT VQFN RGZ 48 250 336.6 336.6 28.6
ADS6148IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6
ADS6148IRGZT VQFN RGZ 48 250 336.6 336.6 28.6
ADS6149IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6
ADS6149IRGZT VQFN RGZ 48 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
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