MOSEL VITELIC
1
V53C16258H
HIGH PERFORMANCE
256K X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
PRELIMINARY
V53C16258H Rev. 3.8 November 1999
HIGH PERFORMANCE 25 30 35 40 45 50
Max. RAS Access Time, (t
RAC
) 25 ns 30 ns 35 ns 40 ns 45 ns 50 ns
Max. Column Address Access Time, (t
CAA
) 13 ns 16 ns 18 ns 20 ns 22 ns 24 ns
Min. Extended Data Out Mode Cycle Time, (t
PC
) 10 ns 12 ns 14 ns 15 ns 17 ns 19 ns
Min. Read/Write Cycle Time, (t
RC
) 45 ns 60 ns 70 ns 75 ns 80 ns 90 ns
Features
■
256K x 16-bit organization
■
EDO Page Mode for a sustained data rate of
100 MHz
■
RAS access time: 25, 30, 35, 40, 45, 50 ns
■
Dual CAS Inputs
■
Low power dissipation
■
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
■
Optional Self Refresh (V53C16258SH)
■
Refresh Interval: 512 cycles/8 ms
■
Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
■
Single +5V
±
10% Power Supply
■
TTL Interface
Description
The V53C16258H is a high speed 262,144 x 16
bit high performance CMOS dynamic random
access memory. The V53C16258H offers a
combination of unique features including: EDO
Page Mode operation for higher sustained
bandwidth with Page Mode cycle times as short as
10ns. All inputs are TTL compatible. Input and
output capicatance is significantly lowered to
increase performance and minimize loading. These
features make the V53C16258H ideally suited for a
wide variety of high performance computer systems
and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns) Power Temperature
Mark
K T 25 30 35 40 45 50 Std.
0
°
C to 70
°
C • • •••••• • Blank
–40
°
C to +85
°
C • • •••••• • I
2
V53C16258H Rev. 3.8 November 1999
MOSEL VITELIC
V53C16258H
FAMILY DEVICE PKG (tRAC)
SPEED
PWR.
V 5 3 C 2 5 8
25 (25 ns)
30 (30 ns)
35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)
TEMP. BLANK (0°C to 70°C)
I (–40°C to +85°C)
BLANK (NORMAL)
K (SOJ)
H (5V)
T (TSOP-II)
H16
16258H-01
S (OPTIONAL STANDARD
SELF REFRESH)
S
Pin Names
A
0
–A
8
Address Inputs
RAS Row Address Strobe
UCAS Column Address Strobe/Upper Byte Control
LCAS Column Address Strobe/Lower Byte Control
WE Write Enable
OE Output Enable
I/O
1
–I/O
16
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC No Connect
40-Pin SOJ
PIN CONFIGURATION
Top View
5
6
7
8
9
10
11
12
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
16258H-02
39
40
38
37
36
35
34
33
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Part Name Self Refresh Supply Voltage Package Speed
V53C16258HKxx No Self Refresh 5V SOJ 25/30/35/40/45/50
V53C16258HTxx No Self Refresh 5V TSOP 25/30/35/40/45/50
V53C16258SHKxx Optional Standard Self Refresh (8ms) 5V SOJ 25/30/35/40/45/50
V53C16258SHTxx Optional Standard Self Refresh (8ms) 5V TSOP 25/30/35/40/45/50
40/44 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
5
6
7
8
9
10
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
16258H-03
43
44
42
41
40
39
38
37
36
35
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
3
MOSEL VITELIC
V53C16258H
V53C16258H Rev. 3.8 November 1999
Absolute Maximum Ratings*
Ambient Temperature
Under Bias..................................... –10
°
C to +80
°
C
Storage Temperature (plastic)..... –55
°
C to +125
°
C
Voltage Relative to V
SS
.................–1.0 V to +7.0 V
Data Output Current .....................................50 mA
Power Dissipation..........................................1.0 W
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V
* Note:
Capacitance is sampled and not 100% tested
Symbol Parameter Typ. Max. Unit
C
IN1
Address Input 3 4 pF
C
IN2
RAS, CAS, WE, OE 4 5 pF
C
OUT
Data Input/Output 5 7 pF
Block Diagram
A0
A1
A7
A8
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
9
I/O1
ADDRESS BUFFERS
AND PREDECODERS
X0-X
ROW
DECODERS
512 MEMORY
ARRAY
256K x 16
COLUMN DECODERS
DATA I/O BUS
Y
0-Y8
512 x 16
I/O
BUFFER
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
RAS CLOCK
GENERATOR
OE
WE
LCAS
RAS
•••
8
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
UCAS
256K x 16
16258H-04
4
V53C16258H Rev. 3.8 November 1999
MOSEL VITELIC
V53C16258H
DC and Operating Characteristics
(1-2)
T
A
= 0
°
C to 70
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, unless otherwise specified.
Symbol Parameter Access
Time
V53C16258H
Unit Test Conditions NotesMin. Typ. Max.
I
LI
Input Leakage Current
(any input pin) –10 10
µ
A V
SS
≤
V
IN
≤
V
CC
I
LO
Output Leakage Current
(for High-Z State) –10 10
µ
A V
SS
≤
V
OUT
≤
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating 25 260 mA t
RC
= t
RC
(min.) 1, 2
30 200
35 190
40 180
45 100
50 90
I
CC2
V
CC
Supply Current,
TTL Standby 2 mA RAS, CAS at V
IH
other inputs
≥
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh 25 260 mA t
RC
= t
RC
(min.) 2
30 200
35 190
40 180
45 100
50 90
I
CC4
V
CC
Supply Current,
EDO Page Mode Operation 25 200 mA Minimum Cycle 1, 2
30 140
35 130
40 120
45 90
50 80
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
other inputs
≥
V
SS
2 mA RAS = V
IH
, CAS = V
IL
1
I
CC6
V
CC
Supply Current,
CMOS Standby 1 mA RAS
≥
V
CC
– 0.2 V,
CAS
≥
V
CC
– 0.2 V,
All other inputs
≥
V
SS
I
CC7
Self Refresh Current 400
µ
A CBR Cycle with t
RAS
≥
t
RASS
(Min.) and CAS = V
IL
;
WE = V
CC
–0.2V; A
0
–A
8
and
D
IN
= V
CC
–0.2V
V
CC
Supply Voltage 4.5 5.0 5.5 V
V
IL
Input Low Voltage –1 0.8 V 3
V
IH
Input High Voltage 2.4 V
CC
+ 1 V 3
V
OL
Output Low Voltage 0.4 V I
OL
= 2 mA
V
OH
Output High Voltage 2.4 V I
OH = –2 mA
5
MOSEL VITELIC
V53C16258H
V53C16258H Rev. 3.8 November 1999
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
# Symbol Parameter
25
(100 MHz) 30 35 40 45 50
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1 tRAS RAS Pulse Width 25 75K 30 75K 35 75K 40 75K 45 75K 50 75K ns
2 tRC Read or Write Cycle Time 45 60 70 75 80 90 ns
3 tRP RAS Precharge Time 15 20 25 25 25 30 ns
4 tCSH CAS Hold Time 25 30 35 40 45 50 ns
5 tCAS CAS Pulse Width 4 5 6 7 8 9 ns
6 tRCD RAS to CAS Delay 10 17 12 20 13 24 15 28 18 32 19 36 ns 4
7 tRCS Read Command Setup Time 0 0 0 0 0 0 ns
8 tASR Row Address Setup Time 0 0 0 0 0 0 ns
9 tRAH Row Address Hold Time 4 5 6 7 8 9 ns
10 tASC Column Address Setup Time 0 0 0 0 0 0 ns
11 tCAH Column Address Hold Time 4 5 5 5 6 7 ns
12 tRSH (R) RAS Hold Time (Read Cycle) 7 9 10 10 10 10 ns
13 tCRP CAS to RAS Precharge Time 5 5 5 5 5 5 ns
14 tRCH Read Command Hold Time
Referenced to CAS 0 0 0 0 0 0 ns 5
15 tRRH Read Command Hold Time
Referenced to RAS 0 0 0 0 0 0 ns 5
16 tROH RAS Hold Time Referenced
to OE 4 6 7 8 9 10 ns
17 tOAC Access Time from OE 8 10 11 12 13 14 ns 12
18 tCAC Access Time from CAS 8 10 11 12 13 14 ns 6, 7, 14
19 tRAC Access Time from RAS 25 30 35 40 45 50 ns 6, 8, 9
20 tCAA Access Time from Column
Address 13 16 18 20 22 24 ns 6, 7, 10
21 tLZ OE or CAS to Low-Z Output 0 0 0 0 0 0 ns 16
22 tHZ OE or CAS to High-Z Output 0 5 0 5 0 6 0 6 0 7 0 8 ns 16
23 tAR Column Address Hold Time
from RAS 19 23 25 30 35 40 ns
24 tRAD RAS to Column Address
Delay Time 8 13 9 14 10 17 12 20 13 23 14 26 ns 11
25 tRSH (W) RAS or CAS Hold Time in
Write Cycle 7 9 10 10 10 10 ns
26 tCWL Write Command to CAS
Lead Time 5 7 8 10 13 14 ns
27 tWCS Write Command Setup Time 0 0 0 0 0 0 ns 12, 13
28 tWCH Write Command Hold Time 4 5 5 5 6 7 ns
6
V53C16258H Rev. 3.8 November 1999
MOSEL VITELIC
V53C16258H
29 tWP Write Pulse Width 4 5 5 5 6 7 ns
30 tWCR Write Command Hold Time from
RAS 19 23 25 30 35 40 ns
31 tRWL Write Command to RAS Lead
Time 7 9 10 10 13 14 ns
32 tDS Data in Setup Time 0 0 0 0 0 0 ns 14
33 tDH Data in Hold Time 4 5 5 5 6 7 ns 14
34 tWOH Write to OE Hold Time 5 5 5 6 7 8 ns 14
35 tOED OE to Data Delay Time 5 5 5 6 7 8 ns 14
36 tRWC Read-Modify-Write Cycle Time 67 79 90 95 115 130 ns
37 tRRW Read-Modify-Write Cycle RAS
Pulse Width 46 53 59 64 80 87 ns
38 tCWD CAS to WE Delay 19 21 23 25 32 34 ns 12
39 tRWD RAS to WE Delay in Read-
Modify-Write Cycle 36 41 46 51 62 68 ns 12
40 tCRW CAS Pulse Width (RMW) 27 31 34 38 50 52 ns
41 tAWD Col. Address to WE Delay 24 27 29 31 41 42 ns 12
42 tPC EDO Fast Page Mode Read or
Write Cycle Time 10 12 14 15 17 19 ns
43 tCP CAS Precharge Time 3 3 4 5 6 7 ns
44 tCAR Column Address to RAS Setup
Time 13 16 18 20 22 24 ns
45 tCAP Access Time from Column
Precharge 15 18 20 22 25 27 ns 7
46 tDHR Data in Hold Time Referenced
to RAS 19 23 25 30 35 40 ns
47 tCSR CAS Setup Time CAS-before-
RAS Refresh 5 7 8 10 10 10 ns
48 tRPC RAS to CAS Precharge Time 0 0 0 0 0 0 ns
49 tCHR CAS Hold Time CAS-before-
RAS Refresh 6 7 8 8 10 10 ns
50 tPCM EDO Page Mode
Read-Modify-Write Cycle Time 35 40 43 47 65 70 ns
51 tCOH Output Hold After CAS Low 4 5 5 5 5 5 ns
52 tOES OE Low to CAS High Setup
Time 3 3 3 3 5 5 ns
53 tOEH OE Hold Time from WE during
Read-Modify Write Cycle 5 5 5 5 10 10 ns
# Symbol Parameter
25
(100 MHz) 30 35 40 45 50
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
AC Characteristics
(Cont’d)
7
MOSEL VITELIC
V53C16258H
V53C16258H Rev. 3.8 November 1999
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and t CAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL input and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD
exceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 500 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
18. One CBR refresh or complete set of row refreah cycles must be completed upon exiting Self Refreah Mode.
54 tOEP OE High Pulse Width 4 5 8 10 10 10 ns
55 tTTransition Time (Rise and Fall) 1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 ns 15
56 tREF Refresh Interval (512 Cycles) 8 8 8 8 8 8 ms 17
Optional Self Refresh
57 tRASS RAS Pulse Width During Self
Refresh 100 100 100 100 100 100 µs 18
58 tRPS RAS Precharge Time During
Self Refresh 100 100 100 100 100 100 ns 18
59 tCHS CAS Hold Time Width During
Self Refresh 100 100 100 100 100 100 ns 18
60 tCHD CAS Low Time During Self
Refresh 100 100 100 100 100 100 µs 18
# Symbol Parameter
25
(100 MHz) 30 35 40 45 50
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
AC Characteristics
(Cont’d)
8
V53C16258H Rev. 3.8 November 1999
MOSEL VITELIC
V53C16258H
Truth Table
Notes:
1. Byte Write cycles LCAS or UCAS active.
2. Byte Read cycles LCAS or UCAS active.
3. Only one of the two CAS must be active (LCAS or UCAS).
Function RAS LCAS UCAS WE OE ADDRESS I/O Notes
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL Data Out
Read: Lower Byte L L H H L ROW/COL Lower Byte, Data-Out
Upper Byte, High-Z
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Upper Byte, Data-Out
Write: Word (Early-Write) L L L L X ROW/COL Data-In
Write: Lower Byte (Early) L L H L X ROW/COL Lower Byte, Data-In
Upper Byte, High-Z
Read: Upper Byte (Early) L H L L X ROW/COL Lower Byte, High-Z
Upper Byte, Data-In
Read-Write L L L H→L L→H ROW/COL Data-Out, Data-In 1, 2
EDO Page-Mode Read L H→L H→L H L COL Data-Out 2
EDO Page-Mode Write L H→L H→L L X COL Data-In 2
EDO Page-Mode Read-Write L H→L H→L H→L L→H COL Data-Out, Data-In 1, 2
Hidden Refresh Read L→H→L L L H L ROW/COL Data-Out 2
RAS-Only Refresh L H H X X ROW High-Z
CBR Refresh H→L L L X X X High-Z 3
Self Refresh H→L L H X X X High-Z
9
MOSEL VITELIC
V53C16258H
V53C16258H Rev. 3.8 November 1999
Waveforms of Read Cycle
Waveforms of Early Write Cycle
IH
V
IL
V
RAS
IH
V
IL
V
IH
V
IL
V
tRC (2)
tRAS (1)
tAR (23)
tRP (3)
tCRP (13)
tCSH (4) tRSH (R)(12)
tCAS (5)
tRCD (6)
tCRP (13)
tCAH (11)
tASC (10)
tRAD (24)
tRAH (9)
tASR (8)
tRCS (7)
tRCH (14)
tRRH (15)
tCAR (44)
tCAA (20)
tCAC (18)
ttHZ (22)
tLZ (21)
IH
V
IL
V
WE
OH
V
OL
V
I/O
16258H-05
VALID DATA-OUT
ADDRESS
tOES (52)
RAC (19)
COLUMN ADDRESSROW ADDRESS
tOAC (17)
tHZ (22)
IH
V
IL
V
OE
tROH (16)
UCAS, LCAS
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
tRC (2)
tRAS (1)
tAR (23)
tRP (3)
tCRP (13)
tCSH (4) tRSH (W)(25)
tCAS (5)
tRCD (6)
tCRP (13)
tCAH (11)
t
tRAD (24)
tRAH (9)
tASR (8)
t
tWCR (30) tRWL (31)
tDH (33)
tDHR (46)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V16258H-06
t
tCWL (26) WCH (28)
t
tDS (32)
COLUMN ADDRESS
VALID DATA-IN HIGH-Z
RAS
UCAS, LCAS
WE
OE
I/O
ADDRESS
tCAR (44)
ASC (10)
WCS (27)
WP (29)
ROW ADDRESS
Don’t Care Undefined
10
V53C16258H Rev. 3.8 November 1999
MOSEL VITELIC
V53C16258H
Waveforms of OE-Controlled Write Cycle
Waveforms of Read-Modify-Write Cycle
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
tRC (2)
tRAS (1)
tAR (23)
tRP (3)
tCRP (13)
tRCD (6)
tCRP (13)
tCAH (11)
tASC (10)
tRAH (9)
tASR (8)
ROW ADDRESS COLUMN ADDRESS
tWOH (34)
tDH (33)
tOED (35)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
16258H-07
VALID DATA-IN
tDS (32)
tRAD (24)
RAS
WE
OE
I/O
tCSH (4)
ADDRESS
tCAR (44)
t
tCAS (5)
RSH (W)(12)
tWP (29)
RWL (31)
tCWL (26)
t
UCAS, LCAS
COLUMN
ADDRESS
ROW
ADDRESS
V
V
IH
V
IL
V
IH
V
IL
V
tRP (3)
tCRP (13)
tRCD (6)
tCRP (13)
tCAH (11)
tASC (10)
tRAH (9)
tASR (8)
WP (29)
RWL (31)
tOED (35)
t
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
16258H-08
VALID
DATA-OUT
tRAC (19)
tCWL (26)
t
tRAD (24)
tACS t
tOAC (17)
ttDH (33)
tOEH (53)
tDS (32)
HZ (22)CAC (18)
tLZ (21)
VALID
DATA-IN
IH
V
IL
V
OH
OL
RAS
WE
OE
I/O
ADDRESS
tRWC (36)
tRRW (37)
tAR (23)
tCSH (4) tRSH (W)(25)
tCRW (40)
tRWD (39) CWD (38)
tAWD (41)
t
tCAA (20)
UCAS, LCAS
Don’t Care Undefined
11
MOSEL VITELIC
V53C16258H
V53C16258H Rev. 3.8 November 1999
Waveforms of EDO Page Mode Read Cycle
Waveforms of EDO Page Mode Write Cycle
VALID
DATA OUT
VALID
DATA OUT
COLUMN
ADDRESS
CAC (18)
tHZ (22)
tLZ
HZ (22)
HZ (22)
ROW
ADDRESS COLUMN
ADDRESS
IH
V
IL
V
IH
V
IL
V
RP (3)
t
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
tRAH (9)
tASR (8)
tRCS (7)
tRCH (14)
tCSH (4)
IH
V
IL
V
CP (43)
tASC (10)
RCD (6)
t
tRAS (1)
tRSH (R)(12)
tCAS (5)
tCAH (11)
t
tAR (23)
tCAS (5) tCAS (5)
PC (42)
t
CRP (13)
t t
COLUMN
ADDRESS
t
tCAR (44)
tCAH (11) tRCS (7)
tRCS (7) tRCH (14)
tOAC (17)
t
tOAC (17)
tCAA (20) tRRH (15)
LZ (21)
tRAC (19)
t
tCAC (18)
tOEP (54)
VALID
DATA OUT
tCRP (13)
tt
RAS
UCAS, LCAS
WE
OE
I/O
ADDRESS
tASC (10)
tCOH (5)
CAC (18)
t
HZ (22)
t
CAA (20)
tOES (52)
CAP (45)
t
CAH (11)
16258H-09
ROW
ADD
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
t
tASR (8)
IH
V
IL
V
CP (43)
tASC (10)
RCD (6)
tRSH (W)(25)
COLUMN
ADDRESS
tCAH (11)
tCAS (5) tCAS (5)
tCAR (44)
tRAD (24) tCWL (26)
VALID
DATA IN
tCRP (13)
tWCS (27)
WP (29)
tCAH (11)
tASC (10) tCAH (11)
tDH (33)
tDS (32)
IH
V
IL
V
COLUMN
ADDRESS
RAH (9)
COLUMN
ADDRESS
tCRP (13)
t
tWCH (28)
tCWL (26)
tWCS (27)
WP (29)
tWCH (28)
t
tCWL (26)
tWCS (27)
WP (29)
tWCH (28)
t
VALID
DATA IN
tDH (33)
tDS (32)
VALID
DATA IN
tDH (33)
tDS (32)
tRP (3)
tAR (23)
RAS
WE
OE
I/O
ADDRESS
OPENOPEN
tRWL (31)
t
tCSH (4)
tRAS (1)
t
PC (42)
tt
CAS (5)
UCAS, LCAS
16258H-10
Don’t Care Undefined
12
V53C16258H Rev. 3.8 November 1999
MOSEL VITELIC
V53C16258H
Waveforms of EDO Page Mode Read-Write Cycle
Waveforms of RAS-Only Refresh Cycle
ROW
ADD
IH
V
IL
V
IH
V
IL
V
RP (3)
t
IH
V
IL
V
I/OH
V
I/OL
V
t
tASR (8)
COLUMN
ADDRESS
IH
V
IL
V
CP (43)
tASC (10)
RCD (6)
t
tRAS (1)
tRSH (W)(25)
COLUMN
ADDRESS
tCAH (11)
tCAS (5) tCAS (5)
t
t
tCRP (13)
tCAH (11)
tASC (10) t
tCWD (38)
tLZ (21)
IH
V
IL
V
COLUMN
ADDRESS
tASC (10)
RAH (9)
tWP (29)
tCWL (26)
t
tCWL (26)
tRWL (31)
tAWD (41)
tCAA (20)
ttOAC (17)
tAWD (41)
tOAC (17)
IN
tCAC (18) t
OED (35)
t
DS (32)
tDH (33)
t
LZ
IN
OUT
HZ (22)
t
OED (35)
DS (32)
tDH (33)
t
t
CAP (43)
t
tCAC (18)
tCAA (20)
LZ
IN
HZ (22)
t
OED (35)
DS (32)
tDH (33)
t
t
tCAC (18)
tCAA (20)
CAP (43)
t
tWP (29)
tt
WP (29)
t
CWL (26)
tCAR (44)
tRAD (24)
RAS
WE
OE
I/O
ADDRESS
tAWD (41)
OUT
RAC (19)
t
OAC (17)
tRWD (39)
CAH (11)
PCM (50)
t
tCSH (4)
tCAS (5)
tCWD (38)
HZ (22)
CWD (38)
OUT
UCAS, LCAS
OEH (53)
t
16258H-11
IH
V
IL
V
RAS
IH
V
IL
V
RP (3)
t
IH
V
IL
V
tRAS (1)
tRC (2)
tCRP (13)
tASR (8) tRAH (9)
WE, OE = Don’t careNOTE:
ADDRESS ROW ADD
UCAS, LCAS
16258H-12
Don’t Care Undefined
13
MOSEL VITELIC
V53C16258H
V53C16258H Rev. 3.8 November 1999
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
Waveforms of CAS-before-RAS Refresh Cycle
IH
V
IL
V
IH
V
IL
V
RP (3)
t
IH
V
IL
V
tCSR (47)
tRSH (W)(25)
tRAS (1)
tCHR (49)
tRCS (7)
tWCS (27)
tLZ (21)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
VtDH (33)
tCP (43) tCAS (5)
tRCH (14)
tRRH (15)
tHZ (22)
tRWL (31)
tCWL (26)
tDS (32)
IH
V
IL
V
IH
V
IL
V
READ CYCLE
WRITE CYCLE tWCH (28)
I/O
ADDRESS
WE
WE
I/O DOUT
DIN
RAS
OE
UCAS, LCAS
16258H-13
I/O
IH
V
IL
V
RAS
OH
V
OL
V
IH
V
IL
V
UCAS, LCAS
tRAS (1)
tRC (2)
tCP (43)
tHZ (22)
tCSR (47)
RP (3)
t
tRPC (48) tCHR (49)
RP (3)
t
NOTE: WE, OE, A0–A8 = Don’t care
16258H-14
Don’t Care Undefined
14
V53C16258H Rev. 3.8 November 1999
MOSEL VITELIC
V53C16258H
Waveforms of Hidden Refresh Cycle (Read)
Waveforms of Hidden Refresh Cycle (Write)
IH
V
IL
V
OH
V
OL
V
RP (3)
t
IH
V
IL
V
tASR (8)
tCRP (13)
tRCD (6) tRSH (R)(12)
tRCS (7)
16258H-15
tCHR (49)
tRAD (24)
tASC (10)
t tCAH (11)
ROW
ADD COLUMN
ADDRESS
tRRH (15)
tOAC (17)
tLZ (21)
tHZ (22)
tHZ (22)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
RAS
UCAS, LCAS
WE
OE
I/O
ADDRESS
VALID DATA
RAH (9)
tCAA (20)
tCAC (18)
tRAC (19)
tRAS (1)RP (3)
t
tRAS (1)
tAR (23)
tCRP (13)
tRC (2) tRC (2)
IH
V
IL
V
IH
V
IL
V
RP (3)
t
IH
V
IL
V
t
RAS (1)
t
RC (2)
t
ASR (8)
t
CRP (13)
RP (3)
t
t
RCD (6)
t
RSH (12)
t
WCS (27)
16258H-16
t
RAS (1)
t
AR (23)
t
CHR (49)
t
CRP (13)
t
RAD (24)
t
ASC (10)
t
RAH (9)
t
CAH (11)
ROW
ADD COLUMN
ADDRESS
t
WCH (28)
t
DS (32)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
VALID DATA-IN
t
DHR (46)
t
RC (2)
RAS
UCAS, LCAS
WE
OE
I/O
ADDRESS
t
DH (33)
Don’t Care Undefined
MOSEL VITELIC
V53C16258H
15
V53C16258H Rev. 3.8 November 1999
Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
Waveforms of Self Refresh Cycle
UCAS, LCAS
WE
OE
I/O
ADDRESS
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
RAS
VALID
DATA OUT
VALID
DATA OUT
ROW
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
VALID
DATA IN
tRAS
tCSH
tCRP tRCD tCAS tCP tCP tCP
tCAS tCAS
tPC
tAR
tRAD
tASR tRAH
tRCS tRCH tWCS
tCAA
tCAA
tRAC
tCAC
tCAP
tCAC
16258H-17
tCOH
tDS tDH
tOE
tWCH
tCAH
tASC tCAH
tASC tCAH
tASC
tCAR
tPC tRSH
tRP
IH
V
IL
V
t
RP (3)
16258L 05
IH
V
IL
V
IH
V
IL
V
t
RASS (57)
t
RPS (58)
t
RPC (48)
t
CP (43)
t
CSR (47)
t
CHD (60)
t
RPC (48)
t
OPEN
CHS (59)
UCAS, LCAS
IH
V
IL
V
ADDRESS
IH
V
IL
V
OH
V
OL
V
I/O
RAS
WE
OE
Don’t Care Undefined
16
MOSEL VITELIC
V53C16258H
V53C16258H Rev. 3.8 November 1999
Functional Description
The V53C16258H is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C16258H reads and writes
data by multiplexing an 18-bit address into a 9-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum tRAS time has
expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS
operation. The column address must be held for a
minimum specified by tAR. Data Out becomes valid
only when tOAC, tRAC, tCAA and tCAC are all
satisifed. As a result, the access time is dependent
on the timing relationships between these
parameters. For example, the access time is limited
by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column
address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
Extended Data Output Page Mode
EDO Page operation permits all 512 columns
within a selected row of the device to be randomly
accessed at a high data rate. Maintaining RAS low
while performing successive CAS cycles retains the
row address internally and eliminates the need to
reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS is high. Thus, access begins from the
occurrence of a valid column address rather than
from the falling edge of CAS, eliminating tASC and tT
from the critical timing path. CAS latches the
address into the column address buffer. During
EDO operation, Read, Write, Read-Modify-Write or
Read-Write-Read cycles are possible at random
addresses within a row. Following the initial entry
cycle into Hyper Page Mode, access is tCAA or tCAP
controlled. If the column address is valid prior to the
rising edge of CAS, the access time is referenced to
the CAS rising edge and is specified by tCAP. If the
column address is valid after the rising CAS edge,
access is timed from the occurrence of a valid
address and is specified by tCAA. In both cases, the
falling edge of CAS latches the address and
enables the output.
EDO provides a sustained data rate of 83 MHz for
applications that require high bandwidth such as bit-
mapped graphics or high-speed signal processing.
The following equation can be used to calculate the
maximum data rate:
Self Refresh
Self Refresh mode provides internal refresh con-
trol signals to the DRAM during extended periods of
inactivity. Device operation in this mode provides
additional power savings and design ease by elimi-
nation of external refresh control signals. Self Re-
fresh mode is initiated with a CAS before RAS
(CBR) Refresh cycle, holding both RAS low (tRASS)
and CAS low (tCHD) for a specified period. Both of
these parameters are specified with minimum val-
ues to guarantee entry into Self Refresh operation.
Once the device has been placed in to Self Refresh
mode the CAS clock is no longer required to main-
tain Self Refresh operation.
Data Rate 512
tRC 511 tPC
×+
----------------------------------------=
MOSEL VITELIC
V53C16258H
17
V53C16258H Rev. 3.8 November 1999
The Self Refresh mode is terminated by returning
the RAS clock to a high level for a specified (tRPS)
minimum time. After termination of the Self Refresh
cycle normal accesses to the device may be initiat-
ed immediately, providing that subsequent refresh
cycles utilize the CAS before RAS (CBR) mode of
operation.
Data Output Operation
The V53C16258H Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition
enables the transfer of data to and from the selected
row address in the Memory Array. A RAS high
transition disables data transfer and latches the
output data if the output is enabled. After a memory
cycle is initiated with a RAS low transition, a CAS
low transition or CAS low level enables the internal
I/O path. A CAS high transition or a CAS high level
disables the I/O path and the output driver if it is
enabled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output
drivers. The output drivers, when otherwise
enabled, can be disabled by holding OE high. The
OE signal has no effect on any data stored in the
output latches. A WE low level can also disable the
output drivers when CAS is low. During a Write
cycle, if WE goes low at a time in relationship to
CAS that would normally cause the outputs to be
active, it is necessary to use OE to disable the
output drivers prior to the WE low transition to allow
Data In Setup Time (tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C16258H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and ICC will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
Table 1. V53C16258H Data Output
Operation for Various Cycle Types
Cycle Type I/O State
Read Cycles Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write) High-Z
WE-Controlled Write
Cycle (Late Write) OE Controlled. High
OE = High-Z I/Os
Read-Modify-Write
Cycles Data from Addressed
Memory Cell
EDO Read Cycle Data from Addressed
Memory Cell
EDO Write Cycle
(Early Write) High-Z
EDO Read-Modify-
Write Cycle Data from Addressed
Memory Cell
RAS-only Refresh High-Z
CAS-before-RAS
Refresh Cycle Data remains as in
previous cycle
CAS-only Cycles High-Z
18
V53C16258H Rev. 3.8 November 1999
MOSEL VITELIC
V53C16258H
Package Outlines
40-Pin Plastic SOJ
40/44L-Pin TSOP-II
1.025 TYP. (1.035 MAX.)
[26.04 TYP. (26.29 MAX.)]
0.050 ± 0.006
[1.27 ± 0.152] 0.04 [0.1]
0.026 MIN
[0.660 MIN]
0.144 MAX
[3.66 MAX]
0.400 ±0.005
[10.16 ± 0.127]
0.440 ±0.005
[11.18 ± 0.127]
40
1
21
20
0.368 ± 0.010
[9.35 ± 0.254]
0.010
Unit in inches [mm]
0.025
0.018 +0.004
–0.002
+0.004
–0.002 0.635 +0.102
–0.051
+ 0.004
– 0.002
0.254 +0.102
–0.051
0.457 +0.102
–0.051
0.721 – 0.729
[18.31 – 18.52]
0.0315 BSC
[.8001 BSC]
40 21
1 20
0.039 – 0.047
[0.991 – 1.193]
0.396 – 0.404
[10.06 – 10.26]
0.462 – 0.470
[11.73 – 11.94]
0.012 – 0.016
[0.305 – 0.406] 0.002 – 0.008
[0.051 – 0.203]
0.0047 – 0.0083
[0.119 – .211]
0°–5°
0.017 – 0.023
[0.432 – 0.584]
BASE PLANE
SEATING PLANE
Unit in inches [mm]
19
MOSEL VITELIC
V53C16258H
V53C16258H Rev. 3.8 November 1999
Notes
MOSEL VITELIC
WORLDWIDE OFFICES V53C16258H
© Copyright 1999, MOSEL VITELIC Inc. 11/99
Printed in U.S.A.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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