Philips Semiconductors Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1
1995 Sep 06 853-1448 15704
FEATURES
•8-bit positive edge triggered register
•3-State output buffers
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•Power-up 3-State
•Power-up reset
•Live insertion/extraction permitted
DESCRIPTION
The 74ABT374A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS
Tamb = 25°C; GND = 0V TYPICAL UNIT
tPLH
tPHL Propagation delay
CP to Qn CL = 50pF; VCC = 5V 3.4
3.8 ns
CIN Input capacitance VI = 0V or VCC 4pF
COUT Output capacitance Outputs disabled; VO = 0V or VCC 7pF
ICCZ Total supply current Outputs disabled; VCC =5.5V 110 µA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic DIP –40°C to +85°C74ABT374A N 74ABT374A N SOT146-1
20-Pin plastic SO –40°C to +85°C74ABT374A D 74ABT374A D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C74ABT374A DB 74ABT374A DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C74ABT374A PW 74ABT374APW DH SOT360-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3 Q4
GND
D4
D5
Q5
Q6
D6
D7
Q7
VCC
CP
SA00110
PIN DESCRIPTION
PIN
NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
3, 4, 7, 8,
13, 14, 17,
18 D0-D7 Data inputs
2, 5, 6, 9,
12, 15, 16,
19 Q0-Q7 Data outputs
11 CP Clock pulse input (active rising edge)
10 GND Ground (0V)
20 VCC Positive supply voltage
Philips Semiconductors Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06 2
LOGIC SYMBOL
3 4 7 8 13 14 1817
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
1
11
SA00111
CP
OE
LOGIC SYMBOL (IEEE/IEC)
11
32
45
76
89
C1
13 12
14 15
17 16
18 19
1EN
1D
SA00112
FUNCTION TABLE
INPUTS INTERNAL OUTPUTS
OPERATING MODE
OE CP Dn
INTERNAL
REGISTER Q0 – Q7
OPERATING
MODE
L↑l L L
Latch and read register
L↑h H H
L
a
t
c
h
an
d
rea
d
reg
i
s
t
er
L↑X NC NC Hold
H↑X NC Z
Disable outputs
H↑Dn Dn Z
Di
sa
bl
e ou
t
pu
t
s
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑= Low-to-High clock transition
↑= not a Low-to-High clock transition
LOGIC DIAGRAM
CP Q
D
D0
Q0
CP Q
D
D1
CP Q
D
D2
CP Q
D
D3
CP Q
D
D4
CP Q
D
D5
CP Q
D
D6
CP Q
D
D7
Q1 Q2 Q3 Q4 Q5 Q6 Q7
CP
OE
SA00113
3 4 7 8 13 14 17 18
11
1
2 5 6 9 12 15 16 19
Philips Semiconductors Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06 3
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +7.0 V
IIK DC input diode current VI < 0 –18 mA
VIDC input voltage3–1.2 to +7.0 V
IOK DC output diode current VO < 0 –50 mA
VOUT DC output voltage3output in Off or High state –0.5 to +5.5 V
IOUT DC output current output in Low state 128 mA
Tstg Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN MAX
UNIT
VCC DC supply voltage 4.5 5.5 V
VIInput voltage 0 VCC V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –32 mA
IOL Low-level output current 64 mA
∆t/∆vInput transition rise or fall rate 0 10 ns/V
Tamb Operating free-air temperature range –40 +85 °C
Philips Semiconductors Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06 4
DC ELECTRICAL CHARACTERISTICS
SYMBOL
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°CTamb = –40°C
to +85°CUNIT
MIN TYP MAX MIN MAX
VIK Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V
VCC = 4.5V ; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V
VOH High-level output voltage VCC = 5.0V ; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V
VCC = 4.5V ; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V
VOL Low-level output voltage VCC = 4.5V ; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V
VRST Power-up output low voltage3VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V
IIInput leakage current VCC = 5.5V ; V I = GND or 5.5V ±0.01 ±1.0 ±1.0 µA
IOFF Power-of f leakage current VCC = 0.0V ; V O or VI ≤ 4.5V ±5.0 ±100 ±100 µA
IPU/IPD Power-up/down 3-State
output current VCC = 0.0V ; IO = 1mA; VI = GND or VCC;
VOE = Don’t Care ±5.0 ±50 ±50 µA
IOZH 3-State output High current V CC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA
IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA
ICEX Output High leakage current VCC = 5.5V ; VO = 0.5V; V I = GND or VCC 5.0 50 50 µA
IOOutput current1VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA
ICCH VCC = 5.5V; Outputs High, VI = GND or VCC 110 250 250 µA
ICCL Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or VCC 24 30 30 mA
ICCZ VCC = 5.5V ; Outputs 3–State;
VI = GND or VCC 110 250 250 µA
∆ICC Additional supply current per
input pin2VCC = 5.5V ; one input at 3.4V,
other inputs at VCC or GND 0.5 1.5 1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM Tamb = +25oC
VCC = +5.0V
Tamb = -40 to
+85oC
VCC = +5.0V ±0.5V UNIT
Min Typ Max Min Max
fMAX Maximum clock frequency 1 200 300 200 ns
tPLH
tPHL Propagation delay
CP to Qn 11.7
2.0 3.4
3.8 4.5
4.9 1.7
2.0 5.1
5.2 ns
tPZH
tPZL Output enable time
to High and Low level 3
41.2
2.2 3.5
4.3 4.5
5.4 1.2
2.2 5.4
6.2 ns
tPHZ
tPLZ Output disable time
from High and Low level 3
41.8
1.5 3.6
3.0 4.7
4.1 1.8
1.5 5.2
4.3 ns
Philips Semiconductors Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06 5
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM Tamb = +25oC
VCC = +5.0V Tamb = -40 to +85oC
VCC = +5.0V ±0.5V UNIT
Min Typ Min
ts(H)
ts(L) Setup time, High or Low
Dn to CP 21.5
1.2 0.6
0.3 1.5
1.2 ns
th(H)
th(L) Hold time, High or Low
Dn to CP 21.0
1.0 –0.3
–0.5 1.0
1.0 ns
tw(H)
tw(L) CP pulse width
High or Low 12.0
2.8 0.8
1.0 2.0
2.8 ns
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
VM VM VM
VM VM
1/fMAX
tw(H) tw(L)
tPHL tPLH
CP
Qn
SA00056
W aveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
VM
Dn
VMVM
VMVMVM
CP
ts(H) th(H) ts(L) th(L)
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00107
W aveform 2. Data Setup and Hold Times
OE VM
tPZH tPHZ
0V
Qn VM
VM
SA00066
VOH–0.3V
W aveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE
tPZL tPLZ
0V
Qn
VM
VM
VM
SA00067
VOL+0.3V
W aveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Philips Semiconductors Product specification
74ABT374A
Octal D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06 6
TEST CIRCUIT AND WAVEFORM
PULSE
GENERATOR
RT
VIN VOUT
CLRL
VCC
RL
7.0V
Test Circuit for 3-State Outputs
VMVM
tWAMP (V)
NEGATIVE
PULSE 10% 10%
90% 90%
0V
VMVM
tW
AMP (V)
POSITIVE
PULSE
90% 90%
10% 10% 0V
tTHL (tF)
tTLH (tR)t
THL (tF)
tTLH (tR)
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY Amplitude Rep. Rate tWtRtF
74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns
SWITCH POSITION
TEST SWITCH
tPLZ closed
tPZL closed
All other open
SA00012
D.U.T.
