Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 2 1Publication Order Number:
NTHS5443T1/D
NTHS5443T1
Power MOSFET
P-Channel ChipFET
3.6 Amps, 20 Volts
Features
•Low RDS(on) for Higher Efficiency
•Logic Level Gate Drive
•Miniature ChipFET Surface Mount Package Saves Board Space
Applications
•Power Management in Portable and Battery–Powered Products; i.e.,
Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating Symbol 5 secs Steady
State Unit
Drain–Source Voltage VDS –20 V
Gate–Source Voltage VGS 12 V
Continuous Drain Current
(TJ = 150°C) (Note 1.)
TA = 25°C
TA = 85°C
ID
4.9
3.5
3.6
2.6
A
Pulsed Drain Current IDM 15 A
Continuous Source Current
(Note 1.) IAS –2.1 –1.1 A
Maximum Power Dissipation
(Note 1.)
TA = 25°C
TA = 85°C
PD
2.5
1.3 1.3
0.7
W
Operating Junction and Storage
Temperature Range TJ, Tstg –55 to +150 °C
1. Surface Mounted on 1″ x 1″ FR4 Board.
Device Package Shipping
ORDERING INFORMATION
NTHS5443T1 ChipFET 3000/Tape & Reel
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G
D
S
D
D
D
D
D
1
2
3
45
6
7
8
PIN CONNECTIONS
G
S
D
P–Channel MOSFET
ChipFET
CASE 1206A
STYLE 1
MARKING
DIAGRAM
A4
A4 = Specific Device Code
3.6 AMPS
20 VOLTS
RDS(on) = 65 m
1
2
3
4
8
7
6
5
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THERMAL CHARACTERISTICS
Characteristic Symbol Typ Max Unit
Maximum Junction–to–Ambient (Note 2.)
t 5 sec
Steady State
RthJA 40
80 50
95
°C/W
Maximum Junction–to–Foot (Drain)
Steady State RthJF 15 20 °C/W
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Test Condition Min Typ Max Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = –250 µA –0.6 – – V
Gate–Body Leakage IGSS VDS = 0 V, VGS = 12 V – – 100 nA
Zero Gate Voltage Drain Current IDSS VDS = –16 V, VGS = 0 V – – –1.0 µA
VDS = –16 V, VGS = 0 V,
TJ = 85°C– – –5.0
On–State Drain Current (Note 3.) ID(on) VDS –5.0 V, VGS = –4.5 V –15 – – A
Drain–Source On–State Resistance (Note 3.) rDS(on) VGS = –4.5 V, ID = –3.6 A
VGS = –3.6 V, ID = –3.3 A –
–0.056
0.065 0.065
0.074 Ω
VGS = –2.5 V, ID = –2.7 A – 0.095 0.110
Forward Transconductance (Note 3.) gfs VDS = –10 V, ID = –3.6 A – 10 – S
Diode Forward Voltage (Note 3.) VSD IS = –1.1 A, VGS = 0 V – –0.8 –1.2 V
Dynamic (Note 4.)
Total Gate Charge Qg
V10 V V 45V
– 9.0 14 nC
Gate–Source Charge Qgs VDS = –10 V, VGS = –4.5 V,
I
D
= –3.6 A – 2.2 –
Gate–Drain Charge Qgd
I
D
=
–
3
.
6
A
– 2.2 –
Turn–On Delay Time td(on) – 15 25 s
Rise Time trVDD = –10 V, RL = 10 Ω
ID–10A V
GEN =–45V
– 30 45
Turn–Of f Delay Time td(off) ID –1.0 A, VGEN = –4.5 V,
RG = 6 Ω– 50 75
Fall Time tf
RG
6
Ω
– 35 50
Source–Drain Reverse Recovery Time trr IF = –1.1 A, di/dt = 100 A/µs – 30 60 ns
2. Surface Mounted on 1″ x 1″ FR4 Board.
3. Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
4. Guaranteed by design, not subject to production testing.
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TYPICAL ELECTRICAL CHARACTERISTICS
–6 V
125°C
–1.6 V
0
10
2.5
8
6
31.51
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
–ID, DRAIN CURRENT (AMPS)
4
2
00.5
Figure 1. On–Region Characteristics
0.5
10
8
21.5 2.5
6
4
2
1
03
Figure 2. Transfer Characteristics
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
0.05
24
0.15
0.1
06
Figure 3. On–Resistance versus
Gate–to–Source Voltage
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
–ID, DRAIN CURRENT (AMPS)
191085
0.06
4
0.04
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
–ID, DRAIN CURRENT (AMPS)
–50 0–25 25
1.4
1.2
1
0.8
0.6 50 125100
Figure 5. On–Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C
VGS = –1.4 V
0.2
13
TJ = –55°C
ID = –3.6 A
TJ = 25°C
0.08
0.02
75 150
TJ = 25°C
ID = –3.6 A
VGS = –4.5 V
RDS(on), DRAIN–TO–SOURCE
RESISTANCE (NORMALIZED)
2
25°C
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
1.6
VGS = –4.5 V
VGS = –6 V
–1.8 V
–2 V
–2.2 V
–2.4 V
–3.4 V
–5 V
–4 V
–2.8 V
–2.6 V
VDS ≥ –10 V
05 7623
04 8
1000
100
10 2016
Figure 6. Drain–to–Source Leakage Current
versus Voltage
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
12
VGS = 0 V
–IDSS , LEAKAGE (nA)
10,000
TJ = 150°C
TJ = 100°C
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TYPICAL ELECTRICAL CHARACTERISTICS
VDS = 0 V VGS = 0 V
VGS
10510 15
1800
900
600
300
020
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
C, CAPACITANCE (pF)
04
6
210
4
1
0
Figure 8. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
Qg, TOTAL GATE CHARGE (nC)
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
TJ = 25°C
Coss
Ciss
Crss
ID = –3.6 A
TJ = 25°C
QT
1500
86
2
3
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
24
20
16
4
0
Q2Q1
101
10
1100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
t, TIME (ns)
VDD = –10 V
ID = –1.0 V
VGS = –4.5 V
1000
50
1200
5
8
12
td(off)
td(on)
tf
tr
–VGS –VDS
VDS
100
0.0001 1
0.01 100.10.01
SQUARE WAVE PULSE DURATION (sec)
0.1
1
0.001
Figure 10. Normalized Thermal Transient Impedance, Junction–to–Ambient
Duty Cycle = 0.5
100 1000
NORMALIZED EFFECTIVE TRANSIENT
THERMAL IMPEDANCE
0.2
Single Pulse
0.1
0.05
0.02
PER UNIT BASE = RθJA = 80°C/W
TJM - TA = PDMZθJA(t)
SURFACE MOUNTED
PDM
t1
t2
DUTY CYCLE, D = t1/t2
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Figure 11. Diode Forward Voltage versus
Current
0.50.4 0.6 0.80.7 0.9
20
15
10
5
0
–IS, SOURCE CURRENT (AMPS)
–VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
VGS = 0 V
TJ = 25°C
80 mm
26 mm 28 mm
18 mm
25 mm
Figure 12. Figure 13.
80 mm
26 mm 28 mm
68 mm
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
connections (pins 1, 2, 3, 6, 7, 8) while remaining within the
confines of the basic footprint. The drain copper area is
0.0054 sq. in. (or 3.51 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
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PACKAGE DIMENSIONS
ChipFET
CASE 1206A–03
ISSUE C
BS
C
D
G
L
A
1234
8765
M
J
K
1234
8765
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.95 3.10 0.116 0.122
B1.55 1.70 0.061 0.067
C1.00 1.10 0.039 0.043
D0.25 0.35 0.010 0.014
G0.65 BSC 0.025 BSC
J0.10 0.20 0.004 0.008
K0.28 0.42 0.011 0.017
L0.55 BSC 0.022 BSC
M°5 NOM
S1.80
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A-01 AND 1206A-02 OBSOLETE. NEW
STANDARD IS 1206A-03.
0.05 (0.002) °5 NOM
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
2.00 0.072 0.080
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Notes
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NTHS5443T1/D
ChipFET is a trademark of Vishay Siliconix
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