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tm
74VHC573 Octal D-Type Latch with 3-STATE Outputs
May 2007
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3
74VHC573
Octal D-Type Latch with 3-STATE Outputs
Features
■
High Speed: t
PD
=
5.0ns (Typ.) at V
CC
=
5V
■
High Noise Immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
■
Power Down Protection is provided on all inputs
■
Low Noise: V
OLP
=
0.6V (Typ.)
■
Low Power Dissipation: I
CC
=
4µA (Max.) @ T
A
=
25°C
■
Pin and function compatible with 74HC573
General Description
The VHC573 is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while main-
taining the CMOS low power dissipation. This 8-bit
D-type latch is controlled by a latch enable input (LE)
and an Output Enable input (OE). When the OE input is
HIGH, the eight outputs are in a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Ordering Information
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram Pin Description
Order Number Package
Number
Package Description
74VHC573M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE 3-STATE Output Enable Input
O
0
–O
7
3-STATE Outputs
74VHC573 Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3 2
Logic Symbol
IEEE/IEC
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Functional Description
The VHC573 contains eight D-type latches with
3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW the latches store the information that
was present on the D inputs, a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode, but, this does
not interfere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Inputs Outputs
OE LE D O
n
LHH H
LHL L
LLX O
0
HXX Z
74VHC573 Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3 3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
V
IN
DC Input Voltage –0.5V to +7.0V
V
OUT
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
IK
Input Diode Current –20mA
I
OK
Output Diode Current ±20mA
I
OUT
DC Output Current ±25mA
I
CC
DC V
CC
/GND Current ±75mA
T
STG
Storage Temperature –65°C to +150°C
T
L
Lead Temperature (Soldering, 10 seconds) 260°C
Symbol Parameter Rating
V
CC
Supply Voltage 2.0V to +5.5V
V
IN
Input Voltage 0V to +5.5V
V
OUT
Output Voltage 0V to V
CC
T
OPR
Operating Temperature –40°C to +85°C
t
r
, t
f
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
74VHC573 Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3 4
DC Electrical Characteristics
Noise Characteristics
Note:
2. Parameter guaranteed by design.
Symbol Parameter V
CC
(V) Conditions
T
A
=
25°C T
A
=
–40°C to +85°C
UnitsMin. Typ. Max. Min. Max.
V
IH
HIGH Level Input
Voltage
2.0 1.50 1.50 V
3.0–5.5 0.7 x V
CC
0.7 x V
CC
V
IL
LOW Level Input
Voltage
2.0 0.50 0.50 V
3.0–5.5 0.3 x V
CC
0.3 x V
CC
V
OH
HIGH Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
I
OH
=
–50µA 1.9 2.0 1.9 V
3.0 2.9 3.0 2.9
4.5 4.4 4.5 4.4
3.0 I
OH
=
–4mA 2.58 2.48
4.5 I
OH
=
–8mA 3.94 3.80
V
OL
LOW Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
I
OL
=
50µA 0.0 0.1 0.1 V
3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
3.0 I
OL
=
4mA 0.36 0.44
4.5 I
OL
=
8mA 0.36 0.44
I
OZ
3-STATE Output
Off-State Current
5.5 V
IN
=
V
IH
or V
IL
,
V
OUT
=
V
CC
or GND
±0.25 ±2.5 µA
I
IN
Input Leakage
Current
0–5.5 V
IN
=
5.5V or GND ±0.1 ±1.0 µA
I
CC
Quiescent Supply
Current
5.5 V
IN
=
V
CC
or GND 4.0 40.0 µA
Symbol Parameter V
CC
(V) Conditions
T
A
=
25°C
UnitsTyp. Limits
V
OLP(2)
Quiet Output Maximum
Dynamic V
OL
5.0 C
L
= 50pF 0.9 1.2 V
VOLV(2) Quiet Output Minimum
Dynamic VOL
5.0 CL = 50pF –0.8 –1.0 V
VIHD(2) Minimum HIGH Level
Dynamic Input Voltage
5.0 CL = 50pF 3.5 V
VILD(2) Maximum LOW Level
Dynamic Input Voltage
5.0 CL = 50pF 1.5 V
74VHC573 Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3 5
AC Electrical Characteristics
Notes:
3. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min|
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (Opr.) = CPD • VCC • fIN + ICC / 8 (per Latch). The total CPD when n pcs. of the Latch operates can be
calculated by the equation: CPD(total) = 21 + 8n.
AC Operating Requirements
Symbol Parameter VCC (V) Conditions
TA = 25°C
TA = –40°C
to +85°C
UnitsMin. Typ. Max. Min. Max.
tPLH, tPHL Propagation Delay
Time (LE to On)
3.3 ± 0.3 CL = 15pF 7.6 11.9 1.0 14.0 ns
CL = 50pF 10.1 15.4 1.0 17.5
5.0 ± 0.5 CL = 15pF 5.0 7.7 1.0 9.0
CL = 50pF 6.5 9.7 1.0 11.0
tPLH, tPHL Propagation Delay
Time (D–On)
3.3 ± 0.3 CL = 15pF 7.0 11.0 1.0 13.0 ns
CL = 50pF 9.5 14.5 1.0 16.5
5.0 ± 0.5 CL = 15pF 4.5 6.8 1.0 8.0
CL = 50pF 6.0 8.8 1.0 10.0
tPZL, tPZH 3-STATE Output
Enable Time
3.3 ± 0.3 RL = 1kΩCL = 15pF 7.3 11.5 1.0 13.5 ns
CL = 50pF 9.8 15.0 1.0 17.0
5.0 ± 0.5 CL = 15pF 5.2 7.7 1.0 9.0
CL = 50pF 6.7 9.7 1.0 11.0
tPLZ, tPHZ 3-STATE Output
Disable Time
3.3 ± 0.3 RL = 1kΩCL = 50pF 10.7 14.5 1.0 16.5 ns
5.0 ± 0.5 CL = 50pF 6.7 9.7 1.0 11.0
tOSLH, tOSHL Output to Output
Skew
3.3 ± 0.3 (3) CL = 50pF 1.5 1.5 ns
5.0 ± 0.5 CL = 50pF 1.0 1.0
CIN Input Capacitance VCC = Open 4 10 10 pF
COUT Output Capacitance VCC = 5.0V 6 pF
CPD Power Dissipation
Capacitance
(4) 29 pF
Symbol Parameter
VCC
(V)
TA = 25°C
TA = –40°C to
+85°C
UnitsMin. Typ. Max. Min. Max.
tw(H), tw(L) Minimum Pulse Width (LE) 3.3 ± 0.3 5.0 5.0 ns
5.0 ± 0.5 5.0 5.0
tSMinimum Setup Time 3.3 ± 0.3 3.5 3.5 ns
5.0 ± 0.5 3.5 3.5
tHMinimum Hold Time 3.3 ± 0.3 1.5 1.5 ns
5.0 ± 0.5 1.5 1.5
74VHC573 Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3 6
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
74VHC573 Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3 7
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
74VHC573 Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3 8
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
74VHC573 Octal D-Type Latch with 3-STATE Outputs
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC573 Rev. 1.3 9
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HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
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when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
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2. A critical component in any component of a life support,
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
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development. Specifications may change in any manner without notice.
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published at a later date. Fairchild Semiconductor reserves the right to
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Rev. I27
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