2007 Microchip Technology Inc. DS21161H-page 1
24LCS21A
Features:
Single Supply with Operation Down to 2.5V
Completely Implements DDC1™/DDC2™ Inter-
face for Monitor Identification, Including Recovery
to DDC1
Low-Power CMOS Technology:
- 1 mA active current, typical
-10 A standby current, typical at 5.5V
2-Wire Serial Interface Bus, I2C™ Compatible
100 kHz (2.5V) and 400 kHz (5V) Compatibility
Self-Timed Write Cycle (including Auto-Erase)
Hardware Write-Protect Pin
Page Write Buffer for up to Eight Bytes
1,000,000 Erase/Write Cycles Ensured
Data Retention > 200 years
ESD Protection > 4000V
8-pin PDIP and SOIC Package
Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +70°C
Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 24LCS21A is a
128 x 8-bit dual-mode Electrically Erasable PROM.
This device is designed for use in applications
requiring storage and serial transmission of configura-
tion and control information. Two modes of operation
have been implemented: Transmit-Only mode and
Bidirectional mode. Upon power-up, the device will be
in the Transmit-Only mode, sending a serial bit stream
of the memory array from 00h to 7Fh, clocked by the
VCLK pin. A valid high-to-low transition on the SCL
pin will cause the device to enter the Transition mode
and look for a valid control byte on the I2C bus. If it
detects a valid control byte from the master, it will
switch into Bidirectional mode, with byte selectable
read/write capability of the memory array using SCL.
If no control byte is received, the device will revert to
the Transmit-Only mode after it receives 128 consec-
utive VCLK pulses while the SCL pin is idle. The
24LCS21A also enables the user to write-protect the
entire memory array using its write-protect pin. The
24LCS21A is available in a standard 8-pin PDIP and
SOIC package in industrial temperature range.
Package Types
Block Diagram
Pin Function Table
Name Function
WP Write-Protect (active low)
VSS Ground
SDA Serial Address/Data I/O
SCL Serial Clock (Bidirectional mode)
VCLK Serial Clock (Transmit-Only mode)
VCC +2.5V to 5.5V Power Supply
NC No Connection
PDIP
SOIC
24LCS21A
NC
NC
WP
Vss
1
2
3
4
8
7
6
5
Vcc
VCLK
SCL
SDA
24LCS21A
NC
NC
WP
Vss
1
2
3
4
8
7
6
5
Vcc
VCLK
SCL
SDA
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
WP
SDA SCL
VCC
VSS
VCLK
1K 2.5V Dual Mode I2C Serial EEPROM
DDC is a trademark of the Video Electronics Standards Assoc.
I2C is a trademark of Philips Corporation.
24LCS21A
DS21161H-page 2 2007 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied................................................................................................-40C to +125C
ESD protection on all pins 4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS VCC = +2.5V to 5.5V
Industrial (I): TA = -40°C to +85°C
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High-level input voltage
Low-level input voltage
VIH
VIL
0.7 VCC
0.3 VCC
V
V
Input levels on VCLK pin:
High-level input voltage
Low-level input voltage
VIH
VIL
2.0
0.2 VCC
V
V
VCC 2.7V (Note)
VCC < 2.7V (Note)
Hysteresis of Schmitt Trigger inputs VHYS .05 VCC —V(Note)
Low-level output voltage VOL1—0.4VIOL = 3 mA, VCC = 2.5V (Note)
Low-level output voltage VOL2—0.6VIOL = 6 mA, VCC = 2.5V
Input leakage current ILI —±1AVIN = VSS or VCC
Output leakage current ILO —±1AVOUT = VSS or VCC
Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note)
T
A = 25C, FCLK = 1 MHz
Operating current ICC Write
ICC Read
3
1
mA
mA
VCC = 5.5V
VCC = 5.5V, SCL = 400 kHz
Standby current ICCS
30
100
A
A
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
VCLK = VSS
Note: This parameter is periodically sampled and not 100% tested.
2007 Microchip Technology Inc. DS21161H-page 3
24LCS21A
TABLE 1-2: AC CHARACTERISTICS
Parameter Symbol
Vcc = 2.5-4.5V
Standard Mode
Vcc = 4.5 - 5.5V
Fast Mode Units Remarks
Min Max Min Max
Clock frequency FCLK 100 400 kHz
Clock high time THIGH 4000 600 ns
Clock low time TLOW 4700 1300 ns
SDA and SCL rise time TR 1000 300 ns (Note 1)
SDA and SCL fall time TF 300 300 ns (Note 1)
Start condition hold time THD:STA 4000 600 ns After this period the first
clock pulse is generated
Start condition setup time T
SU:STA 4700 600 ns Only relevant for repeated
Start condition
Data input hold time THD:DAT 0—0ns(Note 2)
Data input setup time T
SU:DAT 250 100 ns
Stop condition setup time TSU:STO 4000 600 ns
Output valid from clock TAA 3500 900 ns (Note 2)
Bus free time TBUF 4700 1300 ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
T
OF 250 20 + 0.1
CB
250 ns (Note 1), CB 100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP 50 50 ns (Note 3)
Write cycle time TWR 10 10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK TVAA 2000 1000 ns
VCLK high time TVHIGH 4000 600 ns
VCLK low time TVLOW 4700 1300 ns
VCLK setup time TVHST 0—0ns
VCLK hold time TSPVL 4000 600 ns
Mode transition time TVHZ 1000 500 ns
Transmit-only power-up time TVPU 0—0ns
Input filter spike suppression
(VCLK pin)
TSPV 100 100 ns
Endurance 1M 1M cycles 25°C, VCC = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
24LCS21A
DS21161H-page 4 2007 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LCS21A is designed to comply to the DDC
Standard proposed by VESA® (Figure 3-3) with the
exception that it is not Access.bus™ capable. It oper-
ates in two modes, the Transmit-Only mode and the
Bidirectional mode. There is a separate 2-wire protocol
to support each mode, each having a separate clock
input but sharing a common data line (SDA). The
device enters the Transmit-Only mode upon power-up.
In this mode, the device transmits data bits on the SDA
pin in response to a clock signal on the VCLK pin. The
device will remain in this mode until a valid high-to-low
transition is placed on the SCL input. When a valid
transition on SCL is recognized, the device will switch
into the Bidirectional mode and look for its control byte
to be sent by the master. If it detects its control byte, it
will stay in the Bidirectional mode. Otherwise, it will
revert to the Transmit-Only mode after it sees 128
VCLK pulses.
2.1 Transmit-Only Mode
The device will power up in the Transmit-Only mode at
address 00h. This mode supports a unidirectional
2-wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the
Transmit-Only mode (Section 2.2 “Initialization Pro-
cedure”). In this mode, data is transmitted on the SDA
pin in 8-bit bytes, with each byte followed by a ninth,
null bit (Figure 2-1). The clock source for the Transmit-
Only mode is provided on the VCLK pin, and a data bit
is output on the rising edge on this pin. The eight bits in
each byte are transmitted Most Significant bit first.
Each byte within the memory array will be output in
sequence. After address 7Fh in the memory array is
transmitted, the internal Address Pointers will wrap
around to the first memory location (00h) and continue.
The Bidirectional mode Clock (SCL) pin must be held
high for the device to remain in the Transmit-Only
mode.
2.2 Initialization Procedure
After VCC has stabilized, the device will be in the Trans-
mit-Only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit in address
00h. (Figure 2-2).
FIGURE 2-1: TRANSMIT-ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
VCLK
TVAA TVAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB) Bit 7
TVLOWTVHIGH
TVAA TVAA
Bit 8 Bit 7High-Impedance for 9 Clock Cycles
TVPU
12 891011
SCL
SDA
VCLK
VCC
2007 Microchip Technology Inc. DS21161H-page 5
24LCS21A
3.0 BIDIRECTIONAL MODE
Before the 24LCS21A can be switched into the
Bidirectional mode (Figure 3-1), it must enter the Tran-
sition mode, which is done by applying a valid high-to-
low transition on the Bidirectional mode clock (SCL). As
soon it enters the Transition mode, it looks for a control
byte, ‘1010 000X’ on the I2C™ bus, and starts to
count pulses on VCLK. Any high-to-low transition on
the SCL line will reset the count. If it sees a pulse count
of 128 on VCLK while the SCL line is idle, it will revert
back to the Transmit-Only mode and transmit its con-
tents starting with the Most Significant bit in address
00h. However, if it detects the control byte on the I2C™
bus, (Figure 3-2) it will switch to the Bidirectional mode.
Once the device has made the transition to the Bidirec-
tional mode, the only way to switch the device back to
the Transmit-Only mode is to remove power from the
device. The mode transition process is shown in detail
in Figure 3-3.
Once the device has switched into the Bidirectional
mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two-wire
Bidirectional data transmission protocol (I2C™). In this
protocol, a device that sends data on the bus is defined
to be the transmitter, and a device that receives data
from the bus is defined to be the receiver. The bus must
be controlled by a master device that generates the
Bidirectional mode clock (SCL), controls access to the
bus and generates the Start and Stop conditions, while
the 24LCS21A acts as the slave. Both master and
slave can operate as transmitter or receiver, but the
master device determines which mode is activated. In
the Bidirectional mode, the 24LCS21A only responds
to commands for device ‘1010 000X’.
FIGURE 3-1: MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
FIGURE 3-2: SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE
TVHZ
SCL
SDA
VCLK
Transmit-Only
MODE Bidirectional Recovery to Transmit-Only mode
Bit 8
(MSB of data in 00h)
VCLK count = 1 2 3 4 127 128
Transition mode with possibility to return to Transmit-Only mode
Bidirectional
permanently
SCL
SDA
VCLK count = 1 2 n 0
VCLK
Transmit-Only
MODE
S1010 0000 ACK
n < 128
24LCS21A
DS21161H-page 6 2007 Microchip Technology Inc.
FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA®
Communication
is idle
Is Vsync
present?
No
Send EDID™ continuously
using Vsync as clock
High-to-Low
transition on
SCL?
No
Yes
Yes
Stop sending EDID.
Switch to DDC2™ mode.
Display has
transition state
?
optional
Set Vsync counter = 0
Change on
VCLK lines?
SCL, SDA or
No
Yes
High-Low
transition on SCL
?
Reset Vsync counter = 0
No
Yes
Valid
received?
DDC2 address
No
No VCLK
cycle?
Yes
Increment VCLK counter
Yes
Switch back to DDC1™
mode.
DDC2 communication
idle. Display waiting for
address byte.
DDC2B
address
received?
Yes
Receive DDC2B
command
Respond to DDC2B
command
Is display
Access.busTM
Yes
Valid Access.bus
address?
No
Yes
See Access.bus
specification to determine
correct procedure.
Yes
No
Yes
No
No
No
The 24LCS21A was designed to
Display Power-on
or
DDC™ Circuit Powered
from +5 volts
or start timer
Reset counter or timer
(if appropriate)
Counter = 128 or
timer expired?
High-to-Low
transition on
SCL?
No
Yes
comply to the portion of flowchart inside dash box.
Note 1: The base flowchart is copyright 1993, 1994, 1995 Video Electronic Standard Association (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2: The dash box and text “The 24LCS21A and... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS21A.
capable?
2007 Microchip Technology Inc. DS21161H-page 7
24LCS21A
3.1 Bidirectional Mode Bus
Characteristics
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-4).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2 START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3 STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
out (FIFO) fashion.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-4: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: Once switched into Bidirectional mode, the
24LCS21A will remain in that mode until
power is removed. Removing power is the
only way to reset the 24LCS21A into the
Transmit-Only mode.
Note: The 24LCS21A does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
(A) (B) (D) (D) (A)(C)
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
SDA
24LCS21A
DS21161H-page 8 2007 Microchip Technology Inc.
FIGURE 3-5: BUS TIMING START/STOP
FIGURE 3-6: BUS TIMING DATA
3.1.6 SLAVE ADDRESS
After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LCS21A.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LCS21A
(Figure 3-7).
The 24LCS21A monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
FIGURE 3-7: CONTROL BYTE
ALLOCATION
SCL
SDA
Start Stop
VHYS
TSU:STO
THD:STA
TSU:STA
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA
THD:DAT TSU:DAT TSU:STO
TBUF
TAA
TR
Operation Slave Address R/W
Read 1010000 1
Write 1010000 0
R/W A
1010000
Read/Write
Start
Slave Address
2007 Microchip Technology Inc. DS21161H-page 9
24LCS21A
4.0 WRITE OPERATION
4.1 Byte Write
Following the Start signal from the master, the slave
address (four bits), three zero bits (000) and the R/W
bit which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24LCS21A.
After receiving another Acknowledge signal from the
24LCS21A the master device will transmit the data
word to be written into the addressed memory location.
The 24LCS21A acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle, and during this time the 24LCS21A will not
generate Acknowledge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high-to-low during the self-timed
program operation will not halt programming of the
device.
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LCS21A in the same way
as in a byte write. But instead of generating a Stop
condition the master transmits up to eight data bytes to
the 24LCS21A, which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. After
the receipt of each word, the three lower order Address
Pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 5-2).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high-to-low during the self-timed
program operation will not halt programming of the
device.
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
24LCS21A
DS21161H-page 10 2007 Microchip Technology Inc.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: VCLK WRITE ENABLE TIMING
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte
Word
Address Data
S
T
O
P
S
T
A
R
T
A
C
K
SP
A
C
K
A
C
K
VCLK
SCL
SDA
IN
VCLK
THD:STA TSU:STO
TVHST TSPVL
2007 Microchip Technology Inc. DS21161H-page 11
24LCS21A
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.
FIGURE 5-1: ACKNOWLEDGE
POLLING FLOW
FIGURE 5-2: PAGE WRITE
Did Device
Acknowledge
(ACK = 0)?
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Next
Operation
No
Yes
SDA Line
Control
Byte
Word
Address
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data n + 1 Data n + 7
Data (n)
P
S
VCLK
Bus Activity
Master
Bus Activity
24LCS21A
DS21161H-page 12 2007 Microchip Technology Inc.
6.0 WRITE PROTECTION
When using the 24LCS21A in the Bidirectional mode,
the VCLK pin can be used as a write-protect control
pin. Setting VCLK high allows normal write operations,
while setting VCLK low prevents writing to any location
in the array. Connecting the VCLK pin to VSS would
allow the 24LCS21A to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-Only mode.
Additionally, pin 3 performs a flexible write-protect
function. The 24LCS21A contains a write protection
control fuse whose factory default state is cleared.
Writing any data to address 7Fh (normally the
checksum in DDC applications), sets the fuse which
enables the WP pin. Until this fuse is set, the
24LCS21A is always write enabled (if VCLK = 1). After
the fuse is set, the write capability of the 24LCS21A is
determined by both VCLK and WP pins (Table 6-1).
TABLE 6-1: WRITE-PROTECT TRUTH
TABLE
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LCS21A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the
24LCS21A issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24LCS21A discontinues transmission (Figure 7-1).
FIGURE 7-1: CURRENT ADDRESS
READ
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LCS21A as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. Then the master issues the control byte again, but
with the R/W bit set to a one. The 24LCS21A will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LCS21A
discontinues transmission (Figure 7-2).
VCLK WP Address
7Fh Written
Mode
for
00h-7Fh
0X XRead-only
1X No R/W
11/open XR/W
10 Yes Read-only
Control
A
C
K
SP
Byte Data n
Bus Activity
SDA Line
Bus Activity
A
C
K
N
O
Master
10100001
S
T
O
P
S
T
A
R
T
2007 Microchip Technology Inc. DS21161H-page 13
24LCS21A
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTIAL READ
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LCS21A transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LCS21A to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LCS21A contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4 Noise Protection
The 24LCS21A employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt Trigger
and filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte
Word
Address Data n
A
C
K
S
T
A
R
T
N
O
S
T
A
RControl
Byte
A
C
K
A
C
K
SS
T
P
S
T
O
P
10100000 00000111
A
C
K
A
C
K
P
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte
Data n Data n+1 Data n+2 Data n+X
A
C
K
A
C
K
A
C
K
N
O
A
C
K
S
T
O
P
24LCS21A
DS21161H-page 14 2007 Microchip Technology Inc.
8.0 PIN DESCRIPTIONS
8.1 SDA
This pin is used to transfer addresses and data into and
out of the device, when the device is in the Bidirectional
mode. In the Transmit-Only mode, which only allows
data to be read from the device, data is also transferred
on the SDA pin. This pin is an open drain terminal,
therefore the SDA bus requires a pull-up resistor to
VCC (typical 10 K for 100 kHz, 1 K for 400 kHz).
For normal data transfer in the Bidirectional mode, SDA
is allowed to change only during SCL low. Changes
during SCL high are reserved for indicating the Start
and Stop conditions.
8.2 SCL
This pin is the clock input for the Bidirectional mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the device from the Transmit-Only mode to the
Bidirectional mode. It must remain high for the chip to
continue operation in the Transmit-Only mode.
8.3 VCLK
This pin is the clock input for the Transmit-Only mode
(DDC1). In the Transmit-Only mode, each bit is clocked
out on the rising edge of this signal. In the Bidirectional
mode, a high logic level is required on this pin to enable
write capability.
8.4 WP
This pin is used for flexible write protection of the
24LCS21A. When the last memory location (7Fh) is
written with any data, this pin is enabled and
determines the write capability of the 24LCS21A
(Table 6-1).
2007 Microchip Technology Inc. DS21161H-page 15
24LCS21A
APPENDIX A: REVISION HISTORY
Revision F
Corrections to Section 1.0, Electrical Characteristics.
Revision G
Revised Section 8.4; Added On-Line Support page.
Revision H
Features Section - Add Pb-free and remove Commer-
cial Temp; Revised Description; Table 1-1, Remove
Commercial Temp, Revised Input/Output conditions;
Revise Product ID section.
24LCS21A
DS21161H-page 16 2007 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: 24LCS21A Dual Mode I2C Serial EEPROM
24LCS21AT Dual Mode I2C Serial EEPROM (Tape and Reel)
Temperature
Range:
I= -40C to +85C
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
2007 Microchip Technology Inc. DS21161H-page 17
24LCS21A
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
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information:
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To register, access the Microchip web site at
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Notification and follow the registration instructions.
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Users of Microchip products can receive assistance
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Customers should contact their distributor,
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Technical support is available through the web site
at: http://support.microchip.com
24LCS21A
DS21161H-page 18 2007 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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DS21161H24LCS21A
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2007 Microchip Technology Inc. DS21161H-page 19
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21161H-page 20 2007 Microchip Technology Inc.
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