OUTx
GNDOGNDI
INx
VCCO
VCCI Isolation
Capacitor
ENx
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
ISO7842x High-Performance, 8000-V
PK
Reinforced Quad-Channel Digital Isolator
1
1 Features
1 Signaling Rate: Up to 100 Mbps
Wide Supply Range: 2.25 V to 5.5 V
2.25-V to 5.5-V Level Translation
Wide Temperature Range: –55°C to +125°C
Low-Power Consumption, Typical 1.7 mA per
Channel at 1 Mbps
Low Propagation Delay: 11 ns Typical
(5-V Supplies)
Industry leading CMTI (Min): ±100 kV/μs
Robust Electromagnetic Compatibility (EMC)
System-Level ESD, EFT, and Surge Immunity
Low Emissions
Isolation Barrier Life: >40 Years
Wide Body SOIC-16 Package and Extra-Wide
Body SOIC-16 Package Options
Safety and Regulatory Approvals:
8000-VPK Reinforced Isolation per DIN V VDE
V 0884-10 (VDE V 0884-10):2006-12
5.7-kVRMS Isolation for 1 Minute per UL 1577
CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 60601-1 End Equipment
Standards
CQC Certification per GB4943.1-2011
TUV Certification per EN 61010-1 and EN
60950-1
All DW Package Certifications Complete;
DWW Package Certifications Complete per
UL, VDE, TUV and Planned for CSA and CQC
2 Applications
Industrial Automation
Motor Control
Power Supplies
Solar Inverters
Medical Equipment
Hybrid Electric Vehicles
3 Description
The ISO7842x device is a high-performance, quad-
channel digital isolator with a 8000-VPK isolation
voltage. This device has reinforced isolation
certifications according to VDE, CSA, CQC, and TUV.
The isolator provides high electromagnetic immunity
and low emissions at low-power consumption, while
isolating CMOS or LVCMOS digital I/Os. Each
isolation channel has a logic input and output buffer
separated by a silicon-dioxide (SiO2) insulation
barrier.
This device comes with enable pins that can be used
to put the respective outputs in high impedance for
multi-master driving applications and to reduce power
consumption. The ISO7842 device has two forward
and two reverse-direction channels. If the input power
or signal is lost, the default output is high for the
ISO7842 device and low for the ISO7842F device.
See the Device Functional Modes section for further
details.
Used in conjunction with isolated power supplies, this
device helps prevent noise currents on a data bus or
other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
Through innovative chip design and layout
techniques, electromagnetic compatibility of the
ISO7842 device has been significantly enhanced to
ease system-level ESD, EFT, surge, and emissions
compliance.
The ISO7842 device is available in 16-pin SOIC
wide-body (DW) and extra-wide body (DWW)
packages.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
ISO7842
ISO7842F DW (16) 10.30 mm × 7.50 mm
DWW (16) 10.30 mm × 14.0 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
2
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 5
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Power Ratings........................................................... 7
6.6 Insulation Specifications............................................ 8
6.7 Safety-Related Certifications..................................... 9
6.8 Safety Limiting Values .............................................. 9
6.9 Electrical Characteristics–5-V Supply..................... 10
6.10 Supply Current Characteristics–5-V Supply.......... 10
6.11 Electrical Characteristics—3.3-V Supply .............. 11
6.12 Supply Current Characteristics—3.3-V Supply..... 11
6.13 Electrical Characteristics—2.5-V Supply .............. 12
6.14 Supply Current Characteristics—2.5-V Supply..... 12
6.15 Switching Characteristics—5-V Supply................. 13
6.16 Switching Characteristics—3.3-V Supply.............. 13
6.17 Switching Characteristics—2.5-V Supply.............. 14
6.18 Insulation Characteristics Curves ......................... 15
6.19 Typical Characteristics.......................................... 16
7 Parameter Measurement Information ................ 17
8 Detailed Description............................................ 19
8.1 Overview................................................................. 19
8.2 Functional Block Diagram....................................... 19
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 21
9 Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application.................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support................. 26
12.1 Documentation Support ........................................ 26
12.2 Related Links ........................................................ 26
12.3 Receiving Notification of Documentation Updates 26
12.4 Community Resources.......................................... 26
12.5 Trademarks........................................................... 26
12.6 Electrostatic Discharge Caution............................ 26
12.7 Glossary................................................................ 26
13 Mechanical, Packaging, and Orderable
Information........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2016) to Revision G Page
Changed part numbers in the Power Ratings table (previously Power Dissipation Characteristics) .................................... 7
Changed the input-to-output test voltage parameter to apparent charge in the Insulation Specifications ............................ 8
Added the Receiving Notification of Documentation Updates section ................................................................................. 26
Changes from Revision E (March 2016) to Revision F Page
Changed the number of years for the isolation barrier life in the Features section .............................................................. 1
VDE certification is now complete ......................................................................................................................................... 1
Changed VCCO to VCCI for the minimum value of the input threshold voltage hysteresis parameter in all electrical
characteristics tables............................................................................................................................................................ 10
Added VCM to the test condition of the common-mode transient immunity parameter in all electrical characteristics
tables.................................................................................................................................................................................... 10
Added the lifetime projection graphs for DW and DWW packages to the Safety Limiting Values section ......................... 15
Changes from Revision D (December 2015) to Revision E Page
Changed the Safety and Regulatory Approvals list of Features ............................................................................................ 1
Added Features "TUV Certification per EN 61010-1 and EN 60950-1"................................................................................. 1
Changed text in the first paragraph of the Description From: "certifications according to VDE, CSA, and CQC". To:
"certifications according to VDE, CSA, CQC, and TUV." ...................................................................................................... 1
Added Note 1 to Insulation Characteristics ........................................................................................................................... 8
3
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
Changed IEC 60664-1 Ratings Table..................................................................................................................................... 8
Added TUV to the Regulatory Information section and Regulatory Information. Deleted Note 1 in Regulatory
Information ............................................................................................................................................................................. 9
Changed Device I/O Schematics ......................................................................................................................................... 21
Changes from Revision C (July 2015) to Revision D Page
Added Features: DW Package Certifications Complete; DWW Certifications Planned......................................................... 1
Added text to the Description: and extra-wide body (DWW) packages. ............................................................................... 1
Added package: Extra wide SOIC, DWW (16) to the Device Information table..................................................................... 1
Added the 16-DWW Package to Package Insulation and Safety-Related Specifications...................................................... 8
Added the DWW package information to Package Insulation and Safety-Related Specifications ........................................ 8
Added the DWW package information to Regulatory Information.......................................................................................... 9
Changed the MIN value of CMTI in Electrical Characteristics–5-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted
the TYP value of 100 kV/μs.................................................................................................................................................. 10
Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics–5-V Supply.. 10
Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics–5-V
Supply................................................................................................................................................................................... 10
Changed the MIN value of CMTI in Electrical Characteristics—3.3-V Supply, 5 V table From: 70 To: 100 kV/μs,
deleted the TYP value of 100 kV/μs..................................................................................................................................... 11
Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics—3.3-V
Supply................................................................................................................................................................................... 11
Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics—3.3-
V Supply ............................................................................................................................................................................... 11
Changed the MIN value of CMTI in Electrical Characteristics—2.5-V Supply, 5 V table From: 70 To: 100 kV/μs,
deleted the TYP value of 100 kV/μs..................................................................................................................................... 12
Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics—2.5-V
Supply................................................................................................................................................................................... 12
Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics—2.5-
V Supply ............................................................................................................................................................................... 12
Added text to the Application Information section: " isolation voltage per UL 1577." ......................................................... 22
Changes from Revision B (April 2015) to Revision C Page
Added device ISO7482F to the datasheet ............................................................................................................................. 1
Changed the Description to include: " default output is 'high' for the ISO7842 device and 'low' for the ISO7842F device... 1
Changed Thermal Derating Curve for Safety Limiting Current per VDE , Added Thermal Derating Curve for Safety
Limiting Power per VDE ....................................................................................................................................................... 15
Changed From: tPLH and tPHLat 5.5V To: tPLH and tPHL at 5.0 V ........................................................................................... 16
Changed Default Output Delay Time Test Circuit and Voltage Waveforms......................................................................... 18
Added the Device I/O Schematics section .......................................................................................................................... 21
Changes from Revision A (November 2014) to Revision B Page
Changed the document title From: "Quad-Channel Digital Isolator" To: "Quad-Channel 2/2 Digital Isolator"....................... 1
Added Features 2.25 V to 5.5 V Level Translation ................................................................................................................ 1
Changed Features From: Wide Body SOIC-16 Package To: Wide Body and Extra-Wide Body SOIC-16 Package
Options .................................................................................................................................................................................. 1
Changed the Safety and Regulatory Approvals list of Features ............................................................................................ 1
VDE certification is now complete ......................................................................................................................................... 1
4
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
Changed the Simplified Schematic and added Notes 1 and 2............................................................................................... 1
Added the Power Dissipation Characteristics table................................................................................................................ 7
Changed Package Insulation and Safety-Related Specifications .......................................................................................... 8
Changed Insulation Characteristics title From: DIN V VDE 0884-10 (VDE V 0884-10) and UL 1577 Insulation
Characteristics To: Insulation Characteristics ........................................................................................................................ 8
Changed Insulation Characteristics ....................................................................................................................................... 8
Changed the Test Condition of CTI of the table in Package Insulation and Safety-Related Specifications ......................... 8
Changed the MIN value of CTI From" > 600 V To: 600 V .................................................................................................... 8
Changed the table in Regulatory Information......................................................................................................................... 9
Changed Switching Characteristics Test Circuit and Voltage Waveforms .......................................................................... 17
Changed Enable/Disable Propagation Delay Time Test Circuit and Waveform ................................................................. 17
Changed From: VCC1 To: VCCI in Default Output Delay Time Test Circuit and Voltage Waveforms.................................... 18
Changed Common-Mode Transient Immunity Test Circuit.................................................................................................. 18
Deleted INPUT-SIDE and OUTPUT-SIDE from columns 1 and 2 of Function Table ......................................................... 21
Changed the Application Information section ...................................................................................................................... 22
Changed the Application Information section ...................................................................................................................... 22
Added text and typical circuit hook-up figure to the Detailed Design Procedure section .................................................... 23
Changes from Original (October 2014) to Revision A Page
Changed Feature From: All Agencies Approvals Pending To: All Agencies Approvals Planned .......................................... 1
Changed statement in the Description From; "This device is certified to meet reinforced isolation requirements by
VDE and CSA." To: "This device is being reviewed for reinforced isolation certification by VDE and CSA." ....................... 1
Changed RIO MIN value From: 109To: 1011 in the Package Insulation and Safety-Related Specifications table ................ 8
Changed the first row of information in the Regulatory Information table ............................................................................. 9
ISOLATION
GND1 GND298
EN1 EN2107
OUTD IND116
OUTC INC125
INB OUTB134
INA OUTA143
GND1 GND2152
VCC1 VCC2
161
5
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
5 Pin Configuration and Functions
DW and DWW Packages
16-Pin SOIC
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
EN1 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-
impedance state when EN1 is low.
EN2 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-
impedance state when EN2 is low.
GND1 2 Ground connection for VCC1
8
GND2 9 Ground connection for VCC2
15
INA 3 I Input, channel A
INB 4 I Input, channel B
INC 12 I Input, channel C
IND 11 I Input, channel D
OUTA 14 O Output, channel A
OUTB 13 O Output, channel B
OUTC 5 O Output, channel C
OUTD 6 O Output, channel D
VCC1 1 Power supply, VCC1
VCC2 16 Power supply, VCC2
6
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
VCC1,
VCC2 Supply voltage(2) –0.5 6 V
Voltage INx –0.5 VCCX + 0.5(3)
VOUTx –0.5 VCCX + 0.5(3)
ENx –0.5 VCCX + 0.5(3)
IOOutput current –15 15 mA
Surge immunity 12.8 kV
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±6000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2) ±1500
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
(2) To maintain the recommended operating conditions for TJ, see Thermal Information.
6.3 Recommended Operating Conditions MIN NOM MAX UNIT
VCC1,
VCC2 Supply voltage 2.25 5.5 V
IOH High-level output current VCCO(1) = 5 V –4 mAVCCO(1) = 3.3 V –2
VCCO(1) = 2.5 V –1
IOL Low-level output current VCCO(1) = 5 V 4 mAVCCO(1) = 3.3 V 2
VCCO(1) = 2.5 V 1
VIH High-level input voltage 0.7 × VCCI (1) VCCI (1) V
VIL Low-level input voltage 0 0.3 × VCCI(1) V
DR Signaling rate 0 100 Mbps
TJJunction temperature(2) –55 150 °C
TAAmbient temperature –55 25 125 °C
7
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information ISO7842
UNIT
THERMAL METRIC(1) DW (SOIC) DWW (SOIC)
16 Pins 16 Pins
RθJA Junction-to-ambient thermal resistance 78.9 78.9 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 41.6 41.1 °C/W
RθJB Junction-to-board thermal resistance 43.6 49.5 °C/W
ψJT Junction-to-top characterization parameter 15.5 15.2 °C/W
ψJB Junction-to-board characterization parameter 43.1 48.8 °C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
6.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ= 150°C, CL= 15 pF, input a 50 MHz 50% duty cycle square wave
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PDMaximum power dissipation by ISO7842x 200 mW
PD1 Maximum power dissipation by side-1 of
ISO7842x 100 mW
PD2 Maximum power dissipation by side-2 of
ISO7842x 100 mW
8
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
6.6 Insulation Specifications
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
DW DWW
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air >8 >14.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package
surfaceHigh Voltage Feature Description >8 >14.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 >21 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A >600 >600 V
Material group I I
Overvoltage category per IEC
60664-1 Rated mains voltage 600 VRMS I–IV I–IV
Rated mains voltage 1000 VRMS I–III I–IV
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM Maximum repetitive peak isolation
voltage 2121 2828 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); Time dependent dielectric
breakdown (TDDB) Test, see Figure 1 and Figure 2 1500 2000 VRMS
DC voltage 2121 2828 VDC
VIOTM Maximum transient isolation
voltage VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production) 8000 8000 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification) 8000 8000 VPK
qpd Apparent charge(4)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and 3394 VPK
(DWW), tm= 10 s
55
pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and 4525 VPK
(DWW), tm= 10 s
55
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 3977 VPK (DW) and 5303 VPK
(DWW), tm= 1 s
55
CIO Barrier capacitance, input to
output(5) VIO = 0.4 × sin (2πft), f = 1 MHz 2 2 pF
RIO Isolation resistance, input to
output(5)
VIO = 500 V, TA= 25°C >1012 >1012
VIO = 500 V, 100°C TA125°C >1011 >1011
VIO = 500 V at TS= 150°C >109>109
Pollution degree 2 2
Climatic category 55/125/21 55/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%
production) 5700 5700 VRMS
9
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
6.7 Safety-Related Certifications
Certifications for the DW package are complete. DWW package certifications are complete for UL, VDE and TUV and
planned for CSA and CQC.
VDE CSA UL CQC TUV
Certified according to DIN
V VDE V 0884-10 (VDE V
0884-10):2006-12 and DIN
EN 60950-1 (VDE 0805
Teil 1):2011-01
Approved under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
Certified according to UL
1577 Component
Recognition Program
Certified according to GB
4943.1-2011
Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced insulation
Maximum transient
isolation voltage, 8000 VPK;
Maximum repetitive peak
isolation voltage, 2121 VPK
(DW), 2828 VPK (DWW);
Maximum surge isolation
voltage, 8000 VPK
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., 800 VRMS
(DW package) and 1450 VRMS
(DWW package) max working
voltage (pollution degree 2,
material group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage (DW package)
Single protection, 5700
VRMS
Reinforced Insulation,
Altitude 5000 m, Tropical
Climate, 250 VRMS
maximum working voltage
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS (DW
package) and 1000 VRMS (DWW
package)
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS (DW package) and
1450 VRMS (DWW package)
Certificate number:
40040142 Master contract number:
220991 File number: E181974 Certificate number:
CQC15001121716 Client ID number: 77311
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISSafety input, output, or supply
current
RθJA = 78.9°C/W, VI= 5.5 V, TJ= 150°C, TA= 25°C 288 mARθJA = 78.9°C/W, VI= 3.6 V, TJ= 150°C, TA= 25°C 440
RθJA = 78.9°C/W, VI= 2.75 V, TJ= 150°C, TA= 25°C 576
PSSafety input, output, or total
power RθJA = 78.9°C/W, TJ= 150°C, TA= 25°C 1584 mW
TSMaximum safety temperature 150 °C
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
10
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
6.9 Electrical Characteristics–5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1) 0.4 VCCO(1) 0.2 V
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI (1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx -10
CMTI Common-mode transient immunity VI= VCCI(1) or 0 V, VCM = 1500 V; see
Figure 14 100 kV/μs
CIInput capacitance VI= VCC/2 + 0.4 × sin (2πft), f = 1 MHz,
VCC = 5 V 2 pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
6.10 Supply Current Characteristics–5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY
CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current
Disable
EN1 = EN2 = 0V, VI= 0 V (ISO7842F),
VI= VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI= VCCI(1)
(ISO7842F), VI= 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal
VI= 0 V (ISO7842F), VI= VCCI(1)
(ISO7842) ICC1, ICC2 2 2.7 mA
VI= VCCI(1) (ISO7842F), VI= 0 V
(ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with
square wave clock input;
CL= 15 pF
1 Mbps ICC1, ICC2 3.3 4.6 mA
10 Mbps ICC1, ICC2 4.2 5.6 mA
100 Mbps ICC1, ICC2 13.7 16.6 mA
ISO7842DWW AND ISO7842FDWW
Supply current
Disable
EN1 = EN2 = 0V, VI= 0 V (ISO7842F),
VI= VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI= VCCI(1)
(ISO7842F), VI= 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal
VI= 0 V (ISO7842F), VI= VCCI(1)
(ISO7842) ICC1, ICC2 2 2.8 mA
VI= VCCI(1) (ISO7842F), VI= 0 V
(ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with
square wave clock input;
CL= 15 pF
1 Mbps ICC1, ICC2 3.4 4.7 mA
10 Mbps ICC1, ICC2 4.3 5.9 mA
100 Mbps ICC1, ICC2 14 17.3 mA
11
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA; see Figure 11 VCCO(1) 0.4 VCCO(1) 0.2 V
VOL Low-level output voltage IOL = 2 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI= VCCI(1) or 0 V, VCM = 1500 V; see
Figure 14 100 kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY
CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current
Disable
EN1 = EN2 = 0 V, VI= 0 V (ISO7842F), VI
= VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI= VCCI(1) (ISO7842F),
VI= 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal
VI= 0 V (ISO7842F), VI= VCCI(1)
(ISO7842) ICC1, ICC2 2 2.7 mA
VI= VCCI(1) (ISO7842F), VI= 0 V
(ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with
square wave clock input;
CL= 15 pF
1 Mbps ICC1, ICC2 3.3 4.5 mA
10 Mbps ICC1, ICC2 4 5.2 mA
100 Mbps ICC1, ICC2 10.8 12.9 mA
ISO7842DWW and ISO7842FDWW
Supply current
Disable
EN1 = EN2 = 0 V, VI= 0 V (ISO7842F), VI
= VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI= VCCI(1) (ISO7842F),
VI= 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal
VI= 0 V (ISO7842F), VI= VCCI(1)
(ISO7842) ICC1, ICC2 2 2.8 mA
VI= VCCI(1) (ISO7842F), VI= 0 V
(ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with
square wave clock input;
CL= 15 pF
1 Mbps ICC1, ICC2 3.4 4.7 mA
10 Mbps ICC1, ICC2 4.1 5.5 mA
100 Mbps ICC1, ICC2 11 13.6 mA
12
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –1 mA; see Figure 11 VCCO(1) 0.4 VCCO(1) 0.2 V
VOL Low-level output voltage IOL = 1 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI= VCCI(1) or 0 V, VCM = 1500 V; see
Figure 14 100 kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY
CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current
Disable
EN1 = EN2 = 0 V, VI= 0 V (ISO7842F), VI
= VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI= VCCI(1) (ISO7842F),
VI= 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal
VI= 0 V (ISO7842F), VI= VCCI(1)
(ISO7842) ICC1, ICC2 2 2.7 mA
VI= VCCI(1) (ISO7842F), VI= 0 V
(ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with
square wave clock input;
CL= 15 pF
1 Mbps ICC1, ICC2 3.2 4.5 mA
10 Mbps ICC1, ICC2 3.7 5.1 mA
100 Mbps ICC1, ICC2 8.9 10.8 mA
ISO7842DWW AND ISO7842FDWW
Supply current
Disable
EN1 = EN2 = 0 V, VI= 0 V (ISO7842F), VI
= VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI= VCCI(1) (ISO7842F),
VI= 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal
VI= 0 V (ISO7842F), VI= VCCI(1)
(ISO7842) ICC1, ICC2 2 2.8 mA
VI= VCCI(1) (ISO7842F), VI= 0 V
(ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with
square wave clock input;
CL= 15 pF
1 Mbps ICC1, ICC2 3.3 4.6 mA
10 Mbps ICC1, ICC2 3.8 5.3 mA
100 Mbps ICC1, ICC2 9 11.5 mA
13
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 6 11 16 ns
PWD Pulse width distortion(1) |tPHL tPLH| 0.55 4.1 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 2.5 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
trOutput signal rise time See Figure 11 1.7 3.9 ns
tfOutput signal fall time 1.9 3.9 ns
tPHZ Disable propagation delay, high-to-high impedance
output
See Figure 12
12 20 ns
tPLZ Disable propagation delay, low-to-high impedance
output 12 20 ns
tPZH
Enable propagation delay, high impedance-to-high
output for ISO7842 10 20 ns
Enable propagation delay, high impedance-to-high
output for ISO7842F 2 2.5 μs
tPZL
Enable propagation delay, high impedance-to-low
output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low
output for ISO7842F 10 20 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See
Figure 13 0.2 9 μs
tie Time interval error 216 1 PRBS data at 100 Mbps 0.90 ns
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 6 10.8 16 ns
PWD Pulse width distortion(1) |tPHL tPLH| 0.7 4.2 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 2.2 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
trOutput signal rise time See Figure 11 0.8 3 ns
tfOutput signal fall time 0.8 3 ns
tPHZ Disable propagation delay, high-to-high impedance
output
See Figure 12
17 32 ns
tPLZ Disable propagation delay, low-to-high impedance
output 17 32 ns
tPZH
Enable propagation delay, high impedance-to-high
output for ISO7842 17 32 ns
Enable propagation delay, high impedance-to-high
output for ISO7842F 2 2.5 μs
tPZL
Enable propagation delay, high impedance-to-low
output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low
output for ISO7842F 17 32 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V.
See Figure 13 0.2 9 μs
tie Time interval error 216 1 PRBS data at 100 Mbps 0.91 ns
14
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 7.5 11.7 17.5 ns
PWD Pulse width distortion(1) |tPHL tPLH| 0.66 4.2 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction Channels 2.2 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
trOutput signal rise time See Figure 11 1 3.5 ns
tfOutput signal fall time 1.2 3.5 ns
tPHZ Disable propagation delay, high-to-high impedance
output
See Figure 12
22 45 ns
tPLZ Disable propagation delay, low-to-high impedance
output 22 45 ns
tPZH
Enable propagation delay, high impedance-to-high
output for ISO7842 18 45 ns
Enable propagation delay, high impedance-to-high
output for ISO7842F 2 2.5 μs
tPZL
Enable propagation delay, high impedance-to-low
output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low
output for ISO7842F 18 45 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V.
See Figure 13 0.2 9 μs
tie Time interval error 216 1 PRBS data at 100 Mbps 0.91 ns
Ambient Temperature (qC)
Safety Limiting Current (mA)
0 50 100 150 200
0
100
200
300
400
500
600
700
D014
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Ambient Temperature (qC)
Safety Limiting Power (mW)
0 50 100 150 200
0
200
400
600
800
1000
1200
1400
1600
1800
D015
Power
Stress Voltage (VRMS)
Time to Fail (s)
400 1400 2400 3400 4400 5400 6400 7400 8400 9400
1.E+1
1.E+2
1.E+3
1.E+4
1.E+5
1.E+6
1.E+7
1.E+8
1.E+9
1.E+10
1.E+11
Safety Margin Zone: 2400 VRMS, 63 Years
Operating Zone: 2000 VRMS, 34 Years
20%
87.5%
TDDB Line (<1 PPM Fail Rate)
15
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
6.18 Insulation Characteristics Curves
TAupto 150°C Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS
Figure 1. Reinforced Isolation Capacitor Life Time
Projection for Devices in DW Package
TAupto 150°C Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS
Figure 2. Reinforced Isolation Capacitor Life Time
Projection for Devices in DWW Package
Figure 3. Thermal Derating Curve for Limiting Current per
VDE Figure 4. Thermal Derating Curve for Limiting Power per
VDE
Free-Air Temperature (oC)
Power Supply Under-Voltage Threshold (V)
-50 0 50 100 150
1.7
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
D005
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
Free-Air Temperature (oC)
Propagation Delay Time (ns)
-60 -30 0 30 60 90 120
8
9
10
11
12
13
D006
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
tPHL at 3.3 V
tPLH at 5.0 V
tPHL at 5.0 V
High-Level Output Current (mA)
High-Level Output Voltage (V)
-15 -10 -5 0
0
1
2
3
4
5
6
D003
VCC at 2.5 V
VCC at 3.3 V
VCC at 5.0 V
Low-Level Output Current (mA)
Low-Level Output Voltage (V)
0 5 10 15
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
D004D001
VCC at 2.5 V
VCC at 3.3 V
VCC at 5.0 V
Data Rate (Mbps)
Supply Current (mA)
0 25 50 75 100 125 150
0
4
8
12
16
20
24
D001
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5.0 V
ICC2 at 5.0 V
Data Rate (Mbps)
Supply Current (mA)
0 25 50 75 100 125 150
0
2
4
6
8
10
D002
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5.0 V
ICC2 at 5.0 V
16
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
6.19 Typical Characteristics
TA= 25°C CL= 15 pF
Figure 5. Supply Current vs Data Rate (With 15-pF Load)
TA= 25°C CL= No Load
Figure 6. Supply Current vs Data Rate (With No Load)
TA= 25°C
Figure 7. High-Level Output Voltage vs High-level Output
Current
TA= 25°C
Figure 8. Low-Level Output Voltage vs Low-Level Output
Current
Figure 9. Power Supply Undervoltage Threshold vs Free-Air
Temperature Figure 10. Propagation Delay Time vs Free-Air Temperature
Input
Generator
(See Note A)
Input
Generator
(See Note A)
IN OUT
Isolation Barrier
IN OUT
Isolation Barrier
VO
VO
CL
See Note B
CL
See Note B
50
50
0 V
3 V
EN
EN
VCCO
RL = 1 k±1%
RL = 1 k±1%
VI
VI
VO
VI
tPZL
VCC / 2
50%
VCC
VCC / 2
VOH
0 V
VOL
tPLZ
0.5 V
VO
VI
tPZH
VCC / 2
50%
VCC
VCC / 2
VOH
0 V
0 V
tPHZ
0.5 V
Copyright © 2016, Texas Instruments Incorporated
IN OUT
CL
See Note B
VO
VI
VOL
VOH
VCCI
0 V
tr
Isolation Barrier
50
Input
Generator
(See Note A) VIVO
tf
tPLH tPHL
50% 50%
50% 50%
90%
10%
Copyright © 2016, Texas Instruments Incorporated
17
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
7 Parameter Measurement Information
A. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr3
ns, tf3 ns, ZO= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristics Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR 10 kHz, 50% duty cycle,
tr3 ns, tf3 ns, ZO= 50 Ω.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Enable/Disable Propagation Delay Time Test Circuit and Waveform
IN OUT
Isolation Barrier
EN
VCCO
CL
See Note A
S1
GNDOGNDI +±
VCM
+
±
VOH or VOL
C = 0.1 µF ±1% C = 0.1 µF ±1%
VCCI
Pass-fail criteria:
The output must
remain stable.
Copyright © 2016, Texas Instruments Incorporated
VO
OUT
IN
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
CC
See Note A
CL
VI
0 V
tfs
fs high
VO
VI2.7 V
50%
VCC VCC
VOL
VOH
Isolation Barrier
fs low
Copyright © 2016, Texas Instruments Incorporated
18
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
Parameter Measurement Information (continued)
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Default Output Delay Time Test Circuit and Voltage Waveforms
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Common-Mode Transient Immunity Test Circuit
TX IN
RX OUT
Carrier signal through
isolation barrier
TX IN
Oscillator
OOK
Modulation
Transmitter
Emissions
Reduction
Techniques
TX Signal
Conditioning Envelope
Detection
RX Signal
Conditioning
Receiver
EN
RX OUT
SiO2 based
Capacitive
Isolation
Barrier
Copyright © 2016, Texas Instruments Incorporated
19
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The ISO7842 device uses an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a
silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. If the EN pin is low
then the output goes to high impedance. The ISO7842 device also incorporates advanced circuit techniques to
maximize the CMTI performance and minimize the radiated emissions because of the high-frequency carrier and
IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 15, shows a functional
block diagram of a typical channel.
8.2 Functional Block Diagram
Figure 15. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 16 shows a conceptual detail of how the ON-OFF keying scheme works.
Figure 16. On-Off Keying (OOK) Based Modulation Scheme
20
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
(1) See for detailed isolation ratings.
8.3 Feature Description
Table 1 lists the device features.
Table 1. Device Features
PART NUMBER CHANNEL DIRECTION RATED ISOLATION MAXIMUM DATA RATE DEFAULT OUTPUT
ISO7842 2 Forward, 5700 VRMS / 8000 VPK (1) 100 Mbps High
2 Reverse
ISO7842F 2 Forward, 5700 VRMS / 8000 VPK (1) 100 Mbps Low
2 Reverse
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7842
device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
Input (Device Without Suffix F)
Output Enable
OUTx
VCCO
~20 W
INx
1.5 MW
985 W
Input (Device With Suffix F)
VCCI VCCI
VCCI
INx
1.5 MW
985 W
VCCI VCCI
VCCI VCCI
Enx
2 MW
1970 W
VCCO VCCO
VCCO VCCO
Copyright © 2016, Texas Instruments Incorporated
21
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC 2.25 V); PD = Powered down (VCC 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
(2) A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4 Device Functional Modes
Table 2 lists the ISO7842 functional modes.
Table 2. Function Table(1)
VCCI VCCO INPUT
(INx)(2)
OUTPUT
ENABLE
(ENx)
OUTPUT
(OUTx) COMMENTS
PU PU
H H or open H Normal Operation:
A channel output assumes the logic state of its input.
L H or open L
Open H or open Default Default mode: When INx is open, the corresponding channel output goes to
its default logic state. Default= High for ISO7842 and Low for ISO7842F.
X PU X L Z A low value of Output Enable causes the outputs to be high-impedance
PD PU X H or open Default
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. Default= High for IISO7842 and
Low for ISO7842F.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
X PD X X Undetermined When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
8.4.1 Device I/O Schematics
Figure 17. Device I/O Schematics
VCC1 VCC2
GND1 GND2
16
14
12
2, 8 9, 15
P3.1
P3.0
UCA0TXD
UCA0RXD
11
15
16
12
4
XOUT
XIN
5
6
2
MSP430F2132
INA
OUTD
1
3
5
4
6
ISO7842
DVss
DVcc
0.1 F
0.1 F 0.1 F
EN1 EN2
7 10
INB 13
11
OUTB
INC
IND
16
0.1 F
OUTC
Vcc
GND
15
T1IN
9
11
12
10
C2±
3
R1OUT
T2IN
14
13
5
7
8
VS±6
4
2
1
R2OUT
VS+
C1+
C1±
C2+
TRS232
4.7 k4.7 k
R1IN
T1OUT
R2IN
T2OUT
1 F 1 F
1 F 1 F
TxD
RxD
RST
CST
ISOGND
10 F0.1 F
MBR0520L
MBR0520L
1:2.1
0.1 F
3
1
D2
SN6501
D1
Vcc
4, 5
2
GND
3.3 V
IN
ONGND
OU
T
1 5
43 LP2985-50 3.3 F
10F
Isolation
Barrier
VIN
5 VISO
2
BP
10 nF
OUTA
Copyright © 2016, Texas Instruments Incorporated
22
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7842 device is a high-performance, quad-channel digital isolator with a 5.7-kVRMS isolation voltage per
UL 1577. The device comes with enable pins on each side that can be used to put the respective outputs in high
impedance for multi-master driving applications and reduce power consumption. The ISO7842 device uses
single-ended CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both
supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because of the single-ended
design structure, digital isolators do not conform to any specific interface standard and are only intended for
isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data
controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
Figure 18 shows the typical isolated RS-232 interface implementation.
Figure 18. Isolated RS-232 Interface
1
2
3
4
5
6
7
8
16
14
13
12
11
10
9
INB OUTC
VCC2
VCC1
0.1 µF 0.1 µF
Copyright © 2016, Texas Instruments Incorporated
INA OUTB
OUTD IND
OUTC INC
VCC1
GND1
INA
INB
OUTC
OUTD
EN1
GND1
VCC2
GND2
OUTA
OUTB
INC
IND
EN2
GND2
GND1 GND2
GND1 GND2
EN EN
ISO7842
23
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 3.
Table 3. Design Parameters
PARAMETER VALUE
Supply voltage 2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1 0.1 µF
Decoupling capacitor from VCC2 and GND2 0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7842 device only requires two external bypass capacitors to operate.
Figure 19. Typical ISO7842 Circuit Hook-Up
9.2.3 Application Curve
The typical eye diagram of the ISO7842 device indicates low jitter and wide open eye at the maximum data rate
of 100 Mbps.
Figure 20. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C
24
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas InstrumentsSN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 Transformer Driver for Isolated Power Supplies.
10 mils
10 mils
40 mils FR-4
0r ~ 4.5
Keep this
space free
from planes,
traces, pads,
and vias
Ground plane
Power plane
Low-speed traces
High-speed traces
25
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 21). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
Figure 21. Layout Example Schematic
26
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Digital Isolator Design Guide
Isolation Glossary
LP2985 150-mA Low-noise Low-dropout Regulator With Shutdown
MSP430G2x32, MSP430G2x02 Mixed Signal Microcontroller
SN6501 Transformer Driver for Isolated Power Supplies
TRS232 Dual RS-232 Driver/Receiver With IEC61000-4-2 Protection
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
ISO7842 Click here Click here Click here Click here Click here
ISO7842F Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
27
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8
0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
B
NOTE 4
7.6
7.4
4221009/B 07/2016
SOIC - 2.65 mm max height
DW0016B
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
TYPICAL
DETAIL A
SCALE 1.500
28
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
www.ti.com
EXAMPLE BOARD LAYOUT
(9.75)
R0.05 TYP
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (1.65)
16X (0.6)
14X (1.27)
16X (2)
16X (0.6)
4221009/B 07/2016
SYMM
SOIC - 2.65 mm max height
DW0016B
SOIC
SYMM
SEE
DETAILS
1
89
16
SYMM
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
SCALE:4X
LAND PATTERN EXAMPLE
SYMM
1
89
16
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SEE
DETAILS
29
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
R0.05 TYP
16X (1.65)
16X (0.6)
14X (1.27)
(9.75)
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4221009/B 07/2016
SOIC - 2.65 mm max height
DW0016B
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
89
16
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
BASED ON 0.125 mm THICK STENCIL
SOLDER PASTE EXAMPLE
SCALE:4X
SYMM
SYMM
1
89
16
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
30
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
www.ti.com
PACKAGE OUTLINE
C
0 -8
17.4
17.1
14X 1.27
16X 0.51
0.31 (2.286)
2.65 MAX
2X
8.89
0.3
0.1
TYP
0.28
0.22
(1.625)
A
NOTE 3
10.4
10.2
B
NOTE 4
14.1
13.9
0.25
GAGE PLANE
1.1
0.6
SOIC - 2.65 mm max heightDWW0016A
PLASTIC SMALL OUTLINE
4221501/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0,15 mm per side.
4. This dimension does not include interlead flash.
PIN 1 ID AREA
1
8
0.25 A B C
9
16
0.1 C
SEATING PLANE
SEE DETAIL A
TYPICAL
DETAIL A
SCALE 1.000
31
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
www.ti.com
EXAMPLE BOARD LAYOUT
14X
(1.27)
(16.25)
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
16X (0.6)
16X (2) (14.25) (14.5)16X (1.875)
16X (0.6)
(16.375)
14X
(1.27)
SOIC - 2.65 mm max heightDWW0016A
PLASTIC SMALL OUTLINE
4221501/A 11/2014
SYMM
SYMM
LAND PATTERN EXAMPLE
STANDARD
SCALE:3X
1
89
16
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
OPENING
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
SOLDER MASK
METAL UNDER SOLDER MASK
OPENING
SOLDER MASK
DEFINED
PCB CLEARANCE & CREEPAGE OPTIMIZED
LAND PATTERN EXAMPLE
SCALE:3X
SYMM
SYMM
1
89
16
32
ISO7842
,
ISO7842F
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
www.ti.com
Product Folder Links: ISO7842 ISO7842F
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
www.ti.com
EXAMPLE STENCIL DESIGN
(16.25)
14X (1.27)
16X (2)
16X (0.6)
16X (1.875)
16X (0.6)
14X (1.27)
(16.375)
SOIC - 2.65 mm max heightDWW0016A
PLASTIC SMALL OUTLINE
4221501/A 11/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
STANDARD
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
SYMM
SYMM
1
89
16
PCB CLEARANCE & CREEPAGE OPTIMIZED
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
SYMM
SYMM
1
89
16
33
ISO7842
,
ISO7842F
www.ti.com
SLLSEJ0G OCTOBER 2014REVISED MARCH 2017
Product Folder Links: ISO7842 ISO7842F
Submit Documentation FeedbackCopyright © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 27-Feb-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ISO7842DW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7842
ISO7842DWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7842
ISO7842DWW ACTIVE SOIC DWW 16 45 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7842
ISO7842DWWR ACTIVE SOIC DWW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7842
ISO7842FDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7842F
ISO7842FDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7842F
ISO7842FDWW ACTIVE SOIC DWW 16 45 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7842F
ISO7842FDWWR ACTIVE SOIC DWW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7842F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Feb-2017
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO7842DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7842DWWR SOIC DWW 16 1000 330.0 24.4 18.0 10.0 3.0 20.0 24.0 Q1
ISO7842FDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7842FDWWR SOIC DWW 16 1000 330.0 24.4 18.0 10.0 3.0 20.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7842DWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7842DWWR SOIC DWW 16 1000 367.0 367.0 45.0
ISO7842FDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7842FDWWR SOIC DWW 16 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
ISO7842DWR ISO7842DW ISO7842FDWR ISO7842FDW ISO7842DWW ISO7842FDWW ISO7842DWWR
ISO7842FDWWR