LP5990 www.ti.com SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 LP5990 Micropower 200mA CMOS Low Dropout Voltage Regulator Check for Samples: LP5990 FEATURES DESCRIPTION * * * The LP5990 regulator is designed to meet the requirements of portable, battery-powered systems providing an accurate output voltage, low noise and low quiescent current. 1 2 * * * * * * * * * * Operation from 2.2V to 5.5V Input 1% Accuracy Over Temp Range Output Voltage from 0.8V to 3.6V in 50mV Increments 30 A Quiescent Current (Enabled) 10nA Quiescent Current (Disabled) 160mV Dropout at 200mA Load 60 VRMSOutput Voltage Noise 60 s Start-Up Time 500s Shut-Down Time PSRR 55 dB at 10 kHz Stable with 0402 1.0F Ceramic Capacitors Logic Controlled Enable Thermal-Overload and Short-Circuit Protection The LP5990 will provide a 1.8V output from a low input voltage of 2.2V and can provide 200mA to an external load. When switched into shutdown mode via a logic signal at the enable pin, the power consumption is reduced to virtually zero. Fast shut-down is achieved by the push pull architecture. The LP5990 is designed to be stable with space saving 0402 ceramic capacitors as small as 1F, this gives an overall solution size of < 2.5mm 2. Performance is specified for a -40C to 125C junction temperature range. APPLICATIONS * * Cellular Phones Hand-Held Information Appliances The device is available in DSBGA Package (0.4mm pitch) and is available with 1.2V,1.3V,1.8V,2.8V,3.0V,3.3V and 3.6V outputs. Lower voltage options down to 0.8V are available on request. For all other output voltage options please contact your local TI sales office. PACKAGE * 4-Bump DSBGA, 0.4 mm Pitch 866 m x 917 m (Lead Free) TYPICAL APPLICATION CIRCUIT VIN VIN 1.0 F CIN VOUT VOUT LP5990 1.0 F COUT VEN VEN Capacitor Case Size = 0402 GND GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007, Texas Instruments Incorporated LP5990 SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 www.ti.com CONNECTION DIAGRAMS Figure 1. 4-Bump Thin DSBGA Package, 0.4mm pitch Package Number YFQ0004CEA VIN VEN VEN VIN B2 A2 A2 B2 B1 A1 GND A1 GND VOUT VOUT Bottom View B1 Top View The actual physical placement of the package marking will vary from part to part. PIN DESCRIPTIONS Pin No. Symbol Name and Function DSBGA VEN Enable input; disables the regulator when 0.35V. Enables the regulator when 1.0V. A1 GND Common ground. B1 VOUT Output voltage. A 1.0 F Low ESR capacitor should be connected to this Pin. Connect this output to the load circuit. B2 VIN A2 Input voltage supply. A 1.0 F capacitor should be connected at this input. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) VIN Pin: Input Voltage -0.3 to 6.0V VOUT Pin: Output Voltage -0.3 to (VIN + 0.3V) to 6.0V (max) VEN Pin: Enable Input Voltage Continuous Power Dissipation -0.3 to 6.0V (max) (4) Internally Limited Junction Temperature (TJMAX) 150C Storage Temperature Range -65 to 150C Maximum Lead Temperature (Soldering, 10 sec.) ESD Rating (5) 260C Human Body Model Machine Model (1) (2) (3) (4) (5) 2 2 kV 200V Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Internal thermal shutdown circuitry protects the device from permanent damage. The Human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 LP5990 www.ti.com SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 OPERATING RATINGS (1) (2) , VIN: Input Voltage Range 2.2V to 5.5V VEN: Enable Voltage Range Recommended Load Current 0 to 5.5V (max) (3) 0 to 200 mA Junction Temperature Range (TJ) Ambient Temperature Range (TA) (1) -40C to +125C (3) -40C to +85C Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (JA), as given by the following equation: TA-MAX = TJ-MAX-OP - (JA x PD-MAX). See applications section. (2) (3) THERMAL PROPERTIES Junction to Ambient Thermal Resistance JA (1) JEDEC Board (DSBGA) (2) 100.6C/W 4L Cellphone Board (DSBGA) (1) 174.8C/W Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Detailed description of the board can be found in JESD51-7 (2) ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TA = 25C. Limits in boldface type apply over the full operating junction temperature range (-40C TJ +125C). Unless otherwise noted, specifications apply to the LP5990 Typical Application Circuit (pg. 1) with: VIN = VOUT (NOM) + 1.0V, or 2.2V, whichever is higher. VEN = 1.0V, CIN = COUT = 1.0 F, IOUT = 1.0 mA. (1), (2) Symbol Parameter Conditions Min Typ VIN Input Voltage VOUT Output Voltage Tolerance VIN = (VOUT(NOM) + 1.0V) to 5.5V Line Regulation VIN = (VOUT(NOM) + 1.0V) to 5.5V, IOUT = 1 mA 1 Load Regulation IOUT = 1 mA to 200 mA 5 ILOAD Load Current See (3) Quiescent Current V -1 1 % VEN = 1.0V, IOUT = 0 mA 0.01 Dropout Voltage (5) IOUT = 200 mA 160 ISC Short Circuit Current Limit See (6) 600 Output Noise Voltage TSHUTDOWN (7) Thermal Shutdown mV (7) 75 35 VEN = <0.35V (Disabled) VDO Power Supply Rejection Ratio 15 mA 30 VEN = 1.0V, IOUT = 200 mA en mV 200 (4) PSRR Units 5.5 0 Maximum Output Current IQ Max 2.2 A 250 mV mA f = 10 kHz, IOUT = 200 mA 55 dB BW = 10 Hz to 100 kHz, VIN = 4.2V, IOUT = 1 mA V OUT = 1.8V 60 VRMS V OUT = 2.8V 85 Temperature 160 Hysteresis 20 C Enable Input Thresholds VIL (1) (2) (3) (4) (5) (6) (7) Low Input Threshold (VEN) VIN = 2.2V to 5.5V 0.35 V All voltages are with respect to the potential at the GND pin. Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not specified, but do represent the most likely norm. The device maintains a stable, regulated output voltage without a load current. Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. This parameter only applies to output voltages above 2.8V. Short Circuit Current is measured with VOUT pulled to 0V. This specification is ensured by design. Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 3 LP5990 SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limits in standard typeface are for TA = 25C. Limits in boldface type apply over the full operating junction temperature range (-40C TJ +125C). Unless otherwise noted, specifications apply to the LP5990 Typical Application Circuit (pg. 1) with: VIN = VOUT (NOM) + 1.0V, or 2.2V, whichever is higher. VEN = 1.0V, CIN = COUT = 1.0 F, IOUT = 1.0 mA. (1), (2) Symbol Parameter Conditions VIH High Input Threshold (VEN) IEN Input Current at VEN Pin (8) Min Typ Max VEN = 5.5V and VIN = 5.5V 2 5 VEN = 0.0V and VIN = 5.5V 0.001 VIN = 2.2V to 5.5V 1.0 Units V A Transient Characteristics VOUT Line Transient Load Transient (7) (7) Trise = Tfall = 30s. VIN = 600 mV 4 IOUT = 1 mA to 200 mA in 1 s -50 IOUT = 200 mA to 1 mA in 1 s 50 mV mV TON Turn on Time To 98% of VOUT(NOM) 60 s TOFF Turn off Time from Enable 100mV of V OUT(NOM)I OUT= 0mA 500 s (8) There is a 3 M resistor between VEN and ground on the device. OUTPUT & INPUT CAPACITOR, RECOMMENDED SPECIFICATIONS (1) Symbol Parameter CIN Input Capacitance COUT Output Capacitance ESR Output/Input Capacitance (1) 4 Conditions Min Nom Capacitance for stability 0.3 1.0 0.3 1.0 5 Max Units F 10 500 m The minimum capacitance should be greater than 0.3 F over the full range of operating conditions. The capacitor tolerance should be 30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions. Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 LP5990 www.ti.com SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified,CIN = COUT = 1.0F, VIN = VOUT(NOM) + 1.0V, VEN = 1.0V, IOUT = 1mA , T A = 25C. Output Voltage Change vs Temperature Ground Current vs Load Current Figure 2. Figure 3. Ground Current vs V IN.I LOAD= 1mA Ground Current vs VIN. I LOAD = 200mA Figure 4. Figure 5. Dropout Voltage Load Transient Response VOUT = 2.8V Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 5 LP5990 SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified,CIN = COUT = 1.0F, VIN = VOUT(NOM) + 1.0V, VEN = 1.0V, IOUT = 1mA , T A = 25C. 6 Load Transient Response. VOUT = 2.8V Short Circuit Current Figure 8. Figure 9. Line Transient Response Line Transient Response Figure 10. Figure 11. Start-up Time Shutdown Characteristics Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 LP5990 www.ti.com SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified,CIN = COUT = 1.0F, VIN = VOUT(NOM) + 1.0V, VEN = 1.0V, IOUT = 1mA , T A = 25C. Power Supply Rejection ratio Output Noise Density Figure 14. Figure 15. Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 7 LP5990 SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 www.ti.com APPLICATION HINTS POWER DISSIPATION AND DEVICE OPERATION The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. As stated in Note 3 of the Operating Ratings table, the allowable power dissipation for the device in a given package can be calculated using the equation: (TJMAX - TA) PD = TJA The actual power dissipation across the device can be represented by the following equation: PD = (VIN - VOUT) x IOUT This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. EXTERNAL CAPACITORS Like any low-dropout regulator, the LP5990 requires external capacitors for regulator stability. The LP5990 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitor is required for stability. The input capacitor should be at least equal to or greater than the output capacitor. It is recommended that a 1.0 F capacitor be connected between the LP5990 input pin and ground. This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: To ensure stable operation it is essential that good PCB practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to connect the battery or other power source to the LP5990, then it is recommended to increase the input capacitor to at least 2.2F. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain 0.3 F over the entire operating temperature range. OUTPUT CAPACITOR The LP5990 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types X5R or X7R) 1.0 F, and with ESR between 5 m to 500 m, is suitable in the LP5990 application circuit. Other ceramic capacitors such as Y5V and Z5U are less suitable owing to their inferior temperature characteristics. (See section in Capacitor Characteristics). For this device the output capacitor should be connected between the VOUT pin and a good ground connection and should be mounted within 1 cm of the device. It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see the section Capacitor Characteristics). The output capacitor must meet the requirement for the minimum value of capacitance (0.3F) and have an ESR value that is within the range 5 m to 500 m for stability. 8 Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 LP5990 www.ti.com SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 CAPACITOR CHARACTERISTICS The LP5990 is designed to work with ceramic capacitors on the input and output to take advantage of the benefits they offer. For capacitance values in the range of 1.0 F to 4.7 F, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1.0 F ceramic capacitor is in the range of 20 m to 40 m, which easily meets the ESR requirement for stability for the LP5990 For both input and output capacitors careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly depending on the conditions of operation and capacitor type. In particular the output capacitor selection should take account of all the capacitor parameters to ensure that the specification is met within the application.Capacitance value can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on particular case size with smaller sizes giving poorer performance figures in general. As an example Figure 16 shows a typical graph showing a comparison of capacitor case sizes in a Capacitance versus DC Bias plot. As shown in the graph, as a result of the DC Bias condition, the capacitance value may drop below the minimum capacitance value given in the recommended capacitor table (0.3F in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommend that the capacitor manufacturer's specifications for the nominal value capacitor are consulted for all conditions as some capacitors may not be suited in the application. The temperature performance of ceramic capacitors varies by type and manufacturer. Most large value ceramic capacitors (2.2 F) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25C to 85C. A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable and holds the capacitance within 15% over the temperature range. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47 F to 4.7 F range. CAP VALUE (% OF NOM. 1 F) Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% _0 1.0 3.0 _ DC Bias (V) 2.0_ 4.0 _ 5.0 _ Figure 16. NO-LOAD STABILITY The LP5990 will remain stable and in regulation with no external load. Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 9 LP5990 SNVS438B - APRIL 2007 - REVISED DECEMBER 2007 www.ti.com ENABLE CONTROL The LP5990 may be switched ON or OFF by a logic input at the ENABLE pin, VEN . A high voltage at this pin will turn the device on. When the enable pin is low, the regulator output is off and the device typically consumes 3 nA. If the application does not require the shutdown feature, the VEN pin should be tied to VIN to keep the regulator output permanently on. The signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. DSBGA MOUNTING The DSBGA package requires specific mounting techniques, which are detailed in TI Application Note AN-1112 (SNVA009). For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device. DSBGA LIGHT SENSITIVITY Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with wavelengths in the red and infra-red part of the spectrum have the most detrimental effect thus the fluorescent lighting used inside most buildings has very little effect on performance. 10 Submit Documentation Feedback Copyright (c) 2007, Texas Instruments Incorporated Product Folder Links: LP5990 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) (3) (4) LP5990TM-1.2/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TM-1.3/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TM-1.8/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TM-2.8/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TM-3.0/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TM-3.3/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TM-3.6/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TMX-1.2/NOPB ACTIVE DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TMX-1.3/NOPB ACTIVE DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TMX-1.8/NOPB ACTIVE DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TMX-2.8/NOPB ACTIVE DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TMX-3.0/NOPB ACTIVE DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TMX-3.3/NOPB ACTIVE DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5990TMX-3.6/NOPB ACTIVE DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Top-Side Markings Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LP5990TM-1.2/NOPB DSBGA YFQ 4 250 178.0 8.4 LP5990TM-1.3/NOPB DSBGA YFQ 4 250 178.0 LP5990TM-1.8/NOPB DSBGA YFQ 4 250 178.0 LP5990TM-2.8/NOPB DSBGA YFQ 4 250 LP5990TM-3.0/NOPB DSBGA YFQ 4 LP5990TM-3.3/NOPB DSBGA YFQ LP5990TM-3.6/NOPB DSBGA YFQ LP5990TMX-1.2/NOPB DSBGA LP5990TMX-1.3/NOPB LP5990TMX-1.8/NOPB 0.92 0.99 0.7 4.0 8.0 Q1 8.4 0.92 0.99 0.7 4.0 8.0 Q1 8.4 0.92 0.99 0.7 4.0 8.0 Q1 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 250 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 4 250 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 4 250 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 LP5990TMX-2.8/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 LP5990TMX-3.0/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 LP5990TMX-3.3/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 LP5990TMX-3.6/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.92 0.99 0.7 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP5990TM-1.2/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5990TM-1.3/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5990TM-1.8/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5990TM-2.8/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5990TM-3.0/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5990TM-3.3/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5990TM-3.6/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5990TMX-1.2/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5990TMX-1.3/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5990TMX-1.8/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5990TMX-2.8/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5990TMX-3.0/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5990TMX-3.3/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5990TMX-3.6/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFQ0004xxx D 0.6000.075 E TMD04XXX (Rev A) D: Max = 0.936 mm, Min =0.876 mm E: Max = 0.902 mm, Min =0.842 mm 4215073/A NOTES: A. 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