ERJ-3RBD6802V - PANASONIC - Datasheet.Support

MCP4706/4716/4726

Features:

• Output Voltage Resolutio ns:

- 12-bit: MCP4726

- 10-bit: MCP4716

-8-bit: MCP4706

• Rail-to-Rail Output

• Fast Settling Time of 6 µs (typical)

• DAC Voltage Reference Options:

-V

REF Pin

• Outp ut Ga in Options:

- Unity (1x)

- 2x, only when VREF pin is used as voltage

source

• Nonvolatile Memory (EEPROM):

- Auto Recall of S aved DAC register setting

- Auto Recall of Saved Device Con figuration

(Voltage Refer enc e, Gain, Pow er-Do w n)

• Power-Down modes:

- Disconnec t s outp ut buffer

- Selection of VOUT pull-down resistors

(640 kΩ, 125 kΩ, or 1 kΩ)

• Low-Power Consumption:

- Normal Operation: 210 µA typical

- Powe r-Down Operation : 60 nA typical

(PD1:PD0 = 11)

• Single-Supply Operation: 2.7V to 5.5V

•I

2C™ Interface:

- Eight Available Addresses

- Standard (100 kbps), Fast (400 kbps), and

High-Speed (3.4 Mbp s ) modes

• Small 6-l ead SOT-23 and DFN (2x2) Packages

• Extended Temperature Range: -40°C to +125°C

Applications:

• Set Point or Offset Trimming

• Sensor Calibra tion

• Low-Power Portable Instrumentation

• PC Peripherals

• Data Acquisition Systems

• Mo tor Control

Package Types

Description:

The MCP4706/4716/4726 are single channel 8-bit,

10-bit, and 12-bit buffered voltage output Digital-to-

Analog Co nverters (D AC) with no nvolatile memory an d

an I2C serial interface. This family will also be referred

to as MCP47X6.

The VREF pin or the device V DD can be se lected as the

DAC’ s reference v oltage. Wh en VDD is selecte d, VDD is

connected internally to the DAC reference circuit.

When the VREF pin is used, the user can select the

output buffer ’s gain to 1 or 2. When the gain is 2, the

VREF pin voltage should be limited to a maximum of

VDD/2.

The DAC register value and Configuration bits can be

programmed to nonvolatile memory (EEPROM). The

nonvolatile memory holds the DAC register and

Configuration bit values when the device is powered

off. A d evice Reset (such a s a Power-on Reset) l atches

these stored values into the volatile memory.

Power-Down modes enable system current reduction

when t he DAC output voltage i s not require d. The VOUT

pin can be configure d to present a low , medium , or high

resistance load.

These de vice s h ave a tw o-wire I2C™ compatible serial

interface for standard (100 kHz), fast (400 kHz), or

High-Speed (3.4 MHz) mode.

These de vice s a re avai lable i n sma ll 6-pi n SOT-23 and

DFN 2x2 mm packages.

OUT

SCL

SDA

SOT-23-6

MCP4706/16/26

2x2 DFN-6*

SCL

SDA

OUT

* Includes Exposed Thermal Pad (EP); see Table 3-1.

REF

8-/10-/12-Bit Voltage Output Digital-to-Analog Converter

with EEPROM and I2C™ Interface

MCP4706/4716/4726

Block Diagram

VDD

VSS

SCL

SDA

VOUT

DAC

EEPROM

PD1:PD0

Amp

I2C™ Interface Logic

VRL

1kΩ

125 kΩ

640 kΩ

VDD

Buffer

Gain (1x or 2x)

(G = 0 or 1)

Resistor Ladder Reference

VREF1:VREF0

Selection

Control

Logic

VREF

PD1:PD0

MCP4706/4716/4726

1.0 ELECTRICAL CHARAC TERISTICS

Absolute Maximum Ratings †

Voltage on VDD with respect to VSS .......................................................................................................... -0.6V to +6.5V

Voltage on all pins with respect to VSS ..............................................................................................-0.3V to VDD + 0.3V

Input clamp current, IIK (VI < 0, VI > VDD) ............................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ..................................................................................................±20 mA

Maximum input current source/sunk by SDA, SCL pins ..........................................................................................2 mA

Maximum output current sunk by SDA Output pin .................................................................................................25 mA

Maximum current out o f V SS pin .............................................................................................................................50 mA

Maximum current into VDD pin................................................................................................................................50 mA

Maximum current sourced by t he VOUT pin ................... ..... ...... ...... ..... ...................................................................40 mA

Maximum current sunk by the VOUT pin..................................................................................................................40 mA

Maximum current sunk by the VREF pin........ ...................... ......................................................................... ............40 µA

Package power dissipation (TA = +50°C, TJ = +150°C)

SOT-23-6...................................................................................................................................................452 mW

DFN-6......................................................................................................................................................1098 mW

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ...............................................................................................-55°C to +125°C

ESD protection on all pins............................................................................................................................≥ 6 kV (HBM)

......................................................................................................................................................................≥ 400V (MM)

Maximum Junction Temperature (TJ) ...................................................................................................................+150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stres s ratin g only and fu nctio nal ope ration o f the d evice at th ose or an y other condit ion s above tho se ind icated in

the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-

ods may affect device reliability.

MCP4706/4716/4726

ELECTR ICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from V OUT to GND, CL = 100 pF,

TA= -40°C to +125°C. Typical values at +25°C.

Parameters Symbol Min Typical Max Units Conditions

Power Requireme nts

Input Voltage VDD 2.7 — 5.5 V

Input Current IDD — 210 400 µA VREF1:VREF0 = 00,

SCL = SDA = VSS, VOUT is unloaded,

volatile DAC Register = 0x000

— 210 400 µA VREF1:VREF0 = 11, VREF = VDD,

SCL = SDA = VSS, VOUT is unloaded,

volatile DAC Register = 0x000

Power-Down Current IDDP — 0.09 2 µA PD1:PD0 = 01 (Note 6),

VOUT not connected

Power-On Reset

Threshold VPOR — 2.2 — V RAM retention voltage, (VRAM) < VPOR

Power-Up Ramp Rate VRAMP 1——V/S(Note 1, Note 4)

DC Accuracy

Offset Err or VOS ±0.02 0.75 % of FSR Code = 0x000h

VREF1:VREF0 = 00, G = 0

Offset Error

Temperature Coefficient VOS/°C — ±1 — ppm/°C -40°C to +25°C

— ±2 — ppm/°C +25°C to +85°C

Zero-Scale Error EZS —0.132.0 LSbMCP4706, Code = 0x00h

—0.52 7.7 LSb MCP4716, Code = 0x000h

—2.05 30.8 LSb MCP4726, Code = 0x000h

Full-Scale Error EFS —0.35.2LSbMCP4706, Code = 0xFFh

—1.1 20.5 LSb MCP4716, Code = 0x3FFh

—4.1 82.0 LSb MCP4726, Code = 0xFFFh

Gain Error

(Note 2) gE-2 -0.10 2 % of FSR MCP4706, Code = 0xFFh

VREF1:VREF0 = 00, G = 0

-2 -0.10 2% of FSR MCP4716, Code = 0x3FFh

VREF1:VREF0 = 00, G = 0

-2 -0.10 2% of FSR MCP4726, Code = 0xFFFh

VREF1:VREF0 = 00, G = 0

Gain Error Drift ΔG/°C — -3 — ppm/°C

Resolution n 8 bits MCP4706

10 bits MCP4716

12 bits MCP4726

INL Error

(Note 7) INL -0.907 ±0.125 +0.907 LSb MCP4706 (codes: 6 to 250)

-3.625 ±0.5 +3.625 LSb MCP4716 (codes: 25 to 1000)

-14.5 ±2 +14.5 LSb MCP4726 (codes: 100 to 4000)

DNL Error

(Note 7) DNL -0.05 ±0.0125 +0.05 LSb MCP4706 (codes: 6 to 250)

-0.188 ±0.05 +0.188 LSb MCP4716 (codes: 25 to 1000)

-0.75 ±0.2 +0.75 LSb MCP4726 (codes: 100 to 4000)

Note 1: This parameter is ensured by design and is not 100% tested.

2: This Gain error does not include Offset error . See Section 1.0 “Electrical Characteristics ” for more details in plots.

3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).

4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD

over time.

5: This parameter is ensured by characterization, and not 100% tested.

6: The PD1:PD0 = 10, and ‘11’ configurations should have the same current.

7: VDD = VREF = 5.5V.

MCP4706/4716/4726

Output Amplifier

Minimum Output

Voltage VOUT(MIN) — 0.01 — V Output Amplifier’s minimum drive

Maximum Output

Voltage VOUT(MAX) —V

DD –

0.04 — V Output Amplifier’s maxi mum drive

Phase Margin PM — 66 — Degree

(°) CL = 400 pF, RL = ∞

Slew Rate SR — 0.55 — V/µs

Short Circuit Current ISC 71524mA

Settling Time tSETTLING —6—µsNote 3

Powe r-Do wn Output

Disable Time Delay TPDD — 1 — µs PD1:PD0 = 00 -> 11, ‘10’, or ‘01’

started from falling edge SCL at end of

ACK bit.

VOUT = VOUT - 10 mV. VOUT not

connected.

Powe r-Do wn Output

Enable Time Delay TPDE — 10.5 — µs PD1:PD0 = 11, ‘10’, or ‘01’ -> “00”

started from falling edge SCL at end of

ACK bit.

Vo latile DAC Register = FFh,

VOUT =10mV. V

OUT not connected.

External Reference (VREF) (Note 1)

Input Range VREF 0.04 — VDD -

0.04 V Buffered mode

0—V

DD V Unbuf fe red mode

Input Impedance RVREF — 210 — kΩUnbuffered mo de

Input Capacitance C_REF — 29 — pF Unbuffe red mode

-3 dB Bandwidth — 86.5 — kHz VREF = 2.048V ± 0.1V,

VREF1:VREF0 =10, G = 0

—67.7— kHzV

REF = 2.048V ± 0.1V,

VREF1:VREF0 =10, G = 1

Total Harmonic

Distortion THD — -73 — dB VREF = 2.048V ± 0.1V,

VREF1:VREF0 =10, G = 0,

Frequency = 1 kHz

Dynamic Performance (Note 1)

Major Code Transition

Glitch — 45 — nV-s 1 LSb change around major carry

(800h to 7FFh)

Digital Feedthrough — <10 — nV-s

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from V OUT to GND, CL = 100 pF,

TA= -40°C to +125°C. Typical values at +25°C.

Parameters Symbol Min Typical Max Units Conditions

Note 1: This parameter is ensured by design and is not 100% tested.

2: This Gain error does not include Offset error . See Section 1.0 “Electrical Characteristics ” for more details in plots.

3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).

4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD

over time.

5: This parameter is ensured by characterization, and not 100% tested.

6: The PD1:PD0 = 10, and ‘11’ configurations should have the same current.

7: VDD = VREF = 5.5V.

MCP4706/4716/4726

Digital Interface

Output Low Volta ge VOL ——0.4 V I

OL = 3 m A

Input High Voltage

(SDA and SCL Pins) VIH 0.7VDD —— V

Input Low Voltage

(SDA and SCL Pins) VIL —

—0.3V

DD V

Input Leakage ILI — — ±1 µA SCL = SDA = VSS or

SCL = SDA = VDD

Pin Capacitance CPIN —— 3 pF (Note 5)

EEPROM

EEPROM Write Time TWRITE —2550ms

Data Retention — 200 — Years At +25°C, (Note 1)

Endurance 1 — — Million

Cycles At +25°C, (Note 1)

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from V OUT to GND, CL = 100 pF,

TA= -40°C to +125°C. Typical values at +25°C.

Parameters Symbol Min Typical Max Units Conditions

Note 1: This parameter is ensured by design and is not 100% tested.

2: This Gain error does not include Offset error . See Section 1.0 “Electrical Characteristics ” for more details in plots.

3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).

4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD

over time.

5: This parameter is ensured by characterization, and not 100% tested.

6: The PD1:PD0 = 10, and ‘11’ configurations should have the same current.

7: VDD = VREF = 5.5V.

MCP4706/4716/4726

1.1 I2C Mode T iming Waveforms and Requirement s

FIGURE 1-1: Power-On and Brown-Out Reset Waveforms.

FIGURE 1-2: I2C Power-Down Command Timing.

TABLE 1-1: RESET TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +125°C (extended)

All parameters apply across the specified operating ranges unless noted.

VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for VDD = 5.5V, TA = +25°C.

Parameters Sym Min Typ Max Units Conditions

Power-Up Reset

Delay tPORD — 60 — µs Moni tor ACK bit respon se to ensure device

responds to command.

Brown-Out Reset

Delay tBORD —1—µsV

DD transitions from VDD(MIN) → > VPOR

VOUT driven to VOUT disabled

Power-Down

Disable Time Delay TPDD —2.5— µsV

DD = 5V

PD1:PD0 → 00 (from ‘01’, ‘10’, or ‘11’),

from falling edge SCL at end of ACK bit.

—5—µsV

DD = 3V

PD1:PD0 → 00 (from ‘01’, ‘10’, or ‘11’),

from falling edge SCL at end of ACK bit.

Power-Down Enable

Ti me Delay TPDE — 10.5 — µs PD1:PD0 → 01, ‘10’, or ‘11’ (from ‘00’),

from falling edge SCL at end of ACK bit.

VDD

SDA

tPORD tBORD

VOUT

SCL VIH VIH

VPOR (VBOR)

VOUT pulled down by internal

500 kΩ (typical) resistor

I2C™ Interface is operational

SDA

SCL

ACK Stop Start ACK

VOUT

tPDE t

PDD

MCP4706/4716/4726

FIGURE 1-3: I2C Bus Start/Stop Bits Timing Waveforms.

TABLE 1-2: I2C BUS START/STOP BITS REQUIREMENTS

I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in Electr i cal Ch arac ter is tics

Param.

No. Symbol Characteristic Min Max Units Conditions

FSCL SCL pin Frequency Standard mode 0 100 kHz Cb = 400 pF, 2.7V - 5.5V

Fast mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5V

High-Speed 1.7 0 1.7 MHz Cb = 400 pF, 4.5V - 5.5V

High-Speed 3.4 0 3.4 MHz Cb = 100 pF, 4.5V - 5.5V

D102 CbBus capacitive

loading 100 kHz mode — 400 pF

400 kHz mode — 400 pF

1.7 MHz mode — 400 pF

3.4 MHz mode — 100 pF

90 TSU:STA Start condition 100 kHz mode 4700 — ns Only relevant for repeated

Start condition

Setup time 400 kHz mode 600 — ns

1.7 MHz mode 160 — ns

3.4 MHz mode 160 — ns

91 THD:STA Start condition 100 kHz mode 4000 — ns After this period, the first

clock pulse is generated

Hold tim e 400 kHz mode 600 — ns

1.7 MHz mode 160 — ns

3.4 MHz mode 160 — ns

92 TSU:STO Stop condition 100 kHz mode 4000 — ns

Setup time 400 kHz mode 600 — ns

1.7 MHz mode 160 — ns

3.4 MHz mode 160 — ns

93 THD:STO Stop condition 100 kHz mode 4000 — ns

Hold tim e 400 kHz mode 600 — ns

1.7 MHz mode 160 — ns

3.4 MHz mode 160 — ns

94 THVCSU HVC to SCL Setup time 25 — uS High Voltage Commands

95 THVCHD SCL to HVC Hold time 25 — uS High Voltage Commands

91 93

SCL

SDA

Start

Condition Stop

Condition

90 92

VIH

111

VIL

MCP4706/4716/4726

FIGURE 1-4: I2C Bus Data Ti ming.

90 91 92

100 101

103

106 107

109 109 110

102

SCL

SDA

Out

TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE)

I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in Electric al Ch arac ter ist ics

Param.

No. Sym Characteristic Min Max Units Conditions

100 THIGH Clock high time 100 kHz mode 4000 — ns 2.7V -5.5V

400 kHz mode 600 — ns 2.7V-5.5V

1.7 MHz mo de 120 ns 4.5V-5.5V

3.4 MHz mo de 60 — ns 4.5V-5.5V

101 TLOW Clo ck low time 100 kHz mode 4700 — ns 2.7V-5.5V

400 kHz mode 1300 — ns 2.7V-5.5V

1.7 MHz mo de 320 ns 4.5V-5.5V

3.4 MHz mo de 160 — ns 4.5V-5.5V

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (4 00 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but

the requirement tSU;DAT ≥250 ns must then be met. This will automatically be the case if the device does

not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL

signal, it must output the next data bit to the SDA line.

TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before

the SCL line is released.

3: The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of

the fallin g edge of the SC L signal. Th is specific ation is not a part of the I2C specific ation, but m ust be tested

in order to ensure that the output data will meet the setup and hold specifications for the receiving device.

4: Use Cb in pF for the calculations.

5: Not Tested. This parameter ensured by characterization.

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the

I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time ( TLOW) can be

affected. Data Input: This par ameter must be longer than tSP.

Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.

7: Ensured by the TAA 3.4 M Hz specification test.

8: The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).

MCP4706/4716/4726

102A(5) TRSCL SCL rise time 100 kHz mode — 1000 ns Cb is specified to be from

10 to 400 pF (100 pF

maxi mu m for 3.4 MHz

mode)

400 kHz mode 20 + 0.1Cb 300 ns

1.7 MHz mo de 20 80 ns

1.7 MHz mode 20 160 ns After a Repeated Start

condition or an

Acknowledge bit

3.4 MHz mo de 10 40 ns

3.4 MHz mode 10 80 ns After a Repeated Start

condition or an

Acknowledge bit

102B(5) TRSDA SDA rise time 100 kHz mode — 1000 ns Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mode 20 + 0.1Cb 300 ns

1.7 MHz mo de 20 160 ns

3.4 MHz mo de 10 80 ns

103A(5) TFSCL SCL fall time 100 kHz mode — 300 ns Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mode 20 + 0.1Cb 300 ns

1.7 MHz mo de 20 80 ns

3.4 MHz mo de 10 40 ns

103B(5) TFSDA SDA fall time 100 kHz mode — 300 ns Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mo de 20 + 0.1Cb(4)300 ns

1.7 MHz mo de 20 160 ns

3.4 MHz mo de 10 80 ns

TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in Electr ic al Char ac teri st ics

Param.

No. Sym Characteristic Min Max Units Conditions

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (4 00 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but

the requirement tSU;DAT ≥250 ns must then be met. This will automatically be the case if the device does

not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL

signal, it must output the next data bit to the SDA line.

TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before

the SCL line is released.

3: The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of

the fallin g edge of the SCL signal. This specific ation is not a part of the I2C specific ation, but m ust be tested

in order to ensure that the output data will meet the setup and hold specifications for the receiving device.

4: Use Cb in pF for the calculations.

5: Not Test ed. This parameter ensured by characterization .

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the

I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time ( TLOW) can be

affected. Data Input: This par ameter must be longer than tSP.

Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.

7: Ensured by the TAA 3.4 M Hz specification test.

8: The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).

MCP4706/4716/4726

106 THD:DAT Data input hold

time 100 kHz mode 0 — ns 2.7V-5.5V, Note 6

400 kHz mode 0 — ns 2.7V-5.5V, Note 6

1.7 MHz mo de 0 — ns 4.5V-5.5V, Note 6

3.4 MHz mo de 0 — ns 4.5V-5.5V, Note 6

107 TSU:DAT Data input setup

time 100 kHz mode 250 — ns Note 2

400 kHz mode 100 — ns

1.7 MHz mode 10 — ns

3.4 MHz mode 10 — ns

109 TAA Output valid

from clock 100 kHz mode — 3750 ns Note 1, Note 8

400 kHz mo de — 1200 ns

1.7 MHz mode — 150 ns Cb = 100 pF,

Note 1, Note 7, Note 8

— 310 ns Cb = 400 pF,

Note 1, Note 5, Note 8

3.4 MHz mode — 150 ns Cb = 100 pF,

Note 1, Note 8

110 TBUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free

before a new transmission

can start

400 kHz mo de 13 00 — ns

1.7 MHz mode N/A — ns

3.4 MHz mode N/A — ns

TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in Electric al Ch arac ter ist ics

Param.

No. Sym Characteristic Min Max Units Conditions

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (4 00 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but

the requirement tSU;DAT ≥250 ns must then be met. This will automatically be the case if the device does

not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL

signal, it must output the next data bit to the SDA line.

TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before

the SCL line is released.

3: The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of

the fallin g edge of the SC L signal. Th is specific ation is not a part of the I2C specific ation, but m ust be tested

in order to ensure that the output data will meet the setup and hold specifications for the receiving device.

4: Use Cb in pF for the calculations.

5: Not Tested. This parameter ensured by characterization.

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the

I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time ( TLOW) can be

affected. Data Input: This par ameter must be longer than tSP.

Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.

7: Ensured by the TAA 3.4 M Hz specification test.

8: The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).

MCP4706/4716/4726

111 TSP Input filter spike

suppression

(SDA and SCL)

100 kHz mode — 50 ns NXP Spec states N/A

400 kHz mode — 50 ns

1.7 MHz mode — 10 ns Spike suppression

3.4 MHz mo de — 10 ns Spike suppres si on

TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I2C™ AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in Electr ic al Char ac teri st ics

Param.

No. Sym Characteristic Min Max Units Conditions

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (4 00 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but

the requirement tSU;DAT ≥250 ns must then be met. This will automatically be the case if the device does

not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL

signal, it must output the next data bit to the SDA line.

TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before

the SCL line is released.

3: The MCP47X6 device must provide a data hold time to bridge the undefined part between VIH and VIL of

the fallin g edge of the SCL signal. This specific ation is not a part of the I2C specific ation, but m ust be tested

in order to ensure that the output data will meet the setup and hold specifications for the receiving device.

4: Use Cb in pF for the calculations.

5: Not Test ed. This parameter ensured by characterization .

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the

I2C bus line. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time ( TLOW) can be

affected. Data Input: This par ameter must be longer than tSP.

Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.

7: Ensured by the TAA 3.4 M Hz specification test.

8: The specification is not part of the I2C specification. TAA = THD:DAT + TFSDA (or TRSDA).

MCP4706/4716/4726

TEMPERATURE CHARACTERISTICS

Electrical Sp ecifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.

Parameters Symbol Min Typical Max Units Conditions

Temperature Ranges

Specified Temperature Range TA-40 — +125 °C

Operati ng Tempe r atu re Ra nge TA-40 — +125 °C Note 1

Storage Temperature Range TA-65 — +150 °C

Thermal Package Resistances

Thermal Resistance, 6L-SOT-23 θJA —190—°C/W

Thermal Resistance, 6L-DFN (2 x 2) θJA —91—°C/W

Note 1: The MCP47X6 devices operate over this extended temperature range, but with reduced performance.

Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150°C.

MCP4706/4716/4726

NOTES:

MCP4706/4716/4726

2.0 TYP ICAL PERFORMANCE CURV ES

Note: Unless oth erwise indicate d, TA = +25°C, VDD = 5 V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-1: INL vs. Code (code = 100 to

4000) and Temperature (MCP4726).

VDD = 5V, VREF1:VREF0 = 00.

FIGURE 2-2: INL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 5V, VREF1:VREF0 = 00.

FIGURE 2-3: INL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 5V, VREF1:VREF0 = 00.

FIGURE 2-4: INL vs. Code (code = 100 to

4000) and Temperature (MCP4726).

VDD = 2.7V, VREF1:VREF0 = 00.

FIGURE 2-5: INL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 2.7V, VREF1:VREF0 = 00.

FIGURE 2-6: INL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 2.7V, VREF1:VREF0 = 00.

Note: The gra phs and tab les prov ided fo llow ing this note are a sta tistic al sum mary b ased on a limit ed numb er of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-12

-8

-4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-3

-2

-1

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-12

-8

-4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-3

-2

-1

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-7: DNL vs. Code (code = 100

to 4000) and Tem per atu re (MCP4726).

VDD = 5V, VREF1:VREF0 = 00.

FIGURE 2-8: DNL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 5V, VREF1:VREF0 = 00.

FIGURE 2-9: DNL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 5V, VREF1:VREF0 = 00.

FIGURE 2-10: DNL vs. Code (code = 100

to 4000) and Temperature (MCP4726).

VDD = 2.7V, VREF1:VREF0 = 00.

FIGURE 2-11: DNL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 2.7V, VREF1:VREF0 = 00.

FIGURE 2-12: DNL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 2.7V, VREF1:VREF0 = 00.

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-13: Zero-Scale Error (ZSE) vs.

VDD and Temperature (MCP4726).

VREF1:VREF0 = 00.

FIGURE 2-14: Zero-Scale Error (ZSE) vs.

VDD and Temperature (MCP4716).

VREF1:VREF0 = 00.

FIGURE 2-15: Zero-Scale Error (ZSE) vs.

VDD and Temperature (MCP4706).

VREF1:VREF0 = 00.

FIGURE 2-16: Full-Scale Error (FSE) vs.

VDD and Temperature (MCP4726).

VREF1:VREF0 = 00.

FIGURE 2-17: Full-Scale Error (FSE) vs.

VDD and Temperature (MCP4716).

VREF1:VREF0 = 00.

FIGURE 2-18: Full-Scale Error (FSE) vs.

VDD and Temperature (MCP4706).

VREF1:VREF0 = 00.

0.0

0.5

1.0

1.5

2.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

0.0

0.1

0.2

0.3

0.4

0.5

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

0.00

0.05

0.10

0.15

0.20

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

-32.0

-30.0

-28.0

-26.0

-24.0

-22.0

-20.0

-18.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

-8.0

-7.0

-6.0

-5.0

-4.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

-2.0

-1.5

-1.0

-0.5

0.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-19: INL vs. Code (code = 100 to

4000) and Temperature (MCP4726).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-20: INL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-21: INL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-22: INL vs. Code (code = 100 to

4000) and Temperature (MCP4726).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-23: INL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-24: INL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

-12

-8

-4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-3

-2

-1

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-12

-8

-4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-3

-2

-1

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-25: DNL vs. Code (code = 100

to 4000) and Tem per atu re (MCP4726).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-26: DNL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-27: DNL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-28: DNL vs. Code (code = 100

to 4000) and Temperature (MCP4726).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-29: DNL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-30: DNL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-31: Zero-Scale Error (ZSE) vs.

Temperature (MCP4726).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-32: Zero-Scale Error (ZSE) vs.

Temperature (MCP4716).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-33: Zero-Scale Error (ZSE) vs.

Temperature (MCP4706).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-34: Full-Scale Error (FSE) vs.

Temperature (MCP4726).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-35: Full-Scale Error (FSE) vs.

Temperature (MCP4716).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-36: Full-Scale Error (FSE) vs.

Temperature (MCP4706).

VDD = 2.7V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

0.0

0.5

1.0

1.5

2.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

0.0

0.1

0.2

0.3

0.4

0.5

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

0.00

0.05

0.10

0.15

0.20

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

-32.0

-30.0

-28.0

-26.0

-24.0

-22.0

-20.0

-18.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

-8.0

-7.0

-6.0

-5.0

-4.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

-2.0

-1.5

-1.0

-0.5

0.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-37: INL vs. Code (code = 100 to

4000) and Temperature (MCP4726).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-38: INL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-39: INL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-40: INL vs. Code (code = 100 to

4000) and Temperature (MCP4726).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-41: INL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-42: INL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

-12

-8

-4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-3

-2

-1

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-12

-8

-4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-3

-2

-1

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

INL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-43: DNL vs. Code (code = 100

to 4000) and Tem per atu re (MCP4726).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-44: DNL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-45: DNL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-46: DNL vs. Code (code = 100

to 4000) and Temperature (MCP4726).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-47: DNL vs. Code (code = 25 to

1000) and Temperature (MCP4716).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-48: DNL vs. Code (code = 6 to

250) and Temperature (MCP4706).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 1024 2048 3072 4096

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0 128 256 384 512 640 768 896 1024

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0 32 64 96 128 160 192 224 256

-40C

+25C

+85C

+125C

Volatile DAC Register Code

DNL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-49: Zero-Scale Error (ZSE) vs.

Temperature (MCP4726).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-50: Zero-Scale Error (ZSE) vs.

Temperature (MCP4716).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-51: Zero-Scale Error (ZSE) vs.

Temperature (MCP4706).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-52: Full-Scale Error (FSE) vs.

Temperature (MCP4726).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-53: Full-Scale Error (FSE) vs.

Temperature (MCP4716).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-54: Full-Scale Error (FSE) vs.

Temperature (MCP4706).

VDD = 2.7V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

0.0

0.5

1.0

1.5

2.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

0.0

0.1

0.2

0.3

0.4

0.5

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

0.00

0.05

0.10

0.15

0.20

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Zero Scale Error (LSb)

-32.0

-30.0

-28.0

-26.0

-24.0

-22.0

-20.0

-18.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

-8.0

-7.0

-6.0

-5.0

-4.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

-2.0

-1.5

-1.0

-0.5

0.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Full Scale Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-55: INL vs. Code (code = 100 to

4000) and VDD (2.7V, 5V, 5.5V) (MCP4726).

VREF1:VREF0 = 10, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-56: INL vs. Code (code = 25 to

1000) and VDD (2.7V, 5V, 5.5V) (MCP4716).

VREF1:VREF0 = 10, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-57: INL vs. Code (code = 6 to

250) and VDD (2.7V, 5V, 5.5V) (MCP4706).

VREF1:VREF0 = 10, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-58: DNL vs. Code (code = 100

to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726).

VREF1:VREF0 = 10, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-59: DNL vs. Code (code = 25 to

1000) and VDD (2.7V, 5V, 5.5V) (MCP4716).

VREF1:VREF0 = 10, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-60: DNL vs. Code (code = 6 to

250) and VDD (2.7V, 5V, 5.5V) (MCP4706).

VREF1:VREF0 = 10, G = 1, VREF = VDD/2,

Temp = +25°C.

-8

-4

0 1024 2048 3072 4096

2.7V

5.0V

5.5V

Volatile DAC Register Code

INL Error (LSb)

-3

-2

-1

0 128 256 384 512 640 768 896 1024

2.7V

5.0V

5.5V

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

2.7V

5.0V

5.5V

Volatile DAC Register Code

INL Error (LSb)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 1024 2048 3072 4096

2.7V

5.0V

5.5V

Volatile DAC Register Code

DNL Error (LSb)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 128 256 384 512 640 768 896 1024

2.7V

5.0V

5.5V

Volatile DAC Register Code

DNL Error (LSb)

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0 32 64 96 128 160 192 224 256

2.7V

5.0V

5.5V

Volatile DAC Register Code

DNL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-61: INL vs. Code (code = 100 to

4000) and VDD (2.7V, 5V, 5.5V) (MCP4726).

VREF1:VREF0 = 11, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-62: INL vs. Code (code = 25 to

1000) and VDD (2.7V, 5V, 5.5V) (MCP4716).

VREF1:VREF0 = 11, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-63: INL vs. Code (code = 6 to

250) and VDD (2.7V, 5V, 5.5V) (MCP4706).

VREF1:VREF0 = 11, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-64: DNL vs. Code (code = 100

to 4000) and VDD (2.7V, 5V, 5.5V) (MCP4726).

VREF1:VREF0 = 11, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-65: DNL vs. Code (code = 25 to

1000) and VDD (2.7V, 5V, 5.5V) (MCP4716).

VREF1:VREF0 = 11, G = 1, VREF = VDD/2,

Temp = +25°C.

FIGURE 2-66: DNL vs. Code (code = 6 to

250) and VDD (2.7V, 5V, 5.5V) (MCP4706).

VREF1:VREF0 = 11, G = 1, VREF = VDD/2,

Temp = +25°C.

-8

-4

0 1024 2048 3072 4096

2.7V

5.0V

5.5V

Volatile DAC Register Code

INL Error (LSb)

-3

-2

-1

0 128 256 384 512 640 768 896 1024

2.7V

5.0V

5.5V

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

2.7V

5.0V

5.5V

Volatile DAC Register Code

INL Error (LSb)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 1024 2048 3072 4096

2.7V

5.0V

5.5V

Volatile DAC Register Code

DNL Error (LSb)

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0 128 256 384 512 640 768 896 1024

2.7V

5.0V

5.5V

Volatile DAC Register Code

DNL Error (LSb)

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0 32 64 96 128 160 192 224 256

2.7V

5.0V

5.5V

Volatile DAC Register Code

DNL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-67: INL vs. Code (code = 100 to

4000) and VREF (MCP4726).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Tem p = +25°C.

FIGURE 2-68: INL vs. Code (code = 25 to

1000) and VREF (MCP4716).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Tem p = +25°C.

FIGURE 2-69: INL vs. Code (code = 6 to

250) and VREF (MCP4706).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Tem p = +25°C.

FIGURE 2-70: DNL vs. Code (code = 100

to 4000) and VREF (MCP4726).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.

FIGURE 2-71: DNL vs. Code (code = 25 to

1000) and VREF (MCP4716).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.

FIGURE 2-72: DNL vs. Code (code = 6 to

250) and VREF (MCP4706).

VDD = 5V, VREF1:VREF0 = 10, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.

-8

-4

0 1024 2048 3072 4096

Volatile DAC Register Code

INL Error (LSb)

-2

-1

0 128 256 384 512 640 768 896 1024

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 1024 2048 3072 4096

1V 2V 3V

4V 5V

Volatile DAC Register Code

DNL Error (LSb)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 128 256 384 512 640 768 896 1024

1V 2V 3V

4V 5V

Volatile DAC Register Code

DNL Error (LSb)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 32 64 96 128 160 192 224 256

1V 2V 3V

4V 5V

Volatile DAC Register Code

DNL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-73: INL vs. Code (code = 100 to

4000) and VREF (MCP4726).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Tem p = +25°C.

FIGURE 2-74: INL vs. Code (code = 25 to

1000) and VREF (MCP4716).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Tem p = +25°C.

FIGURE 2-75: INL vs. Code (code = 6 to

250) and VREF (MCP4706).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Tem p = +25°C.

FIGURE 2-76: DNL vs. Code (code = 100

to 4000) and VREF (MCP4726).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.

FIGURE 2-77: DNL vs. Code (code = 25 to

1000) and VREF (MCP4716).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.

FIGURE 2-78: DNL vs. Code (code = 6 to

250) and VREF (MCP4706).

VDD = 5V, VREF1:VREF0 = 11, G = 0,

VREF = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C.

-8

-4

0 1024 2048 3072 4096

Volatile DAC Register Code

INL Error (LSb)

-2

-1

0 128 256 384 512 640 768 896 1024

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 32 64 96 128 160 192 224 256

Volatile DAC Register Code

INL Error (LSb)

-1.0

-0.5

0.0

0.5

1.0

0 1024 2048 3072 4096

1V 2V 3V

4V 5V

Volatile DAC Register Code

DNL Error (LSb)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 128 256 384 512 640 768 896 1024

1V 2V 3V

4V 5V

Volatile DAC Register Code

DNL Error (LSb)

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 32 64 96 128 160 192 224 256

1V 2V 3V

4V 5V

Volatile DAC Register Code

DNL Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25 °C, VDD = 5V, VSS = 0V, VRL = Internal, Gai n = x 1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-79: Output Error vs.

Temperature (MCP4726). VDD = 2.7V and 5V,

VREF1:VREF0 = 00, Code = 4000.

FIGURE 2-80: Output Error vs.

Temperature (MCP4716). VDD = 2.7V and 5V,

VREF1:VREF0 = 00, Code = 1000.

FIGURE 2-81: Output Error vs.

Temperature (MCP4706). VDD = 2.7V and 5V,

VREF1:VREF0 = 00, Code = 250.

FIGURE 2-82: Output Error vs.

Temperature (MCP4726). VDD = 2.7V and 5V,

VREF1:VREF0 = 10, G = 0, VREF = VDD,

Code = 4000.

FIGURE 2-83: Output Error vs.

Temperature (MCP4716). VDD = 2.7V and 5V,

VREF1:VREF0 = 10, G = 0, VREF = VDD,

Code = 1000.

FIGURE 2-84: Output Error vs.

Temperature (MCP4706). VDD = 2.7V and 5V,

VREF1:VREF0 = 10, G = 0, VREF = VDD,

Code = 250.

-36.0

-34.0

-32.0

-30.0

-28.0

-26.0

-24.0

-22.0

-20.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

-8.0

-7.0

-6.0

-5.0

-4.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

-36.0

-34.0

-32.0

-30.0

-28.0

-26.0

-24.0

-22.0

-20.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

-8.0

-7.0

-6.0

-5.0

-4.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25 °C, V DD = 5V, VSS = 0V, VRL = Internal, Gain = x 1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-85: Output Error vs.

Temperature (MCP4726). VDD = 2.7V and 5V,

VREF1:VREF0 = 11, G = 0, VREF = VDD,

Code = 4000.

FIGURE 2-86: Output Error vs.

Temperature (MCP4716). VDD = 2.7V and 5V,

VREF1:VREF0 = 11, G = 0, VREF = VDD,

Code = 1000.

FIGURE 2-87: Output Error vs.

Temperature (MCP4706). VDD = 2.7V and 5V,

VREF1:VREF0 = 11, G = 0, VREF = VDD,

Code = 250.

-36.0

-34.0

-32.0

-30.0

-28.0

-26.0

-24.0

-22.0

-20.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

-8.0

-7.0

-6.0

-5.0

-4.0

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

Output Error (LSb)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-88: IDD vs. Temperature.

VDD = 2.7V and 5V, VREF1:VREF0 = 00.

FIGURE 2-89: IDD vs. Temperature.

VDD = 2.7V and 5V, VREF1:VREF0 = 10, G = 0,

VREF = VDD.

FIGURE 2-90: IDD vs. Temperature.

VDD = 2.7V and 5V, VREF1:VREF0 = 11, G = 0,

VREF = VDD.

FIGURE 2-91: Power-down Current vs.

Temperature.

VDD = 2.7V, 3.3V, 4.5V, 5.0V and 5.5V,

PD1:PD0 = 11.

100

125

150

175

200

225

250

-40 -20 0 20 40 60 80 100 120

2.7V

3.3V

4.5V

5.0V

5.5V

Temperature (°C)

IDD (uA)

100

125

150

175

200

225

250

-40 -20 0 20 40 60 80 100 120

2.7V

3.3V

4.5V

5.0V

5.5V

Temperature (°C)

IDD (uA)

100

125

150

175

200

225

250

-40 -20 0 20 40 60 80 100 120

2.7V

3.3V

4.5V

5.0V

5.5V

Temperature (°C)

IDD (uA)

100

200

300

400

500

-40 -20 0 20 40 60 80 100 120

2.7V

3.3V

4.5V

5.0V

5.5V

Temperature (°C)

IPowerDown (nA)

MCP4706/4716/4726

Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-92: VIH Threshold of SDA/SCL

Inputs vs. Tempe r ature and VDD.

FIGURE 2-93: VIL Threshold of SDA/SCL

Inputs vs. Tempe r ature and VDD.

FIGURE 2-94: VOUT vs. Resistive Load.

VDD = 5.0V.

FIGURE 2-95: VOUT vs. Source/Sink

Current. VDD = 5.0V.

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

VIH (% VDD)

-40 -20 0 20 40 60 80 100 120

2.7V

5.0V

5.5V

Temperature (°C)

VIL (% VDD)

0 1000 2000 3000 4000 5000

Load Resistance (RL) (

)

VOUT (V)

Code = FFFh

03691215

ISOURCE/SINK (mA)

VOUT (V)

Code = FFFh Code = 000h

MCP4706/4716/4726

Note: Unle ss oth erwise i ndica ted, TA = +25°C, VDD = 5V, VSS = 0V, VREF = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.

FIGURE 2-96: Full-Scale Settling Time

(000h to FFFh) (MCP4726).

FIGURE 2-97: Full-Scale Settling Time

(FFFh to 000h) (MCP4726).

FIGURE 2-98: Half-Scale Settling Time

(400h to C00h) (MCP4726).

FIGURE 2-99: Half-Scale Settling Time

(C00h to 400h) (MCP4726).

FIGURE 2-100: Exiting Power-Down Mode

(MCP4726, Volatile DAC Register = FFFh).

MCP4706/4716/4726

3.0 PIN DESCRIPTIONS

An overview of the pin functions are described in

Section 3.1 “Analog Output Voltage Pin (VOUT)”

through Section 3.7 “Exposed Pad (EP)”. The

descriptions of the pins are listed in Table 3-1.

TABLE 3-1: MCP47X6 PINOUT DESCRIPTION

SOT-23 DFN Symbol I/O Buffer

Type Standard Function

6L 6L

16 V

OUT A Analog Buffered analog voltage output pin

25V

SS — P Ground reference pin for all circuitries on the device

34V

DD — P Supply Voltage Pin

4 3 SDA I/O ST I2C™ Serial Data Pin

52 SCL IST

I2C Serial Clock Pin

61V

REF A Analog Voltage Reference Input Pin

— 7 EP — — Exposed Pad (Note 1)

Legend: A = Analog pins I = Digital input (high Z)

O = Digital output I/O = Input / Output

P = Power

Note 1: The DFN package has a c ontact on the bottom of the package. This contact is conductively connected to

the die substrate, and therefore should be unconnected or connected to the same ground as the device’s

VSS pin.

MCP4706/4716/4726

3.1 Analog Output Voltage Pin (VOUT)

VOUT is the DAC analog output pin. The DAC output

has an output amplifier. VOUT can swing from

approximately 0V to approximately VDD. The f u ll -s c a le

range of the DAC output is from VSS to G * VRL, where

G is the gain selection option (1x or 2x).

In Normal m ode, the DC impedance o f the output p in is

about 1Ω. In Power-Down mode, the output pin is

internally connected to a known pull-down resistor of

1kΩ, 125 kΩ, or 640 kΩ. The power-down selection

bits settings are shown in Table 4-2.

3.2 Positive Power Supply Input (VDD)

VDD is the po siti ve sup ply vo ltage i nput pin. T he in put

supply voltage is relative to VSS.

The pow er su pply a t the V DD pin sho uld be as clean a s

possible for a good DAC performance. It is

recommended to use an appropriate bypass capacitor

of about 0.1 µF (ceramic) to ground. An additional

10 µF capacitor (tantalum) in parallel is also

recommended to further attenuate high-frequency

noise present in application boards.

3.3 Ground (VSS)

The VSS pin is the device ground reference.

The user must connect the VSS pin to a ground plane

through a low-impedance connection. If an analog

ground path is available in the application Printed

Circuit Board (PCB), it is highly recommended that the

VSS pin be tied to the analog ground path or isolated

within an analog ground plane of the circuit board.

3.4 Serial Data Pin (SDA)

SDA is the serial data pin of the I2C inte rface. The SDA

pin is us ed to writ e or re ad the DAC regist ers and Con-

figuratio n bits. The SDA pin is an ope n-drain N-channe l

driver. Therefore, it needs a pull-up resistor from the

VDD line to the SDA pin. Except for Start and Stop

conditions, the data on the SDA pin must be stable

during the high period of the clock. The high or low

state of the SDA pin can only change when the clock

signal on th e SCL pi n is low. Refer to Section 5.0 “I2C

Serial In terface” for more deta ils of I2C s erial interface

communication.

3.5 Serial Clock Pin (SCL)

SCL is the serial clock pin of the I2C interface. The

MCP47X6 de vi ce s a ct only as a s la ve an d the SCL pi n

accept s only external se rial clock s. The inpu t data from

the master device is shifted into the SDA pin on the

rising edges of the SCL clock and output from the

device occurs at the falling edges of the SCL clock. The

SCL pin is an open-drain N-channel driver. Therefore,

it needs a pull-up resistor from the VDD line to the SCL

pin. Refer to Section 5.0 “I2C Serial Interface” for

more details about I2C serial interface communication.

3.6 Voltage Reference Pin (VREF)

This pin is used for the external voltage reference input.

The user can select VDD voltage or the VREF pin

voltage as the reference resistor ladder’s voltage

reference.

When the VREF pi n signal is selected, the re is an optio n

for this voltage to be buffered or unbuffered. This is

offered in cases where the reference voltage does not

have the current ca p ab ili ty not to drop it s v ol t age when

connected to the internal resistor ladder circuit.

When th e VDD is se lecte d as refe rence volt age, this pi n

is disconnected from the internal circuit.

See Section 4.2 “DAC’s (Resistor Ladder)

Reference Voltage” and Table 4-4 for more details on

the Configuration bits.

3.7 Exposed Pad (EP)

This pad is conductively connected to the device's

substrate. This pad should be tied to the same potential

as the VSS pin (or left un co nne ct ed). This p ad could be

used to assist as a heat sink for the device when

connected to a PCB heat sink.

MCP4706/4716/4726

4.0 GENERAL DESCRIP T ION

The MCP4706, MCP4716, and MCP4726 devices are

single channel voltage output 8-bit, 10-bit, and 12-bit

DAC devices with nonvolatile memory (EEPROM) and

an I2C serial interface . This fam ily will be referred to as

MCP47X6.

The devices use a resistor ladder architecture. The

resistor ladder DAC is driven from a software

selectable voltage reference source. The source can

be eith er the devic e’ s in ternal VDD or the external VREF

pin voltage.

The DAC output is buffered with a low power and

precision output amplifier (op amp). This output

amplifier provides a rail-to-rail output with low offset

voltage and low noise. The gain of the output buffer is

software configurable.

This device also has user programmable nonvolatile

memory (EEPROM), whic h al lows the us er to save th e

desired POR/BOR value of the DAC register and

dev ice Configuration bits.

The devices use a two-wire I2C serial communication

inter fac e a nd op erat e w i th a s in gle s upply volt a ge from

2.7V to 5.5V.

4.1 Power-On Reset/Brown-Out Reset

(POR/BOR)

The internal Power-on Reset (POR)/Brown-out Reset

(BOR) circuit monitors the power supply voltage (VDD)

during operation. This circuit ensures correct device

start-up at system power-up and power-down events.

VRAM is the RAM reten tion volt age an d is alw ays low er

than the POR trip poi nt voltage.

POR occurs as the v oltage is risin g (ty pic al ly from 0V),

while BOR occurs as the voltage is falling (typically

from VDD(MIN) or high er).

When the rising VDD voltage crosses the VPOR trip

point, the following occurs:

• Nonvolatile DAC register value latched into

volatile DAC register

• Nonvolatile Configuration bit values latched into

volatile Configuration bits

• POR Status bit is set (“1”)

• The Reset delay timer starts; when timer times

out (tPORD), the I2C interface is operational.

The analog output (VOUT) state will be determined by

the state of the volatile Configuration bits and the DAC

When the falling VDD voltage crosses the VPOR trip

point, the following occurs:

• Device is forc ed into a power-dow n st ate

(PD1:PD0 = 11). Analog circuitry is turned off.

• Volatile DAC register is forced to 000h

• Volatile Configuration bits VREF1, VREF0 and G

are forced to ‘0’

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

FIGURE 4-1: Power-on Reset Operation.

VPOR TPORD

VDD(MIN)

Normal Operation

BOR Reset,

volatile DAC Register = 000h

volatile VREF1:VREF0 = 00

Device in Below

VRAM

Device in POR stateunknown

state minimum

operating

voltage

Device in

unknown

state

Device

in power

down

state

(60 µs max.)

volatile G = 0

volatile PD1:PD0 = 11

VBOR

Volatile memory

retains data value Volatile memo ry

becomes corrupted

POR starts Reset Delay Timer.

When timer times out, I2C™ interface

can operate (if VDD >= VDD(MIN))

EEPROM data latched into volatile

Configuration bits and DAC register.

POR Status bit is set (“1”)

POR Reset forced active

MCP4706/4716/4726

4.2 DAC’s (Resistor Ladder)

Refe renc e Vo ltage

The device can be configured to use one of three

voltage sources for the resistor ladder’s reference

voltage (VRL) (see Figure 4-2). These are:

1. VDD pin voltage

2. VREF pin voltage int erna lly buffered

3. VREF pin voltage unb uffered

The selec tion of the voltage is specified with the volatile

VREF1:VREF0 Configuration bits (see Table 4-4). There

are nonvolatile and volatile VREF1:VREF0 Configuratio n

bits . On a POR/BO R ev ent , the s t ate of the n onv ol atil e

VREF1:VREF0 Configuration bits are latched into the

volatile V REF1:VREF0 Configur ation bits.

When the user selects the VDD as reference, the VREF

pin voltage is not connected to the resistor ladder.

If the VREF pin is selected, then select between the

Buffered or Unbuffered mode.

In Unbu ffe red mod e, the VREF pin v olt ag e may b e from

VSS to VDD.

In Buffered mode, the VREF pin voltage may be from

0.01V to VDD-0.04V. The input buffer (amplifier) pro-

vides low offset voltage, low noise, and a very high

input impedance, with only minor limitations on the

input range and frequency response.

FIGURE 4-2: Resistor Ladder Reference

Voltage Selection Block Diagram.

4.3 Resistor Ladder

The resis tor l add er is a dig it a l potentiomet er w ith the B

Terminal internally grounded and the A terminal

connected to the selected reference voltage (see

Figure 4-3). The volatile DAC register controls the

wiper position. Th e wiper voltage (VW) is proportional to

the DAC register value divided by the number of

resistor elements (RS) in the ladder (256, 1024, or

4096) related to the VRL voltage.

The resistor ladder (RRL) has a typical impedance of

approximately 210 kΩ. This resistor ladder resistance

(RRL) may vary from device to device up to ±20%.

Since this is a voltage divider configuration, the actual

RRL resistance does not effect the output given a fixed

voltage at VRL.

If the unbuffered VREF pin is used as the VRL voltage

source, this voltage source should have a low output

impedance.

When the DAC is powered down, the resistor ladder is

disconnected from the selected reference voltage.

FIGURE 4-3: Resistor Ladder.

Note: In Unbuffered mode, the voltage source

should have a low output impedance. If

the voltage source has a high output

impedance, then the voltage on the

VREF’s pin would be lower than expected.

The resistor ladder has a typical

impedance of 210 kΩ and a typical

capac i tance o f 29 pF.

Note: Any variation or noises on the reference

source c an dire ctl y affect the DAC output.

The reference voltage needs to be as

clean as possible for accurate DAC

performance.

VRL

VDD

Buffer

Reference

VREF1:VREF0

Selection

VREF

Note: The maximum wiper position is 2n - 1,

while the number of resistors in the

resistor ladder is 2n. This means that

when the DAC register is at full scale,

there is one resistor element (RS)

between the wiper and the VRL volt ag e.

RS(2n)

RS(2n - 1)

RS(2n - 2)

RS(1)

2n - 1

2n - 2

RRL

VRL

DAC

VW = * VRL

DAC Register Value

# Resistors in Resistor Ladder

Where:

# Resistors in Resistor Ladder = 256 (MCP4706)

1024 (MCP4716)

4096 (MCP4726)

PD1:PD0

MCP4706/4716/4726

4.4 Output Buffer/VOUT Operation

The DAC output is buffered with a low power and

precision output amplifier (op amp). Figure 4-4 shows

a block diagram.

This amplifier provides a rail-to-rail output with low

offset voltage and low noise. The user can select the

output gain of the output amplifier. Gain options are:

a) Gain of 1, with either VDD or VREF pin used as

reference voltage

b) Gain of 2, only when VREF pin is used as

reference voltage. The VREF pin voltage should

be limited to VDD/2.

The amplifier’s output can drive the resistive and high

capacitive loads without oscillation. The amplifier

provides a maximum load current which is enough for

most programmable voltage reference applications.

Refer to Section 1.0 “Electrical Characteristics” for

the specifications of the output amplifier.

In any of the three Power-Down modes, the op amp is

powered down and its output becomes a high-

impedance to the VOUT pin.

FIGURE 4-4: Output Buffer Block

Diagram.

4.4.1 PROGRAMMABLE GAIN

The amplifier’s gain is controlled by the Gain (G)

Configuration bit (See Table 4-4) and the VRL reference

selection. When the VRL reference selection is the

devi ce’s VDD v oltage, th e G b it i s ign ored an d a gain of

1 is used. The volatile G bit value can be modified by:

• POR event

• BOR event

•I

2C Write commands

•I

2C General Call Reset command

4.4.2 OUTPUT VOLTAGE

The volatile DAC register’s value controls the analog

VOUT voltage, along with the device’ s five Configuration

bits. The volatile DAC register’s value is unsigned

binary.

The formula for the output voltage is given in

Equation 4-1. Table 4-1 shows examples of volatile

DAC register values and the corresponding theoretical

VOUT voltage f or the MCP47X6 devices.

EQUATION 4-1: CALCULATING OUTPUT

VOLTAGE (VOUT)

The DAC register value will be latched on the falling

edge of the Acknowledge pulse of the Write

comman d’s last byt e. Then t he VOUT v oltage wil l start

driving to the new value.

The following events update the analog voltage output

(VOUT):

• Power-on Reset or General Call Reset command:

Output is updated with EEPROM data.

• Falling edge of the Acknowledge pulse of the last

Write command byte.

4.4.2.1 Resolution/Step Voltage

The Step volt age is d ependent o n the d evice res olution

and the output voltage range. One LSb is defined as

the ideal voltage difference between two successive

codes. The step voltage can easily be calculated by

using Equation 4-1 where the DAC register value is

equal to 1.

Note: The l oad res ist ance must s t ay high er than

5kΩ for the stable and expected analog

output to meet electrical specifications.

VOUT

Amp

Gain (1x or 2x)

(G = 0 or 1)

Note: When Ga in = 2 (VRL = VREF),

if VREF > VDD/2, the VOUT voltage will be

limited to VDD. So if VREF = VDD, then the

VOUT voltage will not change for volatile

DAC register values mid-scale and

greate r , since the op amp is at it s full scale

output.

VOUT = * Gain

VRL * DAC Register Value

# Resistors in Resistor Ladder

# Resistors in Resistor Ladder = 4096 (MCP4726)

1024 (MCP4716)

256 (MCP4706)

MCP4706/4716/4726

4.4.3 OUTPUT SLEW RA TE

Figure 4-5 shows an example of the slew rate of the

VOUT pin. The slew rate can be affected by the

charact eristics of the circuit connected to the VOUT pin.

FIGURE 4-5: VOUT pin Slew Rate.

4.4.4 SMALL CAPACITIVE LOAD

With a smal l capac itive load, the output buf fer’s current

is not af fected by the capacitive load (CL). However , the

VOUT pin’s voltage is not a step transition from one

output value (wiper code value) to the next output

value. The ch ang e of the VOUT volt ag e is lim ited b y the

output buffer’s characteristics, so the VOUT pin voltage

will have a slope from the old voltage to the new

voltage. This slope is fixed for the output buffer, and is

referred to as the buffer slew rate (SRBUF).

4.4.5 LARGE CAPACITIVE LOAD

With a larger capacitive load, the slew rate is deter-

mined by two factors:

• The output buffer’s short circuit current (ISC)

•The V

OUT pin’s external load

IOUT cannot exceed the output buffer’s short circuit

current (ISC) which fixes the output buffer slew rate

(SRBUF). The voltage on the capacitive load (CL), V CL,

changes at a rate proportional to IOUT, which fixes a

capacitive load slew rate (SRCL).

So the VCL voltage slew rate is limited to the slower of

the output buffer’s internally set slew rate (SRBUF) and

the capacitive load slew rate (SRCL).

4.4.6 DRIVING RESISTIVE AND

CAPACITIVE LOADS

The VOUT pin can drive up to 100 pF of capacitive load

in para llel with a 5 k Ω resistive load (to meet electrical

specifications). Figure 2-94 shows the VOUT vs.

Resist ive Load.

VOUT drops slowly as the load resistance decreases

after about 3.5 kΩ. It is recommended to use a load

with RL greater than 5 kΩ.

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response. That is, since the VOUT pin’s voltage does

not quickly follow the buffer’s input voltage (due to the

large capacitive load), the output buffer will overshoot

the desired target voltage. Once the driver detects this

overshoot, it compensates by forcing it to a voltage

below the target. This causes voltage ringing on the

VOUT pin.

So, w hen driving large capacitive loads with the output

buffer, a small series resistor (RISO) at the output (see

Figure 4-6) improves the output buffer’s stability

(feedback loop’s phase margin) by making the output

load res istiv e at hi gher fre quenc ies. Th e band widt h wil l

be generally lower than the bandwidth with no

capacitive load.

FIGURE 4-6: Circuit to Stabilize Output

Buffer for Large Capacitiv e Load s (C L).

The RISO resistor value for your circuit needs to be

selected. The resulting frequency response peaking

and step response overshoot for this RISO resistor

value should be verified on the bench. Modify the

RISO’s resistance value until the output characteristics

meet your requirements.

A method to evaluate the system’s performance is to

inject a step voltage on the VREF pin and observe the

VOUT pin’s characteristics.

Time

Slew Rate =

Wiper = A

VOUT

VOUT(A)

VOUT(B)

Wiper = B

| VOUT(B) - VOUT(A) |

Note: Additional insight into circuit design for

driving capacitive loads can be found in

AN884 “Driving Cap aciti ve Load s With O p

Amps” (DS00884).

VOUT

Amp

RISO RL

VCL

MCP4706/4716/4726

TABLE 4-1: DAC INPUT CODE VS. ANALOG OUTPUT (VOUT) (VDD = 5.0V)

Device Volatile DAC

Selection

(2)

VOUT (4)

Equation uV Equation V

MCP4726

(12-bit)

1111 1111 1111

5.0V 5.0V/4096 1,220.7 1x VRL * (4095/4096) * 1 4.998779

2.5V 2.5V/4096 610.4 1x VRL * (4095/4096) * 1 2.499390

2x(3) V

RL * (4095/4096) * 2) 4.998779

0111 1111 1111

5.0V 5.0V/4096 1,220.7 1x VRL * (2047/4096) * 1) 2.498779

2.5V 2.5V/4096 610.4 1x VRL * (2047/4096) * 1) 1.249390

2x(3) V

RL * (2047/4096) * 2) 2.498779

0011 1111 1111

5.0V 5.0V/4096 1,220.7 1x VRL * (1023/4096) * 1) 1.248779

2.5V 2.5V/4096 610.4 1x VRL * (1023/4096) * 1) 0.624390

2x(3)VRL * (1023/4096) * 2) 1.248779

0000 0000 0000

5.0V 5.0V/4096 1,220.7 1x VRL * (0/4096) * 1) 0

2.5V 2.5V/4096 610.4 1x VRL * (0/4096) * 1) 0

2x(3)VRL * (0/4096) * 2) 0

MCP4716

(10-bit)

11 1111 1111

5.0V 5.0V/1024 4,882.8 1x VRL * (1023/1024) * 1 4.995117

2.5V 2.5V/1024 2,441.4 1x VRL * (1023/1024) * 1 2.497559

2x(3)VRL * (1023/1024) * 2 4.995117

01 1111 1111

5.0V 5.0V/1024 4,882.8 1x VRL * (511/1024) * 1 2.495117

2.5V 2.5V/1024 2,441.4 1x VRL * (511/1024) * 1 1.247559

2x(3)VRL * (511/1024) * 2 2.495117

00 1111 1111

5.0V 5.0V/1024 4,882.8 1x VRL * (255/1024) * 1 1.245117

2.5V 2.5V/1024 2,441.4 1x VRL * (255/1024) * 1 0.622559

2x(3)VRL * (255/1024) * 2 1.245117

00 0000 0000

5.0V 5.0V/1024 4,882.8 1x VRL * (0/1024) * 1 0

2.5V 2.5V/1024 2,441.4 1x VRL * (0/1024) * 1 0

2x(3)VRL * (0/1024) * 1 0

MCP4706

(8-bit)

1111 1111

5.0V 5.0V/256 19,531.3 1x VRL * (255/256) * 1 4.980469

2.5V 2.5V/256 9,765.6 1x VRL * (255/256) * 1 2.490234

2x(3)VRL * (255/256) * 2 4.980469

0111 1111

5.0V 5.0V/256 19,531.3 1x VRL * (127/256) * 1 2.480469

2.5V 2.5V/256 9,765.6 1x VRL * (127/256) * 1 1.240234

2x(3)VRL * (127/256) * 2 2.480469

0011 1111

5.0V 5.0V/256 19,531.3 1x VRL * (63/256) * 1 1.230469

2.5V 2.5V/256 9,765.6 1x VRL * (63/256) * 1 0.615234

2x(3)VRL * (63/256) * 2 1.230469

0000 0000

5.0V 5.0V/256 19,531.3 1x VRL * (0/256) * 1 0

2.5V 2.5V/256 9,765.6 1x VRL * (0/256) * 1 0

2x(3)VRL * (0/256) * 2 0

Note 1: VRL is the resistor ladder ’s reference voltage. It is independent of VREF1:VREF0 selection.

2: Gain selection of 2x requires voltage reference source to come from VREF pin and

requires VREF pin voltage ≤ VDD / 2.

3: Requires G = 1, VREF1:VREF0 = 10 or ‘11’, and VRL ≤ VDD/2.

4: These theoretical calculations do not take into account the Offset and Gain errors.

MCP4706/4716/4726

4.5 Power-Down Operation

To allow the application to conserve power when the

DAC operation is not required, three Power-Down

modes are available. The Power-Down Configuration

bits (PD1:PD0) control the power-down operation

(Figure 4-7). All Power-Down modes do the following:

• Turn off most of its interna l ci rcu it s (op am p, resis-

tor ladder, ...)

• Op amp output becomes high-impedance to the

VOUT pin

• Disconnects resistor ladder from reference

voltage (VRL)

• Ret ain s th e va lue of the volatile DAC re gist er a nd

Configura tion bit s, and th e nonvolati le (EEPROM)

DAC register and Configuration bits

Depending on the selected Power-Down mode, the

following will occur:

•V

OUT pin is switched to one of three resistive pull-

down s (See Table 4-2)

- 640kΩ (typical)

- 125kΩ (typical)

-1kΩ (typical)

There is a delay (TPDE) between the PD1:PD0 bits

changing from ‘00’ to either ‘01’, ‘10’, or ‘11’ and the op

amp no longer driving the VOUT output and the pull-

down resistors are sin ki ng current.

In any of the P owe r -D ow n mo des, whe r e the VOUT pin

is not externally connected (sinking or sourcing

current), th e power-dow n current will typicall y be 60 nA

(see Section 1.0 “Electrical Characteristics”).

Section 6.0 “MCP47X6 I2C Commands” describes

the I2C comman ds for writ ing th e power-dow n bit s. The

commands that can update the volatile PD1:PD0 bits

are:

• Write Volatile DAC Register

• Write Volatile Memory

• Write All Memor y

• Write Volatile Configuration Bits

• General Call Reset

• General Call Wake-up

FIGURE 4-7: Op Amp to VOUT Pin Block

Diagram.

4.5.1 EXITING POWER-DOWN

When the device exits the Power-Down mode, the

following occurs:

• Disabled circuits (op amp, resistor ladder, ...) are

turned on

• Resistor ladder is connected to selected

reference voltage (VRL)

• Selected pull-down resistor is disconnected

•The V

OUT output will be driven to the voltage

represented by the volatile DAC register’s value

and Configuration bits

The VOUT output signal will require time as these

circuit s are powe red up and the ou tput volta ge is driven

to the specified value as determined by the volatile

DAC register and Configuration bits.

The following events will change the PD1:PD0 bits to

‘00’ and therefore exit the Power-Down mode. These

are:

•Any I

2C Write command for where the PD1:PD0

bits are ‘00’

•I

2C General Call Wake-up Command

•I

2C General Call Reset Comma nd

(if nonvolatile PD1:PD0 bits are ‘00’)

Note: The I2C serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

I2C master device.

TABLE 4-2: POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

PD1 PD0 Function

00Normal operation

011kΩ resistor to ground

10125 kΩ resistor to ground

11640 kΩ resistor to ground

Note: Since the op amp and resisto r ladder were

powered off (0V), the op amp’s input

volt age (VW) can b e consid ered 0V. There

is a delay (TPDD) between the PD1:PD0

bits updated to ‘00’ and the op a mp driving

the VOUT output. The op amp’s settling

time (from 0V) needs to be taken into

account to ensure the VOUT voltage

reflects the selected value.

VOUT

PD1:PD0

Amp

1kΩ

125 kΩ

640 kΩ

Gain (1x or 2x)

(Gx = 0 or 1)

MCP4706/4716/4726

4.6 Device Resets

Device Resets can be grouped into two types: Resets

due to change in voltage (POR/BOR Reset), and

Resets caused by the system master (such as a

microcontroller).

After a device Reset, and when VDD ≥ VDD(MIN), the

device memory may be written or read.

4.6.1 POR/BOR RESET OPERATION

The POR an d BO R trip po ints are at the s am e vol tage,

and ar e determi ned if the VDD voltage is rising or falling

(see Figure 4-1). What occurs is different, depending if

the Reset is a POR or BOR Reset.

POR Reset (VDD Rising)

On a POR Reset, the nonvolatile m emory values (DAC

volatile memory. This configures the analog output

(VOUT) circuitry. A Reset d elay tim er a lso st art s. During

this delay time, the I2C interface will not accept

commands.

BOR Reset (VDD Falling)

On a BOR Reset, the device is forced into a power-

down st ate. The volatile PD1:PD0 bits are forced to ‘11’

and all other volatile memory forced to ‘0’. The I2C

interface will not accept commands.

4.6.2 RESET COMMANDS

When the MCP47X6 is in the valid operating voltage,

the I2C General Call Reset command will force a

Reset event. This is similar to the POR Reset, except

that the Reset delay timer is not started.

In the cas e whe re the I2C interface bu s do es not s ee m

to be responsive, the technique shown in Section 8.9

“Software I2C Interface Reset Sequence” can be

used to force the I2C interface to be reset.

4.7 DAC Registers, Configuration

Bits, and Status Bits

The MCP47X6 devices have both volatile and

nonvolatile (EEPROM) memory. Figure 4-8 show s the

volatile and nonvolatile memory and their interaction

due to a POR event.

There are f ive Configu ration bits in both the v olatile and

nonvolatile memory, the DAC registers in both the

volatil e and nonv olatile memory, and tw o volatile S t atus

bits . The DAC registe rs (volatile a nd nonvolati le) will be

either 12-b its (MC P4726), 10- bits (M CP4716), or 8-bit s

(MCP4706) wide.

When the device is first powered up, it automatically

uploads the EEPROM memory values to the volatile

memory. The volatile memory determines the analog

output (VOUT) pin voltage. After the device is powered

up, the user can update the device memory.

The I2C interface is how this memory is read and

written. Refer to Section 5.0 “I2C Serial Interface”

and Section 6.0 “MCP47X6 I2C Commands” for

more details on the reading and writing the device’s

memory.

When the nonvolatile memory is written (using the I2C

Write All Memory command), the volatile memory is

written with the same values. The device starts writing

the EEPROM cell at the Acknowledge pulse of the

EEPROM Write command.

Table 4-3 show s the operat ion of the devic e S ta tus bits,

Table 4-4 show s the ope rati on of th e dev ic e Conf igu r a-

tion bits, and Table 4-5 shows the factory default value

of a POR /BO R e ve nt f or th e d ev ic e Co nfig ura tion bi ts.

There are two Status bits. These are only in volatile

memory and give indication o n the st atus of the dev ice.

The POR bit indicates if the device VDD is above or

below the POR tri p poin t. During n ormal operati on, thi s

bit should be ‘1’. The RDY/BSY bit indicates if an

EEPROM write cycle is in progress. While the

RDY/BSY bit is low (during the EEPROM writing), all

commands are ignored, except for the Read command.

FIGURE 4-8: DAC Memory and POR Interaction.

VREF1

DAC Regist er Valu e (1)

N.V. Memory

Config Bits

Vol. Memory

POR Event

VREF0 PD1 PD0 G

VREF1 VREF0 PD1 PD0 GRDY/BSY POR

Status Bits (2)

DMAX D1 D0

Note 1: The DMAX value depends on the device. For the MCP4706: DMAX = D7, MCP4716: DMAX = D9,

and the MCP4726: DMAX = D11.

2: Status bits are read-only.

MCP4706/4716/4726

TABLE 4-3: STATUS BITS OPERATION

Name Function

RDY/BSY This bit indicates the state of the EEPROM program memory

1 = EEPROM is not in a programming cycle

0 = EEPROM is in a programming cycle

POR Power-on R ese t Status Indica tor (flag)

1 = Device is powered on with VDD > VPOR.

Ensure that VDD is above VDD(MIN) to ensure proper opera tio n.

0 = Device is in powered off state. If this value is read, VDD < VDD(MIN) < VPOR.

Unreliable device operation should be expected.

TABLE 4-4: CONFIGURATION BITS

Name Function

VREF1:VREF0 Resistor Ladder Voltage Reference (VRL) Selection bits

0x =V

DD (Unbuffe red)

10 =V

REF pin (Unbuffered)

11 =V

REF pin (Buffered)

PD1:PD0 Power-Down Selection bits

When the DAC is powered down, most of the internal circuits are powered off and the op amp is

disconnected from the VOUT pin.

00 = Not Powered Down (Normal operation)

01 = Powered Down – VOUT is loaded with 1 kΩ resistor to ground.

10 = Powered Down – VOUT is loaded with 100 kΩ resistor to ground.

11 = Powered Down – VOUT is loaded with 500 kΩ resistor to ground.

Note: See Table 4-2 and Figure 4-7 for more details.

G Gain Selection bit

0 = 1x (gain of 1)

1 = 2x (gain of 2). Not applicable when VDD is used as VRL

Note: If VREF = VDD, the device uses a gain of 1 only, regardless of the gain selection bit (G)

setting.

TABLE 4-5: CONFIGURATION BIT VALUES AFTER POR/BOR EVENT

R/W R/W R/W R/W R/W Comment

Bit Name VREF1 VREF0 PD1 PD0 G

POR Event 0(1) 0(1) 0(1) 0(1) 0(1) When VDD transitions from V DD < VPOR to VDD > VPOR

BOR Event 00110When VDD transiti ons from V DD > VBOR to VDD < VBOR

Note 1: Default configuration when the device is shipped to customer. The POR/BOR value may be modified by

writing the corresponding nonvolatile Configuration bit.

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Comment

Bit Name —(2) —

(2) —

(2) D7 D6 D5 D4 D3 D2 D1 D0 MCP4706

—(2) —

(2) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCP4716

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCP4726

POR/BOR Event 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1)

Note 1: Default configuration when the device is shipped to customer. The POR/BOR value may be modified by

writing the corresponding nonvolatile Configuration bit.

2: This device does not implement this bit, so there is no corresponding POR/BOR value.

MCP4706/4716/4726

5.0 I2C SERIAL INTERFACE

The MCP47X6 devices support the I2C serial prot ocol.

The MCP47X6 I2C’s module operates in Slave mode

(does not generate the serial clock).

5.1 Overview

This I2C interface is a two-wire interface. Figure 5-1

shows a typical I 2C inte rfac e con nec ti on.

The I2C inte rf ac e s pe c if i es di ffe re nt c om mu ni ca t io n bi t

rates. The se are re ferre d to as Standard , Fas t or Hig h-

Speed modes. The MCP47X6 supports these three

modes. The bit rates of these modes are:

• Standard mode: bit rates up to 100 kbit/s

• Fast mode: bit rates up to 400 kbit/s

• High-Speed mode (HS mode): bit rates up to

3.4 Mbit/s

A devi ce that se nds data ont o the bus is define d as a

transmitter, and a device receiving data as a receiver.

The bus has to be controlled by a m as ter device w hic h

generates the serial clock (SCL), controls the bus

access and generates the Start and Stop conditions.

The MC P47X6 device works as sla ve. Both mast er and

slave can operate as transmitter or receiver, but the

master device determines which mode is activated.

Communication is initiated by the master

(microcontroller) which sends the Start bit, followed by

the slave address byte. The first byte transmitted is

always the slave address byte, which contains the

device code, the address bits, and the R/W bit.

FIGURE 5-1: Typical I2C Interface.

The I2C s erial prot ocol only d efines th e field type s, fiel d

lengths, timings, etc. of a frame. The frame content

defines the behavior of the device. For details on the

frame content (commands/data) refer to Section 6.0

“MCP47X6 I2C Commands”.

Refer to the NXP I2C document for more details on the

I2C specifications.

5.2 Signal Descriptions

The I2C interface uses up to two pins (signals). These

are:

• SDA (Serial Data)

• SCL (Serial Clock)

5.2.1 SERIAL DATA (SDA)

The Serial Data (SDA) signal is the data signal of the

device. The value on this pin is latched on the rising

edge of the SCL signal when the signal is an input.

With the exce ption of the S t art and S top conditio ns, the

high or low st ate of th e SDA pin c an o nly c ha nge whe n

the clock signal on the SCL pin is low. During the high

period of the clock, the SDA pin’s value (high or low)

must b e stabl e. Cha nges i n the SDA pi n’s value w hile

the SCL pin is High will be interpreted as a Start or a

Stop condition.

5.2.2 SERIAL CLOCK (SCL)

The Serial Clock (SCL) signal is the clock signal of the

device. The rising edge of the SCL signal latches the

value on the SDA pin.

The MCP47X6 will not stretch the clock signal (SCL)

since mem ory read acc es s oc curs fast eno ugh .

Depending on the clock rate mode, the interface will

dis play di fferent char acteristics.

SCL

MCP4XXX

SDA

Host

Controller

Typical I2C™ Interface Connections

MCP4706/4716/4726

5.3 I2C Operation

The MCP47X6’s I2C module is compatible with the

NXP I2C specification. The following lists some of the

module’s features:

• 7-bit slave addressing

• Supports three clock rate modes:

- Standard mode, clock rates up to 100 kHz

- Fast mode, clock rates up to 400 kHz

- High-speed mode (HS mode), clock rates up

to 3.4 MHz

• Support multi-master applications

• General call addressing (Reset and Wake-Up

commands)

The I2C 10-bit Addressing mode is not supported.

The NXP I2C specification only defines the field types,

field lengths, timings, etc. of a frame. The frame

content defines the behavior of the device. The frame

content for the MCP47X6 is defined in Section 6.0

“MCP47X6 I2C Commands”.

5.3.1 I2C BIT STATES AND SEQUENCE

Figure 5-8 shows the I 2C transf er sequenc e. The seria l

clock is generated by the master. The following

definitions are used for the bit states:

• Start bit (S)

• Data bit

• Acknowledge (A) bit (driven low) /

No Ac knowledge (A) bit (not driven low)

• Repeated Start bit (Sr)

• Stop bit (P)

5.3.1.1 Start Bit

The S t art bit (see Figure 5-2) indi cates t he begin ning of

a dat a transfer sequ ence. The S t art bit is de fined as the

SDA signal falling when the SCL signal is “High”.

FIGURE 5-2: Start Bit.

5.3.1.2 Data Bit

The SD A signal m ay cha nge st ate whil e the SC L signa l

is Low. While the SCL signal is High, the SDA signal

MUST be stable (see Figure 5-3).

FIGURE 5-3: Data Bit.

5.3.1.3 Acknowledge (A) Bit

The A bit (see Figure 5-4) is typically a response from

the receiving device to the transmitting device.

Depend ing on the context of the transfer sequenc e, the

A bit may indica te differ ent thin gs. Ty pically, the slave

device will supply an A response after the Start bit and

8 “data” bits have been received. An A bit has the SDA

signal low.

FIGURE 5-4: Acknowledge Waveform.

Not A (A) Response

The A bit has the SDA signal high. Table 5-1 shows

some of the conditions where the slave device will

issue a Not A (A).

If an error cond ition occurs (s uch as an A instea d of A),

then a Start bit must be issued to reset the command

state machine .

SDA

SCL S

1st Bit 2nd Bit

SDA

SCL Data Bit

1st Bit 2nd Bit

TABLE 5-1: MCP47X6 A/A RESPONSES

Event Acknowledge

Bit

Response Comment

General Call A

Slave Address

valid A

Slave Address

not valid A

Communication

during

EEPROM write

cycle

A After device has

received address

and command,

and valid

conditions for

EEPROM write

Bus Collision N/A I2C module

Resets, or a

“Don’t Care” if

the collision

occurs on the

Master’s “S tart

bit”

SDA

SCL

MCP4706/4716/4726

5.3.1.4 Repeated Start Bit

The Repeated Start bit (see Figure 5-5) indicates the

current master device wishes to continue

communicating with the current slave device without

rele as in g t he I 2C bus. The Repeated Start condition is

the same as the Start condition, except that the

Repea ted Start bit foll ow s a Start bit (with the Da t a bits

+ A bit) and not a Stop bit.

The Start bit is the beginning of a data transfer

sequence and is defined as the SDA signal falling when

the SCL signal is “High”.

FIGURE 5-5: Repeat Start Condition

Waveform.

5.3.1.5 Stop Bit

The Stop bit (see Figure 5-6) Indicates the end of the

I2C Dat a T ransfer Se quence. Th e S top bit i s defined a s

the SDA signal rising when the SCL signal is “High”.

A Stop bit resets the I2C interface of all MCP47X6

devices.

FIGURE 5-6: Stop Condition Receive or

Transmit Mode.

5.3.2 CLOCK STRETCHING

“Clock Stretching” is something that the receiving

Device can do, to allow additional time to “respond” to

the “data” t hat has been received.

The MCP47X6 will not stretch the clock signal (SCL)

since mem ory read acc es s oc curs fast eno ugh .

5.3.3 ABORTING A TRANSMISSION

If any part of the I2C transmission does not meet the

command format, it is abort ed. This can be intentionally

accomplished with a Start or Stop condition. This is

done so that noisy transmission s (usually a n extra S ta rt

or Stop condition) are aborted before they corrupt the

device.

FIGURE 5-7: Typi cal 8- Bi t I2C Waveform Format.

FIGURE 5-8: I2C Data States and Bit Sequence.

Note 1: A bus collision during the Repeated Start

conditi on oc curs if:

• SDA is sampled low when SCL goes

from low to high.

• SCL goes low before SDA is asserted

low. This may indicate that another

master is attempting to transmit a

data "1".

SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA A / A

1st Bit

SDA

SCL

S2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit PA / A

SCL

SDA

Start

Condition Stop

Condition

Data allowed

to change Data or

A valid

MCP4706/4716/4726

5.3.4 SLOPE CONTROL

The MCP47X6 implements slope control on the SDA

output.

As the device transitions from HS mode to FS mode,

the slope control parameter will change from the HS

specification to the FS specification.

For Fast (F S) and H ig h-Speed (HS) mod es, the dev ic e

has a spi ke su ppress ion and a Schmid t Trigger at SDA

and SCL inputs.

5.3.5 DEVICE ADDRESSING

The addres s byte is the firs t byte receive d following the

Start condition from the master device. The

MCP47X6’s slave address consists of a 4-bit fixed code

(‘1100’) and a 3-bit code that is user specified when the

device is ordered. This allows up to eight MCP47X6

devices on a single I2C bus.

Figure 5-9 shows the I2C slave address byte format,

which cont ain s the seve n addre ss bi ts and a read/w rite

(R/W) bit. Table 5-2 shows the eight I2C slave address

options and their respective device order code.

FIGURE 5-9: Slave Address Bits in the

I2C Control Byte.

Start bit R e ad/ Write bi t

Address Byte

R/W ACK

Acknowledge bit

Slave Addr ess

1100

Slave Address (7-bits)

A2 A1 A0

Note: Address Bits (A2:A0) specified at time of device

order, see Table 5-2.

Fixed User Specified

TABLE 5-2: I2C ADDRESS/ORDER CODE

7-bit I2C™

Address Device Order Code Comment

‘1100000’MCP47x6A0-E/xx

MCP47x6A0T-E/xx Tape and Reel

‘1100001’MCP47x6A1-E/xx

MCP47x6A1T-E/xx Tape and Reel

‘1100010’MCP47x6A2-E/xx

MCP47x6A2T-E/xx Tape and Reel

‘1100011’MCP47x6A3-E/xx

MCP47x6A3T-E/xx Tape and Reel

‘1100100’MCP47x6A4-E/xx

MCP47x6A4T-E/xx Tape and Reel

‘1100101’MCP47x6A5-E/xx

MCP47x6A5T-E/xx Tape and Reel

‘1100110’MCP47x6A6-E/xx

MCP47x6A6T-E/xx Tape and Reel

‘1100111’MCP47x6A7-E/xx

MCP47x6A7T-E/xx Tape and Reel

Note 1: The s ample ce nter will generall y stock I2C

address ‘1100000’, other addresses may

be available.

2: ‘xx’ in the order code is the device

package code (CH for SOT-23 and MAY

for DFN)

MCP4706/4716/4726

5.3.6 HS MODE

The I2C spe cific ation re quires that a High -Speed mode

device must be ‘activated’ to operate in High-Speed

(3.4 Mbit/s) mode. This is done by the master sending

a special address byte following the Start bit. This byte

is referred to as the High-Speed Master Mode Code

(HSMMC).

The MCP47 X6 device does not ack nowled ge this byte.

However, upon receiving this command, the device

switches to HS mode. The device can now

communicate at up to 3.4 Mbit/s on SDA and SCL

lines. The devic e w i ll sw it ch out of the HS mode on th e

nex t Stop condition.

The master code is sent as follows:

1. Start condition (S)

2. High-Speed Master Mode Code (0000 1XXX),

The XXX bits are uni que to the High -Speed (HS)

mode master.

3. No Acknowledge (A)

After switching to the High-Speed mode, the next

transferre d by te i s t he I2C c ontr ol b yte , w hi ch spe ci fie s

the device to communicate with, and any number of

dat a bytes plus a cknowledgem ents. The ma ster device

can then e ith er is su e a R ep eate d Start bit to addre ss a

different device (at High-Speed) or a Stop bit to return

to Fast/Standard bus speed. After the Stop bit, any

other master device (in a multi-master system) can

arbitrate for the I2C bus.

See Figure 5-10 for illustration of HS mode command

sequence.

For more information on the HS mode, or other I2C

modes, please refer to the NXP I2C specification.

5.3.6.1 Slope Control

The slope control on the SDA output is different

betwee n the Fa st/Standard Speed and the High-Speed

clock modes of the interface.

5.3.6.2 Pulse Gobbler

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

FIGURE 5-10: HS Mode Sequence.

SA ‘0 0 0 0 1 X X X’b Sr A

‘Slave Address’ A/A“Data”

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

R/W

P = Stop bit (Stop condition terminates HS mode)

F/S- mode HS mode

HS mode continues

F/S mode

Sr A

‘Slave Address’R/W

HS Select Byte Control Byte Command/D ata Byte(s)

Control Byte

MCP4706/4716/4726

5.3.7 GENERAL CALL

The General Call is a method that the “master” device

can communicate with all other “slave” devices. In a

multi-master application, the other master devices are

operating in Slave mode. The General Call address

has two documented formats. These are shown in

Figure 5-11.

The MCP47X6 has two General Call commands. The

function of these commands are:

• Reset the device(s) (Software Reset)

• Wake-Up the device(s)

For det ails on the o peration of th e MCP47X6’ s Genera l

Call commands, see Section 6.6 “I2C General Call

Commands”.

FIGURE 5-11: General Call Formats.

Note: Only one General Call command per issue

of the General Call control byte. Any

additional General Call commands are

ignored and Not Acknowledged.

0000S0000 XxxxxAxx0AP

General Call Address

Second Byte

“7-bit Command”

Reserved 7-bit Commands (By I2C Specification – NXP specification # UM10204, Rev. 03 19 June 2007)

‘0000 011’b - Reset and write programmable part of slave address by hardware

‘0000 010’b - Write programmable part of slave address by hardware

‘0000 000’b - NOT Allowed

The Followi ng is a “Hardw are Gene ral Call ” Format

0000S0000 XxxxxAxx1 A

General Call Address

Second Byte

“Master Address”

Xxxxx xxXAP

n occurrenc es of (Dat a + A)

This indicates a “Hardware General Call”

MCP4706/4716/4726

6.0 MCP47X6 I2C COMMANDS

The I2C protocol does not specify how commands are

forma tted, s o this secti on spe cifie s the M CP47 X6’ s I2C

command formats and operation.

The commands can be grouped into the following

categories:

• Write memory

• Read memory

• General Call commands

The supported commands are shown in Table 6-2.

Many of these commands allow for continuous

operation. This means that the I2C master does not

generate a Stop bit but repeats the required

data/clocks. This allows faster updates since the

overhead of the I2C control byte is removed. Table 6-1

shows the supported commands and the required

number of bit clocks for both single and continuous

commands.

Write commands, determined by the R/W bit = 0, use

up to three command codes bits (C2:C0) to determine

the write’s operation.

The Read command is strictly determined by the R/W

bit = 1. There are two format s of the com mand , one for

12-bit and 10-bit devices and a second for 8-bit

devices.

The General Call commands utilize the I2C

specification reserved General Call command address

and command codes.

6.0.1 ABORTING A TRANSMISSION

A Restart or Stop condition in an expected data bit

position will abort the current command sequence and

data will not be written to the MCP47X6.

TABLE 6-1: I2C COMMANDS - NUMBER

OF CLOCKS

Command # of Bit

Clocks (1)

Operation Mode

Write Volatile DAC Register

Command (2) Single 29

Continuous 18n + 11

Write Volatile Memory

Command Single 38

Continuous 27n + 11

Write All Memory Command Single 38

Continuous 27n + 11

Write Volatile Configuration

Bits Co mm an d Single 20

Continuous 9n + 11

Read Command (12 and

10-bit DAC Register) (2)Single 65

Continuous 54n + 11

Read Command

(8-bit DAC Register) (2)Single 47

Continuous 36n + 11

Note 1: “n” indicates the number of times the command

operation is to be repeated.

2: This command is useful to determine when an

EEPROM programming cycle has completed

(RDY/BSY Status bit)

TABLE 6-2: MCP47X6 SUPPORTED COMMANDS

Command

Code

(Note 1)Command Name

Writes Volatile

Memory?

Writes

EEPROM

Memory?

Command

during

EEPROM

Write

Cycle?

Comment

C2 C1 C0 Config. DAC Config. DAC

00X

Write Volatile DAC Register

Command (Note 2) PD1:PD0

only Yes No No No Writes volatile power-down bits

so can also be used to exit a

power-down state.

010

Write Volatile Memory

Command Yes Yes No No No

011

Write All Memory Comm and Yes Yes Yes Yes No

100Write Volatile Configuration

Bits Command Yes No No No No

101

Reserved N/A N/A N/A N/A N/A Reserved (Note 3)

110

111 N/A N/A N/A N/A Reserved ( Note 3)

N/A

Read Com man d N/A N/A N/A N/A Yes Determined by R/W bit in I2C™

Control byte

General Call Reset N/A N/A N/A N/A No Determined by General Call

command byte after the I2C

General Call address.

General Call Wake-up N/A N/A N/A N/A No

Note 1: These bits are the MSb of the 2nd byte in the I2C Write command. See Figure 6-1 to Figure 6-4.

2: X = Don’t Care bit. This command format does not use C0 bit.

3: Device operation is not specified.

MCP4706/4716/4726

6.1 Write Volatile DAC Register

(C2:C0 = 00x)

This command is used to update the volatile DAC

bits (PD1:PD0). This command is typically used for a

quick update of the analog output by modifying the

minimum parameters. The EEPROM values are not

affected by this co mmand.

Figure 6-1 show s an ex am pl e of th e com ma nd f orm at ,

where a Stop bit completes the command.

The volatile DAC register and Power-down

Configuration bits are updated with the written date at

the completion of the ACK bit (falling edge of SCL).

After this ACK bit, the I2C master should generate a

Stop bit or the I2C master can repeat the 2nd

(2 command bits + 2 power-down bits + 4 data bits

(b11:b08)) and the 3rd byte (8 data bits (b07:b00)).

Repeating the 2nd and 3rd bytes allows a continuous

command where the volatile DAC register can be

updated without the communication overhead of the

device addressing byte (1st byte).

The device updates the VOUT at the falling edge of the

Acknowledge pulse of the 3rd byte.

FIGURE 6-1: Write Volatile DAC Register Command.

Device Addressing Data bits (8 bits)

Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse.

Note 1

2: The 2nd-3rd bytes can be repeated after the 3rd byte by continued clocking before issuing Stop bit.

Command

3: ACK bit generated by MCP47X6.

Note 2

b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00

MCP4726 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

MCP4716 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X

MCP4706 X X X X D07 D06 D05 D04 D03 D02 D01 D00

SDA

SCL

A2 A1 A01100 0000PD1 PD0 b11 b10 b09 b08 0b07 b06 b05 b04 b03 b02 b01 b00 0

Data bits (4 bits)

Data bit s (12 bits)

Start bit ACK bit (3)

Read/Write bit (Write)

Stop bit

SAR/W A A P

Power

bits Down

bits

ACK bit (3) ACK bit

(3)

Legend: X = don’t care

D11:D00 = 12-bit data for MCP4726 device

D09:D00 = 10-bit data for MCP4716 device

D07:D00 = 8-bit data for MCP4706 device

MCP4706/4716/4726

6.2 Write Volatile Memory

(C2:C0 = 010)

This W rite comma nd is used to update the vol atile DAC

not affected by this command. Figure 6-2 shows an

example of this Write command.

The volatile DAC register and Configuration bits are

updated with the written date at the completion of the

ACK bit (falling edge of SCL).

After this ACK bit, the I2C master should generate a

Stop bit or the I2C master can repeat the 2nd

(3 command bits + 5 Configuration bits), and the 3rd

byte (8 data bits (b15:b08)), and the 4th byte (8 data

bits (b07:b00)). Repeating the 2nd through 4th bytes

allows a continuous command where the volatile DAC

the communication overhead of the device addressing

byte (1st byte).

FIGURE 6-2: Write Volatile Memory Command.

Device Addressing Data bits (8 bits) (3rd byte)

Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse.

Note 1

2: The 2nd-4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit.

Command

3: ACK bit generated by MCP47X6.

Note 2

b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00

MCP4726 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X

MCP4716 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X

MCP4706 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X X X

SDA

SCL

A2 A1 A01100 0001 PD1 PD0 G 0b15 b14 b13 b12 b11 b10 b09 b08 0

Ref.

Data bits (16 bits) (3rd + 4th bytes)

Start bit ACK bit (3)

Read/Write bit (Write)

Stop bit

SAR/W A A

Power-

bits Down

bits

ACK bit (3) ACK bit

(3)

Legend: X = don’t care

D11:D00 = 12-bit data for MCP4726 device

D09:D00 = 10-bit data for MCP4716 device

D07:D00 = 8-bit data for MCP4706 device

VREF1 VREF0

Data bits (8 bits) (4th byte)

b07 b06 b05 b04 b03 b02 b01 b00 0

A P

ACK bit (3)

Voltage

Select

bits

Gain

bit

MCP4706/4716/4726

6.3 Write All Memory

(C2:C0 = 011)

This Write command is used to update the volatile and

nonvolatile (EEPROM) DAC register value and

Config uration bit s. Figure 6-3 shows an e xample of this

Write command.

•V

OUT update: At the falling edge of the

Acknowledge pulse of the 4th byte.

• EEPROM update: At the falling edge of the

Acknowledge pulse of the 4th byte.

The DAC register and Power-down Configuration bits

(volatile and EEPROM) are updated with the written

date at the completion of the ACK bit (falling edge of

SCL). The EEPROM memory requires time (TWC) for

the values to be written. Another Write All Memory

command should not be issued until the EEPROM

write is complete.

Write commands which only update volatile memory

(C2:C0 = 00x or ‘010’) can be issued. Read

commands and the General Call commands may not

be issued.

FIGURE 6-3: Write All Memory Command.

Note: RDY/BSY bit toggles to “low” and back to

“high” after the EEPROM write is

completed. The state of the RDY/BSY bit

can be monitored by a Read command.

Device Addressing Data bits (8 bits) (3rd byte)

Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse.

Note 1

2: The 2nd-4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit.

Command

3: ACK bit generated by MCP47X6.

Note 2

b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00

MCP4726 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X

MCP4716 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X

MCP4706 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X X X

SDA

SCL

A2 A1 A01100 0001 PD1 PD0 G 0b15 b14 b13 b12 b11 b10 b09 b08 0

Ref.

Data bits (16 bits) (3rd + 4th bytes)

Start bit ACK bit (3)

Read/Write bit (Write)

Stop bit

SAR/W A A

Power-

bits Down

bits

ACK bit (3) ACK bit

(3)

Legend: X = don’t care

D11:D00 = 12-bit data for MCP4726 device

D09:D00 = 10-bit data for MCP4716 device

D07:D00 = 8-bit data for MCP4706 device

VREF1 VREF0

Data bits (8 bits) (4th byte)

b07 b06 b05 b04 b03 b02 b01 b00 0

A P

ACK bit (3)

Voltage

Select

bits

Gain

bit

MCP4706/4716/4726

6.4 Write Volatile Configuration Bit s

(C2:C0 = 100)

This Write command is used to update the volatile

Configuration register bits only. This command is a

quick method to modify the configuration of the DAC,

such as the selection of the resistor ladder reference

voltage, the op amp gain, and the power-down state.

Figure 6-4 shows an example of this Write command.

FIGURE 6-4: Write Volatile Configuration Bits Command.

Device Addressing

Note 1: The device updates VOUT at the falling edge of the SCL at the end of this ACK pulse.

Note 1

2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit.

Command

3: ACK bit generated by MC P47X6.

Note 2

SDA

SCL

A2 A1 A01100 0010 PD1 PD0 G 0

Configuration bits

Start bit ACK bit (3)

Read/Write bit (Write)

Stop bit

SAR/W A

bits

ACK bit (3)

VREF1 VREF0 P

MCP4706/4716/4726

6.5 READ COMMAND

This command reads all the device memory. This

includes the volatile and nonvolatile (EEPROM) DAC

status bit s.

This com m and is exe cu ted when the I2C contr ol byte’s

Read/Write bit is a ‘1’ (read).

This command has two different formats based on the

resolution of the device. The 12-bit and 10-bit devices

use the format in Figure 6-5, while the 8-bit device uses

the format in Figure 6-6.

The 2nd byte (Configuration bits) indicates the current

condition of the device operation. The RDY/BSY bit

indicates EEPROM writing status.

FIGURE 6-5: Read Command Format for 12-bit DAC (MCP4726) and 10-bit DAC (MCP4716).

Device Addressing

Note 1: The 2nd-7th bytes can be repeated after the 7th byte by continued clocking before issuing Stop bit.

2: ACK bit generated by MCP47X6.

3: ACK bit generated by I2C Master.

b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00

MCP4726 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 0 0 0 0

MCP4716 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 0 0 0 0 0 0

SDA

SCL

A2 A1 A01100 1 0

PD1 PD0 G

Data bits (16 bits) (3rd + 4th bytes, and 6th + 7th bytes)

Start bit ACK bit (2)

Read/Write bit (Read)

SAR/W

Legend: D11:D00 = 12-bit data for MCP4726 device

D09:D00 = 10-bit data for MCP4716 device

VREF1 VREF0 A

RDY POR

Vol. Data bi ts (8 bits) (4t h byte)

b08 0b07 b06 b05 b04 b03 b02 b01 b00 0

0b15 b14 b13 b12 b11 b10 b09

Vol. Data bits (8 bits) (3rd byte)

ACK bit (3) ACK bit (3)

Note 1

Stop bit

A/N P

ACK/NACK bit (4)

NV Data bits (8 bits) (7th byte)

b08 0b07 b06 b05 b04 b03 b02 b01 b00 0/1

0b15 b14 b13 b12 b11 b10 b09

NV Data bits (8 bits) (6th byte)

ACK bit (3) ACK bit (3)

ACK bit (3)

PD1 PD0 G1

VREF1 VREF0

RDY POR

Vol. Vol. Configuration

Status

bits bits

Vol. NV Configuration

Status

bits bits

4: ACK/NACK bit generated by I2C Master.

MCP4706/4716/4726

FIGURE 6-6: Read Command Format for 8-bit DAC (MCP4706).

Device Addressing Vol. Data bits (8 bits) (3rd byte)

Note 1:

Note 1

The 2nd-5th bytes can be repeated after the 5th byte by continued clocking before issuing Stop bit.

Vol.

2: ACK bit generated by MCP47X6.

b07 b06 b05 b04 b03 b02 b01 b00

MCP4706 D07 D06 D05 D04 D03 D02 D01 D00

SDA

SCL

A2 A1 A01100 1 0 PD1 PD0 G 0b07 b06 b05 b04 b03 b02 b01 b00 0

Vol. Configuration

Data bits (8 bits) (3rd and 5th bytes)

Start bit ACK bit (2)

Read/Write bit (Read)

Stop bit

SAR/W A A

Status

ACK bit (3) ACK bit

(3)

Legend: D07:D00 = 8-bit data for MCP4706 device

VREF1 VREF0

A/N P

ACK/NACK bit (4)

RDY POR

NV Data bits (8 bits) (5th byte)

0b07 b06 b05 b04 b03 b02 b01 b00 0/1

ACK bit (3)

PD1 PD0 G1

VREF1 VREF0

RDY POR

Vol. NV Configuration

Status

bits bits

3: ACK bit generated by I2C™ master.

4: ACK/NACK bit generated by I2C™ master.

MCP4706/4716/4726

6.6 I2C General Call Commands

The device acknowledges the General Call Address

command (0x00 in the first byte). The meaning of the

general call address is always specified in the second

byte. The I2C specifica tion does not al low “00000000”

(00h) in the second byte. Please refer to the Phillips I2C

document for more details on the General Call

specifications.

The MCP47X6 devices support the following I2C

general calls :

• General Call Reset

• General Call Wake-Up

6.6.1 GENERAL CA LL RESET

The d evic e pe rform s Ge nera l Cal l Re set if th e se cond

byte is “00000110” (06h). At the acknowledgement of

this byte, the device will abort the current conversion

and perfor m the fol lowi ng tasks:

• Internal Rese t similar to a Power-on Re set (POR).

The contents of the EEPROM are loaded into the

DAC registers and analog output is available

immediately.

• This is a similar event to the POR. The VOUT will

be available immediately, but after a short time

delay following the Acknowledgement pulse. The

VOUT value is determined by the EEPROM

contents.

This c ommand allows m ultiple MCP47X6 de vices t o be

reset synchronously.

FIGURE 6-7: General Call Reset Command.

General Call Address

Note 1: At the falling edge of the SCL at the end of this ACK pulse a Reset occurs (start-up timer starts and DAC register

Note 1

2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit.

General Call Reset Command

3: ACK bit generated by MCP47X 6.

Note 2

SDA

SCL

0000000 0000 0

Start bit ACK bit (3)

Read/Write bit (Write)

Stop bit

SAR/W A

ACK bit (3)

00110

latched).

MCP4706/4716/4726

6.6.2 GENERAL CALL WAKE-UP

If the second byte is “00001001” (09h), the device

forces the volatile power-down bits to ‘00’. The

nonvolatile (EEPROM) power-down bit values are not

affected by this co mmand.

This command allows multiple MCP47X6 devices to

wake-up synchronously.

FIGURE 6-8: General Call Wake-Up Command.

Note: This comm and do es no t adhere to the I2C

specification where if the LSb of the 2nd

byte is a ‘1’, it is a ‘Hardw are General Ca ll’

(see the NXP I2C Specification).

General Call Address

Note 1: At the falling edge of the SCL, at the end of this ACK pulse, the volatile PD1:PD0 bits are forced to ‘00’.

Note 1

2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit.

General Call Wake-Up

3: ACK bit generated by MCP47X6.

Note 2

SDA

SCL

0000000 0000 0

Start bit ACK bit (3)

Read/Write bit (Write)

Stop bit

SAR/W A

ACK bit (3)

01001

Command

MCP4706/4716/4726

NOTES:

MCP4706/4716/4726

7.0 TERMINOLOGY

7.1 Resolution

The resol uti on is the num be r of DA C outp ut s t ate s th at

divide the full-scale range. For the 12-bit DAC, the

resoluti on is 212, m eaning th e DAC cod e ranges f rom 0

to 4095.

7.2 Least Significant bit (LSb)

Normally this is thought of as the ideal voltage

difference between two successive codes. This bit has

the smallest val ue or weight of all bits in the register.

For a given output voltage range, which is typically the

voltage between the Full-Scale voltage and the Zero-

Scale v oltage (VOUT(FS) - VOUT(ZS)), it is d ivide d b y th e

resolution of the device (Equation 7-1).

EQUATION 7-1: LSb VOLTAGE

CALCULATION

7.3 Monotonicity

Normally this is thought of as the VOUT v oltage never

decreasing, as the DAC register code is continuously

incremented by 1 code step (LS b).

7.4 Full-Scale Error (FSE)

The Full-Scale error (see Figure 7-4) is the sum of

Off set error plus Gai n error . It i s the dif ference b etween

the ide al and meas ured DAC ou tput volta ge with a ll bits

set to one (DAC input code = FFFh for 12-bit DAC).

EQUATION 7-2: FULL-SCALE ERROR

7.5 Zero-Scale Error (ZSE)

The Zero-Scale error (see Figure 7-4) is the difference

betwee n the idea l and mea sured VOUT voltag e with th e

volatile DAC register equal to 000h. The Zero-Scale

error is the same as the Offset error for this case

(volatile DAC register = 000h).

EQUATION 7-3: ZERO-SCALE ERROR

7.6 Offset Error

The Offset error (see Figure 7-1) is the deviation from

zero voltage output when the volatile DAC register

value = 000h (zero scale voltage). This error affects all

codes by the same amount. The Offset error can be

calibrated by software in application circuits.

FIGURE 7-1: Offset Error Example.

VLSb = VOUT(FS) - VOUT(ZS)

2N - 1

2N = 4096 (MCP4726)

1024 (MCP4716)

256 (MCP4706)

FSE = VOUT(@FS) - VIDEAL(@FS)

VLSb

Where:

FSE is exp re sse d i n LSb

VOUT(@FS) is the VOUT voltage when the DAC

VIDEAL(@FS) is the ide al out put voltage when the

DAC regist er code is at Full-s cale.

VLSb is the delta voltage of one DAC re gi st er code

step (su ch as code 000h to co de 001h).

ZSE = VOUT(@ZS)

VLSb

Where:

FSE is exp re sse d i n LSb

VOUT(@ZS) is the VOUT voltage when the DAC

regist er code is at Zero-scale.

VLSb is the delta voltage of one DAC re gi st er code

step (su ch as code 000h to co de 001h).

Analog

Output

Ideal Transfer Function

Actual Transfer Function

DAC Input Code

Offset

Error

(ZSE)

MCP4706/4716/4726

7.7 Integral Nonlinearity (INL)

The Integral Nonlinearity (INL) error is the maximum

deviation of an actual transfer function from an ideal

transfer function (straight line).

In the MCP47X6, INL is calculated using two end points

(zero and full scale). INL can be expressed as a per-

centage of full scale range (FSR) or in a fraction of an

LSb. INL i s al so cal led rela tive acc uracy. Equation 7-4

shows how to calculate the INL error in LSb and

Figure 7-2 shows an example of INL accuracy.

EQUATION 7-4: INL ERROR

FIGURE 7-2: INL Accuracy Exa mpl e.

7.8 Differenti a l N on lin e a r ity (DNL )

The D iffer ential No nlinea rity (DNL) error (see Figure 7-3)

is the measure of step size between codes in actual

transfer function. The ideal step size between codes is

1 LSb. A DNL err or of zero wo uld imply t hat ev ery code

is exactl y 1 LSb wide. If the DNL error is les s than 1 LSb,

the DAC ensures monotonic output and no missing

codes. The DNL error between any two adjacent codes

is ca lc ulated as f ol lo w s:

EQUATION 7-5: DNL ERROR

FIGURE 7-3: DN L Ac cu r acy Exa mpl e.

INL VOUT VIdeal

–()

LSb

---------------------------------------=

Where:

INL is expressed in LSb.

VIdeal = Code*LSb

VOUT = T he outp ut vol t ag e mea su red wi th

a given DAC input code

010001000

Analog

Output

(LSb)

DAC Input Code

011 111100 101

110

Ideal Transfer Function

Actual Transfer Function

INL = < -1 LSb

INL = 0.5 LSb

INL = - 1 LSb

DNL ΔVOUT LSb–

LSb

----------------------------------=

Where:

DNL is expressed in LSb.

ΔVOUT = The measured DAC output

voltage difference between two

adjacent input codes

010001000

Analog

Output

(LSb)

DAC Input Code

011 111100 101

DNL = 2 LSb

DNL = 0.5 LSb

110

Ideal T ransfer Function

Actual Transfer Function

MCP4706/4716/4726

7.9 Gain Error

The Gain error (see Figure 7-4) is the difference

between the actual full-scale output voltage from the

ideal output voltage of the DAC transfer curve. The

Gain error is calculated after nullifying the Offset error,

or Full-Scale error minus the Offset error.

The Gain error indicates how well the slope of the

actual transfer function matches the slope of the ideal

transfer function. The Gain error is usually expressed

as percent of full-scale range (% of FSR) or in LSb.

In the MCP4706/4716/4726, the Gain error is not

calibrated at the factory and most of the Gain error is

contributed by the output buffer (op amp) saturation

near the code range beyond 4000d. For the

applications that need the Gain error specification less

than 1% maximum, the user may consider using the

DAC code range between 100d and 4000d instead of

using full code range (code 0 to 4095d). The DAC

output of the code range between 100d and 4000d is

much more linear than full-scale range (0 to 4095d).

The Gai n e rror c an be ca lib rate d out by sof t wa re i n th e

application.

FIGURE 7-4: Gain Error and Fu ll-Scale

Error Example.

7.10 Gain Error Drift

The Gain error drift is the variation in Gain error due to

a change in ambient temperature. The Gain error drift

is typically expressed in ppm/oC.

7.11 Offset Error Drift

The Offset error drift is the variation in Offset error due

to a change in ambient temperature. The Offset error

drift is typically expressed in ppm/oC.

7.12 Settling Time

The Settli ng time is the time delay re quired for the VOUT

voltage to settle into its new output value. This time is

measure d from the star t of code tra nsition, to when th e

VOUT voltage is within the specified accuracy.

In the MCP47X6, the settling time is a measure of the

time delay until the VOUT voltage reaches within 0.5

LSb of its final value, when the volatile DAC register

changes from 400h to C00h.

7.13 Major-Code Transition Glitch

Major-code transition glitch is the impulse energy

injected into the DAC analog output when the code in

the DAC reg ister c hange s state. It is n ormally speci fie d

as the area of the glitch in nV-Sec, and is measured

when th e digit al co de is c hanged by 1 LSb a t the maj or

carry transition (Example: 011...111 to 100...

000, or 100... 000 to 011 ... 111).

7.14 Digital Feedthrough

The digital feed t h rou gh is the g litc h th at ap pears at the

analog out put ca used by coup ling from the digit al inp ut

pins of the device. The area of the glitch is expressed

in nV-Sec, and is measured with a full scale change

(Example: all 0s to all 1s and vice versa) on the digital

input pins. The digital feedthrough is measured when

the DAC is not being written to the output register.

7.15 Power-Supply Rejection Ratio

(PSRR)

PSRR indicates how the output of the DAC is affected

by changes in the supply voltage. PSRR is the ratio of

the change in VOUT to a change in VDD for full-scale

output of the DAC. The VOUT is measured while the

VDD is varied +/- 10%, and expressed in dB or µV/V.

Analog

Output

Actual Transfer Function

DAC Input Code

Gain Error

Ideal T ransfer Function

after Offset Error is removed

Full-Scale

Error

Zero-Scale

Error

MCP4706/4716/4726

NOTES:

MCP4706/4716/4726

8.0 TYPICAL APPLICATIONS

The MCP47X6 family of devices are general purpose,

single channel voltage output DACs for various

applications where a precision operation with

low-power and nonvolatile EEPROM memory is

needed.

Since the devices include a nonvolatile EEPROM

memory, the user can utilize these devices for

applications that require the output to return to the

previous set-up value on subsequent power-ups.

Applications generally suited for the devices are:

• Set Point or Offset Trimming

• Sensor Calibra tion

• Port ab le Instrum en t ati on (Batte ry Pow ere d)

• Mo tor Control

8.1 Connecting to I2C BUS using

Pull-Up Resistors

The SCL and SDA pins of the MCP47X6 devices are

open-drai n configura tions. Thes e pins requi re a pull-up

resistor as shown in Figure 8-2.

The pull-up resistor values (R1 and R2) for SCL and

SDA pins depend on the operating speed (standard,

fast, and high speed) and loading capacitance of the

I2C bus line. A higher value of the pull-up resistor

consumes less power, but increases the signal

transition time (higher RC time constant) on the bus

line. Therefore, it can limit the bus operating speed.

The low er re si sto r va lue, on the othe r hand, consu me s

higher power, but allows higher operating speed. If the

bus line has higher capacitance due to long metal

traces or multiple device connections to the bus line, a

smaller pull-up resistor is needed to compensate the

long RC time constant. The pull-up resistor is typically

chosen between 1 kΩ and 10 kΩ ranges for Standard

and Fast modes, and less than 1 kΩ for High-Speed

mode.

8.1.1 DEVICE CONNECTION TEST

The use r can test the presence o f the device on the I2C

bus l ine usi ng a simple I2C command. This test can be

achieved by checking an acknowledge response from

the device after sending a Read or Write command.

Figure 8-1 shows an example with a Read command.

The steps are:

a) Set the R/W bit “High” in the device’s address

byte.

b) Check the ACK bit of the address byte.

If the device acknowledges (ACK = 0) the

command, then the device is connected,

otherwi se it is not conne cte d.

c) Send Stop bit.

FIGURE 8-1: I2C Bus Connection Test.

123456789

SCL

SDA 1101A2 A1 A0 1

Start

Bit

Addr e ss Byte

Address bits

Device Code R/W

Stop

Bit

Device

ACK

Response

MCP4706/4716/4726

8.2 Power Supply Considerations

The pow e r s ourc e should be as clean as p os si ble . Th e

power supply to the device is also used for the DAC

voltage reference internally if the internal VDD is

selected as the resistor ladder’s reference voltage

(VREF1:VREF0 = 00 or 01).

Any noise induced on the VDD line can affect the DAC

perfor mance . Typical app licati ons will require a byp ass

capacitor in order to filter out high-frequency noise on

the VDD li ne. Th e noi se can be induced onto the po w er

supply’s traces or as a result of changes on the DAC

output. The bypass capacitor helps to minimize the

effect of these noise sources on signal integrity.

Figure 8-2 shows an example of using two bypass

capacitors (a 10 µF tantalum capacitor and a 0.1 µF

ceramic capacitor) in parallel on the VDD line. These

cap acitors shou ld b e p lac ed as close to the VDD pin as

possible (within 4 mm). If the application circuit has

separate digital and analog power supplies, the VDD

and VSS pi ns of t he dev ice shou ld reside on the analo g

plane.

FIGURE 8-2: Example MCP47X6 Circuit

with SOT-23 package.

Analog

VDD

SDA

SCL

OUT

R1 R2

To MCU

R1 and R2 are I2C™ pull-up resistors:

R1 and R2:

5kΩ - 10 kΩ for fSCL =100 kHz to 400 kHz

~700Ω fo r fSCL =3.4 MHz

C1: 0.1 µF capacitor Ceramic

C2: 10 µF capacitor Tantalum

C3: ~ 0.1 µF Optional to reduce noise

in VOUT pin.

C4: 0.1 µF capacitor Ceramic

C5: 10 µF capacitor Tantalum

MCP47X6

Optional

(a) Circuit when VDD is selected as reference

(Note: VDD is connected to the reference circuit internally.)

(b) Circuit when external reference is used.

Output

REF

Analog

VDD

SDA

SCL

OUT

R1 R2

To MCU

MCP47X6

Optional

Output

REF

Optional

REF

Note: Pin assignment is opposite in DFN-6 package.

MCP4706/4716/4726

8.3 Application Examples

The MCP47X6 devices are rail-to-rail output DACs

designed to operate with a VDD range of 2.7V to 5.5V.

The internal output op amplifier is robust enough to

drive common, small-signal loads directly, thus

eliminating the cost and size of external buffers for

most applications. The user can use gain of 1 or 2 of

the output op amplifier by setting the Configuration

reference or use external reference. Various user

options and easy-to-use features make the devices

suitable for various modern DAC applications.

Application examples include:

• Decreasing Output Step Size

• Building a “Window” DAC

• Bipolar Operation

• Select ab le Ga in and Of fset Bipolar Voltage Outp ut

• Designing a Double-Precision DAC

• Building Programmable Current Source

• Ser ial Interface Communi c ation Times

• Software I2C Interface Reset Sequence

• Power Supply Considerations

• Layout Co ns ide rati ons

8.3.1 DC SET POINT OR CALIBRATION

A common application for the devices is a

digitally-controlled set point and/or calibration of

variable parameters, such as sensor offset or slope.

For example, the MCP4726 provides 4096 output

steps. If voltage reference is 4.096V, the LSb size is

1 mV. If a smaller output step size is desired, a lower

external voltage reference is needed.

8.3.1.1 Decreasing Output Step Size

If the application is calibrating the bias voltage of a

diode or tran sistor , a bia s voltage range of 0.8V may be

desired with about 200 µV resolution per step. Two

common methods to achieve small step size are using

lower VREF p in volt age or using a volt age divi der on the

DAC’s output.

Using an external voltage reference (VREF) is an

option, if the external reference is available with the

desired output voltage range. However, occasionally,

when using a low-voltage reference voltage, the noise

floor causes a SNR error that is intolerable. Using a

voltage divider method is another option, and provides

some advantages when external voltage reference

needs to be very low, or when the desired output

voltage is not available. In this case, a larger value

reference voltage is used, while two resistors scale the

output range down to the precise desired level.

Figure 8-3 illustrates this concept. A bypass capacitor

on the output of the voltage divider plays a critical

function in a ttenuat ing th e o utput n oise of the DAC an d

the induced noise from the environment.

FIGURE 8-3: Example Circuit Of Set Point

or Threshold Calibration.

EQUATION 8-1: VOUT AND VTRIP

CALCULATIONS

VCC+

VCC–

VOUT

I2C™

2-wire

VREF

Optional

MCP47X6

VDD

VOR2C1

RSENSE

Comp.

VDD

VTRIP

Vtrip VOUT

R1R2

--------------------

⎝⎠

⎜⎟

⎛⎞

VOUT = VREF • G • DAC Register Value

MCP4706/4716/4726

8.3.1.2 Building a “Window” DAC

When calibrating a set point or threshold of a sensor,

typica lly only a sma ll portion of the DAC outp ut range is

utilized. If the LSb size is adequate enough to meet the

application’s accuracy needs, the unused range is

sacrificed without consequences. If greater accuracy is

needed, then the output range will need to be reduced

to increase the resolution around the desired threshold.

If the threshold is not near VREF, 2 • VREF, or VSS, then

creating a “window” around the threshold has several

advantages. One simple method to create this “window”

is to use a voltage divider network with a pull-up and

pull-down resistor. Figure 8-4 and Figure 8-6 illustrate

this concept.

FIGURE 8-4: Single-Supply “Window”

DAC.

EQUATION 8-2: VOUT AND VTRIP

CALCULATIONS

8.4 Bipolar Operation

Bipolar operation is achievable by utilizing an external

operational amplifier. This configuration is desirable

due to the w ide variety and avai lability of op amp s. This

allows a general purpose DAC, with its cost and

availability advantages, to meet almost any desired

output voltage range, power and noise performance.

Figure 8-5 illustrates a simple bipolar voltage source

configuration. R1 and R2 allow the gain to be selected,

while R3 and R4 shift the DAC's output to a selected

of fset. Note that R4 can be tied to V DD, ins tea d o f VSS,

if a higher offset is desired.

FIGURE 8-5: Digitally-Controlled Bipolar

Voltage Source Example Circuit.

EQUATION 8-3: VOUT, VOA+, AND VO

CALCULATIONS

VCC+

VCC–

I2C™

2-wire

VREF

Optional

MCP47X6

VDD

VOUT R2C1

VCC+

VCC–

RSENSE

Comp.

VTRIP

R23 R2R3

R2R3

-------------------=

V23 VCC+R2

()VCC-R3

()+

R2R3

------------------------------------------------------=

VTRIP VOUTR23 V23R1

R1R23

---------------------------------------------=

Thevenin

Equivalent

R23

V23

VOUT VTRIP

VOUT = VREF • G • DAC Register Value

VCC+

VCC–

I2C™

2-wire

VREF

Optional

MCP47X6

VDD

VOUT

VIN R1

R4C1

VOA+

VOA+ = VOUT • R4

R3 + R4

VOUT = VREF • G • DAC Register Value

VO = VOA+ • ( 1 + ) - VDD • ( )

MCP4706/4716/4726

8.5 Selectabl e Gain and Offset Bipolar

Voltage Output

In some applications, precision digital control of the

output range is desirable. Figure 8-6 illustrates how to

use the DAC devices to achieve this in a bipolar or

single-supply application.

This circuit is typically used for linearizing a sensor

whose slope and offset varies.

The equation to design a bipolar “window” DAC would

be utilized if R3, R4 and R5 are populated.

8.5.1 BIPOLAR D A C EXAMPLE USING

MCP4726

An output step size of 1 mV, with an output range of

±2.05V, is desired for a particular application.

S tep 1: Ca lc ula te th e ra nge : +2. 05V – (-2.0 5V) = 4 .1V.

Step 2: Calculate the resolution needed:

4.1V/1 mV = 4100

Since 212 = 4096, 12-b it resolution is desired.

Step 3: The amplifier gain (R2/R1), multiplied by

full-scale VOUT (4.096V), must be equal to the

desired minimum output to achieve bipolar

operation. Since any gain can be realized by

choosing resistor values (R1+R2), the VREF value

must be se lecte d first. If a VREF of 4.096V is used,

solve f or th e am pl ifi er’s gai n b y s ett ing the D AC to

0, knowing that the output needs to be -2.05V.

The equatio n can be sim pl ifi ed to:

S tep 4: Next, solve for R3 and R4 by s etting th e DAC to

4096, k nowing th at the outp ut nee ds to be +2.05V.

FIGURE 8-6: Bi po lar Voltage Source with

Selectable Gain and Offset.

EQUATION 8-4: VOUT, VOA+, AND VO

CALCULATIONS

EQUATION 8-5: BIPOLAR “WINDOW” DAC

USING R4 AND R5

–

---------2.05–

4.096V

-----------------=

If R1 = 20 kΩ and R2 = 10 kΩ, the gain will be 0.5.

------1

---=

R3R4

+()

------------------------2.05V 0.5 4.096V

⋅

()+

1.5 4.096V

⋅

------------------------------------------------------- 2

---==

If R4 = 20 kΩ, then R3 = 10 kΩ

R3VCC+

VCC–

VOUT

I2C™

2-wire

VREF

Optional

MCP4726

VDD

VIN R1

R4C1

Optional

VOA+

VCC+

VCC–

C1 = 0.1 µF

Offset Adjust Gain Adjust

VOUT = VREF • G • DAC Register Value

VOA+ = VOUT • R4 + VCC- • R5

R3 + R4

VO = VOA+ • ( 1 + ) - VIN • ( )

Thevenin

Equivalent V45 VCC+R4VCC-R5

R4R5

---------------------------------------------=

VIN+ VOUTR45 V45R3

R3R45

---------------------------------------------=

R45 R4R5

R4R5

-------------------=

VOVIN+ 1R2

------+

⎝⎠

⎛⎞

VAR2

------

⎝⎠

⎛⎞

–=

Offset Adjust Gain Adjust

MCP4706/4716/4726

8.6 Designing a Double-Precision

DAC

Figure 8-7 shows an example design of a single-supply

voltage output capable of up to 24-bit resolution. This

requires two 12-bit DACs. This design is simply a

voltage divider with a buffered output.

As an example, if a similar application to the one

developed in Section 8.5.1 “Bipolar DAC Example

Using MCP4 726” required a re solution of 1 µV instea d

of 1 mV, and a range of 0V to 4.1V, then 12-bit

resolution would not be adequate.

Step 1: Calculate the resolution needed:

4.1V/1 µV = 4.1 x 106. Since 222 =4.2x10

22-bit resolution is desired. Since

DNL = ±0.75 LSb, this design can be attempted

with the 12-bit DAC.

Step 2: Since DACB’s VOUTB h as a res ol uti on o f 1 mV,

it s outpu t only ne eds to be “pul led” 1/1 000 to me et

the 1 µV target. Dividing VOUTA by 1000 would

allow the application to compensate for DACB’s

DNL error.

Step 3: If R2 is 100Ω, then R1 needs to be 100 kΩ.

Step 4: The resulting transfer function is shown in the

equation of Example 8-6.

FIGURE 8-7: Simple Double Precision

DAC using MCP4726.

EQUATION 8-6: VOUT CALCULATION

8.7 Building Programmable Current

Source

Figure 8-8 shows an example of building a

progra mmab le current source us ing a volt age followe r.

The curren t se ns or res is tor i s used to convert t he DA C

voltage output into a digitally-selectable current source.

The smaller RSENSE is, the less power dissipated

across it. However , this also reduces the resolution that

the current can be controlled.

FIGURE 8-8: Digitally-Controlled Current

Source.

R1VCC+

VCC–

VOUT

I2C™

2-wire

VREF

Optional

MCP4726 (A)

VDD

I2C™

2-wire

VREF

Optional

MCP4726 (B)

VDD

0.1 µF

VOA

VOB

VOUT =

G = Selected Op Amp Gain

VOA * R2 + VOB * R1

R1 + R2

VOA = (VREF * G * DAC A Register Value)/4096

VOB = (VREF * G * DAC B Register Value)/4096

Where:

RSENSE

Load

VCC+

VCC–

VOUT

ILVOUT

Rsense

---------------

-------------

IbIL

----=

β = Common-Emitter Current Gain. where

VDD

I2C™

2-wire

VREF

Optional

MCP47X6

VDD

(or VREF)

MCP4706/4716/4726

8.8 Serial Interface Communication

Times

Table 8-1 shows time/frequency of the supported

operations of the I2C serial interface for the different

serial interface operational frequencies. This, along

with the VOUT output performance (such as slew rate),

would be used to determine your application’s volatile

DAC register update rate.

TABLE 8-1: SERIAL INTERFACE TIMES / FREQUENCIES

Command Writes V olatile

Memory? Wri te s EE PROM

Memory?

# of

Serial

Inter-

face Bits

(2)

Command Time (uS) Command Frequency

(kHz)

Code

Function C2 C1 C0 Config. DAC Config. DAC 100

kHz 400k

Hz 3.4

MHz 100

kHz 400

kHz 3.4

MHz

00XWrite

Volatile DAC Yes(1) Yes No No 29 290 72.5 8.5 3.4 13.8 117.2

010Write

Volatile

Memory

Yes Yes No No 38 380 95 11.2 2.6 10.5 89.5

0 1 1 Write All

Memory Yes Yes Yes Yes 38 380 95 11.2 2.6 10.5 89.5

100Write NV

Configura-

tion Bi ts

Yes No No No 20 200 50 5.9 5.0 20.0 170.0

N/A Read N/A N/A N/A N/A 77 750 187.5 22.1 1.3 5.3 45.3

Note 1: Only the volatile PD1:PD0 bits of the Configuration bits are written.

2: Includes the Start or Stop bits.

MCP4706/4716/4726

8.9 Software I2C Interface Reset

Sequence

At times, it may become necessary to perform a

Software Reset Sequence to ensure the MCP47X6

device is in a correct and known I2C interface state.

This technique only resets the I2C state machine.

This is useful if the MCP47X6 device powers up in an

incorrect state (due to excessive bus noise, etc), or if

the master device is reset during communication.

Figure 8-9 shows the communication sequence to

software reset the device.

FIGURE 8-9: Software Reset Sequence

Format.

The 1st Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

master device. In this mode, the device is monitoring

the data bus in Receive mode and can detect if the

Start bit forces an internal Reset.

The nine bits of ‘1’ are used to force a Reset of those

device s that cou ld not be res et by the prev ious S tar t bit.

This occurs only if the MCP47X6 is driving an A bit on

the I2C bus, or is in Output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I2C

bus. In both of thes e case s, the previo us Start bi t could

not be generat ed due to the MC P47X6 hol ding the bu s

low. By sending out nine ‘1’ bits, it is ensur ed that the

device will see an A bit (the master device does not

drive the I2C bus low to acknowledge the data sent by

the MCP47X6), which also forces the MCP47X6 to

reset.

The 2nd Start bit is sent to address the rare possibility

of an erroneous write. This could occur if the master

device was reset while sending a Write command to th e

MCP47X6, AND then as the master device returns to

normal operation a nd issues a S tart condition, whi le the

MCP47X6 is issuing an acknowledge. In this case, if

the 2nd Start bit is not sent (and the Stop bit was sent)

the MCP47X6 could initiate a write cycle.

The S top bit terminate s the current I2C bus a ctivity. The

MCP47X6 waits to detect the next Start condition.

This sequence does not effect any other I2C devices

which may be on the bus, as they should disregard this

as an invalid command.

Note: This techn ique i s docu mente d in AN 1028.

S‘1’‘1’‘1’‘1’‘1’‘1’‘1’‘1’ S P

Start

bit

Nine bits of ‘1’

Start bit

Stop bit

Note: The potential for this erroneous write

ONLY oc cur s if the mas ter de vice is rese t

while sending a Write command to the

MCP47X6.

MCP4706/4716/4726

8.10 Design Considerations

In the de sign of a syst em with the MCP4706/4716 /4726

devices, the following considerations should be taken

into accou nt:

•Power Supply Conside ration s

•Layout Considerations

8.10.1 POW ER SUP PLY

CONSIDERATIONS

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-10 illustrates an

appropria te bypass strategy.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close (within 4 mm) to the device power pin (VDD) as

possible.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, VDD and

VSS should reside on the analog plane.

FIGURE 8-10: Typical Mic roc ont ro ll er

Connections.

8.10.2 LAYOUT CONSIDERATIONS

Several layout considerations may be applicable to

your application. These may include:

•Noise

•PCB Area Requirements

8.10.2.1 Noise

Inductively-coupled AC transients and digital switching

noise c an degra de the in put and output s ignal integri ty,

potentially masking the MCP47X6’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Nois e Ratio (SNR). Multi-layer

boards utilizing a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are crit ical to achieving the per formance that the sili con

is capable of providing. Particularly harsh

environments may require shielding of critical signals.

Separate digital and analog ground planes are

recommended. In this case, the VSS pin and the groun d

pins of the VDD capacitors should be terminated to the

analog ground plane.

8.10.2.2 PCB Area Requirements

In some applic ations , PCB area is a crit eria for de vice

selection. Table 8-2 shows the typical package

dimens ion s a nd are a fo r the different packa ge opti ons .

The tab le also sh ows the relati ve area fac tor comp ared

to the sm allest are a. For sp ace critic al applicati ons, the

DFN package would be the suggested package.

VDD

VSS VSS

MCP47X6

0.1 µF

PIC® Microcontroller

0.1 µF

SCL

VOUT

VREF SDA

Note: Breadboards and wire-wrapped boards

are not recommended.

TABLE 8-2: PACKAGE FOOTPRINT (1)

Package Package Footprint

Pins

Type Code

Dimensions

(mm)

Area (mm2)

Relative Area

Length Width

6 SOT-23 CH 2.90 2.70 7.83 1.96

6 DFN MAY 2.00 2.00 4.00 1

Note 1: Does not include recommended land

pattern dimensions. Dimensions are

typical values.

MCP4706/4716/4726

NOTES:

MCP4706/4716/4726

9.0 DEVELOPME NT SUPPORT

Development supp ort can be classified into two group s.

These are:

• Development Tools

• Technical Documentation

9.1 Development Tools

Several development tools are available to assist in

your design and evaluation of the MCP47X6 devices.

The currently available tools are shown in Table 9-1.

These boards may be purchased directly from the

Microchip web site at www.microchip.com.

9.1.1 MCP47X6 PICtail™ PLUS

DAUGHTER BOARD

The MCP47X6 PICtail™ Plus Daughter Board (order

number: ADM00317) is available from Microchip

Technology Inc. This board works with Microchip’s

PICkit™ Serial Analyzer and PIC® Explorer 16

Development Board. The firmware example is also

available for the Explorer 16 Development Board with

PIC24FJ128.

Figure 9-1 shows the MCP47X6 PICtail™ Plus

Daughter Board being used with a PIC® Explorer 16

Devel opment Bo ard (ord er num ber: ADM0 0317), while

Figure 9-2 shows the MCP47X6 PICtail™ Plus

Daughter Board being used with a PICkit™ Serial

Analyzer. The PICkit™ Serial Analyzer allows the user

to quickly evaluate the DAC operation. Refer to the

“MCP47X6 PICtail™ Plus Daughter Board User’s

Guide” (DS51932) for detailed descriptions on

operating the daughter board.

Refer to www.microchip.com for further information on

this product and related material for the users.

FIGURE 9-1: MCP47X6 PICtail ™Plus

Daughter Board with PIC® Explorer 16

Development Board.

FIGURE 9-2: MCP47X6 PICtail™ Plus

Daughter Board with PICkit™ Serial Analyzer.

MCP47X6 PICtail™ Plus Explorer 16

Daugh ter Board

inserted into PICtail™ Connector

Development Board

MCP47X6 PICtail™ Plus Daughter Board

TABLE 9-1: DEVELOPMENT TOOLS

Board Name Part # Supported Devices

SC70-6 and SOT-23-6/8 to DIP-8 Evaluation Board SC70EV MCP4706, MCP4716, MCP4726

MCP47X6 PICtail™ Plus Da ug ht e r B o ar d E v al ua t ion

Board(1, 2) ADM00317 MCP47X6

Note 1: Requires a PICDEM™ Demo board. See the User’s Guide for additional information and requirements.

2: Requires a PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements.

MCP4706/4716/4726

9.2 Technical Documentation

Several ad ditional technical docume nts are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs, and Design Guides. Table 9-2 shows

some of these documents.

TABLE 9-2: TECHNICAL DOCUMENTATION

Application

Note Number Title Literature #

AN1326 Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications DS01326

— Signal Chain Design Guide DS21825

— Analog Solutions for Automotive Applications Design Guide DS01005

MCP4706/4716/4726

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu me ric trac ea bil ity code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb- free JEDEC desig nator ( )

can be found on the outer packaging for this package.

Note: In the even t the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Address

Option Code

MCP4706A0T-E/CH MCP4716A0T-E/CH MCP4726A0T-E/CH

A0 (00) DBNN DFNN DKNN

A1 (01) DCNN DGNN DLNN

A2 (10) DDNN DHNN DMNN

A3 (11) DENN DJNN DPNN

Address

Option Code

MCP4706A0T-E/MAY MCP4716A0T-E/MAY MCP4726A0T-E/MAY

A0 (00) AAA AAE AAP

A1 (01) AAB AAF AAQ

A2 (10) AAC AAG AAR

A3 (11) AAD AAH AAS

6-Lead SO T-23 Examp le

XXNN

DC25

6-Lead DFN (2x2x0.9 mm) Example

AAB

256

PIN 1 PIN 1

MCP4706/4716/4726





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    

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    

    

   

    

    

PIN 1 ID BY

LASER MARK

123

A2 c

   

MCP4706/4716/4726

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP4706/4716/4726

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP4706/4716/4726

APPENDIX A: REVIS I ON HISTORY

Revision C (April 2012)

The following is the list of modifications:

1. Updated the layout of the Absolute Maximum

Rating page.

2. Added three new sections, Section 4.4.3

“Output Slew Rate”, Section 4.4.4 “Small

Capacitive Load” and Section 4.4.5 “Large

Capacitive Load”.

3. Enhanced former Section 4.4.3 (now

Section 4.4.6 “Driving Resistive and

capacitive Loads”).

4. Updated the descriptive information related to

the ACK bit in FIGURE 6-5: “Read Command

Format for 12-bit DAC (MCP4726) and 10-bit

DAC (MCP4716).”

5. Corrected DFN package code and drawings to

MAY code (from MA code). Both MA and MAY

have the same dimensions/footprint.

Revision B (September 2011)

The following is the list of modifications:

1. Updated references to graphics and equations

in the text.

2. Updated notes in FIGURE 6-6: “Read

Command Format for 8- bit DAC (MCP4706).”

Revision A (February 2011)

• Original Rele ase of this Document .

MCP4706/4716/4726

NOTES:

MCP4706/4716/4726

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP4706: Single Channel 8-Bit DAC

with EEPROM Memory

MCP4716: Single Channel 10-Bit DAC

with EEPROM Memory

MCP4726: Single Channel 12-Bit DAC

with EEPROM Memory

Address Options: A0 = “1100000” I2C Address.

Devices ordered from the Microchip

Sample center will have this address.

A1 = “1100001” I2C Address.

A2 = “1100010” I2C Address.

A3 = “1100011” I2C Address.

A4 = “1100100” I2C Address.

A5 = “1100101” I2C Address.

A6 = “1100110” I2C Address.

A7 = “1100111” I2C Address.

Tape and Reel: T = Tape and Reel

Temperature

Range: E = -40°C to +125°C

Package: CH = Plastic Small Outline Transistor

(SOT-23-6), 6-lead

MAY= Plastic Dual Flat, No Lead Package

(2x2 DFN), 6-lead

Examples:

a)MCP4706A0T-E/CH: 8-bit VOUT resolution,

I2C Address “1100000”,

Tape and Reel, Extended

Temp., 6LD SOT-23 pkg.

b)MCP4706A6T-E/CH: 8-bit VOUT resolution,

I2C Address “1100110”,

Tape and Reel, Extended

Temp., 6LD SOT-23 pkg.

c) MCP4706A0T -E/MAY: 8-bit VOUT resolution,

I2C Address “1100000”,

Tape and Reel, Extended

Temp., 6LD DFN pkg.

d)MCP4706A6T-E/MAY: 8-bit VOUT resolution,

I2C Address “1100110”,

Tape and Reel, Extended

Temp., 6LD DFN pkg.

a)MCP4716A0T-E/CH: 10-bit VOUT resolution,

I2C Address “1100000”,

Tape and Reel, Extended

Temp., 6LD SOT-23 pkg.

b)MCP4716A6T-E/CH: 10-bit VOUT resolution, I2C

Address “1100110”, Tape

and Reel, Extended

Temp., 6LD SOT-23 pkg.

c) MCP4716A0T-E/MAY: 10-bit VOUT resolution,

I2C Address “1100000”,

Tape and Reel, Extended

Temp., 6LD DFN pkg.

d)MCP4716A6T-E/MAY: 10-bit VOUT resolution,

I2C Address “1100110”,

Tape and Reel, Extended

Temp., 6LD DFN pkg.

a)MCP4726A0T-E/CH: 12-bit VOUT resolution,

I2C Address “1100000”,

Tape and Reel, Extended

Temp., 6LD SOT-23 pkg .

b)MCP4726A6T-E/CH: 12-bit VOUT resolution,

I2C Address “1100110”,

Tape and Reel, Extended

Temp., 6LD SOT-23 pkg.

c) MCP4726A0T-E/MAY: 12-bit VOUT resolution,

I2C Address “1100000”,

Tape and Reel, Extended

Temp., 6LD DFN pkg.

d)MCP4726A6T-E/MAY: 12-bit VOUT resolution,

I2C Address “1100110”,

Tape and Reel, Extended

Temp., 6LD DFN pkg.

PART NO. XXX

Address Temperature

Range

Device

/XX

Package

Options

Tape and

Reel

MCP4706/4716/4726

NOTES:

Information contained in this publication regarding device

applications and the lik e is p rovided on ly for yo ur c on ve n ien ce

and may be superseded by updates . I t is y our respo ns ibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPL AB, PIC , PI Cmi cro, PI CSTART,

PIC32 logo, rfPIC and UNI/O are registered trademark s of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLA B, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance , TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-62076-16 1-8

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in t he

intended manner and under normal conditions.

• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hoppin g

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

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11/29/11

PCN # SYST-03CSRF021

03 Apr 2012

Data Sheet - MCP4706/4716/4726 Data Sheet Data Sheet Document Revision

Attachments:

MCP4706/4716/4726 Data Sheet

Please contact your local Microchip sales office with questions or concerns regarding this

notification.

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SYST-03CSRF021

Microchip has released a new DeviceDoc for the MCP4706/4716/4726 Data Sheet of devices. If

you are using one of these devices please read the document located at MCP4706/4716/4726

Data Sheet.

Notification Status: Final

Description of Change: -Updated layout of Absolute Maximum Rating page -Added 3 new

sections, Section 4.4.3 “Output Slew Rate”, Section 4.4.4 “Small Capacitive Load” and Section

4.4.5 “Large Capacitive Load”. -Enhanced former Section 4.4.3 (now Section 4.4.6 “Driving

Resistive and capacitive Loads”) -Corrected DFN package code and drawings to MAY code (from

MA code). Both MA and MAY have the same dimensions/footprint.

Pre Change: N/A

Post Change: N/A

Impacts to Data Sheet: None

Reason for Change: To Improve Productivity

Change Implementation Status: Complete

Date Document Changes Effective: 03 Apr 2012

NOTE: Please be advised that this is a change to the document only the product has not been

changed..

Markings to Distinguish Revised from Unrevised Devices:N/A

PCN # SYST-03CSRF021

products or services."