Product Folder Order Now Technical Documents Support & Community Tools & Software TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 TI PanelbusTM Digital Receiver 1 Features 3 Description * * The Texas Instruments TFP401A-Q1 device is a TI PanelbusTM flat-panel display product, and is part of a comprehensive family of end-to-end DVI 1.0compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP401A-Q1 device finds applications in any design requiring highspeed digital interface. 1 * * * * * * * * * * * Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 3: -40C to 85C Ambient Operating Temperature Range - Device HBM ESD Classification Level H2 - Device CDM ESD Classification Level C3B Supports Pixel Rates Up to 165 MHz (Including 1080p and WUXGA at 60 Hz) Digital Visual Interface (DVI) Specification Compliant(1) True-Color, 24-Bit/Pixel, 16.7M Colors at 1 or 2 Pixels per Clock Laser-Trimmed Internal Termination Resistors for Optimum Fixed Impedance Matching Skew Tolerant Up to One Pixel-Clock Cycle 4x Oversampling Reduced Power Consumption - 1.8-V Core Operation With 3.3-V I/Os and Supplies(2) Reduced Ground Bounce Using Time-Staggered Pixel Outputs Low Noise and Good Power Dissipation Using TI PowerPADTM Packaging Advanced Technology Using TI 0.18-m EPIC-5TM CMOS Process TFP401A-Q1 Incorporates HSYNC Jitter Immunity(3) (1) The TFP401A-Q1 device incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal. (2) The TFP401A-Q1 device has an internal voltage regulator that provides the 1.8-V core power supply from the external 3.3-V supplies. (3) The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays. The TFP401A-Q1 is compliant with the DVI Specification Rev. 1.0. The TFP401A-Q1 device supports display resolutions up to 1080p and WUXGA in 24-bit true-color pixel format. It also offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time-staggered pixel outputs for reduced ground bounce. PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultralow ground inductance. The TFP401A-Q1 combines Panelbus circuit innovation with TI's advanced 0.18-m EPIC-5TM CMOS process technology, along with TI PowerPAD package technology to achieve a reliable, lowpowered, low-noise, high-speed digital interface solution. Device Information(1) PART NUMBER TFP401A-Q1 PACKAGE BODY SIZE (NOM) PQFP (100) 14.00 mm x 14.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. TFP401 Diagram 2 Applications Copyright (c) 2017, Texas Instruments Incorporated * * * * * (4) High-Definition TV HD PC Monitors Digital Video HD Projectors DVI/HDMI Receiver HDMI video-only 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 7 1 1 1 2 3 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 DC Digital I/O Electrical Characteristics.................... 7 DC Electrical Characteristics .................................... 7 AC Electrical Characteristics..................................... 7 Timing Requirements ............................................... 8 Switching Characteristics ........................................ 10 Typical Characteristics .......................................... 11 Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Application ................................................. 17 9 Power Supply Recommendations...................... 21 9.1 9.2 9.3 9.4 DVDD ...................................................................... OVDD...................................................................... AVDD ...................................................................... PVDD ...................................................................... 21 21 21 21 10 Layout................................................................... 22 10.1 Layout Guidelines ................................................. 22 10.2 Layout Example .................................................... 23 10.3 TI PowerPAD 100-TQFP Package ....................... 26 11 Device and Documentation Support ................. 27 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 27 12 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History Changes from Original (November 2012) to Revision A Page * Added the Device Information table, Pin Configuration and Functions section, ESD Ratings table, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 * Changed Changed Features From: "Device HBM ESD Classification Level C3B" To: "Device CDM ESD Classification Level C3" .......................................................................................................................................................... 1 * Changed the Operating free-air temperature MIN value From: 0C To: -40C and the MAX value From: 70C To: 85C in the Recommended Operating Conditions ................................................................................................................ 6 * Changed the Thermal Information table values ..................................................................................................................... 6 2 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 5 Pin Configuration and Functions 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 100 QO1 QO0 HSYNC VSYNC DE OGND ODCK OVDD CTL3 CTL2 CTL1 GND DVDD QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 OVDD OGND QE15 QE14 DFO PD ST PIXS GND DVDD STAG SCDT PDO QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 OVDD OGND QE8 QE9 QE10 QE11 QE12 QE13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 OGND QO23 OVDD AGND Rx2+ Rx2- AVDD AGND AVDD Rx1+ Rx1- AGND AVDD AGND Rx0+ Rx0- AGND RxC+ RxC- AVDD EXT_RES PVDD PGND RSVD OCK_INV 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 QO22 QO21 QO20 QO19 QO18 QO17 QO16 GND DVDD QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 OGND OVDD QO7 QO6 QO5 QO4 QO3 QO2 PZP Package 100-Pin PQFP PowerPAD Package (Top View) Pin Functions PIN TYPE (1) DESCRIPTION NAME NO. AGND 79, 83, 87, 89, 92 GND Analog ground - Ground reference and current return for analog circuitry AVDD 82, 84, 88, 95 VDD Analog VDD - Power supply for analog circuitry. Nominally 3.3 V 42, 41, 40 DO General-purpose control signals - Used for user-defined control. CTL1 is not powered down through PDO. DO Output data enable - Used to indicate time of active video display versus non-active display or blank time. During blank, the device transmits only HSYNC, VSYNC, and CTL[3:1]. During times of active display, or non-blank, the device transmits only pixel data, QE[23:0], and QO[23:0]. High: Active display time Low: Blank time Output clock data format - Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support, the ODCK clock runs continuously. For DSTN support, ODCK only clocks when DE is high; otherwise, ODCK remains low when DE is low. High: DSTN support - ODCK held low when DE = low Low: TFT support - ODCK runs continuously. CTL[3:1] DE 46 DFO 1 DI GND 5, 39, 68 GND Digital ground - Ground reference and current return for digital core DVDD 6, 38, 67 VDD Digital VDD - Power supply for digital core. Nominally 3.3 V. EXT_RES 96 AI Internal impedance matching - The TFP401A-Q1 device has internal optimization for impedance matching at 50 . An external resistor tied to this pin has no effect on device performance. HSYNC 48 DO Horizontal sync output (1) DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 3 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com Pin Functions (continued) PIN NAME NO. TYPE (1) DESCRIPTION RSVD 99 DI OVDD 18, 29, 43, 57, 78 VDD Output driver VDD - Power supply for output drivers. Nominally 3.3 V ODCK 44 DO Output data clock - Pixel clock. The device synchronizes all pixel outputs QE[23:0] and QO[23:0] (if in 2-pixels-per-clock mode), along with DE, HSYNC, VSYNC and CTL[3:1], to this clock. OGND 19, 28, 45, 58, 76 GND OCK_INV PD 100 2 Reserved. Tie this pin high for normal operation. Output driver ground - Ground reference and current return for digital output drivers DI ODCK polarity - Selects ODCK edge to which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL[3:1]) latch. Normal mode: High: Latches output data on rising ODCK edge Low: Latches output data on falling ODCK edge DI Power down - An active-low signal that controls the TFP401A-Q1 power-down state. During power down, all output buffers switch to a high-impedance state. The device powers down all analog circuits and disables all inputs, except for PD. If leaving PD unconnected, an internal pullup defaults the TFP401A-Q1 device to normal operation. High : Normal operation Low: Power down Output drive power down - An active-low signal that controls the power-down state of the output drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. When PDO is left unconnected, an internal pullup defaults the TFP401AQ1 device to normal operation. High: Normal operation; output drivers on Low: Output drive powered down PDO 9 DI PGND 98 GND PLL GND - Ground reference and current return for internal PLL. Pixel select - Selects between 1- and 2-pixels-per-clock output modes. During the 2-pixels-perclock mode, the device outputs both even pixels, QE[23:0], and odd pixels, QO[23:0], in tandem on a given clock cycle. During 1-pixel-per-clock mode, the device outputs even and odd pixels sequentially, one at a time, with the even pixel first, on the even-pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel). High: 2 pixels per clock Low: 1 pixel per clock PIXS 4 DI PVDD 97 VDD PLL VDD - Power supply for internal PLL DO Even green-pixel output - Output for even and odd green pixels when in 1-pixel-per-clock mode. Output for even-only green pixel when in 2-pixels-per-clock mode. Output data synchronizes to the output data clock, ODCK. LSB: QE8, pin 20 MSB: QE15, pin 27 DO Even red-pixel output - Output for even and odd red pixels when in 1-pixel-per-clock mode. Output for even-only red pixel when in 2-pixels-per-clock mode. Output data synchronizes to the output data clock, ODCK. LSB: QE16, pin 30 MSB: QE23, pin 37 DO Odd blue-pixel output - Output for odd-only blue pixel when in 2-pixels-per-clock mode. Not used, and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data clock, ODCK. LSB: QO0, pin 49 MSB: QO7, pin 56 DO Odd green-pixel output - Output for odd-only green pixel when in 2-pixels-per-clock mode. Not used, and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data clock, ODCK. LSB: QO8, pin 59 MSB: QO15, pin 66 DO Odd red-pixel output - Output for odd-only red pixel when in 2-pixels-per-clock mode. Not used, and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data clock, ODCK. LSB: QO16, pin 69 MSB: QO23, pin 77 QE[8:15] QE[16:23] QO[0:7] QO[8:15] QO[16:23] 4 20-27 30-37 49-56 59-66 69-75, 77 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 Pin Functions (continued) PIN NAME NO. TYPE (1) DESCRIPTION 10-17 DO Even blue-pixel output - Output for even and odd blue pixels when in 1-pixel-per-clock mode. Output for even-only blue pixel when in 2-pixels-per-clock mode. Output data synchronizes to the output data clock, ODCK. LSB: QE0, pin 10 MSB: QE7, pin 17 RxC+ 93 AI Clock positive receiver input - Positive side of reference clock. TMDS low-voltage signal differential-input pair. RxC- 94 AI Clock negative receiver input - Negative side of reference clock. TMDS low-voltage signal differential-input pair. Rx0+ 90 AI Channel-0 positive receiver input - Positive side of channel-0. TMDS low-voltage signal differential-input pair. Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank. Rx0- 91 AI Channel-0 negative receiver input - Negative side of channel-0. TMDS low-voltage signal differential-input pair. Rx1+ 85 AI Channel-1 positive receiver input - Positive side of channel-1 TMDS low-voltage signal differentialinput pair. Channel-1 receives green-pixel data in active display and CTL1 control signals in blank. Rx1- 86 AI Channel-1 negative receiver input - Negative side of channel-1 TMDS low-voltage signal differential-input pair. Rx2+ 80 AI Channel-2 positive receiver input - Positive side of channel-2 TMDS low-voltage signal differentialinput pair. Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank. Rx2- 81 AI Channel-2 negative receiver input - Negative side of channel-2 TMDS low-voltage signal differential-input pair QE[0:7] SCDT 8 DO Sync detect - Output to signal when the link is active or inactive. The link is active when DE is actively switching. The TFP401A-Q1 device monitors the state of DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive. High: Active link Low: Inactive link ST 3 DI Output drive strength select - Selects output drive strength for high- or low-current drive. (See dc specifications for IOH and IOL versus the ST state). High: High drive strength Low: Low drive strength STAG 7 DI Staggered pixel select - An active-low signal used in the 2-pixels-per-clock pixel mode (PIXS = high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. High: Normal simultaneous even-and-odd pixel output Low: Time-staggered even-and-odd pixel output VSYNC 47 DO Vertical sync output Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 5 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Supply-voltage range (1) DVDD, AVDD, OVDD, PVDD MIN MAX UNIT -0.3 4 V Input-voltage range, logic and analog signals -0.3 4 V Operating ambient temperature range, TA -40 85 C Storage temperature, Tstg -65 150 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Human-body model (HBM), per AEC Q100-002 (1) V(ESD) (1) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 UNIT 2000 All pins 750 Corner pins (1, 25. 26. 50. 51, 75, 76, and 100) 750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions VDD Supply voltage (DVDD, AVDD, PVDD, OVDD) Rt Single-ended analog-input termination resistance TA Operating free-air temperature MIN NOM MAX UNIT 3 3.3 3.6 V 45 50 55 -40 25 85 C 6.4 Thermal Information TFP401A-Q1 THERMAL METRIC (1) PZP (PQFP) UNIT 100 PINS RJA Junction-to-ambient thermal resistance 24.9 C/W RJC(top) Junction-to-case (top) thermal resistance 13.2 C/W RJB Junction-to-board thermal resistance 8.4 C/W JT Junction-to-top characterization parameter 0.2 C/W JB Junction-to-board characterization parameter 8.5 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 0.7 C/W (1) 6 For more information about traditional and new thermal metrics, see the Semicondictor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 6.5 DC Digital I/O Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level digital input voltage 2 DVDD V VIL Low-level digital input voltage 0 0.8 V IOH High-level output drive current IOL Low-level output drive current IOZ Hi-Z output leakage current ST = high, VOH = 2.4 V 5 10 16.3 ST = low, VOH = 2.4 V 3 6 10.3 ST = high, VOL = 0.8 V 8 13 19 ST = low, VOL = 0.8 V 4 7 11 PD = low or PDO = low -1 mA mA 1 A 6.6 DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VID Analog-input differential voltage (1) VIC Analog-input common-mode voltage (1) VI(OC) Open-circuit analog input voltage IDD(2PIX) Normal 2-pixels-per-clock power-supply current (2) ODCK = 82.5 MHz, 2 pixels per clock IPD Power-down current (3) PD = low IPDO Output-drive power-down current (3) PDO = low (1) (2) (3) MIN MAX UNIT 75 TYP 1200 mV AVDD - 300 AVDD - 37 mV AVDD - 10 AVDD + 10 mV 370 mA 10 mA 35 mA Specified as dc characteristic with no overshoot or undershoot Alternating 2-pixel black and 2-pixel white patterns. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF. Analog inputs are open-circuit (transmitter disconnected from the TFP401A-Q1 device). 6.7 AC Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VID(2) fODCK Differential input sensitivity TEST CONDITIONS (1) ODCK frequency PIXS = low (1-PIX/CLK) PIXS = high (2-PIX/CLK) ODCK duty-cycle (1) MIN TYP MAX UNIT 150 1560 mVp-p 25 165 12.5 82.5 45% 60% MHz 75% Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 7 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com 6.8 Timing Requirements PARAMETER tps TEST CONDITIONS Analog input intra-pair (+ to -) differential skew (1) tccs Analog input inter-pair or channel-to-channel skew tijit Worst-case differential input-clock jitter tolerance (1) (4) tf1 Fall time of data and control signals (5) (6) tr1 Rise time of data and control signals (5) (6) tr2 Rise time of ODCK clock (5) tf2 Fall time of ODCK clock (5) tsu1 th1 tsu2 th2 tpix (1) (2) (3) (4) (5) (6) MIN (1) Setup time, data and control signal to falling edge of ODCK Hold time, data and control signal to falling edge of ODCK Setup time, data and control signal to rising edge of ODCK Hold time, data and control signal to rising edge of ODCK TYP MAX UNIT 0.4 tbit (2) 1 tpix (3) 50 ps ST = low, CL = 5 pF 2.4 ST = high, CL = 10 pF 1.9 ST = low, CL = 5 pF 2.4 ST = high, CL = 10 pF 1.9 ST = low, CL = 5 pF 2.4 ST = high, CL = 10 pF 1.9 ST = low, CL = 5 pF 2.4 ST = high, CL = 10 pF 1.9 1 pixel per clock, PIXS = low, OCK_INV = low 1.8 2 pixels per clock, PIXS = high, STAG = high, OCK_INV = low 3.8 2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = low 0.6 1 pixel per clock, PIXS = low, OCK_INV = low 0.6 2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = low 2.5 2 pixels per clock, PIXS = high, STAG = high, OCK_INV = low 2.9 1 pixels per clock, PIXS = low, OCK_INV = high 2.1 2 pixels per clock, PIXS = high, STAG = high, OCK_INV = high 1.5 1 pixel per clock, PIXS = low, OCK_INV = high 0.3 2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = high 2.4 2 pixels per clock, PIXS = high, STAG = high, OCK_INV = high 2.1 Pixel time (3) 6.06 ns ns ns ns ns 4 2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = high ns ns ns 40 ns Specified by Characterization. tbit is 1/10 the pixel time, tpix. tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK, is equal to tpix when in 1-pixelper-clock mode or 2 tpix when in 2-pixels-per-clock mode. Measured differentially at 50% crossing using ODCK output clock as trigger Rise and fall times measured as time between 20% and 80% of signal amplitude Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1]. tr1 QE[23:0], QO[23:0], DE, CTK[3:1], HSYNC, VSYNC tf1 80% 80% 20% 20% Figure 1. Rise and Fall Times of Data and Control Signals 8 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 tr2 tf2 80% ODCK 80% 20% 20% Figure 2. Rise and Fall Times of ODCK 1/fODCK ODCK Figure 3. ODCK Frequency t(su1) t(su2) t(h1) t(h2) VOH ODCK VOH VOL VOL VOH VOL VOH VOL VOH VOL QE[23:0], QO[23:0] DE, CTL[3:1], HSYNC, VSYNC VOH VOL OCK_INV Figure 4. Data Setup and Hold Times to Rising and Falling Edges of ODCK VOH ODCK td(st) QE[23:0] 50% Figure 5. ODCK High to QE[23:0] Staggered Data Output PD VIL tpd(PDL) QE[23:0], QO[23:0], ODCK, DE, CTL[3:1], HSYNC, VSYNC, SCDT Figure 6. Delay From PD Low to Hi-Z Outputs PDO VIL tpd(PDOL) QE[23:0], QO[23:0], ODCK, DE, CTL[3:2], HSYNC, VSYNC Figure 7. Delay From PDO Low to Hi-Z Outputs Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 9 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com VIH PD tp(PDH-V) DFO, ST, PIXS, STAG, Rx[2:0]+, Rx[2:0]-, OCK_INV Figure 8. Delay From PD Low to High Until Inputs Are Active tt(HSC) tt(FSC) DE SCDT Figure 9. Time From DE Transitions to SCDT Low and SCDT High 6.9 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tpd(PDL) Propagation delay time from PD low to Hi-Z outputs tpd(PDOL) Propagation delay time from PDO low to Hi-Z outputs tt(HSC) Delay time from DE transition to SCDT low (1) 1e6 tpix tt(FSC) Delay time from DE transition to SCDT high (1) 1600 tpix td(st) Delay time, ODCK latching edge to QE[23:0] data output 0.25 tpix (1) STAG = low, PIXS = high 9 ns 9 ns Amount of time detected between DE transitions determines whether link is active or inactive. SCDT indicates link activity. tps Rx+ 50% Rx- Figure 10. Analog Input Intra-Pair Differential Skew twL(PDL_MIN) PD VIL Figure 11. Minimum Time PD Low 10 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 TX2 50% TX1 tccs TX0 50% Figure 12. Analog Input Channel-to-Channel Skew tDEL tDEH DE Figure 13. Minimum DE Low and Maximum DE High 6.10 Typical Characteristics 180 160 140 Imax (mA) 120 100 80 60 40 20 TFP401 0 0 20 40 60 80 100 120 140 160 180 200 Input Clock (MHz) D001 Figure 14. Imax vs Input Frequency Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 11 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com 7 Detailed Description 7.1 Overview The TFP401A-Q1 device is a digital visual interface (DVI)-compliant TMDS digital receiver used in digital flatpanel display systems to receive and decode TMDS-encoded RGB pixel data streams. In a digital display system, a host (usually a PC or workstation) contains a TMDS-compatible transmitter that receives 24-bit pixel data along with appropriate control signals. The host encodes the data and control signals into a high-speed lowvoltage differential serial bit stream (fit for transmission over a twisted-pair cable) to a display device. The display device (usually a flat-panel monitor) requires a TMDS-compatible receiver like the TI TFP401A-Q1 device to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data is then suitable for application directly to the flat-panel drive circuitry to produce an image on the display. Host and display separation distances can be up to 5 meters or more, making serial transmission of the pixel data preferable. Support of modern display resolutions up to UXGA requires a high-bandwidth receiver with good jitter and skew tolerance. 7.2 Functional Block Diagram 3.3 V 3.3 V 1.8 V Regulator Internal 50-W Termination 3.3 V RED(0-7) Rx2+ Rx2- + _ Channel 2 CH2(0-9) Latch CTL2 Channel 1 Rx1+ Rx1- + _ Rx0+ Rx0- + _ Latch RxC+ RxC- + _ PLL QE(0-23) QO(0-23) CTL3 Latch Data Recovery and Synchronization Channel 0 CH1(0-9) TMDS Decoder CH0(0-9) GRN(0-7) CTL1 BLU(0-7) VSYNC HSYNC Panel Interface ODCK DE SCDT CTL3 CTL2 CTL1 VSYNC HSYNC Copyright (c) 2017, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 TMDS Pixel Data and Control Signal Encoding The device transmits only one of two possible transition-minimized differential signaling (TMDS) characters for a given pixel at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent, and transmits the character that minimizes the number of transitions to approximate a dc balance of the transmission line. Reception of RGB pixel data during active display time uses three TMDS channels, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. Reception of these control signals occurs during inactive display or blanking-time. Blanking-time is when DE = low. The following table maps the received input data to the appropriate TMDS input channel in a DVI-compliant system. 12 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 Feature Description (continued) Table 1. TMDS Pixel Data and Control Signal Encoding RECEIVED PIXEL DATA ACTIVE DISPLAY DE = HIGH OUTPUT PINS (VALID FOR DE = HIGH) INPUT CHANNEL Red[7:0] Channel-2 (Rx2 ) QE[23:16] QO[23:16] Green[7:0] Channel-1 (Rx1 ) QE[15:8] QO[15:8] Blue[7:0] Channel-0 (Rx0 ) QE[7:0] QO[7:0] RECEIVED CONTROL DATA BLANKING DE = LOW OUTPUT PINS (VALID FOR DE = LOW) INPUT CHANNEL CTL[3:2] Channel-2 (Rx2 ) CTL[3:2] CTL[1: 0] (1) Channel-1 (Rx1 ) CTL1 HSYNC, VSYNC Channel-0 (Rx0 ) HSYNC, VSYNC (1) Some TMDS transmitters transmit a CTL0 signal. The TFP401A-Q1 device decodes and transfers CTL[3:1] and ignores CTL0 characters. CTL0 is not available as a TFP401A-Q1 output. The TFP401A-Q1 device discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking, in effect, the state of DE. 7.3.2 TFP401A-Q1 Clocking and Data Synchronization The TFP401A-Q1 device receives a clock reference from the DVI transmitter that has a period equal to the pixel time, tpix. Another name for the frequency of this clock is the pixel rate. Because the TMDS encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the required pixel rate to support a UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS serial bit rate is 10x the pixel rate, or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate channels (or twisted-pair wires) of long distances (3-5 meters), there is no assurance of phase synchronization between the data steams and the input reference clock. In addition, skew between the three data channels is common. The TFP401A-Q1 device uses a 4x oversampling scheme of the input data streams to achieve reliable synchronization with up to 1-tpix channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of high-speed serial data transmission; hence, the TFP401A-Q1 design for high jitter tolerance. A phase-locked loop (PLL) conditions the input clock of the TFP401A-Q1 device to remove high-frequency jitter from the clock. The PLL provides four 10x clock outputs of different phase to locate and sync the TMDS data streams (4x oversampling). During active display, the pixel data encoding is for transition minimization, whereas in blank, the control data encoding is for transition maximization. Transmitting in blank for a minimum period of time, 128 tpix, requires a DVI-compliant transmitter to ensure sufficient time for data synchronization when the receiver sees a transition-maximized code. Synchronization during blank, when the data is transition-maximized, ensures reliable data-bit boundary detection. Phase synchronization to the data streams, maintained as long as the link remains active, is unique for each of the three input channels. 7.3.3 TFP401A-Q1 TMDS Input Levels and Input Impedance Matching The TMDS inputs to the TFP401A-Q1 receiver have a fixed single-ended termination to AVDD. A laser trim process internally optimizes the TFP401A-Q1 device to fix the impedance precisely at 50 . The device functions normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets. The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching to standard 50- DVI cables. Figure 15 shows a conceptual schematic of a DVI transmitter and TFP401A-Q1 receiver connection. A transmitter drives the twisted-pair cable through a current source, usually using an open-drain type of output driver. The internal resistor, matched to the cable impedance at the TFP401A-Q1 input, provides a pullup to AVDD. Naturally, with the transmitter disconnected and the TFP401A-Q1 DVI inputs left unconnected, the TFP401A-Q1 receiver inputs pull up to AVDD. Figure 16 shows the single-ended differential signal and fulldifferential signal. The design of the TFP401A-Q1 device is for response to differential signal swings ranging from 150 mV to 1.56 V, with common-mode voltages ranging from (AVDD - 300 mV) to (AVDD - 37 mV). Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 13 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com DVI Transmitter TI TFP401/401A Receiver AVDD DVI Compliant Cable Internal Termination at 50 W DATA DATA + _ Current Source Copyright (c) 2017, Texas Instruments Incorporated Figure 15. TMDS Differential Input and Transmitter Connection VIDIFF AVCC 1/2 VIDIFF +1/2 VIDIFF -1/2 VIDIFF AVCC - 1/2 VIDIFF a) Single-Ended Input Signal b) Differential Input Signal Figure 16. TMDS Inputs 7.3.4 TFP401A-Q1 Device Incorporates HSYNC Jitter Immunity Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and if the position of HSYNC shifts continuously, the receiver can lose track of the input timing, causing pixel noise to occur on the display. For this reason, one should use a DVI-compliant receiver with HSYNC jitter immunity in all displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem. The TFP401A-Q1 integrates HSYNC regeneration circuitry that provides a seamless interface to these noncompliant transmitters. The regeneration circuitry always fixes the position of the data enable (DE) signal in relation to data, irrespective of the location of HSYNC. The TFP401A-Q1 receiver uses the DE and clock signals to recreate stable vertical and horizontal sync signals. The circuit filters the HSYNC output of the receiver and shifts HSYNC to the nearest eighth bit boundary, producing a stable output with respect to the data, as shown in Figure 17. This ensures accurate data synchronization at the input of the display timing controller. This HSYNC regeneration circuit is transparent to the monitor, and removal is unnecessary even if the transmitted HSYNC is stable. For example, the PanelBus line of DVI 1.0-compliant transmitters, such as the TFP6422 and TFP420, do not have the HSYNC jitter problem. The TFP401A-Q1 device operates correctly with either compliant or noncompliant transmitters. In contrast, the TFP401A-Q1 device is ideal for customers who have control over the transmit portion of the design, such as bundled-system manufacturers and for internal monitor use (the DVI connection between monitor and panel modules). 14 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 ODCK HSYNC Shift by 1 Clock HSYNC IN DE HSYNC OUT Figure 17. HSYNC Regeneration Timing Diagram 7.4 Device Functional Modes 7.4.1 TFP401A-Q1 Modes of Operation The TFP401A-Q1 device provides system design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. Table 2 outlines the various supportable panel modes, along with appropriate external control pin settings. Table 2. Supported Panel Modes PANEL TFT or 16-bit DSTN PIXEL RATE ODCK LATCH EDGE ODCK DFO PIXS OCK_INV 1 pixel per clock Falling Free run 0 0 0 TFT or 16-bit DSTN 1 pixel per clock Rising Free run 0 0 1 TFT 2 pixels per clock Falling Free run 0 1 0 TFT 2 pixels per clock Rising Free run 0 1 1 24-bit DSTN 1 pixel per clock Falling Gated low 1 0 0 None 1 pixel per clock Rising Gated low 1 0 1 24-bit DSTN 2 pixels per clock Falling Gated low 1 1 0 24-bit DSTN 2 pixels per clock Rising Gated low 1 1 1 7.4.2 TFP401A-Q1 Output Driver Configurations The TFP401A-Q1 device provides flexibility by offering various output driver features for use to optimize power consumption, ground bounce, and power-supply noise. The following sections outline the output driver features and their effects. Output Driver Power Down (PDO = low): Pulling PDO low places all the output drivers, except CTL1 and SCDT, into a high-impedance state. One can tie the SCDT output, which indicates link-disabled or link-inactive, directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. An internal pullup on the PDO pin defaults the TFP401A-Q1 device to the normal nonpower-down output-drive mode if left unconnected. Drive Strength (ST = high for high drive strength, ST = low for low drive strength): The TFP401A-Q1 device allows for selectable output drive strength on the data, control, and ODCK outputs. See the DC Electrical Characteristics table for the values of IOH and IOL current drives for a given ST state. The high output-drive strength offers approximately two times the drive as the low output-drive strength. Time-Staggered Pixel Output: This option works only in conjunction with the 2-pixels-per-clock mode (PIXS = high). Setting STAG = low time-staggers the even- and odd-pixel outputs so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design, this can help reduce the amount of system ground bounce and power-supply noise. The time stagger is such that in 2-pixelsper-clock mode, the even pixel is delayed from the latching edge of ODCK by 0.25 tcip. (tcip is the period of ODCK. The ODCK period is 2 tpix when in 2-pixels-per-clock mode.) Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 15 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the TFP401A-Q1 drive-strength and staggered-pixel options allow flexibility to reduce system power-supply noise, ground bounce, and EMI. Power Management: The TFP401A-Q1 device offers several system power-management features. The output-driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 go into a high-impedance state while the rest of the device circuitry remains active. Power down (PD = low) of the TFP401A-Q1 device is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers go into a Hi-Z state. Of all the inputs, only PD remains active. The TFP401A-Q1 device does not respond to any digital or analog inputs until PD is pulled high. Both PDO and PD have internal pullups, so if left unconnected they default the TFP401A-Q1 device to normal operating modes. Sync Detect: The TFP401A-Q1 device offers an output, SCDT, to indicate link activity. The TFP401A-Q1 device monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the TFP401A-Q1 device considers the link inactive, and drives SCDT low. While SCDT is low, if two DE transitions are detected within 1600 pixel clock periods, the device considers the link active and pulls SCDT high. A use of SCDT is to signal a system power management circuit to initiate a system power down when the device considers the link inactive. One can also tie the SCDT directly to the TFP401A-Q1 PDO input to power down the output drivers when the link is inactive. It is not recommended to use SCDT to drive the PD input, because once in complete power-down, the analog inputs are ignored and the SCDT state does not change. An external system power-management circuit to drive PD is preferred. 16 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TFP401A-Q1 is a DVI (Digital Visual Interface) compliant digital receiver that is used in digital flat panel display systems to receive and decode T.M.D.S. encoded RGB pixel data streams. In a digital display system a host, usually a PC or workstation, contains a DVI compliant transmitter that receives 24 bit pixel data along with appropriate control signals and encodes them into a high speed low voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will require a DVI compliant receiver like the TI TFP401A-Q1 to decode the serial bit stream back to the same 24 bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. The TFP401A-Q1 will support resolutions up to UXGA. 8.2 Typical Application Figure 18. Typical Application 8.2.1 Design Requirements Table 3. Design Parameters PARAMETER VALUE Power supply 3.3 V-DC at 1 A Input clock Single-ended Input clock frequency range 25 MHz to 165 MHz Output format 24 bits/pixel Input clock latching Rising edge I2C EEPROM support No De-skew No 8.2.2 Detailed Design Procedure 8.2.2.1 Data and Control Signals The trace length of data and control signals out of the receiver should be kept as close to equal as possible. Trace separation should be ~5X Height. As a general rule, traces also should be less than 2.8 inches if possible (longer traces can be acceptable). Calculation: Delay = 85 x SQRT er er = 4.35; relative permitivity of 50% resin FR-4 at 1 GHz (1) (2) Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 17 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com Delay = 177 pS/inch (3) space Length of rising edge = Tr(picoseconds)/Delay; Tr = 3 nS = 3000 ps/177 ps per inch = 16.9 inches (4) (5) (6) space Length of rising edge / 6 = Max length of trace for lumped circuit 16.9 / 6 = 2.8 inches (7) (8) Figure 19. TFP401A-Q1 App Info Data and Control Signals 8.2.2.2 Configuration Options The TFP401A-Q1 can be configured in several modes depending on the required output format, for example 1byte/clock, 2-bytes/clock, falling/rinsing clock edge. You can leave place holders for future configuration changes. 18 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 Copyright (c) 2017, Texas Instruments Incorporated Figure 20. TFP401A-Q1 App Info Config Options 8.2.2.3 Power Supplies Decoupling Digital, analog and PLL supplies must be decoupled from each other to avoid electrical noise on the PLL and the core. Copyright (c) 2017, Texas Instruments Incorporated Figure 21. TFP401A-Q1 App Info Power Decoupling Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 19 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com 8.2.3 Application Curves Sometimes the Panel does not support the same format as the GPU (graphics processor unit). In these cases the user must decide how to connect the unused bits. The below plots show the mismatches between the 18-bit GPU and a 24-bit LCD where "x" and "y" represent the 2 LSB of the Panel. 250 250 B2 B1 = GND, B0 = 1 x=GND, y=1 B2 B1 B0 = B7 B6 B5 x=B7, y=B6 200 Pixel Value (dec) Pixel Value (dec) 200 150 100 150 100 50 50 0 0 1 3 5 7 9 11 13 15 17 19 Pixel Samples 21 23 25 27 29 31 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 Pixel Samples Figure 22. 16b GPU to 24b LCD 20 Submit Documentation Feedback Figure 23. 18B GPU to 24b LCD Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 9 Power Supply Recommendations Use solid ground planes, tie ground planes together with as many vias as is practical. This will provide a desirable return path for current. Each supply should be on separate split power planes, where each power plane should be as large an area as possible. Connect PanelBus receiver power and ground pins and all bypass caps to appropriate power or ground plane with via. Vias should be as fat and short as practical, the goal is to minimize the inductance. 9.1 DVDD Place one 0.01-uF capacitor as close as possible between each DVDD device pin (Pins 6, 38, 67) and ground. 9.2 OVDD Place one 0.01-F capacitor as close as possible between each OVDD device pin (Pins 18, 29, 43, 57, 78) and ground. A 22-F tantalum capacitor should be placed between the supply and 0.01-uF capacitors. A ferrite bead should be used between the source and the 22-uF capacitor. 9.3 AVDD Place one 0.01-uF capacitor as close as possible between each AVDD device pin (Pins 82, 84, 88, 95) and ground. A 22-uF tantalum capacitor should be placed between the supply and 0.01-uF capacitors. A ferrite bead should be used between the source and the 22-uF capacitor. 9.4 PVDD Place three 0.01-F capacitors in parallel as close as possible between the PVDD device pin (Pin 97) and ground. A 22-F tantalum capacitor should be placed between the supply and 0.01-F capacitors. A ferrite bead should be used between the source and the 22-uF capacitor. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 21 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com 10 Layout 10.1 Layout Guidelines 10.1.1 Layer Stack The pinout of Texas Instruments High Speed Interface (HSI) devices features differential signal pairs and the remaining signals comprise the supply rails, VCC and ground, and lower speed signals such as control pins. As an example, consider a device X which is a repeater/re-driver, so both its inputs and outputs are high-speed differential signals. These guidelines can be applied to other high-speed devices such as drivers, receivers, multiplexers, and so on. A minimum of four layers is required to accomplish a low EMI PCB design. Layer stacking should be in the following order (top-to-bottom): high-speed differential signal layer, ground plane, power plane and control signal layer. Figure 24. Layer Stack 10.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+) Trace impedance should be controlled for optimal performance. Each differential pair should be equal in length and symmetrical and should have equal impedance to ground with a trace separation of 2X to 4X Height. A differential trace separation of 4X Height yields about 6% cross-talk (6% effect on impedance). We recommend that differential trace routing should be side by side, though it is not important that the differential traces be tightly coupled together because tight coupling is not achievable on PCB traces. Typical ratios on PCB's are only 2050%, 99.9% is the value of a well-balanced twisted pair cable. Each differential trace should be as short as possible (< 2 inches preferably) with no 90 angles. These high-speed transmission traces hould be on layer 1 (top layer). RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+ signals all route directly from the DVI connector pins to the device, no external components are needed. 22 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 10.2 Layout Example * DVI connector trace matching Figure 25. DVI Connector * Keep data lines as far as possible from each other Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 23 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com Layout Example (continued) Figure 26. Data Route * 24 Connect the thermal pad to ground Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 Layout Example (continued) Figure 27. GND Route Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 25 TFP401A-Q1 SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 www.ti.com 10.3 TI PowerPAD 100-TQFP Package The TFP401A-Q1 device comes in TI's thermally enhanced PowerPAD 100-TQFP package. The PowerPAD package is a 14-mm x 14-mm x 1-mm TQFP outline with 0.5-mm lead pitch. The PowerPAD package has a specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline. The TI 100-TQFP PowerPAD package offers a back-side solder plane that connects directly to the die mount pad for enhanced thermal conduction. There is no thermal requirement for soldering the back side of the TFP401A-Q1 device to the application board, because the device power dissipation is well within the package capability when not soldered. Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations. Connection of the PowerPAD back side to a PCB ground plane helps to improve EMI, ground bounce, and power-supply noise performance, because the die pad is electrically connected to the chip substrate and hence to chip ground. Table 4 outlines the thermal properties of the TI 100-TQFP PowerPAD package. The 100-TQFP non-PowerPAD package is included only for reference. Table 4. TI 100-TQFP (14 mm x 14 mm x 1 mm) With 0.5-mm Lead Pitch PARAMETER Theta-JA (1) Theta-JC (2) (1) (2) Maximum power dissipation (1) (2) (3) (1) (2) (3) 26 WITHOUT PowerPADTM PACKAGE PowerPADTM PACKAGE, NOT CONNECTED TO PCB THERMAL PLANE PowerPADTM PACKAGE, CONNECTED TO PCB THERMAL PLANE (1) 45C/W 27.3C/W 17.3C/W 3.11C/W 0.12C/W 0.12C/W 1.6 W 2.7 W 4.3 W Specified with 2-oz. (0.071 mm thick) Cu PCB plating Airflow is at 0 LFM (0 m/s) (no airflow). Measured at ambient temperature, TA = 70C Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 TFP401A-Q1 www.ti.com SLDS190A - NOVEMBER 2012 - REVISED FEBRUARY 2017 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks PowerPAD, EPIC-5, Panelbus, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TFP401A-Q1 27 PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) TFP401AIPZPRQ1 ACTIVE Package Type Package Pins Package Drawing Qty HTQFP PZP 100 1000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Op Temp (C) Device Marking (4/5) -40 to 85 TFP401AI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2014 OTHER QUALIFIED VERSIONS OF TFP401A-Q1 : * Catalog: TFP401A * Enhanced Product: TFP401A-EP NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jun-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device TFP401AIPZPRQ1 Package Package Pins Type Drawing HTQFP PZP 100 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 17.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 17.0 1.5 20.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jun-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TFP401AIPZPRQ1 HTQFP PZP 100 1000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. 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IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2017, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: TFP401AIPZPRQ1