HIP6018CB - Intersil Corporation

224

TM HIP6018

Advanced PWM and Dual Linear Power

Control

The HIP6018 provides the power control and protection for

three output volt ages in high-performan ce microprocessor

and computer applications. The IC integrates a PWM

controllers, a linear regulator and a linear controller as well

as the monitoring and protecti on functio ns into a single

package. The PWM contr oller regulates the micr oprocessor

core voltage with a synchronous-rectified buck converter .

The linear controller regulates power for the GTL bus and

the l inear r egulat or prov ides power for th e clock dr iver circui t.

The HIP6018 includes an Intel-compatible, TTL 5-input

digi tal-t o-analog c onverter (DAC) t hat adjusts the core PWM

output volta ge fr om 2.1VDC to 3.5VDC in 0.1V increments

and from 1.8VDC to 2.05VDC in 0.05V steps. The precision

reference and vol tage-mode control provide ±1% static

regulatio n. The linea r regulat or uses an int ernal pass d evice

to provide 2.5V±2. 5%. The li near controller dri ves an

external N-channel MOSFET to provide 1.5V±2.5%.

The HIP6018 monitors all the output voltages. A single

Power Goo d si gnal i s is sued wh en the c ore is within ±10% of

the DAC setting and the other levels are above their under-

volt age levels. Additional built-in over-vol tage protection for

the core output use s the l ower MOSFET to prevent output

voltages above 115% of the DAC setting. The PWM over-

current func ti on m onitors the output curren t by usi ng the

volt age drop across the upper MOSFET’s rDS(ON),

eli m inating th e need for a curr ent sensing resisto r.

Features

• Provides 3 Regulated Voltages

- Mi croprocessor Core, Clock and GTL Power

• Drives N-Channel MOSFETs

• Operates from +3.3V, +5V and +12V Inputs

• Simple Si ngle-Loop PWM Control Design

- Vol tage-Mode Control

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratios

• Excellent Output Voltage Regulation

- Cor e PWM Outp ut: ±1% Over Temperature

- Other Outputs: ±2.5% Over Temperature

• TTL-compatible 5-Bit Dig it al-to-Analog Core Output

Vo lt a ge S e le ct io n

- Wide Range . . . . . . . . . . . . . . . . . . . 1.8VDC to 3.5VDC

- 0.1V Steps . . . . . . . . . . . . . . . . . . . . 2.1VDC to 3.5VDC

- 0.05V Steps . . . . . . . . . . . . . . . . . . 1.8VDC to 2. 05V DC

• Power-Good Output Voltage M onitor

• Microprocessor Core Voltage Protection Against Shorted

MOSFET

• Over-Voltage and Over -Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFET’s rDS(ON)

• Small Conver ter Size

- Constant Fr equency Opera ti on

- 200kHz Free-Running Osci ll ator; Programm able from

50kHz to over 1MHz

Applications

•Full Motherboard Power Regulation for Computers

•Low-Voltage Distributed Power Supplies

Pinout

HIP6018 (SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE PKG.

NO.

HIP6018CB 0 to 70 24 Ld SOI C M 24.3

HIP60 18EVAL 1 Ev alua tion Board

VCC

VID4

VID3

VID2

FB2

VIN2

UGATE1

OCSET1

PGND

LGATE1

GND

FB3

VOUT2

PHASE1

FAULT

VID1

FB1

DRIVE3

VID0

PGOOD

VSEN1

COMP1

Data S heet Apri l 1999 FN44 97.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-8 88-INTERSIL o r 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.

225

Block Diagram

0.23A 115%

110%

90%

INHIBIT

PWM

COMP

ERROR

AMP

VCC

PGOOD

PWM

GND

VSEN1 OCSET1

VID0

VID1VID2

VID3 FB1 COMP1

DACOUT

UGATE1

PHASE1

200mA

11µA

VID4

LGATE1

PGND

VOUT2

DRIVE3

FB3

INHIBIT

0.3V

-1.26V

POWER-ON

RESET (POR)

OSCILLATOR

GATE

CONTROL

VCC

LOWER

DRIVE

UPPER

UNDER-

VOLTAGE

FB2

LINEAR

LUV

OC1

OC2

TTL D/A

CONVERTER

(DAC)

VIN2

FAULT SOFT-

START

AND FAULT

LOGIC

DRIVE

FIGURE 1.

HIP6018

226

Simplified Power System Diagram

Typical Application

PWM1

+5VIN

VOUT1

VOUT2

VOUT3

LINEAR

HIP6018

REGULATOR

CONTROLLER

+3.3VIN

FIGURE 2.

+3.3VIN

VID1

VID2

VID3

VID4 SS

GND

VCC

+5VIN

VID0

+12VIN

VOUT1

PGND

VSEN1

PGOOD

LGATE1

UGATE1

OCSET1

PHASE1 Q1

POWERGOOD

FB1

COMP1

1.8V TO 3.5V

DRIVE3

FB3

VOUT2

COUT2

1.5V

2.5V

COUT3

CIN

COUT1

Q3 CR1

LOUT1

HIP6018

VOUT3

VOUT2

FAULT

FB2

CSS

VIN2

FIGURE 3.

HIP6018

227

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V

PGOOD, RT, FAULT, and GATE VoltageGND - 0.3V to V CC + 0.3V

Input, Output or I/O Voltage. . . . . . . . . . . . . . . . . . GND -0.3V to 7V

Ope rat i ng Condi t io ns

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

SOIC Package (with 3 in2 of copper) . . . . . . . . . . . 65

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CAUTIO N: S tresses abov e those l isted i n “ A bsolute Max imum Ra ting s” ma y cause per manen t dam age to th e de vice. This is a s tress on l y rating and ope ration of th e

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is me asured with the c omponent m ounted on an evaluatio n PC board in free air.

Electrical Speci fications Recommended Operatin g Conditions, Unless Otherwise Noted. Refer to Fig ures 1, 2 and 3

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UN ITS

VCC SUPPLY CURRENT

Nominal Supply ICC UGATE1, DRIVE3, LGATE1, and VOUT2 Open - 10 - mA

POWER-ON RESET

Rising VCC Threshold VOCSET = 4.5V 8.6 - 10.4 V

Falling VCC Threshold VOCSET = 4.5V 8.2 - 10.2 V

Rising VIN2 Under-Voltage Threshold 2.45 2.55 2.65 V

VIN2 Under-Voltage Hysteresis -500- mV

Rising VOCSET1 Threshold -1.25- V

OSCILLATOR

Free Running Frequency RT = OPEN 185 200 215 kHz

T ota l Vari ation 6kΩ < RT to GND < 200kΩ-15 - +15 %

Ramp Amplitu de ∆VOSC RT = Open - 1.9 - VP-P

REFERENCE and DAC

DAC(VID0-VID4) Input Low Voltage --0.8V

DAC(VID0-VID4) Input High Voltage 2.0 - - V

DACOUT Voltage Accuracy -1.0 - +1.0 %

Reference Voltage (P in F B2 and FB3) 1.240 1.265 1.290 V

LINEAR REGULATOR

Regulation 10mA < IVOUT2 < 150m A -2.5 - 2.5 %

Under-Voltage Level FB2UV FB2 Rising - 75 87 %

Under-Voltage Hysteresis -6- %

Over-Current Protection 180 230 - mA

Over-current Protection During Start-Up 560 700 - mA

LINEAR CONTROLLER

Regulation VSEN3 = DRIVE3, 0 < IDRIVE3 < 20mA -2.5 - 2 .5 %

Under-Voltage Level FB3UV FB3 Rising - 75 87 %

HIP6018

228

Under-Voltage Hysteresis -6- %

DRIVE3 Source Current VIN2 - DRIVE3 > 0.6V 20 40 - mA

PWM CONTROLLER ERROR AMPLIFIER

DC Gain -88- dB

Ga in - Ban dw idt h P rod uc t GBWP - 1 5 - M H z

Slew Rate SR COMP = 10pF - 6 - V/µs

PWM CONTROLLER GATE DRIVER

Upper Drive Source IUGATE VCC = 12V, VUGATE1 (or VGATE2) = 6V - 1 - A

Upper Drive Sink RUGATE VUGATE1-PHASE1 = 1V - 1 .7 3.5 Ω

Lower Drive Source ILGATE VCC = 12V, VLGATE1 = 1V - 1 - A

Lower Drive Sink RLGATE VLGATE1 = 1V - 1 .4 3.0 Ω

PROTECTION

VOUT1 Over-Voltage Trip VSEN1 Rising 112 115 118 %

FAULT Sourc ing Curre n t IOVP VFAULT = 10 V 10 14 - mA

OCSET1 Current Source IOCSET VOCSET = 4.5VDC 170 200 230 µA

Soft-Start Current ISS -11- µA

Chip Shutdown Soft-Start Threshold --1.0V

POWER GOOD

VOUT1 Upper Threshold VSEN1 Rising 108 - 110 %

VOUT1 Under Voltage VSEN1 Rising 92 - 94 %

VOUT1 Hysteresis (VSEN1 / DA COUT ) Upper/ Lower Threshold - 2 - %

PGOOD Voltage Low VPGOOD IPGOOD = -4mA - - 0.5 V

Electrical Speci fications Recommended Operatin g Conditions, Unless Otherwise Noted. Refer to Fig ures 1, 2 and 3 (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UN ITS

Typical Performance Curves

FIGURE 4. RT RESISTANCE vs FRE QUENCY FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY

10 100 1000

SWITCHING FREQUENCY (kHz)

RESISTANCE (kΩ)

100

1000 RT PULLUP

TO +12V

RT PULLDOWN TO VSS

100 200 300 400 500 600 700 800 900 1000

100

SWITCHING FREQUENCY (kHz)

ICC (mA)

CGATE = 660pF

CUGATE1 = CLGATE1 = CGATE CGATE = 4800pF

CGATE = 3600pF

CGATE = 1500pF

VVCC = 12V, VIN = 5 V

HIP6018

229

Functional P in Description

VSEN1 (Pin 19)

This pin i s connecte d t o the PWM conve rter’ s output volt age.

The PG OOD and OVP com parator circuits use this signal to

report output voltage status and for over vol tage protec tion.

OCSET1 (Pin 20)

Connect a resistor (ROCSET) fr om this pi n to the drain of t he

upper MO SFET. ROCSET, an i nternal 200µA current source

(IOCSET), and the upper MOSFET on- resistance (rDS(ON))

set th e PWM converter over- current (OC) trip point

according to the following equation:

An over-curre nt trip cyc les the soft-start function. Sustaining

an over-curre nt for 2 soft-st art interval s shuts down the

controller.

SS ( P in 9)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 11µA (typically) cur rent source, sets

the soft-start interval of the conve rt er.

Pull ing this pin low with an open drain signal will shut down

the IC.

VID0, VID1, VID2, VID3, VID4 (Pin s 6, 5, 4, 3 an d 2)

VID0-4 are the input pins to the 5-bit DAC. The states of

these five pin s program the int ernal voltage reference

(DACOUT). The level of DACOUT sets the core converter

output voltage. It also sets the core PGOOD and OVP

thresholds.

COMP1 and FB1 (Pins 17 and 18)

COMP1 and FB1 are the avail able ext ernal pins of th e PWM

error ampli fi er. The FB1 pin is t he inverting input of the error

amplifier. Si mil arly, the COMP1 pin is the error amplifi er

output. These pi ns are used to compensate the volt age-

control feed back loop of the PWM convert er.

GND (Pin 14)

Signal ground for the IC. All vol tage level s are measured

with respect to this pin.

PGOOD (Pin 7)

PGOOD is an open collector output used to indicate the

stat us of the output volt ages. This pin is pulled l ow when the

core out put is not within ±10% of the DACOUT reference

volt age and the other out puts are below their under- voltage

thresholds.

The PGOOD o utput is open for VID codes that inhibit

operation. See Table 1.

PHASE1 (Pin 23)

Connect the PHASE pin to the PWM converter’s upper

MOSFET sour ce. This pin is used to monitor the voltage

drop across the upper MOSFET f or over-current protec ti on.

UGATE1 (Pin 24)

Connect UGATE pin to the PWM converter’s upper

MOSFET gat e. This pin prov ides the gat e drive f or the upp er

MOSFET.

PGND (Pin 21)

This i s the power ground connection. Tie the PWM

converter’ s lower MOSFET source to th is pin.

LGATE1 (Pin 22)

Connect LGATE1 to the PWM converter’s lower MOSFET

gate. This pin provi des the gate dri ve for t he lower MOSFET.

VCC (Pin 1)

Provide a 12V bias supply f or the IC to this pin. This pi n also

provides the gate bias charge for all the MOSFETs

controlled by the IC.

RT ( Pin 10)

This pi n provides oscillator switch ing frequency adjustment.

By placi ng a resistor (RT) from thi s pin to GND, the nominal

200kHz switching fr equency is incr eased accor ding to the

following equation:

Conversely, connecting a pull-up resistor (RT) from this pi n

to VCC reduces the switchi ng fr equency according to the

following equation:

FAULT (Pin 8)

This pi n is low dur ing no rmal operation, but i t is pull ed to

VCC in the even t of an over-voltage or over-current

condition.

DRIVE3 (Pin 15)

Connect this pin to the gate of an external M OSFET. This

pin provides th e dri ve for the linear controll er’ s pass

transistor.

FB3 (Pin 16)

Connect this pin to a resi stor divider to set the linear

controlle r out put voltage.

VOUT2 ( P in 13)

Output o f t he li near regul ator. Supplies current up to 23 0mA.

FB2 (Pin 11)

Connect this pin to a resi stor divider to set the linear

regulator output voltage.

IPEAK IOCSET ROCSET

rDS ON()

----------------------------------------------------=

Fs 200kHz 510×6

RTkΩ()

---------------------+≈(RT to GND)

Fs 200kHz 410

RTkΩ()

---------------------–≈(RT to 12V)

HIP6018

230

VIN2 ( Pin 12)

This pin supplies power to the int ernal regul ator. Connec t

this pin to a suitable 3. 3V source.

Additionally, this pin is used to monitor the 3.3V sup ply. If,

following a startup cycle, the voltage drops below 2.05V

(typically), the chip shuts down. A new soft-start cyc le is

ini tiated upon r eturn of the 3.3V supply above the under -

voltage threshold.

Description

Operation

The HIP6018 monitors and precisely controls 4 output

volt age levels (Refer to Figures 1, 2, and 3). It is desi gned

for microprocessor computer applications with 3.3V and 5V

power, and 12V bias input from an ATX power supply. The

IC has one PWM cont roller, a linear controller, and a l inear

regulator. The PWM cont roller is designed to regulate the

microprocessor core voltage (VOUT1) by driving 2

MOSFETs ( Q1 and Q2) in a synchronous-rect if ied buck

converter conf iguration. The core volt age is regula ted to a

level programmed by the 5-bit digital-to-analog converter

(DAC). An integ rated l inear regulat or suppl ies t he 2.5V cl ock

power (VOUT2). The linear controller drives an external

MOSFET (Q3) to supply the GTL bus power (VOUT3).

Initialization

The HIP6018 automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input supply voltages. The POR monitors the

bias voltage (+12VIN) at the VCC p in, t he 5 V input volt age

(+5VIN) on the OCSET1 pin, and the 3.3V input on the VIN2

pin. The nor mal level on OCSET1 is equa l to +5VIN less a

fixed voltage drop (see over-current protection). The POR

function initiates soft-start operation after all three input supply

voltages exceed their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence. Initially,

the voltage on the SS p in rapidly increases to approximately

1V (thi s m inimizes t he soft-start interval ). Then an internal

11µA cur rent sour ce charge s an exte rna l capaci tor (CSS) on

the SS pi n to 4V. The PWM err or ampli fier ref erence i nput (+

terminal) and output (COMP1 pin) is cla mp ed to a level

proportion al to the SS pin voltage. As the SS pin voltage

slews from 1V to 4V, the output clamp generates PHASE

pulses of increasing width that charge the out put

capaci tor( s). After this init ial stage, the r ef erence inp ut cl amp

slows the output voltage rate-of -r ise and provides a smooth

transition to the fi nal set voltage. Additionally bot h li near

regulator’s referenc e inputs are clam ped to a voltage

proportional to the SS pin voltage. This method provides a

rapid and contro ll ed output vol tage rise.

Figure 3 shows the soft-start sequence for the typical

appli cation. At T0 the SS vol tage rapidly increases to

approximatel y 1V. At T1, th e SS pin and err or amplifier

output voltage reach the valley of the oscillator’s triangle

wave. The oscillator’s triangular waveform is compare d to

the clamped error amplifier output voltage. As the SS pin

voltage increases, the pul se-width on the PHASE pin

increases. The interval of increasing pulse-width continues

until each output reaches sufficient voltage to transfer

control to the input reference clamp. If we consider the 2.0V

output (VOUT1) in Figure 3, this time occurs at T2. During

the interv al betw een T2 and T3, t he err or ampli fie r

reference ram ps t o the final val ue and the conver ter

regulates t he output to a voltage propor tional to the SS pin

voltage. At T3 the i nput cl amp vo ltage exceeds t he

reference vol tage and th e output voltage i s in regu lation.

The remaining outputs are also programmed to follow the

SS pin voltage. Each linear output (VOUT2 and VOUT3)

initially follows a ramp similar to that of the PWM output.

When eac h output reaches suff icient voltage the input

reference cl am p slows the ra te of output volta ge ri se. T he

PGOOD signal toggles ‘high’ when all output voltage levels

have exc eeded their unde r-volta ge level s. See t he Sof t-Star t

Interval secti on under Applications Gu idelines for a

procedure to determine the soft -start interval.

Fau lt P rot ec ti on

All three outputs are monitored and protected against

extreme overload. A sustained overload on any li near

FIGURE 6. SOF T-START INTERVAL

TIME

PGOOD

SOFT-START

(1V/DIV)

OUTPUT

(0.5V/DIV)

VOLTAGES

VOUT1 (DAC = 2V)

VOUT2 ( = 2.5V)

VOUT3 ( = 1.5V)

T1 T2 T3T0

(2V/DIV)

HIP6018

231

regulator output or an over-voltage on the PWM output

disables all converter s and drives the FAULT pin to VCC.

Figure 7 shows a simplified schematic of the fault logic. An

over-voltage detected on VSEN1 immediately sets the fa ult

latch. A sequence of three over-current fault signals also

sets the fault latch. A comparator indicates when C SS is fully

charged (UP signal ), such that an under- voltage event on

either linear output (FB2 or FB3) is ignored until after the

soft-start interval (T4 in Figure 6). At startup, this allows

VOUT2 and VOUT3 to slew up over inc reased time in tervals,

with out generati ng a fault. Cycling the bias input voltage

(+12VIN on the VCC pin) off then on resets the counter and

the fault latch.

Over-Voltage Pr otection

During operation, a short on the upper PWM MOSFET (Q1)

causes VOUT1 to increase. When the output exceeds th e

over-voltage threshol d of 115% (t ypical) of DACOUT, the

over-volt age com parator trips to set the faul t latch and tu rns

Q2 on as required in orde r to regulate VOUT1 to 1.15 x

DACOUT. This blows t he input fuse and reduces VOUT1.

The faul t latch raises the FAULT pi n close to VCC potential.

A separate over-v oltage circuit provides protection during

the in itial appli cation of power. For voltages on the VCC pin

below t he power-on reset (and above ~4V), VOUT1 is

monitored for voltages exceeding 1.26V. Should VSEN1

exceed this level, the lower MOSFET (Q2) is driven on as

needed to regulat e VOUT1 to 1. 26 V .

Over-Current Protection

All output s are prot ected agai nst exce ssiv e over- current s.

The PWM contr olle r uses th e upper MO SF ET’ s on-

resistance, rDS(ON) t o m onito r the curren t for prot ection

against short ed ou tput s. The linea r reg ulato r monit ors the

current of the integ rated power device and signal s an over-

current condi tion f or curre nts in exce ss of 230m A.

Additionally, both the linear regulator and the linear

controller monitor FB2 and FB3 for under-voltage to protect

against exces sive curre nts.

Figures 8 and 9 illustrate the over-current protection with an

overload on OUT1. The overload is appl ied at T0 and the

current increases thr ough the output induct or (LOUT1). A t time

T1, the OVER-CURRENT1 comparator trips when the voltage

across Q1 (ID • rDS(ON)) exceeds the level programmed by

ROCSET. This inhibits al l out puts, discharges the soft-start

capacitor (CSS) with a 11µA current sink, and increments t he

counter. CSS r ech a r g e s at T2 a nd initiates a soft-start cycle

with the error amplifiers cl amped by soft-start. With OUT1 still

overloaded, the in ductor current increases to trip the over-

curr ent com parator . Again, thi s in h i bi t s all o ut p u ts , but the

soft-start voltage continues increasing to 4V before

discharging. The count er in crements to 2. T he soft-start cycle

repeats at T3 and tri ps the over -current comparator. The SS

pin voltage increases to 4V at T4 and the counter increments to

3. This sets the fault latch to disable t he converter. The fault is

reported on the FAULT pin.

The li near regulat or operates i n the same way as PW M 1 to

over-curre nt f aults. Additi onally, the l inear regulator and

li near control ler monitor the f eedback pins for an under-

voltage. Shoul d excessive currents cause FB2 or FB3 to fall

below t he li near under-voltage thre shold, the LUV signal

sets the over- curr ent lat ch if C SS is fully charged. Bl anking t he

LUV signal during the CSS charge interval allows the l inear

outputs to build above the under- voltage thr eshold duri ng

normal s tar t-up. Cycl ing the bi as input power of f th en on

resets the count er and the fault latch.

Resistor ROCSET1 programs the over- current tri p level for the

PWM converter. As shown in Figure 9, the internal 200µA

current sink develops a voltage across ROCSET (VSET) that is

referenced to VIN. The DRIVE signal enables the over-current

comparator (OVER-CURRENT1). When the voltage across the

upper MOSFET (VDS(ON)) exceeds VSET, the over-current

comparator trips to set the over-current latch. Both VSET and

VDS are referenced to VIN and a small capacitor across

ROCSET hel p s VOCSET track the vari ations of VIN due to

FAULT

LATCH

POR

COUNTER

OC1

LUV

0.15V

VCC

FAULT

FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC

OVER

CURRENT

LATCH INHIBIT

INDUCTOR CURRENTSOFT-START

FIGURE 8. OVER-CURRENT OPERATION

TIME

T1 T2 T3T0 T4

FAULT/RT

10V

OVERLOAD

APPLIED

COUNT

= 1 COUNT

= 2 COUNT

= 3

FAULT

REPORTED

HIP6018

232

MOSFET switching. The over-current function will trip at a peak

inductor current ( IPEAK) determined by:

The OC trip point varies with MOSFET’s temperature. To avoid

over-current tripping in the normal operating load range,

determine the ROCSET resist or f rom the equati on above with:

1. The maxi mum rDS(ON) at the highest junction

temperature.

2. Th e mi ni m um I OCSET from the specification table.

3. Determine IPEAK for IPEAK > IOUT(MAX) + (∆I)/2,

where ∆I is the output induct or ri pple cur rent.

For an equ ation for the outpu t induc to r ripple curr ent see

the section under compon ent guidel ines t itled ‘Output

Inductor Sel ecti on’.

OUT1 Voltage Program

The output voltage of the PWM converter is programmed to

discrete levels between 1.8VDC and 3.5VDC. This output is

designe d to suppl y the micropr oces sor core volta ge. The

voltage identification (VID) pins program an internal voltage

reference (DACOUT) through a TTL-compatible 5-bit

digital-to-analog converter. The level of DACOUT also sets

the PG OOD and OVP thr esh old s. Tabl e 1 specif ies the

DACOU T vol tage f or the di fferen t combi nati ons of

connections on the VID pins. The VID pins can be left open

for a logic 1 input, becau se they ar e inte rnally pulled up t o

+5V by a 10µA (typically) current source. Changing the VID

inputs duri ng operat ion is not recom men ded. The sud den

change in the resu lting refer ence vo ltage could to ggle th e

PGOOD signal and exercise the over-voltage protection. Al l

VID pin combi nations r esulting in an INHIBIT di sable the IC

and the open-collector at the PGOOD pin.

Application Guidelines

Soft-Start Interval

Initially, the soft- start func ti on clamps the error amplifier’s

output of the PWM converter. After the out put voltage

increases to appr oximately 8 0% of the set value, the

reference inp ut of the error amplifier is clamped to a volt age

proportion al t o the SS pin vol tage. Both li near outputs follow

a simil ar start -up sequence. The resulting output vol tage

sequence is shown in Figure 6.

IPEAK = IOCSET x ROCSET

rDS ON()

-----------------------------------------------------

UGATE

OCSET

PHASE

OVER-

CURRENT1

GATE

CONTROL

VCC

OC1

200µA

VDS

VSET

ROCSET

VIN = +5V

OVER-CURRENT TRIP: VDS > VSET

(iD • rDS(O N) > IOCSET • ROCSET)

IOCSET

FIGURE 9. OVER-CURRENT DETECTION

PWM VPHASE = VIN - VDS

VOCSET = VIN - VSET

DRIVE

HIP6018

VCC

LGATE

PGND

TABLE 1. VOUT1 VOLT AGE PROGR AM

PIN NAME NOMINAL

OUT1

VOLTAGE

DACOUTVID4 VID3 VID2 VID1 VID0

01XXXINHIBIT

0011XINHIBIT

001011.80

001001.85

000111.90

000101.95

000012.00

000002.05

11111INHIBIT

111102.1

111012.2

111002.3

110112.4

110102.5

110012.6

110002.7

101112.8

101102.9

101013.0

101003.1

100113.2

100103.3

100013.4

100003.5

NOTE: 0 = connected to GND or VSS, 1 = o pen or connected to 5V

through pull-up resistors, X = don’t care

HIP6018

233

The soft -star t funct ion cont rols the outp ut volt age rate of r ise

to lim it the current surge at st art-up. The soft-start interval is

programmed by the soft-start capacitor, CSS. Programming

a faster soft -st art inter val incre ases the peak surge current.

The peak surge current occurs dur ing the initi al output

voltage rise to 80% of the set value.

Shutdown

The PWM output does not switch until the soft-start voltage

(VSS) exc eeds the oscil lator’s valley voltage. Additionally,

the ref erence on each li near’s ampli fier is clamped to the

soft -start volt age. Holding the SS pi n low with an open drain

or collecto r si gnal turns off all three regulators.

The VID codes resul ting in an INHIBIT as sh own in Table 1

also shuts down the IC.

Lay out C on s i dera ti ons

MOSFETs swi tch very fas t and efficiently. The speed with

which the current transitio ns from on e device to anothe r

causes voltage spi kes across the interconnecting

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device ove r-voltag e str ess. Careful component

layout and prin ted circui t design mini mizes the volt age

spikes in the converter. Consider, as an example, the turn-

off tran sition of the upper PWM MOSFET. Prior to turn-off ,

the u pper MOSFET was c arryi ng the f ull load cu rrent . Duri ng

the turn-off, current stops flowing in th e upper MOSFET and

is pi cked up by the lower MOSFET ( and/or parallel Schottky

diode). Any indu ctance in the switched current path

genera tes a larg e volt age spik e duri ng t he swit ching i nterv al.

Careful component selection, tight layout of the critical

com ponents, and short, wide cir cuit traces minimize the

magn itude of voltage spikes. Contact Intersil for evaluation

board drawings of the component placement and prin ted

cir cuit board.

There are two sets of critical compone nts in a DC-DC

converter using a HIP6018 controller. The power

com ponents are the most critica l because they swi tch large

amou nts of energy. The cri tical smal l si gnal compon ents

connect to sensi tive nodes or supply criti cal bypassing

current.

The power components should be placed first . Locate the

input capacitors close to the power sw it ches. Minimize the

length of the conn ections between the input capacitor s and

the power switches. Loc ate the output induc tor and output

capacitors between the MOSFETs and the load. Locate th e

PWM cont rol ler close t o the MOSFETs.

The critica l small signa l components include the byp ass

capacitor for VCC and the sof t-star t capacitor, CSS. Loc ate

these components close to thei r co nnecting pin s on the

control IC. Minimize any leakage cur rent paths from SS

node because the internal current source is only 11µA.

A multi-layer printed circuit board is recommended. Figure 10

shows the connections of the cr it ical components in the

converte r. Note that cap a c itors CIN and C OUT could each

represent numerous physical capacitors. Dedi cate one solid

layer for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate anot her

soli d layer as a power pl ane and break this plane into

smaller islands of common voltage levels. The power plane

should support the input power and output power nodes.

Use copper filled polygons on the top and bottom circ uit

laye rs for the phase nodes. Use th e remainin g print ed c ircuit

layers for small si gnal wiring. The wiring traces fr om the

control IC to the MOSFET gate and source sho uld be sized

to carry 1A curren ts. The tr aces for OUT2 need only be

siz ed fo r 0 .2 A . Loc a te C OUT2 close to the HIP6018 IC.

PWM Controller Feedback Compensation

Both PWM controller s use voltage- m ode control fo r out put

regulatio n. Thi s section highlights the design consi deration

for a vol tage-mode controller. Apply the methods and

considerations to both PWM controllers.

Figure 11 highlights the voltage-mode control loop for a

sync hronous -rectified buck co nverter. The o utput voltage is

regulated to the reference voltage level. The reference

voltage level is the DAC output voltage for the PWM

controller. The error amplifier output (VE/A) is compared with

the oscillator (OSC) triangular wave to provide a pulse-width

modulated wave with an amplitude of VIN at the PHASE node.

The PWM wave is smoothed by the output filter (LO and CO).

The modulator transfer function is the smal l-signal transfer

function of VOUT/VE/A. Th is function is dominated by a DC

gain an d the outp ut fil ter, wit h a dou ble pol e break freque ncy

at FLC and a zero at FESR. The DC gain of the modulator is

simply the input voltage, VIN, divided by the peak-to- peak

oscillator voltage, ∆VOSC.

VOUT1

CSS

+12V CVCC

LOAD

VIA CONNECTION TO GROUND PLANE

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

LOUT1

COUT1

CR1

LOAD

CIN

VOUT3

+5VIN

FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

KEY

HIP6018

SS PGND

LGATE1

UGATE1

PHASE1

GATE3

VCC GND

VIN2

+3.3VIN

LOAD

COUT2

VOUT2

OCSET1 ROCSET1

COCSET1

HIP6018

234

Modula tor Break Fr equ ency Equations

The com pensation net work c onsists of the err or amplifier

internal to the HIP6 018 and the impedance networks ZIN

and ZFB. The g oal of the compen sation network is t o provi de

a closed loop transfer function with an acceptable 0dB

crossing frequency (f0dB) and adequate p hase m argin.

Phase ma rgi n is the difference between the cl osed loop

phase at f0dB and 180 degrees. The equations below relate

the compensation network’s poles, zeros and gain to the

com ponents (R1, R2, R3, C1, C2, a nd C3) in Figur e 11.

Use these guidelines for locating the poles and zeros of the

com pensation net work:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)

3. Place 2ND Zero at Filter’ s Double Pole

4. Place 1ST Pole at the ESR Zero

5. Place 2ND Pole at Half the Switching Frequency

6. Check Gai n against Erro r Ampli fier’s O pen-Loop Gain

7. Estim ate Phase Margin - Repeat i f Necessary

Compens ation Break Frequ ency Equations

Figure 12 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual modulator gain has a peak due

to the high Q factor of the output filter at FLC, which is not

shown in Figure 12. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

er r or a mpl if ie r gai n boun ds th e c om pe nsat i on ga in. C he ck t h e

compensation gain at FP2 with the capabilities of the error

amplifier. The closed loop gain is constructed on the log-log

graph of Figure 12 by adding the modulator gain (in dB) to the

compensation gain (in dB). This is equivalent to multiplying

the modulator transfer function to the compensation transfer

function and plotting the gain.

The com pensation gai n uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth loop. A

stable contr ol l oop has a 0dB gain crossi ng wit h

-20dB/decade slope and a phase margin great er than 45

degrees. Incl ude worst case component vari ati ons when

determining phase margin.

Component Selection Guidelines

Output Cap acitor Selection

The output capacitors for each output have uni que

requirements. In general th e ou tput capaci tors should be

selected to meet t he dynam ic regulation requirements.

Additionally, the PWM converters require an out put

capacitor to filter the current ripple. The linear regulator is

int ernall y compe nsated and requires an output capac itor that

meets the stability requi rements. The lo ad transient for the

FIGURE 11. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

VOUT

OSC

REFERENCE

ESR

VIN

∆VOSC

ERROR

AMP

PWM DRIVER

(PARASITIC)

ZFB

REFERENCE

R3R2 C3

COMP

VOUT

ZFB

HIP6018

ZIN

COMP

DRIVER

DETAILED FEEDBACK COMPENSATION

PHASE

VE/A

-ZIN

FLC 1

2πLOCO

××

----------------------------------------= FESR 1

2πESR CO

××

-----------------------------------------=

FZ1 1

2πR×2C1×

-----------------------------------=

FZ2 1

2πR1 R3+()C3××

-------------------------------------------------------=

FP1 1

2πR2C1 C2×

C1 C2+

----------------------





××

-------------------------------------------------------=

FP2 1

2πR×3C3×

-----------------------------------=

100

-20

-40

-60

FP1

FZ2

10M1M100K10K1K10010

OPEN LOOP

ERROR AMP GAIN

FZ1 FP2

20LOG

FLC FESR

COMPENSATION

GAIN (dB)

FREQUENCY (Hz)

GAIN

20LOG

(VIN/∆VOSC)

MODULATOR

GAIN

(R2/R1)

FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP

GAI N

HIP6018

235

microprocessor core requires high quality capacitors t o

supply the high slew rate (di/dt) current demands.

PWM Output Capacitors

Modern microprocessors produce transient load rates above

10A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and ESL (effective

series inductance) parameters rather than actual capacitance.

High fr equency dec oupling capac itors should be placed as

clos e to the po wer pins o f the l oad as p hysical ly pos sible . Be

careful not to add inductance i n the ci rcuit board wiring that

could cancel the usefulness of these low inductance

com ponents. Consul t wi th the ma nufacturer of the load on

specific dec oupling requ irements.

Use only specialized low-ESR capacitors intended for

switching regulator applications for the bulk capacitors. The

bulk capacitor’s ESR determines the output ripple voltage and

the initial voltage drop after a high slew-rate transient. An

alum inum elect rolyti c capacitor’ s ESR value is related to the

case size with lower ESR ava ilable in larger case sizes.

However, the equivalent series inductance of these capacitors

increases with case size and can reduce the usefulness of the

capacitor to high slew-rate transient loading. Unfortunately,

ESL is not a specified parameter. Work with your capacitor

supplier and measure the capacitor’s impedance with

frequency to select suitable components. In most cases,

multiple electrolytic capacitors of small case size perform

better than a single large case capacitor. For a given transient

load m agnitude, the output voltage tr ans ient resp ons e due to

the output capacitor characteristics can be approximated by

the following equation:

Linear Output Capacitors

The output capacitors for the li near regulator and the linear

contr oll er provi de d ynamic loa d c urrent. The linea r cont roller

uses dom inant pole comp ensation integrated in t he error

amplifier and is insensitive to output capacitor selection.

Capacitor, COUT3 shou ld be selected for transient l oad

regulation.

The output capacitor for the linear regul ator provides loop

stability. The linear regulator (OUT2) requires an output

capacitor characteristic show n in Fi gure 13 . The upper li ne

plots the 45 phase margin with 150mA load and the lower

line is the 45 phase margin limit with a 10mA load. Select a

COUT2 capacitor wit h characteri stic bet ween the two li m it s.

Outp ut In duct or S electio n

The PWM converter requires an output inductor. The output

inductor is selected to meet t he output voltage ri pple

requirements and sets the converter’s response time to a

load t ransie nt. The ind uctor value determines the converter’s

rip ple curr ent and th e rippl e volta ge is a functi on of the r ipple

current. The rippl e voltage and current are approximated by

the following equat ions:

Incr easing the value of induc tan ce reduce s the r ipp le cur rent

and volt age. However, the large inductance values reduce

the converter ’s response time to a lo ad transient .

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

HIP6018 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

interval required to slew the inductor current from an initial

current value to the post-transient current level. During this

interval the difference between the inductor current and the

transient current level must be supplied by the output

capacitors. Minimizing the response time can minimize the

output capacitance required.

The response time to a transient is dif ferent for the

appli cation of load and t he removal of load . The following

equations giv e the approximate response time in terval for

appli cation and re mo val of a tr ansient load :

where: ITRAN is the transient load current st ep, tRISE is the

response time to t he application of load, and tFALL is the

response time to t he removal of load. With a +5V input

source, the worst case response time can be either at the

appli cation or r em oval of l oad, and depende nt upon the

output volta ge setting. Be sure to check both of these

equations at the minim um and maximum output levels for

the worst case resp onse ti m e.

VTRAN ESL dITRAN

---------------------×ESR ITRAN

×+=

10 1000100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

CAPACITANCE (µF)

ESR (Ω)

FIGURE 13. COUT2 OUTPUT CAPACITOR

STABLE

OPERATION

∆IVIN VOUT

–

FSLO

--------------------------------VOUT

VIN

----------------×=∆VOUT ∆IESR×=

tRISE LOITRAN

VIN VOUT

–

--------------------------------= tFALL LOITRAN

VOUT

-------------------------------=

HIP6018

236

Input Capacitor Selection

The i mport ant p arameter s f or t he bulk input ca pacit or are th e

volt age rating and the RMS current rating. For r eli able

operation, select the bulk capacitor with volt age and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline.

Use a mix of input bypass capacito rs to control the volt age

overshoot across the MOSFETs. Use ceramic capaci tance

for the high frequency decoupling and bulk capacitors to

suppl y the RMS c urrent. Smal l cera mic c apacit ors should be

placed very clos e to th e upper MOSFET to suppress the

volt age induced in t he parasitic circuit impedances.

For a thr ough hole design, several electrolytic capaci tors

(Panasonic HFQ series or Nichicon PL series or Sany o

MV- GX or equivalent ) may be needed. For surface m ount

designs, solid tantalum capacitor s can be used, but caution

mus t be exercised wi th regard to t he capacitor sur ge current

rating. Thes e capacitors must be capable of handl ing the

surge-curr ent at power-up. The TPS series avail able from

AVX, and the 593D seri es from Sprague are both sur ge

current tested.

MOSFET Selection/Considerations

The HIP6018 requires 3 N-Channe l power MOSFETs . Two

MOSFETs ar e used in the synchronous-rectified buck

topol ogy of t he PWM c onvert er. The l inear contr oller dri ves a

MOSFET as a pass t ransistor. These shou ld be sel ected

based up on rDS(ON), gate suppl y requi rem ents, a nd thermal

management requirements.

PWM1 MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the dominant

design factors. The power dissipation includes two loss

components; conduction loss and switching loss. These

losses are distributed between the upper and lower

MO SFETs ac cor ding t o duty fa ctor (se e th e equat ions belo w).

The conduction loss is the only component of power

dissipation for the lower MOSFET. Only the upper MOSFET

has switching losses, since the lower device turns on into near

zero voltage.

The equations bel ow assum e li near volt age-current

transitions and do not model power loss due to the reverse-

recovery of the lower MOSFET’s body diode. The gate-

charge losses are proportional to the switching frequency

(FS) and ar e dissipated by the HIP6018, thus not

contributing to the MOSFETs’ temperature rise. However,

large gate charge increases the switching interval, tSW

which increases the upper MO SFET switching losses.

Ensure that both MOSFETs are within their maximum

junction temp erature at high am bient tempera ture by

calculating the temperature rise according to package

thermal resi stance specificat ions. A separat e heatsink may

be necessary depending upon MOSFET power, package

type, am bient tempera ture and air flow.

The rDS(ON) is diff erent for the t w o previous equations even

if t he type device is used for both. This is because the gate

drive applied to the upper MOSFET is different than the

lower MOSFET. Figure 14 shows the gate drive where the

upper gate-to-source voltage is approximately VCC less the

input supply. For +5V main power and +12VDC for the bias,

the gate-to-source voltage of Q1 is 7V. The lower gate drive

voltage is +12VDC. A logic-level MOSFET is a good choice

for Q1 and a logic-level MOSFET can be used for Q2 if its

absolute gate-to-source voltage rating exceeds the maximum

voltage applied to VCC.

Rectifier CR1 is a clamp that catches t he negative inductor

voltage swing during t he dead ti me between the turn off of the

lower MOSFET and the turn on of the upper MOSFET. The

diode must be a Schott ky type to prevent the lossy parasitic

MOSFET body diode from conducting. It is acceptable to omit

the diode and let the body diode of the lower MOSFET clamp

the negative inductor swing, but efficiency might drop one or

two percent as a result . The di ode's rated rev erse breakdown

voltage must be gr eater t han twice the maximum input vol tage.

Linear Co nt ro ll er MOS FE T S e l ect io n

The main criteria for selection of MOSFET for the linear

regulator is package selection for efficien t re mo val of heat.

The power dissipat ed in a lin ear regulat or i s:

Select a package and heatsink that mai ntains the ju nction

temperature bel ow the maximum rating while operating at

the highest expected ambient temperature.

PUPPER IO2rDS ON()

×VOUT

VIN

------------------------------------------------------------ IOVIN

×tSW

×FS

----------------------------------------------------+=

PLOWER IO2rDS ON()

×VIN VOUT

–()×

VIN

---------------------------------------------------------------------------------=

+12V

PGND

HIP6018

GND

LGATE

UGATE

PHASE

VCC

+5V OR LESS

NOTE:

VGS ≈ VCC

FIGURE 14. OUTPUT GATE DRIVERS

VGS ≈ VCC -5V

CR1

PLINEAR IOVIN VOUT

–()×=

HIP6018

237

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For information regarding Intersil Corporation and its products, see www.int ersil.com

HIP6018 DC-DC Converter Ap plication Circuit

Figure 15 shows an application ci rcuit of a power supply for

a microprocessor computer system. The power supply

provides the micropro cessor core voltage ( VOUT1), th e GTL

bus voltage (VOUT3) and clock generat or voltage (VOUT2)

from +3.3VDC, +5VDC and + 12VDC. For detailed i nformat ion

on the circuit, i ncluding a Bill-of-Ma ter ials and circuit board

descr ipti on, see Appl icat ion Not e AN9805. Also s ee I nters il’s

web page (http://www.intersil.com).

VID1

VID2

VID3

VID4

GND

VCC

+5VIN

VID0

+12VIN

PGND

VSEN1

PGOOD

LGATE1

UGATE1

OCSET1

PHASE1

POWERGOOD

FB1

COMP1

VIN2

DRIVE3

FB3

VOUT2

FB2

C47

VOUT3

VOUT2

C43-46

C24-36

HIP6018

C16

C1-7 C15

C18

VOUT1

R8 C40

C41

C42 R10 R9

C48

R11

R12

R13

R14

270µF

4x1000µF

C19

1000µF

1µH

6x1000µF

1µF

1000pF

HUF76143

HUF76143 7x1000µF

0.039µF

1.1K

3.5µH

0.68µF

10pF

2200pF

4.99K

2.21K

160K 732K

GND

1.87K

10K

RFD3055

VID1

VID2

VID3

VID4

VID0

(1.8 TO 3.5V)

(1.5V)

(2.5V)

15A

FAULT

120

+3.3VIN

FIGURE 15. APPLICATION CIRCUIT

10 RT

HIP6018