ADVANCE INFORMATION
T
his Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
S
heet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 26190 Rev: BAmendment/0
Issue Date: May 23, 200 2
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29LV640MT/B
64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit
3.0 Volt-only Boot Sector Flas h Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■Single power supply operation
— 3 V for read, erase, and program operations
■Manufactured on 0.23 µm MirrorBit process
technology
■SecSi (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
comma nd se quence
— May be programmed and locked at the factory or by
the customer
■Flexible sector architecture
— One hundred twenty-seven 32 Kword/64-Kbyte
sectors
— Eight 4 Kword/8 Kbyte boot sectors
■Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
■Minimum 100 ,00 0 era se cyc le guar an tee per sector
■20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■High performance
— 90 ns access time
— 25 ns page read times
— 0.4 s typical sector erase time
— 5.9 µs typical write buffer word programming time:
16-word/32-byte write buffer reduces overall
programming time for multiple-word/byte updates
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
■Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
■Package options
— 48-pin TSOP
— 63-ball Fine-pitch BGA
— 64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— WP#/ACC input:
Write Protect input (WP#) protects top or bottom two
sectors re gardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
2Am29LV640MT/BApril 26, 2002
ADVANCE INFORMATION
GENERAL DESCRIPTION
The Am29LV640MT/B is a 64 Mbit, 3.0 volt single
power supply flash memory device organized as
4,194,304 words or 8,388,608 bytes . The device has
an 8-b it/16-bi t bus and ca n be progra mmed ei ther in
the host system or in standard EPROM programmers.
An acce ss tim e of 90, 100, 110, or 12 0 ns is av ai la ble .
Note that each access time has a specific operating
volta ge rang e (V CC) and an I/O voltag e range (V IO), as
specified in the Product Selector Guide and the Order-
ing Information sections. The device is offered in a
48-pin TSOP, 63-ball Fine- pitch BGA or 64-ball F orti-
fied BGA pa ck age . Eac h dev ic e ha s se par ate chi p en-
able (CE#), write enable (WE#) and ou tput enable
(OE#) controls.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a VCC input, a high-voltage accelerated program
(ACC) function provides shorter programming times
through increased current on the WP#/ACC input. This
featur e is inten ded to fac ilitate fa ctory th roughput dur-
ing system production, but may also be used in the
field if desired.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timi ng. Write cycles al so inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The sector erase architecture allows memory sec-
tors to be erased and r eprogr amme d with out a ffectin g
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device prog ra mming an d eras ure ar e in iti ated thr oug h
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monito r the Ready /Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
Hardware data protection measures incl ude a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardwar e sector
protection feature disables both program and erase
opera tions in an y combinat ion of secto rs of memory.
This can be achieved in-system or via programming
equipment.
The E rase Suspend/Erase Res ume feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The Program
Suspend/Program Resume feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
The hardware RESET# pin terminat es any operati on
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The Write Protect (WP#) feature p rotects the top or
bottom two sectors by asserting a logic low on the
WP#/ACC pin. T he protected sector wil l still be pro-
tected even during accelerated programming.
The SecSi (Secured Silicon) Sector provides a
128-word /256-by te area f or code or dat a that c an be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
AMD MirrorBit flash technology co mbines years of
Flash memory manufacturing experience to produce
the highest l evels of qua lity, reliabili ty and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
April 26, 2002 Am29LV640MT/B 3
ADVANCE INFORMATION
MIRRORBIT 64 MBIT DEVICE FAMILY
RELATED DOCUMENTS
To downloa d related docume nts, c lick on the fol lowin g
links or go to www.amd.com→Flash M emory→Prod-
uct Information→MirrorBit→Flash In formati on→Tech-
nical Documentation.
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel Strata F lash Mem or y Devic es
Migrating fro m Sin gle -byt e to Three- by te Devic e IDs
AMD MirrorBit™ White Paper
Device Bus Sector Architecture Packages VIO RY/BY# WP#, ACC WP# Protection
LV065MU x8 Uniform (64 Kbyte) 48-pin TSOP (std. & rev. pinout),
63-ball FBGA Yes Yes ACC only No WP#
LV640MT/B x8/x16 Boot (8 x 8 Kbyte
at top & bottom) 48-pin TSOP, 63-ball Fine-pitch BGA,
64-ball Fortified BGA No Yes WP#/ACC pin 2 x 8 Kbyte
top or bottom
LV640MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout),
64 Fortified BGA Yes Yes WP#/A CC pin 1 x 64 Kbyte
high or low
LV641MH/L x16 Uniform (32 Kword) 48-pin TSOP (std. & rev. pinout) Yes No Separate WP#
and ACC pins 1 x 32 Kword
top or bottom
LV640MU x16 Uniform (32 Kword) 64-ball Fortified BGA Yes Yes ACC only No WP#
4Am29LV640MT/BApril 26, 2002
ADVANCE INFORMATION
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .....................................................10
Word/Byte Configuration ........................................................ 10
Requirements for Reading Array Data ...................................10
Page Mode Read ....................................................................11
Writing Commands/Command Sequences ............................11
Write Buffer .............................................................................11
Accelerated Program Operation .............................................11
Autoselect Functions ..............................................................11
Standby Mode........................................................................ 11
Automatic Sleep Mode ...........................................................12
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode ..............................................................12
Table 2. Am29LV640MT Top Boot Sector Architecture ..................12
Table 3. Am29LV640MB Bottom Boot Sector Architecture .............15
Autoselect Mode..................................................................... 18
Table 4. Autoselect Codes, (High Voltage Method) .......................18
Sector Group Protection and Unprotection .............................19
Table 5. Am29LV640MT Top Boot Sector Protection .....................19
Table 6. Am29LV640MB Bottom Boot Sector Protection ................19
Write Protect (WP#) ................................................................20
Temporary Sector Group Unprotect .......................................20
Figure 1. Temporary Sector Group Unprotect Operation................ 20
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 21
SecSi (Secured Silicon) Sector Flash Memory Region ..........22
Table 7. SecSi Sector Contents ......................................................22
Hardware Data Protection ......................................................22
Low VCC Write Inhibit ............................................................22
Write Pulse “Glitch” Protection ...............................................23
Logical Inhibit ..........................................................................23
Power-Up Write Inhibit ............................................................23
Common Flash Memory Interface (CFI). . . . . . . 23
Table 8. CFI Query Identification String.............................. 23
Table 9. System Interface String......................................................24
Table 10. Device Geometry Definition................................. 24
Table 11. Primary Vendor-Specific Extended Query........... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................25
Reset Command .....................................................................26
Autoselect Command Sequence ............................................26
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..26
Word/Byte Program Command Sequence .............................26
Unlock Bypass Command Sequence .....................................27
Write Buffer Programming ......................................................27
Accelerated Program ..............................................................28
Figure 3. Write Buffer Programming Operation............................... 29
Figure 4. Program Operation.......................................................... 30
Program Suspend/Program Resume Command Sequence ...30
Figure 5. Program Suspend/Program Resume............................... 31
Chip Erase Command Sequence ...........................................31
Sector Erase Command Sequence ........................................31
Erase Suspend/Erase Resume Commands ...........................32
Figure 6. Erase Operation.............................................................. 33
Command Definitions............................................................. 34
Table 12. Command Definitions (x16 Mode, BYTE# = VIH)............ 34
Table 13. Command Definitions (x8 Mode, BYTE# = VIL)............... 35
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 36
DQ7: Data# Polling .................................................................36
Figure 7. Data# Polling Algorithm .................................................. 36
RY/BY#: Ready/Busy#............................................................ 37
DQ6: Toggle Bit I ....................................................................37
Figure 8. Toggle Bit Algorithm........................................................ 38
DQ2: Toggle Bit II ...................................................................38
Reading Toggle Bits DQ6/DQ2 ...............................................38
DQ5: Exceeded Timing Limits ................................................39
DQ3: Sector Erase Timer .......................................................39
DQ1: Write-to-Buffer Abort .....................................................39
Table 14. Write Operation Status ................................................... 39
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 40
Figure 9. Maximum Negative Overshoot Waveform..................... 40
Figure 10. Maximum Positive Overshoot Waveform..................... 40
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 40
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11. Test Setup.................................................................... 42
Table 15. Test Specifications ...................... ............. ............. ......... 42
Key to Switching Waveforms. . . . . . . . . . . . . . . . 42
Figure 12. Input Waveforms and
Measurement Levels...................................................................... 42
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43
Read-Only Operations ...........................................................43
Figure 13. Read Operation Timings............................................... 43
Figure 14. Page Read Timings...................................................... 44
Hardware Reset (RESET#) ....................................................45
Figure 15. Reset Timings............................................................... 45
Erase and Program Operations ..............................................46
Figure 16. Program Operation Timings.......................................... 47
Figure 17. Accelerated Program Timing Diagram.......................... 47
Figure 18. Chip/Sector Erase Operation Timings.......................... 48
Figure 19. Data# Polling Timings (During Embedded Algorithms). 49
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 50
Figure 21. DQ2 vs. DQ6................................................................. 50
Temporary Sector Unprotect ..................................................51
Figure 22. Temporary Sector Group Unprotect Timing Diagram... 51
Figure 23. Sector Group Protect and Unprotect Timing Diagram.. 52
Alternate CE# Controlled Erase and Program Operations .....53
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 54
Erase And Programming Performance. . . . . . . . 55
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 55
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 55
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56
TS056—56-Pin Standard Pinout Thin Small Outline Package
(TSOP) ...................................................................................56
FBE063—6e-Ball Fine-pitch Ball Grid Array (FBGA)
12 x 11 mm Package .............................................................. 57
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
13 x 11 mm Package .............................................................. 58
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 59
April 26, 2002 Am29LV640MT/B 5
ADVANCE INFORMATION
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Part Number Am29LV640MT/B
Speed Option VCC = 3.0–3.6 V 90R
VCC = 2.7–3.6 V 100 110 120
Max . Access Time (ns) 90 100 110 120
Max. CE# Access Time (ns) 90 100 110 120
Max. Page access time (tPACC)25 30 40 40
Max. OE# Access Time (ns) 25 30 40 40
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enab le
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
WP#/ACC
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A21–A0
VCC
6Am29LV640MT/BApril 26, 2002
ADVANCE INFORMATION
CONNECTION DIAGRAMS
C2 D2 E2 F2 G2 H2 J2 K2
C3 D3 E3 F3 G3 H3 J3 K3
C4 D4 E4 F4 G4 H4 J4 K4
C5 D5 E5 F5 G5 H5 J5 K5
C6 D6 E6 F6 G6 H6 J6 K6
C7 D7A7 B7
A8 B8
A1 B1
A2
E7 F7 G7 H7 J7 K7 L7
L8
M7
M8
L1
L2
M1
M2
NC* NC*NC*
NC* NC* NC* NC*
NC* NC*
NC* NC*NC NC
NC NC DQ15/A-1 VSSBYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
VCC DQ4DQ12DQ5A19A21RESET#WE#
DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# VSSCE#A0A1A2A4A3
* Balls are shorted together via the substrate but not connected to the die.
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A1
A17
A7
A6
A5
A4
A3
A2
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
56-Pin Standard TSOP48-Pin Standard TSOP
63-ball Fine-pitch BGA
Top View, Balls Facing Down
April 26, 2002 Am29LV640MT/B 7
ADVANCE INFORMATION
CONNECTION DIAGRAMS
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (TSOP, BGA, SSOP, PDIP,
PLCC). The package and/or data integrity may be
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
B3 C3 D3 E3 F3 G3 H3
B4 C4 D4 E4 F4 G4 H4
B5 C5 D5 E5 F5 G5 H5
B6 C6 D6 E6 F6 G6 H6
B7 C7 D7 E7 F7 G7 H7
B8 C8 D8 E8 F8 G8 H8
NCNCNCVSS
NCNCNC
VSS
DQ15/A-1BYTE#A16A15A14A12
DQ6
DQ13DQ14DQ7A11A10A8
DQ4VCC
DQ12DQ5A19A21RESET#
DQ3DQ11DQ10DQ2A20A18WP#/ACC
DQ1DQ9DQ8DQ0A5A6A17
A3
A4
A5
A6
A7
A8
NC
A13
A9
WE#
RY/BY#
A7
B2 C2 D2 E2 F2 G2 H2
VSS
OE#CE#A0A1A2A4
A2
A3
B1 C1 D1 E1 F1 G1 H1
NCNCVIO
NCNCNCNC
A1
NC
64-Ball Fortified BGA (FBGA)
Top View, Balls Facing Down
8Am29LV640MT/BApril 26, 2002
ADVANCE INFORMATION
PIN DESCRIPTION
A21–A0 = 22 Address inpu ts
DQ14–DQ0 = 15 Data inputs /ou tput s
DQ15/A-1 = DQ15 (Data input/output, word mode),
A-1 (LSB Address input, byte mode)
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
WP#/ACC = Hardware Write Protect input/Pro-
gramming Acceleration input
RESET# = Hardware Reset Pin input
RY/BY# = Ready/Busy output
BYTE# = Selects 8-bit or 16-bit mode
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for
speed opt ion s and vo lta ge
supply tolerances)
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
22 16 or 8
DQ15–DQ0
(A-1)
A21–A0
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
BYTE#
April 26, 2002 Am29LV640MT/B 9
ADVANCE INFORMATION
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid C o mbin a tions
V alid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the loca l AMD sales o ffi ce to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
Am29LV640M T 90R PC I
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
E = 48-Pin Thi n Small Outline Pac ka ge ( TSO P) Standard Pi nout (TS 048)
PC = 64-Ball Fortified Ball Grid Array (FBGA),
1.0 mm pitch, 13 x 11 mm package (LAA064)
WH = 63-Ball Fine Pitch Ball Grid Array (FBGA),
0.80 mm pitch, 12 x 11 mm packa ge (FBE063 )
SPEED OPTION
See Produ ct Sel ec to r Guide and Valid Combinat ions
SECTOR ARCHITECTURE AND WP# PROTECT ION (WP# = VIL)
T = Top boot secto r de vi ce , top two addr es s sectors pr ot ected
B = Bottom boot sector device, bot t om two addres s sectors protect ed
DEVICE NUMBER/DESCRIPTIO N
Am29LV640MT/B
64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit Boot Sector Flash Memory
3.0 Volt-only Re ad, Program, and Erase
Valid Combinations for
TSOP Package Speed
(ns) VCC
Range
Am29LV640MT90R,
Am29LV640MB90R
EI,
FI
90 3.0–3.6 V
Am29LV640MT100,
Am29LV640MB100 100
2.7–3.6 V
Am29LV640MT110,
Am29LV640MB110 110
Am29LV640MT120,
Am29LV640MB120 120
Valid Combinatio ns for
BGA Packages Speed
(ns) VCC
Range
Order Number Package Marking
Am29LV640MT90R WHI L640MT90RI
90 3.0–
3.6 V
PCI L640MT90NI
Am29LV640MB90R WHI L640MB90RI
PCI L640MB10NI
Am29LV640MT100 WHI L640MT10VI
100
2.7–
3.6 V
PCI L640MT10PI
Am29LV640MB100 WHI L640MB10VI
PCI L640MB10PI
Am29LV640MT110 WHI L640MT11VI
110
PCI L640MT11PI
Am29LV640MB110 WHI L640MB11VI
PCI L640MB11PI
Am29LV640MT120 WHI L640MT12VI
120
PCI L640MT12PI
Am29LV640MB120 WHI L640MB12VI
PCI L640MB12PI
10 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
DEVICE BUS OPERATIONS
This section describe s the requirements and use of
the device bus operations, which are initiated through
the in ternal co mmand r egiste r. The comma nd regi ster
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to exec ute the comm and. Th e c onten ts o f th e
register serve as inputs to the internal state machine.
The state m achine outputs dic tate the function of the
device. Tabl e 1 lists the device bu s operat ions, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = V IH, VID = 11.5–12.5 V, VHH = 11.5–12 .5 V, X = Don’ t Care, SA = Sector A ddress,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0 in word mode; A21:A-1 in byte mode. Sector addresses are A21:A12 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the top two or bottom two sectors will be protected or
unprotected as determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected
when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The BY TE# pin contr ols whethe r the devic e data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pi n is set a t logic ‘0 ’, the dev ic e is in byt e
config uration, and only data I/O pi ns DQ0–DQ7 are
active an d controlle d by CE# and OE#. T he data I/O
pins DQ8 –DQ14 are tr i-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and O E# pins to VIL. CE# is the power
contro l and sel ects the devi ce. OE # is the outp ut con-
trol and gates array data to the output pins. WE#
should remain at VIH.
Operation CE# OE# WE# RESET# WP# ACC Addresses
(Note 2) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read L L H H XX AIN DOUT DOUT DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/ E r as e) L H L H (Not e 3) X AIN (Note 4) (Note 4)
Accelerated Pr ogram L H L H (Note 3) VHH AIN (Note 4) (Note 4)
Standby VCC ±
0.3 V XXVCC ±
0.3 V XH XHigh-Z High-Z High-Z
Output Di sab l e L H H H XX XHigh-Z High-Z High-Z
Reset X X X L XX XHigh-Z High-Z High-Z
Sector Group Protect
(Note 2) LHL V
ID HX
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L (Note 4) X X
Sector Group Unprotect
(Note 2) LHL V
ID HX
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L (Note 4) X X
T emporary Sector Group
Unprotect XXX V
ID HX AIN (Note 4) (Note 4) High-Z
April 26, 2002 Am29LV640MT/B 11
ADVANCE INFORMATION
The internal state machine is set for reading array data
upon dev ice power -up, or after a hardwa re res et. Th is
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is n ecessary in this m ode to obtai n array data .
Stand ard micro process or read cyc les that as sert vali d
address es on t he devi ce add ress inputs produ ce va lid
data on t he device data outputs. The device rema ins
enabled for read ac cess until the co mmand register
contents are altered.
See “Rea ding Arra y Data” fo r more inform ation. Refe r
to the AC Read-Onl y Oper ation s tab le for tim ing spec-
ifications and to Figure 13 for the timing diagram.
Refer to the DC Characteristics table for the active
current specification on reading array data.
Page Mode Read
The devi ce is ca pable of fast pag e mode read and is
compatible with the page mode Mask ROM read oper-
ation. T his mode provides faster rea d access s peed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.
The ran dom or initial pa ge access is eq ual to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserte d and reasse rted for a subsequent ac cess,
the access time is tACC or tCE. Fast page mode ac-
cesse s are obtai ned by ke eping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes progra mming data to the dev ice and erasin g
sectors of memor y), the system must dr ive WE# an d
CE# to VIL, and OE# to VIH.
The devic e fe atures a n Unlock Bypas s mode to facil-
itate faster programming. Once the dev ice enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has detai ls on p rogrammin g data to the devic e using
both standard and Unlock Bypass command se-
quences.
An erase operation can erase one sector , multiple sec-
tors, or the ent ire device . Tables 3 and 2 indi cates the
address space that each sector occupies.
Refer to the DC Characteristics table for the active
curre nt spec if ic ati on f or the write mode. T he AC Char -
acteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms . See
“Write Buffer” for more information.
Accelerated Progr am Operation
The device offers accelerated program operations
through the ACC function. T his is one of two func tions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on this pi n, the devi ce auto-
maticall y enters th e aforemention ed Unlock B ypass
mode, temporarily unprotects any protected sectors,
and u ses the h igher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as requir ed by the Unlock Bypass mo de. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not
be at VHH for operations other than accelerated pro-
gramming, or de vice damage may result. In ad dition,
no external pullup is necessary sinc e the WP#/ACC
pin has internal pullup to VCC.
Autoselect Fun ctions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselec t codes from the inter -
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. R efer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The devic e ente rs the CM OS stan dby m ode whe n the
CE# and RE SET# pins ar e both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the s tandby curren t will be gr eater. The devi ce re-
quires standard access time (tCE) for read access
when the devic e is in eithe r of these standby modes,
before it is ready to read data.
12 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
If the device is deselecte d during eras ure or progra m-
ming, the device draws active current until the
operation is completed.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Slee p Mode
The automatic sleep mode minimizes Flash device en-
ergy cons umption. The dev ice automatica lly enables
this mode w hen addr esses r emain s table f or tACC +
30 n s. The aut omatic sleep mode is in dependent of
the CE#, WE# , and OE# control si gnals . Standa rd ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data i s latche d and a lways av ailable t o the s ystem.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
RESET#: Hardware Rese t Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. T he device also resets the i nternal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. Wh en RESE T# is hel d at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Char acteristi cs tables for RESET# pa-
rameters and to Figure 15 for the timing diagram .
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2. Am29LV640MT Top Boot Sector Architecture
Sector Sector Address
A21–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
SA0 0000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh
SA1 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh
SA2 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh
SA3 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh
SA4 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh
SA5 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh
SA6 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh
SA7 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh
SA8 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh
SA9 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh
SA10 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh
SA11 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh
SA12 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh
SA13 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA14 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh
SA15 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh
SA16 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh
SA17 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh
SA18 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh
SA19 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh
SA20 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA21 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA22 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA23 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA24 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA25 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA26 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA27 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
April 26, 2002 Am29LV640MT/B 13
ADVANCE INFORMATION
SA28 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh
SA29 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA30 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA31 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh
SA32 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh
SA33 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA34 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA35 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA36 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA37 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA38 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA39 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA40 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA41 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA42 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA43 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA44 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA45 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA46 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA47 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA48 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA49 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA50 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA51 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA52 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA53 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA54 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA55 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA56 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA57 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA58 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA59 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA60 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA61 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA62 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA63 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh
SA64 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh
SA65 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh
SA66 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh
SA67 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh
SA68 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh
SA69 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh
SA70 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh
SA71 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh
SA72 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh
SA73 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh
SA74 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh
SA75 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh
SA76 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh
SA77 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh
SA78 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh
SA79 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh
SA80 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh
SA81 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh
SA82 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh
Table 2. Am29LV640MT Top Boot Sector Architecture (Continued)
Sector Sector Address
A21–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
14 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
SA83 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh
SA84 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh
SA85 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh
SA86 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh
SA87 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh
SA88 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh
SA89 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh
SA90 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh
SA91 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh
SA92 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh
SA93 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh
SA94 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh
SA95 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh
SA96 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh
SA97 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh
SA98 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh
SA99 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh
SA100 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh
SA101 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh
SA102 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh
SA103 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh
SA104 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh
SA105 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh
SA106 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh
SA107 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh
SA108 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh
SA109 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh
SA110 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh
SA111 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh
SA112 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh
SA113 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh
SA114 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh
SA115 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh
SA116 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh
SA117 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh
SA118 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh
SA119 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh
SA120 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh
SA121 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh
SA122 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh
SA123 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh
SA124 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh
SA125 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh
SA126 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh
SA127 1111111000 8/4 7F0000h–7F1FFFh 3F8000h–3F8FFFh
SA128 1111111001 8/4 7F2000h–7F3FFFh 3F9000h–3F9FFFh
SA129 1111111010 8/4 7F4000h–7F5FFFh 3FA000h–3FAFFFh
SA130 1111111011 8/4 7F6000h–7F7FFFh 3FB000h–3FBFFFh
SA131 1111111100 8/4 7F8000h–7F9FFFh 3FC000h–3FCFFFh
SA132 1111111101 8/4 7FA000h–7FBFFFh 3FD000h–3FDFFFh
SA133 1111111110 8/4 7FC000h–7FDFFFh 3FE000h–3FEFFFh
SA134 1111111111 8/4 7FE000h–7FFFFFh 3FF000h–3FFFFFh
Table 2. Am29LV640MT Top Boot Sector Architecture (Continued)
Sector Sector Address
A21–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
April 26, 2002 Am29LV640MT/B 15
ADVANCE INFORMATION
Table 3. Am29LV640MB Bottom Boot Sector Architecture
Sector Sector Address
A21–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
SA0 0000000000 8/4 000000h–001FFFh 00000h–00FFFh
SA1 0000000001 8/4 002000h–003FFFh 01000h–01FFFh
SA2 0000000010 8/4 004000h–005FFFh 02000h–02FFFh
SA3 0000000011 8/4 006000h–007FFFh 03000h–03FFFh
SA4 0000000100 8/4 008000h–009FFFh 04000h–04FFFh
SA5 0000000101 8/4 00A000h–00BFFFh 05000h–05FFFh
SA6 0000000110 8/4 00C000h–00DFFFh 06000h–06FFFh
SA7 0000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh
SA8 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh
SA9 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh
SA10 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh
SA11 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh
SA12 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh
SA13 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh
SA14 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh
SA15 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh
SA16 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh
SA17 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh
SA18 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh
SA19 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh
SA20 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA21 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh
SA22 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh
SA23 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh
SA24 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh
SA25 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh
SA26 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh
SA27 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh
SA28 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh
SA29 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh
SA30 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh
SA31 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh
SA32 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh
SA33 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA34 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA35 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh
SA36 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA37 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
SA38 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh
SA39 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh
SA40 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA41 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA42 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA43 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA44 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA45 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA46 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA47 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA48 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA49 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA50 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA51 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA52 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA53 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
16 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
SA54 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA55 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA56 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA57 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA58 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA59 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA60 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA61 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA62 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA63 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA64 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA65 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA66 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA67 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA68 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA69 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA70 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh
SA71 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh
SA72 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh
SA73 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh
SA74 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh
SA75 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh
SA76 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh
SA77 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh
SA78 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh
SA79 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh
SA80 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh
SA81 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh
SA82 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh
SA83 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh
SA84 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh
SA85 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh
SA86 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh
SA87 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh
SA88 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh
SA89 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh
SA90 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh
SA91 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh
SA92 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh
SA93 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh
SA94 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh
SA95 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh
SA96 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh
SA97 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh
SA98 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh
SA99 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh
SA100 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh
SA101 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh
SA102 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh
SA103 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh
SA104 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh
SA105 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh
SA106 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh
SA107 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh
SA108 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh
Table 3. Am29LV640MB Bottom Boot Sector Architecture (Continued)
Sector Sector Address
A21–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
April 26, 2002 Am29LV640MT/B 17
ADVANCE INFORMATION
Note: The address range is A21:A-1 in byte mode (BYTE# = VIL) or A21:A0 in word mode (BYTE# = VIH)
SA109 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh
SA110 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh
SA111 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh
SA112 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh
SA113 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh
SA114 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh
SA115 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh
SA116 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh
SA117 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh
SA118 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh
SA119 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh
SA120 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh
SA121 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh
SA122 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh
SA123 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh
SA124 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh
SA125 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh
SA126 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh
SA127 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh
SA128 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh
SA129 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh
SA130 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh
SA131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh
SA132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh
SA133 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh
SA134 1111111000 64/32 7F0000h–7FFFFFh 3F8000h–3FFFFFh
Table 3. Am29LV640MB Bottom Boot Sector Architecture (Continued)
Sector Sector Address
A21–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
18 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
Autoselect Mode
The autos elect mode provid es manufacture r and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algor ithm. Ho wever, the autose lect co des can al so be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Addres s pins
A6, A3, A2, A1, and A0 must be as shown in Table 4.
In addition, when verifying sector protection, the sector
address m us t ap pea r on the appr op riate hi ghe st or der
address bits (see Tables 2 and 3). Table 4 shows the
remaining address bits that are don’t care. When all
necessary bits have been set as required, the pro-
gramming e quipment may then read the correspond-
ing identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register , as shown in Tables 12 and 13. This
method does not requir e VID. Re fer to the Autoselect
Command Sequence section for more information.
Table 4. Autoselect Codes, (High Voltage Method)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Description CE# OE# WE# A21
to
A15
A14
to
A10 A9 A8
to
A7 A6 A5
to
A4
A3
to
A2 A1 A0
DQ8 to DQ15
DQ7 to DQ0
BYTE#
= VIH
BYTE#
= VIL
Manufacturer ID: AMD L L H X X VID X L X L L L 00 X 01h
Device ID
Cycle 1
LLHXX
VID XLX
LLH 22 X 7Eh
Cycle 2 H H L 22 X 10h
Cycle 3 HHH 22 X 00 (bottom boot)
01h (top boot)
Sector Protection
Verification LLHSAX
VID XLX L H L X X 01h (protected),
00h (unprotected)
SecSi Sector Indicator
Bit (DQ7), WP#
protects top two
address sector
LLHXX
VID XLX L HH X X 98h (factory locked),
18h (not factory locked)
SecSi Sector Indicator
Bit (DQ7), WP#
protects bottom two
address sector
LLHXX
VID XLX L HH X X 88h (factory locked),
08h (not factory locked)
April 26, 2002 Am29LV640MT/B 19
ADVANCE INFORMATION
Sector Group Protection and
Unprotection
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent s ectors that ar e protected or unprotected a t
the same time (see Tables 5 and 6). The hardware
sector group unprotection feature re-enables both pro-
gram and erase operations in previously protected
sector groups. S ector group protection /unprotection
can be implemented via two methods.
Secto r pro tec ti on/u nprote ct ion re qui res VID on the R E-
SET# pin only, a nd can be implem ented ei ther in- sys-
tem or via programming equipment. Figure 2 shows
the algorithms and Figure 23 shows the timing dia-
gram. Th is me thod us es s ta ndard mi cr o pr ocess or bus
cycle timing. For sector group unprotect, all unpro-
tected se ctor groups must first be p rotected prior to
the first sector group unprotect write cycle.
The d evice i s shippe d with al l sect or groups unpro-
tected. AMD offers the option of programming and
protecti ng se ctor groups at its factor y pri or to shipp ing
the device through AMD’s ExpressFlash™ Service.
Contact an AMD representative for details.
It is possible to determine whether a sector group is
protect ed or unpro tected. See th e Autoselect Mode
section for details.
Table 5. Am29LV640MT Top Boot
Sector Protection
Sector A21–A12 Sector/
Sector Block Size
SA0 0000000000 8 Kbytes
SA1 0000000001 8 Kbytes
SA2 0000000010 8 Kbytes
SA3 0000000011 8 Kbytes
SA4 0000000100 8 Kbytes
SA5 0000000101 8 Kbytes
SA6 0000000110 8 Kbytes
SA7 0000000111 8 Kbytes
SA8–SA10 0000001XXX,
0000010XXX,
0000011XXX, 192 (3x64) Kbytes
SA11–SA14 00001XXXXX 256 (4x64) Kbytes
SA15–SA18 00010XXXXX 256 (4x64) Kbytes
SA19–SA22 00011XXXXX 256 (4x64) Kbytes
SA23–SA26 00100XXXXX 256 (4x64) Kbytes
SA27-SA30 00101XXXXX 256 (4x64) Kbytes
SA31-SA34 00110XXXXX 256 (4x64) Kbytes
SA35-SA38 00111XXXXX 256 (4x64) Kbytes
SA39-SA42 01000XXXXX 256 (4x64) Kbytes
SA43-SA46 01001XXXXX 256 (4x64) Kbytes
SA47-SA50 01010XXXXX 256 (4x64) Kbytes
SA51-SA54 01011XXXXX 256 (4x64) Kbytes
SA55–SA58 01100XXXXX 256 (4x64) Kbytes
SA59–SA62 01101XXXXX 256 (4x64) Kbytes
SA63–SA66 01110XXXXX 256 (4x64) Kbytes
SA67–SA70 01111XXXXX 256 (4x64) Kbytes
SA71–SA74 10000XXXXX 256 (4x64) Kbytes
SA75–SA78 10001XXXXX 256 (4x64) Kbytes
SA79–SA82 10010XXXXX 256 (4x64) Kbytes
SA83–SA86 10011XXXXX 256 (4x64) Kbytes
SA87–SA90 10100XXXXX 256 (4x64) Kbytes
SA91–SA94 10101XXXXX 256 (4x64) Kbytes
SA95–SA98 10110XXXXX 256 (4x64) Kbytes
SA99–SA102 10111XXXXX 256 (4x64) Kbytes
SA103–SA106 11000XXXXX 256 (4x64) Kbytes
SA107–SA110 11001XXXXX 256 (4x64) Kbytes
SA111–SA114 11010XXXXX 256 (4x64) Kbytes
SA115–SA118 11011XXXXX 256 (4x64) Kbytes
SA119–SA122 11100XXXXX 256 (4x64) Kbytes
SA123–SA126 11101XXXXX 256 (4x64) Kbytes
SA127–SA130 11110XXXXX 256 (4x64) Kbytes
SA131–SA133 1111100XXX,
1111101XXX,
1111110XXX 192 (3x64) Kbytes
SA134 1111111000 8 Kbytes
SA135 1111111001 8 Kbytes
SA136 1111111010 8 Kbytes
SA137 1111111011 8 Kbytes
SA138 1111111100 8 Kbytes
SA139 1111111101 8 Kbytes
SA140 1111111101 8 Kbytes
SA141 1111111111 8 Kbytes
Table 6. Am29LV640MB Bottom Boot
Sector Protection
Sector A21–A12 Sector/
Sector Block Size
SA0 0000000000 8 Kbytes
SA1 0000000001 8 Kbytes
SA2 0000000010 8 Kbytes
SA3 0000000011 8 Kby tes
SA4 0000000100 8 Kbytes
SA5 0000000101 8 Kbytes
SA6 0000000110 8 Kby tes
SA7 0000000111 8 Kby tes
SA8–SA10 0000001XXX,
0000010XXX,
0000011XXX, 192 (3x64) Kbytes
SA11–SA14 00001XXXXX 256 (4x64) Kbytes
SA15–SA18 00010XXXXX 256 (4x64) Kbytes
Sector A21–A12 Sector/
Sector Block Size
20 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the top two or bottom two sectors
without using VID. WP# is one of two functions pro-
vided by the WP#/ACC input.
If the system asserts VIL on the WP #/A CC pin, the de-
vice disables program and erase functions in the first
or last sector independently of whether those sectors
were protected or unprotected using the method de-
scribed in “Sector Group Protection and Unprotection”.
Note that if WP#/ACC is at VIL when the device is in
the standby mode, the maximum input load current is
increased. See the table in “DC Characteristics”.
If the system asser ts VIH on the WP #/ACC pi n, the de-
vice reverts to whether the top or bottom two sectors
were previously set to be protected or unprotected
using the method described in “Sector Group Protec-
tion and Unprotection”. Note: No external pullup is
neces sary sin ce the W P#/ACC pin has in ternal pu llup
to VCC
Temporary Sector Group Unprotect
(Note: In this de vice, a sec tor group cons ists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 6).
This feature allows temporary unp rotection of previ-
ously pro tected sector groups t o change data in -sys-
tem. Th e Sec tor Grou p Unp ro tec t mode is acti vat ed b y
setting the RESET# pin to VID. During this mode, for-
merly protected sector groups can be programmed or
erased by sel ec ti ng the sector gro up ad dres se s. O nc e
VID is removed from the RESET# pin, all the previ-
ously protected sector groups are protected again.
Figure 1 shows the algo rithm, and Figure 22 shows
the timing diagrams, for this feature.
Figure 1. Temporary Sector Group
Unprotect Operation
SA19–SA22 00011XXXXX 256 (4x64) Kbytes
SA23–SA26 00100XXXXX 256 (4x64) Kbytes
SA27-SA30 00101XXXXX 256 (4x64) Kbytes
SA31-SA34 00110XXXXX 256 (4x64) Kbytes
SA35-SA38 00111XXXXX 256 (4x64) Kbytes
SA39-SA42 01000XXXXX 256 (4x64) Kbytes
SA43-SA46 01001XXXXX 256 (4x64) Kbytes
SA47-SA50 01010XXXXX 256 (4x64) Kbytes
SA51-SA54 01011XXXXX 256 (4x64) Kbytes
SA55–SA58 01100XXXXX 256 (4x64) Kbytes
SA59–SA62 01101XXXXX 256 (4x64) Kbytes
SA63–SA66 01110XXXXX 256 (4x64) Kbytes
SA67–SA70 01111XXXXX 256 (4x64) Kbytes
SA71–SA74 10000XXXXX 256 (4x64) Kbytes
SA75–SA78 10001XXXXX 256 (4x64) Kbytes
SA79–SA82 10010XXXXX 256 (4x64) Kbytes
SA83–SA86 10011XXXXX 256 (4x64) Kbytes
SA87–SA90 10100XXXXX 256 (4x64) Kbytes
SA91–SA94 10101XXXXX 256 (4x64) Kbytes
SA95–SA98 10110XXXXX 256 (4x64) Kbytes
SA99–SA102 10111XXXXX 256 (4x64) Kbytes
SA103–SA106 11000XXXXX 256 (4x64) Kbytes
SA107–SA110 11001XXXXX 256 (4x64) Kbytes
SA111–SA114 11010XXXXX 256 (4x64) Kbytes
SA115–SA118 11011XXXXX 256 (4x64) Kbytes
SA119–SA122 11100XXXXX 256 (4x64) Kbytes
SA123–SA126 11101XXXXX 256 (4x64) Kbytes
SA127–SA130 11110XXXXX 256 (4x64) Kbytes
SA131–SA134
1111100XXX,
1111101XXX,
1111110XXX,
1111111XXX
192 (3x64) Kbytes
Table 6. Am29LV640MB Bottom Boot
Sector Protection (Continued)
Sector A21–A12 Sector/
Sector Block Size
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unpro tec t
Comp let ed (N ote 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sector groups unprotected (If WP# = VIL,
the first or last sector will remain protected).
2. All previous ly protected sector groups are protected
once again.
April 26, 2002 Am29LV640MT/B 21
ADVANCE INFORMATION
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up sector
group address
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Read from
sector group address
with A6–A0
= 0xx0010
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Group
Protect complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No
Sector Group
Unprotect:
Write 60h to sector
group address with
A6–A0 = 1xx0010
Set up first sector
group address
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6–A0 = 1xx0010
Read from
sector group
address with
A6–A0 = 1xx0010
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
group
verified?
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No All sector
groups
protected?
Yes
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
Set up
next sector group
address
No
Yes
No
Yes
No
No
Yes
No
Sector Group
Protect
Algorithm
Sector Group
Unprotect
Algorithm
First Write
Cycle = 60h?
Protect
another
sector group?
Reset
PLSCNT = 1
22 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecS i Sector i s 128 words /256 bytes i n
length , and us es a SecSi S ec tor Indicato r Bit (D Q7 ) t o
indicate whether or not the SecSi Sector is locked
when shi ppe d from the facto ry. T his bi t i s per ma nen tly
set at the factory and cannot be changed, which pre-
vents cloning of a factory locked part. This ensures the
securi ty of the E SN once the product is shi ppe d to the
field.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory -locke d vers ion is always prot ected wh en sh ippe d
from the factory, and has the SecSi (Secured Silicon)
Sector Indic ator Bit per manen tly set to a “1.” Th e cus-
tomer-l ockable ve rsion is shi pped with the Sec Si Sec-
tor unprotected, allowing customers to program the
secto r afte r rece iving the d evice. The c ustome r-lock-
able version also has the SecSi Sec tor Indicator Bit
perm anentl y set to a “0.” Thu s, the S ecSi Sec tor In di-
cator Bit preven ts customer-lockable devices from
being used to replace devices that are factory locked.
The SecSi sector address space in this device is allo-
cated as follo ws:
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi S ector Command Sequen ce”). A fter the sys tem
has written the Enter SecSi Sector command se-
quence, it may r ead th e S ecS i Sec tor by usin g the ad-
dresses normally occupied by the first sector (SA0).
This mode of operation continues until the system is -
sues the Exit SecSi Sector command sequence, or
until powe r is remove d from the devic e. On power- up,
or following a hardware reset, the device reverts to
sending commands to sector SA0.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecS i Sector is pr otected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. See Table 7 for
SecSi Sector addressing.
Customers may opt to have their code programmed by
AMD throu gh the AM D Expr essFlas h ser vice. The de-
vices are then shipped from AMD’s factory with the
SecSi Sector perman ently locked. Contact an AMD
repr esentat ive for de tails on usin g AMD’s Exp ress-
Flash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an al ternative to the fac tory -loc ke d ver sion, the de-
vice ma y be ordered s uch that the custom er may pro-
gram and protect the 128-word/256 bytes SecSi
sector.
The system may program the SecSi Sector using the
write- buffer, acceler ated and/or unloc k bypass meth-
ods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
proc edure av aila ble for un prote cting the SecS i Sect or
area and none of the b its in th e Sec Si Sec tor memo ry
space can be modified in any way.
The SecSi Sector area can be protected using one of
the following procedures:
■Write the three-cycle Enter SecSi Sector Region
command sequ enc e, and the n fol low the in- s yste m
sector protect algorithm as shown in Figure 2, ex-
cept that RES ET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “Sector
Group Protection and Unprotection” section.
Once the SecSi Sector is programmed, locked and
verified , the sy stem m ust wri te the E xit Se cSi Sec tor
Region command sequence to return to reading and
writing within the remainder of the array.
Hardware Data Protection
The comm and seq uenc e requirem ent of unlo ck cy cl es
for programming or erasing provides data protection
against inadvertent writes (refer to Tables 12 and 13
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious sys tem level signals during VCC
power-u p and p ower-do wn tran sitio ns, or f rom s ystem
noise.
Low VCC Write Inhibit
When V CC is less than VLKO, th e device does not ac-
cept any write cycles. T his protects data during VCC
power-up and power-down. The command register
Table 7. SecSi Sector Contents
SecSi Sector Address
Range Standard
Factory
Locked ExpressFlash
Factory Locked Customer
Lockablex16 x8
000000h–
000007h 000000h–
00000Fh ESN ESN or
determined
by customer Determined
by customer
000008h–
00007Fh 000010h–
00001Fh Unavailable Determined
by customer
April 26, 2002 Am29LV640MT/B 23
ADVANCE INFORMATION
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subs equent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
greater than VLKO.
Write Pulse “Glitch ” Prot ec tio n
Noise pulses o f less than 5 ns (typical) on OE#, CE #
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and W E# must be a log ical zero whil e OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL an d OE# = VIH during power up,
the device does not accept c ommands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interfac e (CFI) spec ification out-
lines dev ice and host s ystem software in terrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent , JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This de vic e ent er s th e CF I Que ry mo de wh en t he s ys-
tem writes the CFI Qu ery command, 98 h, to addre ss
55h, any time th e device is read y to r ead array d ata.
The system can read CFI information at the addresses
given i n Ta bles 8–11. To termina te reading CFI data,
the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the address es given in Tables 8–11. The
system must write the reset command to return the de-
vice to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
Table 8. CFI Query Identification String
Addresses
(x16) Addresses
(x8) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 26h
28h 0002h
0000h Primary OEM Command Set
15h
16h 2Ah
2Ch 0040h
0000h Address for Primary Extended Table
17h
18h 2Eh
30h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 32h
34h 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
24 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
Table 9. System Interface String
Table 10. Device Geometry Definition
Addresses
(x16) Addresses
(x8) Data Description
1Bh 36h 0027h VCC Min. (wri te/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 38h 0036h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 3Eh 0007h Typical timeout per single byte/word write 2N µs
20h 40h 0007h Ty pical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 42h 000Ah Typical timeout per individual block erase 2N ms
22h 44h 0000h Ty pical timeout for full chip erase 2N ms (00h = not supported)
23h 46h 0001h Max. timeout for byte/word write 2N times typical
24h 48h 0005h Max. timeout for buffer write 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Addresses
(x16) Addresses
(x8) Data Description
27h 4Eh 0017h Device Size = 2N byte
28h
29h 50h
52h 0002h
0000h Flas h De vi ce Interfa ce des cri pti on (refe r to CFI publication 100)
2Ah
2Bh 54h
56h 0005h
0000h Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch 58h 0002h Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
007Fh
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
007Eh
0000h
0000h
0001h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
April 26, 2002 Am29LV640MT/B 25
ADVANCE INFORMATION
Table 11. Primary Vendor-Specific Extended Query
COM MAND DEFIN I T I O N S
Writing speci fic address and data commands or s e-
quences into the command register initiates device op-
erati ons. Tabl es 12 and 13 define the valid register
comma nd seq uence s. Writin g incorrect a ddress an d
data values or writing them in the improper se-
quence resets the device to reading array data.
All addresses are latched on the falling e dge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. R efer to th e AC Ch aracter istics section for timing
diagrams.
Reading Array Data
The de vice i s automa tically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase alg orith m.
After the device accepts an Erase Suspend command,
the devi ce enters the e rase-suspen d-read mod e, after
which the system can read data from any
non-erase -suspended sec tor. After completing a pro-
Addresses
(x16) Addresses
(x8) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 86h 0031h Major version number, ASCII
44h 88h 0033h Minor version number, ASCII
45h 8Ah 0008h Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit
46h 8Ch 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 90h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0004h Sector Protect/Unprotect scheme
04 = 29LV800 mode
4Ah 94h 0000h Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh 96h 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 98h 0001h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh 9Ah 00B5h ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh 9Ch 00C5h ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 9Eh 0002h/
0003h
Top/Bottom Boot Sector Flag
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04 h = Uniform sectors bottom WP# protec t, 05h = Uniform sec tors top
WP# protect
50h A0h 0001h Program Suspen d
00h = Not Supported, 01h = Supported
26 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must iss ue the reset c ommand to retu rn
the device to the read (or erase-suspend-read) mode
if DQ5 goes high during an active program or erase
operation, or if the device is in the autoselect mode.
See the next section , Reset Command, for more infor-
mation.
See also Re quire ments fo r Readin g Array Data in the
Device Bus Operations se ctio n fo r mo re i nfo rmat ion .
The Read-Only Operations table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cy cl es in an er as e co mm and s equ ence before
erasing begins. This resets the device to the read
mode. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the program command sequence is
written while the device is in the Erase Suspend mode,
writing the reset command returns the dev ice to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be wr itten to return to the read mod e. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the dev ice to the
read mod e ( or e ra se -sus pen d-r ead mod e i f th e de vi c e
was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Pro-
gramming operation, the system must write the
Write-to-Buffer-Abort Reset command sequence to
reset the device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
Note: The device ID is read over three cycles. SA = Sector
Address
Tables 12 and 13 show the addr ess and da ta requ ire-
ments. This method is an alternative to that shown in
Table 4, which is intended for PROM programmers
and requires VID on address pin A9. The autoselect
command sequence may be written to an address that
is either in the read or eras e- su sp end -rea d mode . Th e
autoselect command may not be written while the de-
vice is actively programming or erasing.
The au tosele ct c omman d seq uence is initi ated b y fir st
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enter s the autoselec t mode. The syste m
may rea d at any addre ss an y numb er of times withou t
initiating another autoselect command sequence.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word/16-byte random Electronic Serial
Number (ESN). The system can access the SecSi
Secto r region by issuin g the three- cycle Ent er SecSi
Secto r command sequence. The devi ce conti nues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sec tor command se -
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. Tables 12 and
13 show the address and data requirem ents for both
command sequences. See also “Sec Si (Secured Sili-
con) Sector Flash Memory Region” for further informa-
tion.
Word/Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram c ommand se quence is initiated b y writing two
unlock wr ite cycles , followed by the program s et-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
Identifier Code A7:A0
(x16) A6:A-1
(x8)
Manufacturer ID 00h 00h
Device ID, Cycle 1 01h 02h
Device ID, Cycle 2 0Eh 1Ch
Device ID, Cycle 3 0Fh 1Eh
SecSi Sector Factory Protect 03h 06h
Sector Protect Verify (SA)02h (SA)04h
April 26, 2002 Am29LV640MT/B 27
ADVANCE INFORMATION
contr ols or tim ings. T he device autom atical ly prov ides
internally generated program pulses and verifies the
programmed cell margin. Tables 12 and 13 show the
address and data requirements for the word program
comma nd se quen ce .
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresse s are no l onger l atched . The syst em can de ter-
mine the status of the program operation by using
DQ7 or D Q6. Ref er to t he Write O pe ra tio n S tatu s sec -
tion for information on these status bits.
Any commands written to the device during the Em-
bedded Progr am Algorithm are ignor ed. Note that a
hardware reset immediatel y terminates the program
operation. The program command sequence should
be reinitiated once the device has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequenc e and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the devi ce to set DQ5 = 1, or cause the DQ7
and DQ6 status bit s to ind ic ate the operati on was suc-
cessful. However , a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is fo llowed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all tha t is r eq uir e d to pr og ra m in th is mode. T he firs t
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed i n the same ma nner. This mode dispenses
with the initial two unl ock cycl es required in the s tan-
dard program command sequence, resulting in faster
total programming time. Tables 12 and 13 show the re-
quirements for the command sequence.
During the unlo ck byp ass mode, only t he Unloc k By-
pass Program and Unlock Bypass Reset commands
are valid . To exit the unl ock bypas s mode, the sy stem
must issue the two-cycle unlock bypass reset com-
mand se quence . The first cy cle mu st contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
Write Buffer Programming
Write Buffer Programming al lows the sy stem write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than th e standard programming algorithms. The
Write Buffer Pr og ra mmi ng co mma nd sequence is i ni ti-
ated by fi rst writ ing two unlock c ycles . This i s followe d
by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which pro-
gramming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example, if the system will pro-
gram 6 unique address locations, then 05h should be
written to the de vice. This tells the de vice how many
write buffer addresses will be loaded with data and
therefore when to expect the Program Buffer to Flash
command. The number of locations to program cannot
exceed t he s ize o f the write buffer or the operati on wi ll
abort.
The fifth cycle writes the first address location and
data to be pr ogrammed. The w rite-buffer-p age is s e-
lected by addre ss bits AMAX–A4. All sub sequent a d-
dress/data pairs must fall within the
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per-
formed across multiple write-bu ffer pa ges. Thi s also
means that Write Buffer Programming cannot be per-
formed a cros s mu lti ple sec tor s. If t he sy st em attem pts
to load programming data outside of the selected
write-buffer page, the operation will abort.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pai r counter will be
decremented for every data load operation. Th e host
system must therefore account for loading a
write-buffer location more than once. The co unter
decrem ents for each d ata lo ad operati on, no t for e ach
unique write-buffer-address location. Note also that if
an ad dress loca tion i s lo aded m ore than o nce i nto th e
buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations
have been loaded, the system must then write the Pro-
gram Buffer to Flash command at the sector address.
Any other address and data combination aborts the
Write Buffer Programming operation. The device then
begins programming. Data polling should be used
while monitoring the last address location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monito red to dete rmine the d evice sta tus durin g Write
Buffer Programming.
The write-buffer programming operation can be sus-
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
28 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
Buffer Programming operation, the device is ready to
execute the next comm and .
The Write Buffer Programming Sequence can be
aborted in the following ways:
■Load a value that is greater than the page buffer
size during the Number of Locations to Program
step.
■Write to an address in a sector different than the
one specified during the Write-Buffer-Load com-
mand.
■Write an Address/Data pair to a different
write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.
■Write data other than the Confirm Command after
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the last address loc ation loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset
command sequence must be written to reset the de-
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-A bort Res et com mand s equence is r e-
quired whe n using Write-B uffer-Program ming fea tures
in Unlock Bypass mode.
Accelerated Progr am
The device offers accelerated program operations
through the WP#/ACC pin. W hen the sy stem asse rts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock By pass prog ram comman d
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH for operations
other than accelerated program ming, or dev ice dam-
age may result. In addition, no external pullup is nec-
essary since th e WP#/ACC p in has i nternal pul lup to
VCC.
Figure 4 illus tr ates the al gor it hm for the pr og ra m oper-
ation. Refer to the Erase and Program Operations
table in the AC Cha r act eris tic s sec ti on for par am eters ,
and Figure 16 for timing diagrams.
April 26, 2002 Am29LV640MT/B 29
ADVANCE INFORMATION
Figure 3. Write Buffer Programming Operation
Write “Write to Buffer”
command and
Sector Address
Write number of addresses
to program minus 1(WC)
and Sector Address
Write program buffer to
flash sector address
Write first address/data
Write to a different
sector address
FAIL or ABORT PASS
Read DQ7 - DQ0 at
Last Loaded Address
Read DQ7 - DQ0 with
address = Last Loaded
Address
Write next address/data pair
WC = WC - 1
WC = 0 ?
Part of “Write to Buffer”
Command Sequence
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Abort Write to
Buffer Operation?
DQ7 = Data?
DQ7 = Data?
DQ5 = 1?DQ1 = 1?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
to read mode.
Notes:
1. When Sector Address is specified, an y ad dress in
the selected sector is acceptable. However, when
loading Write-Buffer address locati ons with data, a
ll
addresses must fall within the selected Write-Buffe
r
Page.
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this
flowchart location was reached because DQ1=
“1”, then the Write to Buffer operation was
ABORTED. In either case, the proper reset
command must be written before the device can
begin another operation. If DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset command.
4. See Table 13 for command sequences required fo
r
write buffer programming.
(Note 3)
(Note 1)
(Note 2)
30 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
Figure 4. Program Operation
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allows the system to
interr upt a progra mming oper ation or a Write to Buffer
program ming op eratio n so that da ta can be rea d from
any non-suspended sector. When the Program Sus-
pend comma nd is written during a program ming pro-
cess, the device halts the program operation within 1
ms and update s the status bits. Addresses are no t re-
quired when writing the Program Suspend command.
After the programming operation has been sus-
pended, the system can read array data from any
non-s uspended se ctor. The Progr am Suspen d com-
mand may also be issued during a programming oper-
ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus-
pend or Program Suspend. If a read is needed from
the Sec Si Sect or are a (One-t ime Pro gram are a), the n
user must use the proper command sequences to
enter and exit this region.
The system may also write the autoselect command
sequenc e wh en th e de vi ce is i n the Pr og ram S us pen d
mode. The system can read as many autoselect
codes as required . When the devi ce exi ts the autos e-
lect mod e , the devi ce reverts to the Prog ra m S u s pen d
mode, an d is ready fo r another valid opera tion. See
Autoselect Command Sequence for more information.
After the P rogram Res ume command is w ritten, the
device reverts to programming. The system can de-
term ine t he st atus of the pr ogr am op erati on us ing t he
DQ7 or DQ6 status bits, just as in the standard pro-
gram o pera tion. Se e Writ e Operatio n Statu s for more
information.
The system must write the Program Resume com-
mand (address bits are don’t care) to exit the Program
Suspe nd mode an d continu e the prog ramming opera-
tion. Further writes o f the Resume co mmand a re ig-
nored . Ano ther P rogram Susp end co mmand can b e
written after the device has resume programming.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 13 for program command sequence.
April 26, 2002 Am29LV640MT/B 31
ADVANCE INFORMATION
Figure 5. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
comman d sequence i s initi ated by writi ng two unlo ck
cycle s, followed by a se t-up comm and . Two a dditio nal
unlock write cycles are then followed by the chip erase
command, which in turn inv ok es th e E mb edde d E ras e
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to e lectrical
eras e. The syst em is no t requir ed to prov ide any con-
trols or timings during these operations. Tables 12 and
13 show s the address a nd data requirem ents for the
chip erase command sequence.
When the Emb edde d Eras e al gor it hm is com pl ete, the
device returns to the read mode and addresses are no
longer l atched. The system c an determine the status
of the erase operation by us ing DQ7, DQ6, or DQ2.
Refer to th e Write Op eration S tatus section for infor-
mation on these status bits.
Any commands written during the chip erase operation
are ignored . However, note th at a hardw are res et im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 6 illus trates the algorithm for the erase opera-
tion. Refer to th e Erase and Program Operations ta-
bles in the AC Ch arac teris tics se ction fo r para meter s,
and Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector e rase is a six bus cycle op eration. T he sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. T wo ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sec tor erase comman d. Tabl es 12 and 13 shows
the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram
prior to eras e. The Embed ded Erase al gorithm au to-
matically programs and verifies the entire memory for
an all zero data patter n prior to electri cal erase . The
system is not required to provi de any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
betw een the se additi onal cy cles mu st be le ss tha n 50
µs, otherwise erasure may begin. Any sector erase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mend ed tha t pro cessor interr upts be di sable d durin g
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase T imer .). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase-
or
program-suspended sectors
Write Program Resume
Command Sequence
Read data as
required
Done
reading?
No
Yes
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Write address/data
XXXh/B0h
Wait 1 ms
32 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
When the Embe dded Erase alg or ith m is compl ete, the
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, or DQ2 in the e rasi ng se ctor. Re fer to t he
Write Operation Status section for information on
these status bits.
Once the sect or erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. Howev er, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be r einitiated onc e the device has returned to
reading array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase opera-
tion. Refer to th e Erase and Program Operations ta-
bles in the AC Ch aracte risti cs secti on for pa rame ters,
and Figure 18 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data fro m, or prog r am data to , a ny s ector n ot se lec te d
for erasure. This command is valid only during the
sector erase oper ation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chi p erase operation or Embedded P rogram
algorithm.
When the Eras e Suspend comm and is written during
the sector erase operation, the device requires a max-
imum of 20 µs to susp end the eras e operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately term inates th e time- out peri od and su spend s th e
erase operation.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read d ata from or prog ram d ata to any sec tor
not selected for erasure. (The device “erase sus-
pends” all sec tors selected fo r erasure .) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7 , or DQ6 an d DQ 2 to geth er, to determin e
if a sector is actively erasing or is erase-suspended.
Refer to th e Write Op eration S tatus section for infor-
mation on these status bits.
After an erase-suspended program operation is com-
plete, th e device retur ns to the erase- suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer to the Write O peration S tatus section for more
information.
In the erase-su spend- rea d mode, the system ca n also
issue t he a uto sel ec t com mand sequ ence. Refer to th e
Autoselect Mode and Autoselect Command Sequence
sections for details .
To resume the sector erase operation, the system
must write the Eras e Resume command. The add ress
of the erase- suspended sec tor is required wh en writ-
ing this comm and. Fur ther writes of the R esume com-
mand are ignored. Another Erase Suspend command
can be written after the chip has resumed erasing.
April 26, 2002 Am29LV640MT/B 33
ADVANCE INFORMATION
Figure 6. Era se Oper atio n
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table 13 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
34 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
Command Definitions
Table 12. Command Definitions (x16 Mode, BYTE# = VIH)
Legend:
X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address . Addresses latch on the falling edge of the
WE# or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. During unlock cycles, when lower address bits are 555 or 2AAh
as shown in table, address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when device is in read
mode.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
7. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
8. T he device ID must be read in three cycles. The data is 2201h for
top boot and 2200h for bottom boot.
9. If WP# protects the top two address sectors, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
bottom two address sectors, the data is 88h for factory locked and
08h for not factor locked.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer . The
maximum number of cycles in the command sequence is 21.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
14. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
15. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
16. The Erase Resume command is valid only during the Erase
Suspend mode.
17. Command is valid when device is ready to read array da ta or when
device is in autoselect mode.
Command S equence
(Notes)
Cycles
Bus Cycles (Notes 1–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufacturer ID 4 55 5 AA 2A A 55 555 90 X00 0001
Device ID (Note 8) 6 555 AA 2AA 55 555 90 X01 227E X0E 2210 X0F 2200/
2201
SecSi Sector Factory Protect
(Note 9) 4 555 AA 2AA 55 555 90 X03 (Note 9)
Sector Group Protect Verify
(Note 10) 4 555 AA 2AA 55 555 90 (SA)X02 00/01
Enter SecSi Sector Region 3 555 AA 2AA 55 555 88
Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD
Write to Buffer (Note 11) 6 555 AA 2AA 55 SA 25 SA WC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 12) 3 555 AA 2AA 55 555 F0
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 13) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Program/Erase Suspend (Note 15) 1 BA B0
Program/Erase Resume (Note 16) 1 BA 30
CFI Query (Note 17) 1 55 98
April 26, 2002 Am29LV640MT/B 35
ADVANCE INFORMATION
Table 13. Command Definitions (x8 Mode, BYTE# = VIL)
Legend:
X = Don’t care
RA = Read Address of the memory location to be read.
RD = Read Data read from location RA during read operation.
PA = Program Address . Addresses latch on the falling edge of the
WE# or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on the rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. During unlock cycles, when lower address bits are 555 or AAAh
as shown in table, address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
5. No unlock or command cycles required when device is in read
mode.
6. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when the device is in the autoselect mode, or if DQ5 goes high
while the device is providing status information.
7. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
8. The device ID must be read in three cycles. The data is 01h for
top boot and 00h for bottom boot
9. If WP# protects the top two address sectors, the data is 98h for
factory locked and 18h for not factory locked. If WP# protects the
bottom two address sectors, the data is 88h for factory locked and
08h for not factor locked.
10. The data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. The total number of cycles in the command sequence is
determined by the number of words written to the write buffer . The
maximum number of cycles in the command sequence is 37.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
14. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
15. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
16. The Erase Resume command is valid only during the Erase
Suspend mode.
17. Command is valid when device is ready to read array da ta or when
device is in autoselect mode.
Command S equence
(Notes)
Cycles
Bus Cycles (Notes 1–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufacturer ID 4 A AA AA 555 55 AAA 90 X00 01
Device ID (Note 8) 6 AAA AA 555 55 AAA 90 X02 7E X1C 10 X1E 00/01
SecSi Sector Factory Protect
(Note 9) 4 AAA AA 555 55 AAA 90 X06 (Note 9)
Sector Group Protect Verify
(Note 10) 4 AAA AA 555 55 AAA 90 (SA)X04 00/01
Enter SecSi Sector Region 3 AAA AA 555 55 AAA 88
Exit SecSi Sector Region 4 AAA AA 555 55 AAA 90 XXX 00
Program 4 AAA AA 555 55 AAA A0 PA PD
Write to Buffer (Note 11) 6 AAA AA 555 55 SA 25 SA BC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 12) 3 AAA AA 555 55 AAA F0
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass Program (Note 13) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30
Program/Erase Suspend (Note 15) 1 BA B0
Program/Erase Resume (Note 16) 1 BA 30
CFI Query (Note 17) 1 AA 98
36 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 14 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method
for determining whether a program or erase operation is
complete or in progress. The device a lso provid es a
hardware-based output signal, RY/BY#, to determin e
whether an Embedded Program or Erase operation is
in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Poll ing is valid aft er the risi ng ed ge of the
final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum progr ammed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, th e de vi ce o utputs the dat um pr og ra mmed to
DQ7. The sy s tem mu s t prov i de the prog r am add r ess to
read valid status information on DQ7. If a program address
falls wit hin a prot ected sect or, Data # Pol lin g on D Q7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The syste m mu st pr ov ide an a ddr ess within a ny of th e
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sect ors s el ec ted for e rasi ng ar e p rotec ted, Data# Pol l-
ing on DQ7 is active for approximately 100 µs, then
the devi ce retur n s t o th e rea d m ode . If not al l selec te d
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lect ed sect ors tha t are pr otecte d. Howe ver, if the s ys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Just p rior to the com pleti on of an E mbed ded P rogram
or Eras e op erati on, D Q7 m ay c hang e a syn chro nously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid da ta, the da ta output s on DQ0–D Q6 may be s till
invalid. Val id data on DQ0–DQ7 will appear on suc-
cessive read cycles.
Table 14 shows the outputs for Data# Polling on DQ7.
Figure 7 sh ows the Data # Polli ng algo rithm . Figure 19
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 7. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sect
or
erase o perat ion, a va lid ad dress i s any sector add res
s
within the sector bein g erased. During chip erase,
a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” becaus
e
DQ7 may change simultaneously with DQ5.
April 26, 2002 Am29LV640MT/B 37
ADVANCE INFORMATION
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which in dicate s w he ther an E mbe dded Al gor ithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the devic e is in the read mode, the sta ndby
mode, or in the erase-suspend-read mode. Ta ble 14
shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle B it I on DQ 6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedd ed Progra m or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 µs, then retur ns to re adi ng arr ay data. If no t all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice en t ers th e E r as e Su spe nd mo de , DQ 6 st op s t o ggling.
However, the system mus t also u se DQ2 to deter mine
which se cto rs ar e er asi ng or er as e-suspende d. A lte rn a-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling).
If a program address falls within a p rotected sector,
DQ6 tog gles fo r appro ximat ely 1 µs afte r the pro gram
command sequen ce is wri tten, the n returns to readin g
array data.
DQ6 also toggles during the erase-su spend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 14 shows the outputs for Toggle Bit I on DQ6.
Figure 8 shows the toggle bit algorithm. Figure 20 in
the “AC Character istics” section sh ows the toggle bit
timing diagrams. Figure 21 shows the differences be-
tween DQ 2 and DQ6 in gr aphical form. See also th e
subsection on DQ2: Toggle Bit II.
38 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
Figure 8. Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Tog gl e B it II” o n DQ2, whe n u se d wi th DQ6, ind i-
cates whether a particul ar sec tor is activel y erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sect ors that have been selecte d for era-
sure. (T he sys tem m ay use either OE # o r CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode info rmation. Refer to Tabl e 14 to com pare out-
puts for DQ2 and DQ6.
Figure 8 shows the t oggle bit algor ithm in fl owchart
form, and the se ction “DQ 2: Toggle Bi t II” explains the
algorithm. Se e also the RY/BY#: Ready/Busy# sub-
section. Figure 20 shows the toggle bit timing diagram.
Figure 21 shows the differences betw een DQ2 and
DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. W hen-
ever the system initially begins reading toggle bit sta-
tus, it mus t read DQ7–DQ0 at l east twice in a ro w to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system woul d com pare th e new va lue of th e toggle bi t
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read arr ay data on DQ7–DQ0 on the fol-
lowing rea d cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it i s, the system should
then determine again whether the toggle bit is tog-
gling, since th e toggle bit ma y have stopp ed toggling
just as DQ5 went high . If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice d id no t c omp le ted the op er ati on su cc es sf ull y, an d
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high . The sy stem may continue to monitor
the toggle bit and DQ 5 through successive read c y-
cles , determ ining the st atus as de scrib ed in the prev i-
ous para graph . Al ter nat iv ely, it may choos e to pe rf or m
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note: The system should recheck the toggle bit even
if
DQ5 = “1” because the toggl e bit ma y sto p t ogg lin g as DQ
5
chan ges to “1.” See the su bsection s on DQ6 and DQ 2 f
or
more information.
April 26, 2002 Am29LV640MT/B 39
ADVANCE INFORMATION
other system tasks. In this case, the system must start
at the beginning of the algor ith m when it return s to de -
termine the status of the operation (top of Figure 8).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
writ e-to-buffer ti me has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “ 1” to a location that was previo usly pro-
grammed to “0.” Only an erase operation can
change a “0 ” ba ck t o a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to r eturn the device to the re ading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend -p rogr am mod e) .
DQ3: Sector Erase Timer
Afte r writi ng a sector erase comm and sequen ce, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are se lected for erasure, the entire ti me-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the s ector era se comman d is writte n, the syste m
should re ad th e st atu s o f DQ7 (D ata# Poll ing) or DQ 6
(Togg le Bit I) to ensure that the devi ce has accepte d
the command sequence, and then read DQ3. If DQ3 is
“1,” the Em bedded Erase alg orithm has begun; al l fur-
ther c ommands (except Erase Suspend) are ig nored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 14 s hows the status of DQ3 rel ative to the other
status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Unde r these conditi ons DQ1 produ ces a
“1”. The system must issue the
Write-to-Buffer-Abort-Reset command sequence to re-
turn the device to reading array data. See Write Buffer
Table 14. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when tthe device has aborted the write-to-buffer operation.
Status DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) DQ1 RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle N/A 0
Program
Suspend
Mode
Program-
Suspend
Read
Program-Suspended
Sector Invalid (not allowed) 1
Non-Program
Suspended Sector Data 1
Erase
Suspend
Mode
Erase-
Suspend
Read
Erase-Suspended
Sector 1 No toggle 0 N/A Toggle N/A 1
Non-Erase Suspended
Sector Data 1
Erase-Suspend-Program
(Embedded Program) DQ7# Toggle 0 N/A N/A N/A 0
Write-to-
Buffer Bus y (Note 3) DQ7# Toggl e 0 N/A N/A 0 0
Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0
40 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
ABSOLUTE MAXIMUM RATINGS
Storage Te mpe ra ture
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 9. D u ring vo lta ge transiti on s, i npu t or I /O pins
may overs hoot to VCC + 2.0 V for peri ods up to 20 ns. Se e
Figure 10.
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitio ns, A9, OE#,
ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 9. Maximum DC input
voltage on pin A9, OE#, ACC, and RESET# is +12.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to t he device. This
is a stres s rating only; fu nctiona l operati on of the dev ice at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Vo ltages
VCC for full voltage range . . . . . . . . . . . . . . . 2.7–3.6 V
VCC for regulated voltage range. . . . . . . . . . 3.0–3.6 V
Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 9. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 10. Maximum Positive
Overshoot Waveform
April 26, 2002 Am29LV640MT/B 41
ADVANCE INFORMATION
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. T ypical sleep mode current is
200 nA.
6. VCC voltage requirements.
7. Not 100% tested.
Parameter
Symbol Parameter Description
(Notes) Test Conditions Min Typ Max Unit
ILI Input Load Current (1) VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(2, 3) CE# = VIL, OE# = VIH, 5 MHz 15 20 mA
1 MHz 15 20
ICC2 VCC Initial Page Read Current (2, 3) CE# = VIL, OE# = VIH 30 50 mA
ICC3 VCC Intra-Page Read Current (2, 3) CE# = VIL, OE# = VIH 10 20 mA
ICC4 VCC Active Write Current (3, 4) CE# = VIL, OE# = VIH 50 60 mA
ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V,
WP# = VIH 15µA
ICC6 VCC Reset Current (3) RESET# = VSS ± 0.3 V, WP# = VIH 15µA
ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V, WP# = VIH 15µA
IACC ACC Accelerated Program Current (3) CE# = VIL, OE# = VIH ACC pin 10 20 mA
VCC pin 30 60 mA
VIL Input Low Voltage (6) –0.5 0.8 V
VIH Input High Voltage (6) 0.7 x VCC VCC + 0.5 V
VID Voltage for Autoselect an d Temporary
Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min = VIO 0.15 x VCC V
VOH1 Output High Voltag e IOH = –2.0 mA, V CC = VCC min = V IO 0.85 VCC V
VOH2 IOH = –100 µA, V CC = VCC min = VIO VCC–0.4 V
VLKO Low VCC Lock-Out Voltage (7) 2.3 2.5 V
42 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
TEST CONDITIONS Table 15. Test Specifications
Note: If VIO < VCC, the referenc e lev el is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
N
ote: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Test Condition All Speeds Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference levels (See Note) 1.5 V
Output timing measurement
reference levels 0.5 VIO V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 0.5 VIO V OutputMeasurement LevelInput
N
ote: If VIO < VCC, the input m easurement reference level is 0.5 VIO.
Figure 12. Input Waveforms and
Measurement Levels
April 26, 2002 Am29LV640MT/B 43
ADVANCE INFORMATION
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 15 for test specifications.
Parameter
Description Test Setup
Speed Options
JEDEC Std. 90R 101 112 120 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 90 100 110 120 ns
tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 90 100 110 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 110 120 ns
tPACC Page Access Time Max25304040ns
tGLQV tOE Output Enable to Output Delay Max 25 30 40 40 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 ns
tAXQX tOH Output Hold Time From Addresses, CE#
or OE#, Whichever Occurs First Min 0 ns
tOEH Out put Enable Hold
Time (Note 1)
Read Min 0 ns
Toggle and
Data# Po lling Min 10 ns
tOH
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
RESET#
tDF
Figure 13. Read Operation Timings
44 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
* Figure shows word mode. Addresses are A1–A-1 for byte mode.
Figure 14. Page Read Timings
April 26, 2002 Am29LV640MT/B 45
ADVANCE INFORMATION
AC CHARACTERISTICS
Hardware Reset (RESET# )
Note: Not 100% tested.
Parameter
Description All Speed Options UnitJEDEC Std.
tReady RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note) Max 20 µs
tReady RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
Figure 15. Reset Timings
46 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
Parameter Speed Options
JEDEC Std. Description 90R 101 112 120 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns
tAVWL tAS Ad dres s Setu p Time Min 0 ns
tASO Address Set up Tim e to OE# low during tog gle bit
polling Min 15 ns
tWLAX tAH Ad dres s Hold T im e Min 45 ns
tAHT Address Hold Time From CE# or OE# high
during toggle bit polling Min 0 ns
tDVWH tDS Data Setup Ti me Min 45 ns
tWHDX tDH Data Hold Time Min 0 ns
tOEPH Output Enable High during toggle bit polling Min 20 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup T i me Min 0 ns
tWHEH tCH CE# Hold T ime Min 0 ns
tWLWH tWP Write Pulse Width Min 35 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1
Write Buffer Program Operation (Notes 2, 3) T yp 100 µs
Effective Write Buffer Program
Operation (Notes 2, 4) Per Byte Typ 2.95 µs
Per Word Typ 5.9 µs
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4) Per Byte Typ 2.35 µs
Per Word Typ 4.7 µs
Single Word/Byte Program Operation (Note 2) Typ 100 µs
Single Word/Byte Accelerated Programming
Operation (Note 2) Typ 80 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec
tVHH VHH Rise and Fall Time (N ote 1) M in 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
April 26, 2002 Am29LV640MT/B 47
ADVANCE INFORMATION
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
tDS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
t
CH
PA
N
otes:
1
. PA = program address, PD = program data, DOUT is the true data at the program address.
2
. I llustration shows device in word mode.
Figure 16. Program Operation Timings
ACC tVHH
VHH
VIL or VIH VIL or VIH
tVHH
Figure 17. Accelerated Program Timing Diagram
48 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
Notes:
1. SA = sector address (for Sector Erase), V A = V alid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.
Figure 18. Chip/Sector Erase Operation Timings
April 26, 2002 Am29LV640MT/B 49
ADVANCE INFORMATION
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
N
ote: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
r
ead cycle.
Figure 19. Data# Polling Timings (During Embedde d Algorithms)
50 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
OE#
CE#
WE#
A
ddresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read) (second read) (stops toggling)
t
CEPH
t
AHT
t
AS
DQ6/DQ2 Valid Dat
a
Valid
Status Valid
Status Valid
Status
N
ote: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
r
ead cycl e, and array data read cycl e
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
N
ote: DQ2 toggles only when rea d at an addres s within an er ase-su spended s ector . The sy stem may use OE# or CE# to togg
le
D
Q2 and DQ6.
Figure 21. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
April 26, 2002 Am29LV640MT/B 51
ADVANCE INFORMATION
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
R
ESET#
tVIDR
VID
VSS, VIL,
or VIH
VID
VSS, VIL
,
or VIH
CE#
WE#
tVIDR
tRSP
Program or Erase Command Sequence
Figure 22. Temporary Sector Group Unprotect Timing Diagram
52 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Group Protect or Unprotect Verify
VID
VIH
*
For sector group protect, A6–A0 = 0xx0010. For sector group unprotect, A6–A0 = 1xx0010.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
April 26, 2002 Am29LV640MT/B 53
ADVANCE INFORMATION
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
Parameter Speed Options
JEDEC Std. Description 90R 101 112 120 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 ns
tDVEH tDS Data Setup Time Min 45 ns
tEHDX tDH Data Hold Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# Hi gh to WE# Low) Min 0 ns
tWLEL tWS WE# Setup T im e Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 45 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1
Write Buffer Program Operation (Notes 2, 3) Typ 100 µs
Effective Write Buffer Program
Operation (Notes 2, 4) Per Byte Typ 2.95 µs
Per Word Typ 5.9 µs
Accelerated Effective Write Buf fer
Program Operation (Notes 2, 4) Per Byte Typ 2.35 µs
Per Word Typ 4.7 µs
Single Word/Byte Program Operation (Note 2) Typ 100 µs
Single Word/Byte Accelerated Progr amming
Operation (Note 2) Typ 80 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec
54 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
N
otes:
1
. Figure indicates last two bus cycles of a program or erase operation.
2
. PA = program address, SA = sector address, PD = program data.
3
. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4
. Waveforms are for the word mode.
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings
April 26, 2002 Am29LV640MT/B 55
ADVANCE INFORMATION
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables
12 and 13 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Note: Inclu des all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditio ns TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Par amet er Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.4 15 sec Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 90 sec
Effective Write Buffer Program
Time Per Byte 2.95
Per Word 5.9 210 µs
Excludes system level
overhead (Note 5)
Byte/Word Program Time 100 218 µs
Accelerated Effective Program
Time Byte 2.4
Word 4.8 TBD µs
Chip Progr am Time (Note 3) TBD TBD sec
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C10Years
125°C20Years
56 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
April 26, 2002 Am29LV640MT/B 57
ADVANCE INFORMATION
PHYSICAL DIMENSIONS
FBE063—63-Ball Fine-pitch Ball Grid Array (FBGA) 12 x 11 mm Package
Dwg rev AF; 10/99
58 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
PHYSICAL DIMENSIONS
LAA064—64-Ball Fortifi ed Ball Grid Array (FBGA) 13 x 11 mm Package
April 26, 2002 Am29LV640MT/B 59
ADVANCE INFORMATION
REVISION SUMMARY
Revision A (April 26, 2002)
Initial release.
Revisi on B (May 23 , 2002)
Changed p acka gin g fro m 64- ba ll FB GA to 64- ba ll For-
tified BGA.
Changed Bl ock Diagram : Moved V IO from RY/BY# to
Input/Output Buffers.
Changed N ote about WP#ACC pin to indicate in ternal
pullup to VCC.
60 Am29LV640MT/B April 26, 2002
ADVANCE INFORMATION
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advan ced Micro Devices , Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
