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FEATURES
SN54LVT162240. . . WD PACKAGE
SN74LVT162240. . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
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48
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25
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
DESCRIPTION/ORDERING INFORMATION
SN54LVT162240 , , SN74LVT1622403.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719A – JULY 2000 – REVISED NOVEMBER 2006
•Members of the Texas Instruments Widebus™Family
•State-of-the-Art Advanced BiCMOSTechnology (ABT) Design for 3.3-V Operationand Low Static-Power Dissipation•Output Ports Have Equivalent 22- ΩSeriesResistors, So No External Resistors AreRequired
•Support Mixed-Mode Signal Operation (5-VInput and Output Voltages With 3.3-V V
CC
)•Support Unregulated Battery Operation Downto 2.7 V•Typical V
OLP
(Output Ground Bounce) <0.8 Vat V
CC
= 3.3 V, T
A
= 25 °C•I
off
and Power-Up 3-State Support HotInsertion
•Distributed V
CC
and GND Pins MinimizeHigh-Speed Switching Noise•Flow-Through Architecture Optimizes PCBLayout
•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1000-V Charged-Device Model (C101)•Package Options Include Plastic ShrinkSmall-Outline (DL), Thin Shrink Small-Outline(DGG), and Thin Very Small-Outline (DGV)Packages and 380-mil Fine-Pitch Ceramic Flat(WD) Package Using 25-mil Center-to-CenterSpacings
The 'LVT162240 devices are 16-bit buffers/drivers designed specifically for low-voltage (3.3-V) V
CC
operationand to improve both the performance and density of 3-state memory address drivers, clock drivers, andbus-oriented receivers and transmitters. They have the capability to provide a TTL interface to a 5-V systemenvironment.
These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer and provide invertingoutputs and symmetrical active-low output-enable ( OE) inputs.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- Ωseries resistors toreduce overshoot and undershoot.
When V
CC
, is between 0 and 1.5 V, the devices are in the high-impedance state during power up or powerdown. However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN54LVT162240 , , SN74LVT1622403.3-V ABT 16-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
SCBS719A – JULY 2000 – REVISED NOVEMBER 2006
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitrydisables the outputs, preventing damaging current backflow through the devices when they are powered down.The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,which prevents driver conflict.
The SN54LVT162240 is characterized for operation over the full military temperature range of –55 °C to 125 °C.The SN74LVT162240 is characterized for operation from –40 °C to 85 °C.
ORDERING INFORMATION
T
A
PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
74LVT162240DLRG4
Reel of 1000
SN74LVT162240DLRSSOP – DL LVT162240SN74LVT162240DL
Tube of 25
SN74LVT162240DLG4–40 °C to 85 °C
74LVT162240DGGRE4TSSOP – DGG Reel of 2000 LVT162240SN74LVT162240DGGR
74LVT162240DGVRE4TVSOP – DGV Reel of 2000 LZ240SN74LVTH162240DGVR
BLK
FUNCTION TABLE(each 4-bit buffer/driver)
INPUTS
OUTPUT
YOE A
L H LL L HH X Z
2
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47
1A1 46
1A2 44
1A3 43
1A4
1Y1
2
1Y2
3
1Y3
5
1Y4
6
41
2A1 40
2A2 38
2A3 37
2A4
2Y1
8
2Y2
9
2Y3
11
2Y4
12
36
3A1 35
3A2 33
3A3 32
3A4
3Y1
13
3Y2
14
3Y3
16
3Y4
17
30
4A1 29
4A2 27
4A3 26
4A4
4Y1
19
4Y2
20
4Y3
22
4Y4
23
EN1
1
EN4
24
1OE
2OE
3OE
4OE
EN2
48
EN3
25
1 1
1 2
1 3
1 4
SN54LVT162240 , , SN74LVT1622403.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719A – JULY 2000 – REVISED NOVEMBER 2006
LOGIC SYMBOL
(1)
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
Absolute Maximum Ratings
(1)
SN54LVT162240 , , SN74LVT1622403.3-V ABT 16-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
SCBS719A – JULY 2000 – REVISED NOVEMBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 4.6 VV
I
Input voltage range
(2)
–0.5 7 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 7 VV
O
Voltage range applied to any output in the high state
(2)
–0.5 V
CC
+ 0.5 VI
O
Current into any output in the low state 30 mAI
O
Current into any output in the high state
(3)
30 mAI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mADGG package 70θ
JA
Package thermal impedance
(4)
DGV package 58 °C/WDL package 63T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) This current flows only when the output is in the high state and V
O
> V
CC
.(4) The package thermal impedance is calculated in accordance with JESD 51.
4
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Recommended Operating Conditions
(1)
Electrical Characteristics
SN54LVT162240 , , SN74LVT1622403.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719A – JULY 2000 – REVISED NOVEMBER 2006
SN54LVT162240 SN74LVT162240
UNITMIN MAX MIN MAX
V
CC
Supply voltage 2.7 3.6 2.7 3.6 VV
IH
High-level input voltage 2 2 VV
IL
Low-level input voltage 0.8 0.8 VV
I
Input voltage 5.5 5.5 VI
OH
High-level output current –12 –12 mAI
OL
Low-level output current 12 12 mA∆t/ ∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V∆t/ ∆V
CC
Power-up ramp rate 200 200 µs/VT
A
Operating free-air temperature –55 125 –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVT162240 SN74LVT162240PARAMETER TEST CONDITIONS UNITMIN TYP
(1)
MAX MIN TYP
(1)
MAX
V
IK
V
CC
= 2.7 V, I
I
= –18 mA –1.2 –1.2 VV
OH
V
CC
= 3 V, I
OH
= –12 mA 2 2 VV
OL
V
CC
= 3 V, I
OL
= 12 mA 0.8 0.8 VV
CC
= 0 or 3.6 V, V
I
= 5.5 V 10 10Control inputs V
CC
= 3.6 V, V
I
= V
CC
or GND ±1±1I
I
µAV
I
= V
CC
1 1Data inputs V
CC
= 3.6 V
V
I
= 0 –5 –5I
off
V
CC
= 0, V
I
or V
O
= 0 to 4.5 V ±100 µAI
OZH
V
CC
= 3.6 V, V
O
= 3 V 5 5 µAI
OZL
V
CC
= 3.6 V, V
O
= 0.5 V –5 –5 µAV
CC
= 0 to 1.5 V, V
O
= 0.5 V to 3 V,I
OZPU
±100
(2)
±100 µAOE = don't careV
CC
= 1.5 V to 0, V
O
= 0.5 V to 3 V,I
OZPD
±100
(2)
±100 µAOE = don't care
Outputs high 0.19 0.19V
CC
= 3.6 V,I
CC
I
O
= 0, Outputs low 5 5 mAV
I
= V
CC
or GND
Outputs disabled 0.19 0.19V
CC
= 3 V to 3.6 V, One input at V
CC
– 0.6 V,∆I
CC
(3)
0.2 0.2 mAOther inputs at V
CC
or GNDC
i
V
I
= 3 V or 0 4 4 pFC
o
V
O
= 3 V or 0 9 9 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) On products compliant to MIL-PRF-38535, this parameter is not production tested.(3) This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
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Switching Characteristics
SN54LVT162240 , , SN74LVT1622403.3-V ABT 16-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
SCBS719A – JULY 2000 – REVISED NOVEMBER 2006
over recommended operating free-air temperature range, C
L
= 50 pF (unless otherwise noted) (see Figure 1 )
SN54LVT162240 SN74LVT162240
FROM TO V
CC
= 3.3 V V
CC
= 3.3 VPARAMETER V
CC
= 2.7 V V
CC
= 2.7 V UNIT(INPUT) (OUTPUT) ±0.3 V ±0.3 V
MIN MAX MIN MAX MIN TYP
(1)
MAX MIN MAX
t
PLH
1 4.2 5 1 2.5 4 4.6A Y nst
PHL
1 4.2 5 1 2.9 4 4.6t
PZH
1 5 5.5 1 2.8 4.8 5.7OE Y nst
PZL
1 4.9 5.1 1 2.8 4.7 4.9t
PHZ
1.9 4.9 5.4 2 3.5 4.7 5.2OE Y nst
PLZ
1.9 4.7 4.8 2 3.4 4.5 4.5t
sk(LH)
0.5
nst
sk(HL)
0.5
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.
6
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PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
GND
500 Ω
500 Ω
Data Input
Timing Input 2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE W AVEFORMS
SETUP AND HOLD TIMES
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE W AVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7 V
0 V
Input Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOL + 0.3 V
VOH − 0.3 V
≈ 0 V
2.7 V
VOLTAGE W AVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Open
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
SN54LVT162240 , , SN74LVT1622403.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719A – JULY 2000 – REVISED NOVEMBER 2006
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74LVT162240DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVT162240DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVT162240DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVT162240DGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVT162240DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVT162240DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVT162240DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVT162240DL ACTIVE SSOP DL 48 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVT162240DLG4 ACTIVE SSOP DL 48 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVT162240DLR ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVT162240DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN74LVT162240DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1
SN74LVT162240DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVT162240DGGR TSSOP DGG 48 2000 346.0 346.0 41.0
SN74LVT162240DGVR TVSOP DGV 48 2000 346.0 346.0 33.0
SN74LVT162240DLR SSOP DL 48 1000 346.0 346.0 49.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2009
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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