April 2010 Doc ID 11079 Rev 2 1/14
14
STA515W
40-volt, 3-amp, quad power half bridge
Features
Multipower BCD technology
Low input/output pulse width distortion
200 mΩ RdsON complementary DMOS output
stage
CMOS-compatible logic inputs
Thermal protection
Thermal warning output
Undervoltage protection
Short-circuit protection
Description
The STA515W is a monolithic quad half-bridge
stage in Multipower BCD Technology. The device
can be used as a dual bridge or reconfigured, by
connecting pin CONFIG to pins VDD, as a single
bridge with double-current capability.
The device is designed, particularly, to be the
output stage of a stereo all-digital high-efficiency
amplifier. It is capable of delivering 10 W x
4 channels into 4-Ω loads with 10% THD at
VCC = 18 V in single-ended configuration.
It can also deliver 20 W + 20 W into 8-Ω loads
with 10% THD at VCC = 18 V in BTL configuration
or, in single parallel BTL configuration, 40 W into
a 8-Ω load with 10% THD at VCC = 26 V.
The input pins have a threshold proportional to
the voltage on pin VL.
The STA515W comes in a 36-pin PowerSSO
package with exposed pad down (EPD).
PowerSSO36 package
with exposed pad down
Table 1. Device summary
Order code Ambient temp. range Package Packaging
STA515W 0 to 70 °C PowerSSO36 EPD Tube
STA515W13TR 0 to 70 °C PowerSSO36 EPD Tape and reel
www.st.com
Introduction STA515W
2/14 Doc ID 11079 Rev 2
1 Introduction
Figure 1. STA515W circuit for quad single-ended amplifiers
L11 22µH
L12 22µH
C51
1µF
C71
100nF C91
1µF
1µF
1µF
C81
100nF
C31 820µF
C21
2200µF
C58
100nF
C58
100nF
R57
10K
R59
10K
R41
20
R61
5K
R62
5K
R51
6
C53
100nF
C60
100nF
C61
100nF
15
M3
IN1A
IN1A
VL
CONFIG
PWRDNPWR_DN
FAULT
TRISTATE
THWARN
TH_WARN
+3.3V
IN1B
VDD
VDD
VSS
VSS
VCCSIG
VCCSIG
GNDREG
GNDCLEAN
IN2A
IN1B
IN2A
IN2B
PROTECTION
&
LOGIC
REGULATORS
29
23
24
25
27
26
28
30
21
22
33
34
35
36
M2
M5
M4
17
16
OUT1A
GND1A
OUT1A
VCC1A
14
12
10
11
OUT1B
GND1B
OUT1B
VCC1B
13
C52
1µF
+VCC
C62
100nF
7
M17
M15
M16
M14
8
9
OUT2A
GND2A
OUT2A
VCC2A
6
4
2
3
OUT2B
GND2B
D03AU1474bc
OUT2B
VCC2B
5
19
31
20
GNDSUB 1
IN2B 32
C72
100nF C92
1µF
C82
100nF
R52
6
C41
330pF
R42
20
C42
330pF
C32 820µF
L13 22µH
L14 22µH
C73
100nF C93
1µF
C83
100nF
C33 820µF
R43
20
R53
6
C74
100nF C94
1µF
C84
100nF
R54
6
C43
330pF
R44
20
C44
330pF
C34 820µF
R63
5K
R64
5K
R65
5K
R66
5K
R67
5K
R68
5K
4Ω
4Ω
4Ω
4Ω
STA515W Pin description
Doc ID 11079 Rev 2 3/14
2 Pin description
Figure 2. Pin out
Table 2. Pin list
Pin Name Type Description
1 GNDSUB PWR Substrate ground
2, 3 OUT2B O Output half bridge 2B
4 VCC2B PWR Positive supply
5 GND2B PWR Negative supply
6 GND2A PWR Negative supply
7 VCC2A PWR Positive supply
8, 9 OUT2A O Output half bridge 2A
10, 11 OUT1B O Output half bridge 1B
12 VCC1B PWR Positive supply
13 GND1B PWR Negative supply
14 GND1A PWR Negative supply
15 VCC1A PWR Positive supply
16, 17 OUT1A O Output half bridge 1A
18 N.C. - No internal connection
19 GNDCLEAN PWR Logical ground
20 GNDREG PWR Ground for regulator VDD
21, 22 VDD PWR 5-V regulator referred to ground
23 VL PWR High logical state setting voltage, VL
VCCSIG
VCCSIG
VSS
VSS
IN2B
IN2A
IN1B
IN1A
THWARN
FAULT
TRISTATE
PWRDN
CONFIG
VL
VDD
VDD
GNDREG
GNDCLEAN
GNDSUB
OUT2B
OUT2B
VCC2B
GND2B
GND2A
VCC2A
OUT2A
OUT2A
OUT1B
OUT1B
VCC1B
GND1B
GND1A
VCC1A
OUT1A
OUT1A
N.C.
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
STA515W
Pin description STA515W
4/14 Doc ID 11079 Rev 2
24 CONFIG I
Configuration pin:
0: normal operation
1: bridges in parallel, see Parallel-output and high-current
operation on page 9
25 PWRDN I
Stand-by pin:
0: low-power mode
1: normal operation
26 TRISTATE I
Hi-Z pin:
0: all power amplifier outputs in high-impedance state
1: normal operation
27 FAULT O
Fault pin advisor (open-drain device, needs pull-up resistor):
0: fault detected (short circuit or thermal, for example)
1: normal operation
28 THWARN O
Thermal-warning advisor (open-drain device, needs pull-up
resistor):
0: temperature of the IC >130 oC
1: normal operation
29 IN1A I Input of half bridge 1A
30 IN1B I Input of half bridge 1B
31 IN2A I Input of half bridge 2A
32 IN2B I Input of half bridge 2B
33, 34 VSS PWR 5-V regulator referred to +VCC
35, 36 VCCSIG PWR Signal positive supply
Table 2. Pin list
Pin Name Type Description
STA515W Electrical characteristics
Doc ID 11079 Rev 2 5/14
3 Electrical characteristics
Unless otherwise stated, the test conditions for Ta bl e 6 below are VL = 3.3 V, VCC = 30 V,
RL=8Ω, fSW = 384 kHz and Tamb = 25 °C
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage (Pins 4, 7, 12, 15) 40 V
Vmax Maximum voltage on pins 23 to 32 5.5 V
Top Operating temperature range 0 to 70 °C
Ptot Power dissipation (Tcase = 70 °C) 21 W
Tstg, TjStorage and junction temperature -40 to 150 °C
Table 4. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
VCC DC supply voltage (Pins 4, 7, 12, 15) 10 - 36 V
VLInput logic reference 2.7 3.3 5.0 V
Tamb Ambient temperature 0 - 70 °C
Table 5. Thermal data
Symbol Parameter Min Typ Max Unit
Tj-case Thermal resistance junction to case (thermal pad) - - 1.5 °C/W
TjSD Thermal shut-down junction temperature - 150 - °C
Twarn Thermal warning temperature - 130 - °C
thSD Thermal shut-down hysteresis - 25 - °C
Table 6. Electrical characteristics
Symbol Parameter Test conditions Min Typ Max Unit
RdsON
Power P-channel/N-channel
MOSFET RdsON Idd = 1 A - 200 270 mΩ
Idss
Power P-channel/N-channel
leakage Idss VCC = 35 V --50µA
gN
Power P-channel RdsON
matching Idd = 1 A 95--%
gP
Power N-channel RdsON
matching Idd = 1 A 95--%
Dt_s Low current dead time (static) see Figure 3 - 1020ns
Electrical characteristics STA515W
6/14 Doc ID 11079 Rev 2
Dt_d High current dead time
(dynamic)
L = 22 µH, C = 470 nF
RL = 8 Ω, Idd = 3.0 A
see Figure 4
--50ns
td ON Turn-on delay time Resistive load - - 100 ns
td OFF Turn-off delay time Resistive load - - 100 ns
trRise time Resistive load
see Figure 3 --25ns
tfFall time Resistive load
see Figure 3 --25ns
VCC Supply operating voltage - 10 - 36 V
VIN-Low
Half-bridge input, low level
voltage -
-
-V
L
/ 2
-
300 mV
V
VIN-High
Half-bridge input, high level
voltage -V
L
/ 2 +
300 mV
-
-
V
IIN-H High level input current VIN = VL-1-µA
IIN-L Low level input current VIN = 0.3 V - 1 - µA
IPWRDN-H
High level PWRDN pin input
current VL = 3.3 V - 35 - µA
VLow
Low logical state voltage
(pins PWRDN, TRISTATE)
(seeTa bl e 7 )
VL = 3.3V --0.8V
VHigh
High logical state voltage
(pins PWRDN, TRISTATE)
(seeTa bl e 7 )
VL = 3.3 V 1.7 - - V
IVCC-
PWRDN
Supply current from VCC in
power down VPWRDN = 0 V --3mA
IFAULT
Output current on pins
FAULT, THWARN with fault
condition
Vpin = 3.3V -1-mA
IVCC-HiZ
Supply current from VCC in
3-state VTRISTATE = 0 V - 22 - mA
IVCC
Supply current from VCC in
operation (both channels
switching)
Input pulse width
= 50% duty,
switching frequency
= 384 kHz,
no LC filters
-50-mA
IOCP
Overcurrent protection
threshold Isc (short circuit
current limit)
- 36- A
VUVP
Undervoltage protection
threshold --7-V
tpw_min Output minimum pulse width No load 70 - 150 ns
Table 6. Electrical characteristics (continued)
Symbol Parameter Test conditions Min Typ Max Unit
STA515W Electrical characteristics
Doc ID 11079 Rev 2 7/14
Test circuits
Figure 3. Test circuit
Figure 4. Current dead time test circuit
Table 7. Threshold switching voltage variation with voltage on pin VL
Voltage on pin VL, V
L
VLOW max VHIGH min Unit
2.7 0.7 1.5 V
3.3 0.8 1.7 V
5.0 0.85 1.85 V
Table 8. Logic truth table
Pin
TRISTATE
Inputs as per Figure 4 Transistors as per Figure 4
Output mode
INxA INxB Q1 Q2 Q3 Q4
0 x x Off Off Off Off Hi Z
100OffOffOnOnDump
101OffOnOnOffNegative
110OnOffOffOnPositive
111OnOnOffOffNot used
Low current dead time = MAX(DTr,DTf)
OUTxY
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
t
DTfDTr
Duty cycle = 50%
INxY OUTxY
gnd
+Vcc
R 8Ω
+
-vdc = Vcc/2
D03AU1458
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Rload=8Ω
Q2
OUTB
DTout(B) DTin(B)
DTout(A)
C71 470nF C70
470nF
C69
470nF
Iout=4.5A
Iout=4.5A
Q4
Q1
Q3
INB
D03AU1517
INA
DTin(A)
Duty cycle=A Duty cycle=B
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
L68 22µL67 22µ
OUTA
Applications information STA515W
8/14 Doc ID 11079 Rev 2
4 Applications information
The STA515W is a dual channel H-bridge that can deliver 20 W per channel into 8 Ω with
10% THD at VCC = 18 V with high efficiency.
The STA515W converts both DDX and binary-logic-controlled PWM signals into audio
power at the load. It includes a logic interface, integrated bridge drivers, high efficiency
MOSFET outputs and thermal and short-circuit protection circuitry.
In DDX mode, two logic-level signals per channel are used to control the high-speed
MOSFET switches which drive the speaker load in a bridge configuration, according to the
damped ternary modulation operation.
In binary mode, both full-bridge and half-bridge modes are supported.
The STA515W includes overcurrent and thermal protection as well as an undervoltage
lockout with automatic recovery. A thermal warning status is also provided.
Figure 5. Block diagram for DDX or binary modes
Figure 6. Block diagram for binary half-bridge mode
Logic interface and decode
The STA515W power outputs are controlled using one or two logic-level timing signals. In
order to provide a proper logic interface, pin VL must operate at the same voltage as the
DDX control logic supply.
Logic
interface
and
decode
OUTPL
OUTNL
Left
H-bridge
Protection
circuit
Regulators
OUTPR
OUTNR
Right
H-bridge
INL[1,2]
VL
PWRDN
TRISTATE
FAULT
THWARN
INR[1,2]
OUTPL
Left A
bridge
Logic
interface
and
decode
Protection
circuit
Regulators
INL[1,2]
VL
PWRDN
TRISTATE
FAULT
THWARN
INR[1,2]
OUTNL
Left B
bridge
OUTPR
Right A
bridge
OUTNR
Right B
bridge
STA515W Applications information
Doc ID 11079 Rev 2 9/14
Protection circuits
The STA515W includes protection circuitry for overcurrent and thermal overload conditions.
A thermal warning pin (THWARN) is activated low (open-drain MOSFET) when the IC
temperature exceeds 130 °C, which is in advance of the thermal shutdown protection. When
a fault condition is detected an internal fault signal acts to immediately disable the output
power MOSFETs, placing both H-bridges in the high-impedance state. At the same time an
open-drain MOSFET connected to pin FAULT is switched on.
There are two possible modes subsequent to activating a fault:
zShutdown mode:
with pins FAULT (with pull-up resistor) and TRISTATE independent, an activated fault
disables the device, signalling low at pin FAULT.
The device may subsequently be reset to normal operation by toggling pin TRISTATE
from high to low and back to high using an external logic signal.
zAutomatic recovery mode:
This is shown in the applications circuit in Figure 7 and Figure 7 on page 10.
Pins FAULT and TRISTATE are shorted together and connected to a time constant
circuit comprising R59 and C58.
An activated fault forces a reset on pin TRISTATE causing normal operation to resume
following a delay determined by the time constant of the circuit.
If the fault condition is still present, the circuit operation continues, repeating until the
fault condition is removed.
An increase in the time constant of the circuit produces a longer recovery interval.
Care must be taken in the overall system design so as not to exceed the protection
thresholds under normal operation.
Power outputs
The STA515W power and output pins are duplicated to provide a low-impedance path for
the device bridged outputs. All duplicated power, ground and output pins must be connected
for proper operation.
Pins PWRDN or TRISTATE should be used to set all MOSFETS to the high-impedance
state during power-up and until the logic power supply, VL, has settled.
Parallel-output and high-current operation
When using DDX mode, the STA515W outputs can be connected in parallel to increase the
output current capability. In this configuration the device can provide 40 W into 8 Ω.
This mode of operation is enabled with pin CONFIG connected to VDD. The inputs must be
combined to give INLA = INLB and INRA = INRB, then the corresponding outputs can be
shorted together to give OUTLA = OUTLB and OUTRA = OUTRB.
Output filter
A passive 2nd-order filter is used on the STA515W power outputs to reconstruct an analog
audio signal. The system performance can be significantly affected by the output filter
design and choice of passive components.
Filter designs for 4-Ω and 8-Ω loads are shown in the applications circuits of Figure 1 on
page 2 for the half-bridge mode, and Figure 7 and Figure 8 on page 10 for the full bridge.
Applications information STA515W
10/14 Doc ID 11079 Rev 2
Applications circuits
Figure 7 below shows a typical full-bridge circuit for supplying 20 W + 20 W into 8-Ω
speakers with 10% THD at VCC = 18 V.
Figure 7. Typical stereo full-bridge configuration for 20 + 20 W
Figure 8 below shows a single-BTL configuration capable of supplying 40 W into a 4-Ω load
at 10% THD with VCC = 19 V. This result was obtained with peak power for <1 s using the
STA308+STA515W+STA50X demo board. A PWM modulator as driver is required.
Figure 8. Typical single-BTL configuration for 40 W
L18 22µH
L19 22µH
C30
1µF
C20
100nF
C99
100nF
C101
100nF
C107
100nF
C106
100nF
C23
470nF
C55
1000µF
C21
100nF
C58
100nF
C58
100nF
R57
10K
R59
10K
R63
20
R98
6
R100
6
C53
100nF
C60
100nF
C31
220nF
C52
330pF
R104
20
C109
330pF
15
M3
IN1A
IN1A
VL
CONFIG
PWRDNPWR_DN
FAULT
TRISTATE
THWARN
TH_WARN
+3.3V
IN1B
VDD
VDD
VSS
VSS
VCCSIG
VCCSIG
GNDREG
GNDCLEAN
IN2A
IN1B
IN2A
IN2B
PROTECTION
&
LOGIC
REGULATORS
29
23
24
25
27
26
28
30
21
22
33
34
35
36
M2
M5
M4
17
16
OUT1A
GND1A
OUT1A
VCC1A
14
12
10
11
OUT1B
GND1B
OUT1B
VCC1B
13
L113 22µH
L112 22µH
C32
220nF
+VCC
C108
470nF
C31
220nF
7
M17
M15
M16
M14
8
9
OUT2A
GND2A
OUT2A
VCC2A
6
4
2
3
OUT2B
GND2B
D00AU1148Bbc
OUT2B
VCC2B
5
19
31
20
GNDSUB 1
IN2B 32
C110
100nF
C111
100nF
R103
6
R102
6
8Ω
8Ω
10µH
10µH
100nF
FILM
220nF
X7R
220nF
X7R
1µF
X7R
2200µF
63V
220nF
680nF
FILM
100nF
FILM
100nF
10K
10K 3.3
1/2W
3.3
1/2W
100nF
X7R
100nF
X7R
Add.
IN1A
IN1A
VL
CONFIG
PWRDN
nPWR_DN
FAULT
TRISTATE
THWARN
TH_WARN
+3.3V
100nF
100nF
X7R
IN1B
VDD
VDD
VSS
VSS
VCCSIG
VCCSIG
GNDREG
GNDCLEAN
IN1B
IN2A
29
23 N.C.
24
25
27
26
28
30
21
22
33
34
35
36
17
16
18
OUT1A
GND1B
OUT1A
VCC1B
10
13
11 OUT1B
GND1A
OUT1B
14
Vcc
330pF
22Ω
1/2W
4Ω
GND2A
6
2
12
VCC1A
15
VCC2B
4
VCC2A
7
3OUT2B
GND2B
D04AU1545bc
OUT2B
5
19
31
20
GNDSUB 1
IN2B 32
8
9OUT2A
OUT2A
1µF
X7R
Vcc
220nF
STA515W Package mechanical data
Doc ID 11079 Rev 2 11/14
5 Package mechanical data
The STA515W comes in a 36-pin PowerSSO package with exposed pad down (EPD).
Figure 9 below shows the package outline and Ta b l e 9 gives the dimensions.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 9. PowerSSO36 EPD dimensions
Symbol
Dimensions in mm Dimensions in inches
Min Typ Max Min Typ Max
A 2.15 - 2.47 0.085 - 0.097
A2 2.15 - 2.40 0.085 - 0.094
a1 0.00 - 0.10 0.000 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G- - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h- - 0.40 - - 0.016
k 0 - 8 degrees 0 - 8 degrees
L 0.60 - 1.00 0.024 - 0.039
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 6.50 - 7.10 0.256 - 0.280
Package mechanical data STA515W
12/14 Doc ID 11079 Rev 2
Figure 9. PowerSSO36 EPD outline drawing
h x 45°
STA515W Revision history
Doc ID 11079 Rev 2 13/14
6 Revision history
Table 10. Document revision history
Date Revision Changes
Nov-2004 1 Initial release.
27-Apr-2010 2
Added order code STA515W13TR
Modified Figure 1 on page 2
Reconstructed pin list in Table 2 on page 3 with information from
former table 3 Functional pin status
Updated Vlow and Vhigh spec in Table 6 on page 5
Modified Figure 3 and Figure 4 on page 7
Updated applications circuits in Figure 7 and Figure 8 on page 10
STA515W
14/14 Doc ID 11079 Rev 2
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