ISP1763A PCI evaluation board UM0865 User manual Abstract This document describes board level operations of the ISP1763A PCI evaluation board. Two version of the board are available: one for the TFBGA package and the other for the VFQFPN package. The ISP1763A PCI evaluation board allows engineers and software developers to create USB host, device, and OTG features for customer applications. Keywords isp1763a; usb; universal serial bus; host controller; otg; on-the-go CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A ISP1763A PCI evaluation board User manual Legal information UM0865 Legal information (c) Copyright ST-Ericsson, 2010. All rights reserved. Disclaimer The contents of this document are subject to change without prior notice. ST-Ericsson makes no representation or warranty of any nature whatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to warranties of merchantability or fitness for a particular purpose, interpretability or interoperability or, against infringement of third party intellectual property rights, and in no event shall ST-Ericsson be liable to any party for any direct, indirect, incidental and or consequential damages and or loss whatsoever (including but not limited to monetary losses or loss of data), that might arise from the use of this document or the information in it. ST-Ericsson and the ST-Ericsson logo are trademarks of the ST-Ericsson group of companies or used under a license from STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. Trademark list All trademarks and registered trademarks are the property of their respective owners. CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 2 (29) ISP1763A PCI evaluation board User manual Contents UM0865 Contents 1 About this document 5 1.1 Purpose 5 1.2 Revision information 5 1.3 Board history 5 1.4 Reference list 5 2 Introduction 6 2.1 Key features 6 2.2 Basic operation 8 2.2.1 Working with Linux OS 8 2.2.2 Working with Windows CE OS 8 3 Physical description 9 3.1 Board layout 9 3.2 Connectors 9 3.2.1 J1 PLX signals probe connector 10 3.2.2 J2 ISP1763A bus interface 10 3.2.3 J3, J4, J5, and J6 bus test headers 11 3.2.4 USB ports 11 3.2.5 JP1 Xilinx 3-state input 11 3.2.6 JP2 Xilinx PROG input 11 3.2.7 JP3 Xilinx JTAG connector 11 3.2.8 JP4 GND connector 12 3.2.9 JP5 GND connector 12 3.2.10 JP6 +5 V power select 12 3.2.11 JP7 VCC(I/O) select 12 3.2.12 PS1 PC power connector 12 3.2.13 PS2 DC power socket 12 3.2.14 CON1 PCI connector 12 3.2.15 CN1 PXA320 platform connector 13 3.2.16 DC1 DM357platform connector 13 CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 3 (29) ISP1763A PCI evaluation board User manual Contents UM0865 3.2.17 Conf1* butterfly configuration 13 3.3 LEDs 14 3.4 Board components 15 3.4.1 ISP1763A chip 15 3.4.2 PLX9054 and 93LC56C EEPROM 16 3.4.3 Xilinx XC3S500E 17 4 Schematics 18 5 List of materials 25 Glossary CD00257207 29 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 4 (29) ISP1763A PCI evaluation board User manual About this document UM0865 1 About this document 1.1 Purpose This document provides description on how to use the evaluation module to develop software for customers. 1.2 Revision information Table 1 Revision history Date Rev. Comments 2010-02-12 1 First release. 2010-04-05 2 Updated the last paragraph of Section 3.2.3 and Section 3.2.7. Changed the package name from HVQFN to VFQFPN. 1.3 Board history 1.4 CD00257207 Table 2 Board history Date Rev. Comments 2009-10-30 09283-1 ISP1763 PCI evaluation board (TFBGA) first release. 2009-10-30 09282-1 ISP1763 PCI evaluation board (VFQFPN) first release. Reference list Rev 2 [1] Universal Serial Bus Specification Rev. 2.0 [2] PCI Local Bus Specification Version 2.2 [3] PLX PCI 9054 Data Sheet [4] ISP1763A PCI evaluation board - FPGA design (UM0887) CD00259895 [5] ISP1763A Hi-Speed USB OTG controller data sheet CD00264885 [6] ISP1763A programming guide (PM0070) CD00265095 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. www.usb.org ISP1763A 5 (29) ISP1763A PCI evaluation board User manual Introduction UM0865 2 Introduction This section provides a description of the ISP1763A PCI evaluation board along with the key features and a block diagram of the circuit board. 2.1 Key features The ISP1763A is a Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) dual-role controller with two USB ports. Port 1 is configurable as a host controller, an OTG controller, or a peripheral controller, while port 2 is always assigned to the host controller. The ISP1763A bus interface provides SRAM, general-multiplex, NOR, and NAND modes to communicate with most types of microcontrollers and microprocessors. The PCI bridge board allows you to demonstrate the functionality of the ISP1763A on a standard PC with at least one PCI slot. ISP1763A POWER 1.8 V SUPPLY XILINX JTAG 2.5 V SUPPLY 3.3 V SUPPLY PLX9054 EEPROM PCI CONNECTOR Figure 1 Block diagram of the ISP1763A PCI evaluation board Key features include: CD00257207 Rev 2 * 12 MHz crystal clock input * One OTG port, one host only port * Four types of bus interfaces * FPGA configuration * PCI connection 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 6 (29) ISP1763A PCI evaluation board User manual Introduction UM0865 CD00257207 Rev 2 * Multiple voltage power supply * All local bus signals are easily accessible on test headers designed for direct connection of a standard Tektronix logic analyzer Figure 2 ISP1763A PCI evaluation board--VFQFPN Figure 3 ISP1763A PCI evaluation board--TFBGA 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 7 (29) ISP1763A PCI evaluation board User manual Introduction UM0865 2.2 Basic operation 2.2.1 Working with Linux OS Any x86-based computer that has a PCI slot (32-bit, 33 MHz) running with Linux Red Hat kernel can be used. The type of Linux Red Hat installation determines minimum system requirements. The minimum recommended system configuration is a Pentium-class processor (1 GHz) with 128 MB RAM. 2.2.2 Working with Windows CE OS An x86-based computer that has an available PCI slot (32-bit, 33 MHz) running Windows CE ver. 5.0 or ver. 6.0 OS can be used. For ST-Ericsson set-up example, use Gigabyte GA-945GZM-S2 motherboard (on board Ethernet controller disabled) with RealTek PCI Ethernet card (PCI vendor ID is 10ECh and device ID is 8139h), and a standard 1.44 MB floppy disk drive (for system boot up). Follow this hardware configuration as much as possible, especially the motherboard and the Ethernet card. CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 8 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 3 Physical description This section describer the physical layout of the ISP1763A PCI evaluation board and its interface. 3.1 Board layout The ISP1763A PCI evaluation board is 150 x 101.6 mm six-layer (TFBGA) or four-layer (VFQFPN) printed-circuit board that is powered by the PCI slot power. Figure 4 shows the layout of the top view of the ISP1763A PCI evaluation board. Figure 4 3.2 ISP1763A PCI evaluation board - top view Connectors These connectors and jumpers are described in the following sections. CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 9 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 Table 3 3.2.1 Connectors Connector Function J1 PLX signals probe connector 1 J2 ISP1763A bus interface J3 Bus test header. Lower 8-bit AD bus. J4 Bus test header. Control signal of the ISP1763A. J5 Bus test header. Upper 8-bit AD bus. J6 Bus test header. 8-bit address bus. S3 / port 1 Micro-AB USB connector. S2 / port 2 Standard-A USB connector. JP1 Xilinx Tristate input. Tristate input to Xilinx to 3-state signals to the ISP1763A. JP2 Xilinx PROG input. When this jumper is connected, the FPGA code will be loaded to Xilinx from U5. JP3 Xilinx JTAG connector JP4 GND connector JP5 GND connector JP6 +5 V power select JP7 VCC(I/O) select PS1 PC power connector PS2 DC power socket CON1 PCI connector CN1 PXA320 platform connector DC1 DM357 platform connector Conf1* Butterfly configuration J1 PLX signals probe connector This is only for using the logic analyzer. Probe debug signals between FPGA and PLX9054 communication. The default setting is not mounted on board. 3.2.2 J2 ISP1763A bus interface This header has all the address bus, data bus, and control signals of the ISP1763A. CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 10 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 Figure 5 J2 bus interface 3.2.3 J3, J4, J5, and J6 bus test headers These headers are only used to probe bus interface signals. Only for testing. The J3 male header is for lower 8-bit AD[7:0] signals. The J5 male header is for upper 8-bit AD[15:8] signals. The J4 male header is for the DACK, DREQ, IRQ, CLE, ALE/ADV_N, WR_N/RW_N/WE_N, RD_N/DS_N/RE_N/OE_N, and CS_N/CE_N control signals. The J6 male header is for 8-bit A[7:0] signals. 3.2.4 USB ports The ISP1763A has two ports. 3.2.5 * Port 1 can be configured as either the host controller or the peripheral controller. Has a micro-AB USB connector on board. * Port 2 is configured as the host controller. Has a standard-A USB host connector on board. JP1 Xilinx 3-state input This is the 3-state input to Xilinx. Connect pin 1 and pin 2. The Xilinx pins connected to the ISP1763A are not 3-stated. Connect pin 3 and pin 2. The Xilinx pins connected to the ISP1763A are 3-stated. 3.2.6 JP2 Xilinx PROG input This is the Xilinx PROG input. When this jumper is connected, the FPGA code will be loaded to Xilinx from U5. 3.2.7 JP3 Xilinx JTAG connector Figure 6 JP3 JTAG connector Through the JTAG interface, download program into Xilinx XC3S500E. CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 11 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 Use the Xilinx USB blaster to connect the JTAG interface on board. LED1 turns on when FPGA successfully completes configuration. 3.2.8 JP4 GND connector The GND connector is to connect the oscilloscope or logic analyzer probe. 3.2.9 JP5 GND connector The GND connector is to connect the oscilloscope or logic analyzer probe. 3.2.10 JP6 +5 V power select This is the 5 V power supply select. Connect pin 1 and pin 2. 5 V is supplied by external power supply PS1 or PS2. Connect pin 2 and pin 3. 5 V is supplied by the PCI slot (default). 3.2.11 JP7 VCC(I/O) select This is the VCC(I/O) power supply select. Connect pin 1 and pin 2. VCC(I/O) is powered by 3.3 V (default). Connect pin 2 and pin 3. VCC(I/O) is powered by 1.8 V. 3.2.12 PS1 PC power connector Used for external supply of +12 V from the PC power supply. Connect pin 1 and pin 2 of JP6. 5 V is supplied by external power supply PS1. This is not used when the ISP1763A is inserted into the PCI slot. 3.2.13 PS2 DC power socket Used for the external supply of +12 V / 3 A from the DC power supply. Connect pin 1 and pin 2 of JP6. 5 V is supplied by external power supply PS2. This is not used when the ISP1763A is inserted into the PCI slot. 3.2.14 CON1 PCI connector This is the standard PCI bus interface that is compliant with PCI Local Bus Specification Ver. 2.2. All PCI signals are connected to PLX9054 PCI-to-local bus I/O accelerator chip. CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 12 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 3.2.15 CN1 PXA320 platform connector By default, this connector is not mounted. Only for the BSQUARE PXA320 platform use. While using this connector with the PXA320 platform, the ISP1763A PCI evaluation board is powered by external DC +12 V / 3 A power supply PS2. 1. Connect pin 1 and pin 2 of jumper JP6. The evaluation board is powered by the external power supply. 2. Connect pin 1 and pin 2 of jumper JP7. The I/O voltage of the ISP1763A is set at 3.3 V. The PXA320 platform does not provide 1.8 V. 3. Connect pin 2 and pin 3 of jumper JP1. It 3-states all I/O pins from the FPGA connected to the ISP1763A IC. 4. Connect pin 1 and pin 2 of jumper JP2. The FPGA program is loaded from U5. The program has the logic for the 3-state of the pins. 3.2.16 DC1 DM357platform connector By default, this connector is not mounted. Only for the DAVINCI DM357 platform use. While using this connector with the DM357 platform, the ISP1763A PCI evaluation board is powered by external DC +12 V / 3 A power supply PS2. 1. Connect pin 1 and pin 2 of jumper JP6. The evaluation board is powered by the external power supply. 2. Connect pin 2 and pin 3 of jumper JP7. The I/O voltage of the ISP1763A is set at 1.8 V. The DM357 platform does not provide 3.3 V. 3. Connect pin 2 and pin 3 of jumper JP1. It 3-states all I/O pins from the FPGA connected to the ISP1763A IC. 4. Connect pin 1 and pin 2 of jumper JP2. The FPGA program is loaded from U5. The program has the logic for the 3-state of pins. 3.2.17 Conf1* butterfly configuration Frequency selection is done using pins FREQSEL1 and FREQSEL2. The corresponding resistors are mounted to connect FREQSEL1 and FRESEL2 to GND or VCC(I/O). * To connect FREQSEL2 to LOW, mount R111 and remove R113. * To connect FREQSEL2 to HIGH, mount R113 and remove R111. * To connect FREQSEL1 to LOW, mount R112 and remove R114. * To connect FREQSEL1 to HIGH, mount R114 and remove R112. The PIO mode selection is needed only for the actual platform validation. On the x86 platform, PIO mode selection is done using the Xilinx FPGA code. The mounting of resistors (R119 to R122) do not affect the mode selection done by Xilinx. To configure in various modes, refer to ISP1763A PCI evaluation board - FPGA design (UM0887). CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 13 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 When the ISP1763A is connected to customer platform, mode selection is done using pins CLE and ALE/ADV_N. The corresponding resistors are mounted to connect CLE and ALE/ADV_N to GND or VCC(I/O). * To connect CLE to LOW, mount R120 and remove R122. * To connect CLE to HIGH, mount R122 and remove R120. * To connect ALE/ADV_N to LOW, mount R119 and remove R121. * To connect ALE/ADV_N to HIGH, mount R121 and remove R119. Figure 7 Table 4 Butterfly configuration Clock frequency and bus interface configuration Clock frequency 12 MHz (default) 19.2 MHz 24 MHz Reserved Comment FREQSEL2 LOW LOW HIGH HIGH Through R111 to GND. Through R113 to VCC(I/O). FREQSEL1 LOW HIGH LOW HIGH Through R112 to GND. Through R114 to VCC(IO). Bus interface SRAM (default) NAND NOR General multiplex Comment CLE HIGH LOW LOW HIGH Through R120 to GND. Through R122 to VCC(I/O). ALE/ADV_N HIGH LOW HIGH LOW Through R119 to GND. Through R121 to VCC(I/O). 3.3 LEDs The ISP1763A PCI evaluation board has seven LEDs that are located on the top side of the board. Information regarding these LEDs is given in Table 5. CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 14 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 Table 5 LED LED Use Color LED1 JTAG download or program done indicator Orange LED2 VBUS2 volts indicator (After loading the host software, the light will be turned on.) Red LED3 VBUS1 volts indicator (After loading the host software, the light will be turned on.) Red LED4 +5 V indicator Blue LED5 +1.8 V indicator Red LED6 +2.5 V indicator Yellow LED7 +3.3 V indicator Green 3.4 Board components This describes the operation of the major board components on the ISP1763A PCI evaluation board. 3.4.1 ISP1763A chip The ISP1763A PCI evaluation board is available in two packages: TFBGA and VFQFPN. Figure 8 CD00257207 Rev 2 ISP1763A VFQFPN 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 15 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 Figure 9 ISP1763A TFBGA Table 6 ISP1763A chip package information Product Package Package description ISP1763AETTM TFBGA64 64 balls; body 4 x 4 x 0.8 mm ISP1763AHNTM VFQFPN64 64 terminals; body 9 x 9 x 1.0 mm For the schematic design, there is no difference, except the chip footprint. For the PCB layout, TFBGA is six-layered design whereas VFQFPN is only four-layered design. All the components are same on both the boards, except the ISP1763A IC package. 3.4.2 PLX9054 and 93LC56C EEPROM PLX9054 is a PCI-to-local-bus accelerator. The ISP1763A is always a PCI target during initialization, as well as during the data transfer phase to or from the ISP1763A memory. Figure 10 PLX9054 When powering on or asserting the PCI_RESET signal, PLX9054 attempts to read the serial EEPROM to check its presence. CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 16 (29) ISP1763A PCI evaluation board User manual Physical description UM0865 The 93LC56C EEPROM is required for the correct initialization of PLX9054. The serial EEPROM contains information required to initialize PLX9054 registers. For details, refer to Chapter 11 of PLX PCI 9054 Data Sheet. The initial programming of 93C56 must be done in a serial EEPROM programmer. Displaying and adjusting of certain parameters can be done using the PLXmon utility. Figure 11 3.4.3 EEPROM 93C56 Xilinx XC3S500E FPGA ensures adaptation between the ISP1763A generic bus interface and the PLX9054 local bus interface. The FPGA programming can be downloaded through the JTAG interface. Figure 12 Xilinx XC3S500E For detail description of the FPGA programming, refer to ISP1763A PCI evaluation board - FPGA design (UM0887). CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 17 (29) ISP1763A PCI evaluation board User manual Schematics UM0865 4 Schematics ISP1763A PCI EVALUATION BOARD ISP1763A USB PORTS PCI POWER Figure 13 CD00257207 Rev 2 FPGA CONNECTORS Main 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 18 (29) R115 12K,1% 0 RREF2 DIEPAD AGND AD0 AD1 AD2 AD3 VCC(I/O) AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 VCC(I/O) AD12 VCC(IO)_Chip GND VCC(3V3)_Chip C113 VCC(IO)_Chip C98 C99 C100 C101 100NF/50V 0603 10%_LF ADDR7 ADDR6 TP3 RESET# GND FREQSEL2 FREQSEL1 RESET# CLE ALE DACK# DREQ PSW1_N GND VREG D7 D6 D5 D4 D3 D2 D1 D0 DACK# DREQ IRQ CLE ALE WE# RD# CS# D7 D6 D5 D4 D3 D2 D1 D0 J3 J4 1 3 5 7 9 11 13 15 15 13 11 9 7 5 3 1 2 4 6 8 10 12 14 16 16 14 12 10 8 6 4 2 HEADER2X8_LF DACK# DREQ IRQ CLE ALE WE# RD# CS# C102 D15 D14 D13 D12 D11 D10 D9 D8 C103 D15 D14 D13 D12 D11 D10 D9 D8 J5 J6 C104 R112 C105 DNM 10K 0603 1/16W 1%_LF R119 10K 0603 1/16W 1%_LF DNM R120 2 4 6 8 10 12 14 16 16 14 12 10 8 6 4 2 VCC(3V3)_Chip GND 0 C106 C107 R113 100NF/50V 0603 10%_LF 1 0 0 1 VCC(IO)_Chip DNM 0 0 1 1 1 General Multiplex NOR 1 SRAM 10K 0603 1/16W 1%_LF R122 10K 0603 1/16W 1%_LF R121 10K 0603 1/16W 1%_LF 10K 0603 1/16W 1%_LF DNM R114 10NF/50V 0603 10% X7R_LF 19.2MHz 24MHz FSEL1_datasheet FREQSEL2 FSEL0_datasheet FREQSEL1 ALE CLE 3 0 12MHz FREQSEL2 0 ALE 0 NAND CLE BUS interface FREQSEL1 Clk frequency: SMB SOCKET S1 DNM C110 18PF/50V 0603 5%_LF 5 1 2 4 C111 18PF/50V 0603 5%_LF 10K 0603 1/16W 1%_LF X2 1 3 5 7 9 11 13 15 15 13 11 9 7 5 3 1 HEADER2X8_LF ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 100NF/50V 0603 10%_LF 10K 0603 1/16W 1%_LF R111 10NF/50V 0603 10% X7R_LF CS10 12.000MABJ-UT 0R 0R DNM C109 100nF R118 10K R117 10K VCC(IO)_Chip C108 + R123 R124 VCC(IO)_Chip TP4 DNM RESET# Decoupling capacitor 10NF/50V 0603 10% X7R_LF PLACE SUFFICIENT SPACE BETWEEN THE HEADERS FOR LA PROBE CONNECTION 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R116 12K , 1% U6 ISP1763A VFQFPN RREF1 10NF/50V 0603 10% X7R_LF PSW1_N AGND VREG(1V2) X2 X1/CLKIN AGND FREQSEL2 FREQSEL1 RESET_N CLE ALE/ADV_N DACK DREQ V(CC(I/O) A7 A6 100NF/50V 0603 10%_LF HEADER2X8_LF (c) Copyright ST-Ericsson, 2010. All rights reserved. 10NF/50V 0603 10% X7R_LF ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 Rev 2 PSW1_N 100NF/50V 0603 10%_LF HEADER2X8_LF CD00257207 VBUS1 VBUS1 19 (29) ISP1763A ID ID GND DP1_Chip DP1_Chip GND DM1_Chip DM1_Chip GND ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 VREG ISP1763A 2010-04-05 Figure 14 GND 1 2 VCC(IO)_Chip D0 D1 3 4 D2 5 D3 6 D4 7 8 D5 9 D6 D7 10 D8 11 D9 12 D10 13 D11 14 15 D12 16 TP5 C112 + DNM CS# RD# WE# IRQ 100NF/50V 0603 10%_LF 4.7uF/10V DP2_Chip DP2_Chip GND DM2_Chip DM2_Chip OC2 OC2 PSW2_N PSW2_N GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DP2 AGND DM2 OC2/VBUS2 PSW2_N AGND RREF2 VCC(3V3) ID AGND DP1 AGND DM1 AGND RREF1 OC1/VBUS1 AD13 AD14 AD15 VREG(1V2) CS_N/CE_N RD_N/DS_N/RE_N/OE_N WR_N/R W_N/WE_N INT VCC(I/O) A0 A1 A2 A3 A4 A5 VREG(1V2) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D13 D14 D15 4.7uF/10V Schematics User manual ISP1763A PCI evaluation board UM0865 S3 MIC2026-2 OUTA ENA VIN FLGA GND FLGB OUTB ENB U8 OUT1 8 7 6 5 1 2 3 4 V3V3 +5V_usb_Chip 100uF/16V C119 + DNM V3V3 100nF R133 R134 Port2 S2 VBUS DD+ GND Chassis Chassis 1 2 3 4 5 6 0R LED3 LED RED 3MM_LF + A2 VBUS1 U9 USBULC6-2F3 DNM A1 B1 FB1 VBUS1 B2 C114 100uF/16V BLM31A260S R137 560R 0603 1/16W 1%_LF R138 PSW1_N VBUS1 OC2 PSW2_N USB CON TYPE A RECEPTACLE DNM PSW1_N 0R VBUS1 0R OC2 PSW2_N +5V_usb_Chip R132 0R ID DM2_Chip DP2_Chip C115 100NF/50V 0603 10%_LF DNM U7 USBULC6-2F3 OUT2 R125 560R 0603 1/16W 1%_LF LED2 LED RED 3MM_LF DM2_Chip DP2_Chip DNM R126 0R OC2 OC2 (c) Copyright ST-Ericsson, 2010. All rights reserved. +5V_usb_Chip C116 100NF/50V 0603 10%_LF C118 4.7uF/35V C117 + ID Rev 2 A2 10K DNM DM1_Chip DP1_Chip ID=0, A ID=1, B DNM CD00257207 A1 B1 Host Socket U11 USBULC6-2F3 USB ports B2 10K R131 20 (29) ISP1763A 2010-04-05 Figure 15 R135 10K 10K R129 R130 DM1_Chip DP1_Chip A2 OUT2 100K R128 10K DNM B1 FB2 BLM31A260S A2 Port 1 A1 B1 R127 U10 USBULC6-2F3 A1 1 2 3 4 5 6 7 8 9 B2 10K DNM B2 VBUS DD+ ID GND Chassis Chassis Chassis Chassis USB_AB_MICRO OTG Soc ket Schematics User manual ISP1763A PCI evaluation board UM0865 R136 C33 C39 GND D15 D14 D13 D12 GND D11 D10 D9 D8 GND D7 D6 D5 D4 GND D3 D2 D1 D0 C44 C45 C48 C49 C50 J2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 FD2X20_LF C53 V2V5 C54 V3V3 C55 C58 C59 C60 CS# RD# WE# IRQ DREQ GND DACK# ALE CLE RESET# GND ADDR7 ADDR6 ADDR5 ADDR4 GND ADDR3 ADDR2 ADDR1 ADDR0 C63 C64 C65 C68 C69 CS# RD# WE# IRQ DREQ DACK# ALE CLE RESET# ADDR7 ADDR6 ADDR5 ADDR4 C79 C78 ADDR3 ADDR2 ADDR1 ADDR0 C73 C74 C71 C76 C81 C80 C66 C75 C61 C70 C56 C82 CLE ALE WE# RD# IRQ CS# DREQ V2V5 R61 R62 R63 R64 R65 0R 0R 0R 0R 0R 0R 0R 0R 0R R66 R67 R68 R69 0R 0R VIO R70 R71 0R 0R VIO V1V2 ADDR7 ADDR6 R72 R73 0R 0R 0R 0R DACK# RESET# ADDR5 ADDR4 R74 R75 R76 R77 R78 R79 R80 R81 0R 0R 0R 0R ADDR3 ADDR2 ADDR1 ADDR0 D15 D14 D13 D12 0R 0R 0R 0R TP1 0R 0R 0R 0R 0R 0R 0R 0R R82 R83 R84 R85 R90 R91 R92 R93 D11 D10 D9 D8 VIO V2V5 R94 R95 R96 R97 DNM 0R TP2 GND V2V5 VIO V1V2 GND VIO GND GND VIO V2V5 TMS GND GCLK LCLK 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 GND IO1_L01P/A16 IO1_L01N/A15 IO1_L02P/A14 IO1_L02N/A13 IP VCCAUX IO1_L03P IO1_L03N/VREF VCCO1 IO1_L04P IO1_L04N VCCINT IP IO1_L05P/A12 IO1_L05N/A11 GND IO1_L06P IO1_L06N/VREF IP VCCO1 IO1_L07P/A10/RHCLK IO1_L07N/A9/RHCLK1 IO1_L08P/A8/RHCLK2 IO1_L08N/A7/RHCLK3 IP GND IO1_L09P/A6/RHCLK4 IO1_L09N/A5/RHCLK5 IO1_L10P/A4/RHCLK6 IO1_L10N/A3/RHCLK7 IP/VREF IO1_L11P/A2 IO1_L11N/A1 IO1_L12P IO1_L12N/A0 GND IP VCCO1 IO1_L13P IO1_L13N IO1_L14P IO1_L14N IP VCCAUX IO1_L15P/HDC IO1_L15N/LDC0 IO1_L16P/LDC1 IO1_L16N/LDC2 IP TMS GND GCLK V2V5 VIO 20 19 V3V3 18 TDO 17 16 15 14 13 12 11 LCLK V2V5 VIO VIO DIN For Debug VIO VIO For Debug For Debug For Debug Dout V1V2 10K 10K V2V5 10K R60 VIO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C43 Female - IDE connector pin orientation of the header as seen from the top view (top layer) C38 100NF/50V 0603 Y5V_LF C34 100NF/50V 0603 Y5V_LF C40 C51 C77 D7 D6 D5 D4 D3 D2 D1 D0 22R 22R R88 U5 XCF04S D0 VCCJ NC VCCO CLK VCCINT TDI TDO TMS NC TCK NC NC CF OE/RST CEO NC NC CE GND INIT GND Bank 1 V2V5 V1V2 10K M0 GND R49 M1 10K 1763_tristate_n R50 V3V3 Bank 2 Bank 0 V3V3 Bank 3 V2V5 V3V3 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 1 2 JP4 HEADER1X2_LF JP5 V2V5 TSIZ0 TSIZ1 V1V2 LW/R# V3V3 V3V3 V2V5 V3V3 HEADER1X2_LF GND V3V3 V2V5 LA16 LA17 LA18 V3V3 GND LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 GND LA28 LA29 LA30 LA31 LW/R# V3V3 LD0 LD1 GND LD2 LD3 TSIZ1 V1V2 LD4 LD5 GND LD6 LD7 V2V5 TSIZ0 LD8 LD9 LD10 LD11 JP3 JTAG JP1 6 5 4 3 2 1 VIO R102 R103 R104 R105 V3V3 1 2 3 100R 100R 100R 100R TMS TDI TDO TCK 1763_tristate_n 4.7K R101 DNM R100 68R LD[15..0] V2V5 V3V3 HEADER1X3_LF 2 PIN MALE HEADER FOR CRO PROBE U3 XC3S500E R110 4.7K GND IP IO3_L16N IO3_L16P IO3_L15N IO3_L15P VCCO3 IO/VREF VCCAUX IP IO3_L14N IO3_L14P IO3_L13N IO3_L13P VCCO3 GND IO3_L12N IO3_L12P IO3_L11N IO3_L11P IP IO3_L10N/LHCLK7 IO3_L10P/LHCLK6 IO3_L09N/LHCLK5 IO3_L09P/LHCLK4 GND IP IO3_L08N/LHCLK3 IO3_L08P/LHCLK2 IO3_L07N/LHCLK1 IO3_L07P/LHCLK0 VCCO3 IP/VREF IO3_L06N IO3_L06P GND IO3_L05N IO3_L05P IP VCCINT IO3_L04N IO3_L04P GND IO3_L03N IO3_L03P VCCAUX IP IO3_L02N/VREF IO3_L02P IO3_L01N IO3_L01P PROG_B R99 0R hswap HSWAP: 0:user io pull up enable HSWAP: 1:user io pull up disable during configuration: 10K C35 C46 C72 VIO 10NF/50V 0603 10% X7R_LF C41 C67 100NF/50V 0603 Y5V_LF V3V3 C36 C62 C92 C57 C96 R87 R86 V3V3 C95 100NF/50V 0603 Y5V_LF C91 C52 C90 C47 VIO V1V2 C87 OSCCLK OSCCLK C89 C42 C86 V3V3 C88 C37 C85 4 C94 10NF/50V 0603 10% X7R_LF C84 4 R89 0R DNM DIN CLK TDOI TMS TCK 1 2 3 4 5 6 7 8 9 10 JP2 HEADER1X2_LF PROG_B When connect jumper, FPGA can be loaded W\hen disconnect jumper, FPGA can't be loaded (c) Copyright ST-Ericsson, 2010. All rights reserved. C83 OSC 2 50MHz OSCCLK PROG_B INIT DONE LD12 100NF/50V 0603 Y5V_LF 2 R109 0R 4U7F/10V 0603 Y5V_LF U4 1 20 1OE Vcc 2 19 1A1 2OE 18 3 2Y4 1Y1 17 4 1A2 2A4 5 16 2Y3 1Y2 15 6 1A3 2A3 7 14 2Y2 1Y3 8 13 1A4 2A2 9 12 2Y1 1Y4 10 11 GND 2A1 4.7K 4.7K Rev 2 DNM SW1 DNM LED1 LED ORANGE 0603_LF R98 R48 DR EQ0# LD12 10K V2V5 21 (29) CD00257207 SN74LVT244BPW C97 FPGA CONFIG R107 R106 4U7F/10V 0603 Y5V_LF VIO V3V3 R108 V2V5 120R 0603 1/10W 1%_LF LA[31..16] M2 10K R51 GC LK GND DACK0# 10K 10K 10K 10K R52 R53 R54 R55 VIO 10K 10K GND R56 R57 V1V2 V2V5 R58 R59 TEST ISP1763A FPGA 2010-04-05 Figure 16 LR EADY# R47 GND 157 158 159 160 161 162 163 164 165 166 167 168 169 V1V2 170 LREADY# 171 172 GND 173 174 175 V3V3 176 177 178 179 180 181 GND 182 183 184 185 186 187 GND 188 189 190 V3V3 191 192 193 TEST 194 V2V5 195 196 197 GND 198 199 200 DNM 0R V3V3 201 LD15 202 203 LD14 204 205 LD13 206 hswap TDI 207 GND 208 LHOLD 1 2 DONE CLK 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 DONE IO2_L17N/CCLK IO2_L17P/VS0/A17 IP IO2_L16N/VS1/A18 IO2_L16P/VS2/A19 IO2/VREF IO2_L15N/A20 IO2_L15P/A21 GND IO2_L14N/A22 IO2_L14P/A23 VCCAUX IP IO2_L13N IO2_L13P VC CO2 IO2_L12N/DIN/D0 IO2_L12P/M0 GND IO/M1 IO2_L11N/D1/GCLK3 IO2_L11P/D2/GCLK2 IP2_L10N/M2/GCLK1 IP2_L10P/R DWRB /GCLK0 GND IO2_L09N/D3/GCLK15 IO2_L09P/D4/GCLK14 IO/D5 IO2_L08N/D6/GCLK13 IO2_L08P/D7/GCLK12 VC CO2 IP2_L07N/VREF IP2_L07P GND IO2_L06N IO2_L06P VC CINT VCCAUX IO2_L05N IO2_L05P IO2_L04N IO2_L04P IO2_L03N/MOSI/CSIB IO2_L03P/DOUT/BUSY VC CO2 IP2_L02N IP2_L02P IO2_L01N/INTB IO2_L01P/CSOB IP GND TDOI TCK TDO TC K IP IO0_L01P IO0_L01N IO0_L02P IO0_L02N/VREF IO0_L03P IO0_L03N VCCAUX IO0_L04P IO0_L04N/VREF IP VCCINT IO0_L05P IO0_L05N GND IO0_L06P IO0_L06N VCCO0 IO0_L07P/GCLK4 IO0_L07N/GCLK5 IO0/VREF IO0_L08P/GCLK6 IO0_L08N/GCLK7 GND IO0_L09P/GCLK8 IO0_L09N/GCLK9 IO0_L10P/GCLK10 IO0_L10N/GCLK11 IO GND IO0_L11P IO0_L11N VCCO0 IO0_L12P IO0_L12N/VREF IP VCCAUX IO0_L13P IO0_L13N GND IO0_L14P IO0_L14N/VREF VCCO0 IO0_L15P IO0_L15N IP IO0_L16P IO0_L16N/HSWAP TDI GND LINT# LRESET# BLAST# LSERR# ADS# LHOLDA V2V5 LHOLD LINT# LR ESET# BLAST# LS ERR# ADS# LHOLDA X1 V3V3 SPXO018044 1 3 1 3 C93 100NF/50V 0603 Y5V_LF 15PF/50V 0603 5%_LF Schematics User manual ISP1763A PCI evaluation board UM0865 C6 C9 C10 C11 C12 10NF /50V 0603 10%_LF 10NF /50V 0603 10%_LF 10NF /50V 0603 10%_LF TRST +12V TMS TDI +5V INTA INTC +5V RESERVED VIO RESERVED C13 10NF /50V 0603 10%_LF C16 V3V3 C15 10NF /50V 0603 10%_LF C17 C18 C19 C20 C21 V3V3 10NF /50V 0603 10%_LF C22 C23 C24 V3V3 1 AD28 2 AD27 3 AD26 4 AD25 5 C/BE3# 6 7 IDSEL 8 AD24 AD23 9 10 AD22 11 AD21 12 AD20 13 AD19 14 AD18 15 AD17 C/BE2# 16 FRAME# 17 IRDY# 18 GND 19 V3V3 20 TRDY# 21 DEVSEL#22 STOP# 23 LOCK# 24 PERR# 25 SERR# 26 27 GND 28 V3V3 29 PAR C/BE1# 30 31 AD16 32 AD15 33 AD14 34 AD13 35 V3V3 36 AD12 37 AD11 38 AD10 39 AD9 40 AD8 C/BE0# 41 42 AD7 43 AD6 GND 44 10NF /50V 0603 10%_LF C25 C26 10NF /50V 0603 10%_LF C27 C28 10NF /50V 0603 10%_LF C29 C30 10NF /50V 0603 10%_LF V3V3 V3V3 V3V3 R34 10K LCLK R35 10K 10NF /50V 0603 10%_LF V3V3_PCI V3V3_PCI V3V3_PCI V3V3_PCI V3V3_PCI V3V3 TPGNT#1 V5V0_PCI V5V0_PCI 10NF /50V 0603 10%_LF C/BE0# AD13 AD11 GND AD9 GND PAR AD15 FRAME# GND TRDY# GND STOP# AD22 AD20 GND AD18 AD16 AD28 AD26 GND AD24 IDSEL GNT# GND PME# AD30 RST# INTA# C14 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 V3V3_PCI VDD AD28 AD27 AD26 AD25 C/BE3 IDSEL AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 C/BE2 FRAME IRDY VSS VDD TRDY DEVSEL STOP LOCK PERR SERR VSS VDD PAR C/BE1 AD16 AD15 AD14 AD13 VDD AD12 AD11 AD10 AD9 AD8 C/BE0 AD7 AD6 VSS C32 100PF/50V 0603 5%_LF V3V3 DNM R38 0R V3V3 V3V3 V3V3 V3V3V3V3 V3V3 LREADY# 10K C7 C8 -12V TCK GND TDO +5V +5V INTB INTD PRSNT1 RESERVED PRSNT2 3V3_AUX RST VIO GNT GND PME AD30 3V3 AD28 AD26 GND AD24 IDSEL 3V3 AD22 AD20 GND AD18 AD16 3V3 FRAME GND TRDY GND STOP 3V3 RESERVED RESERVED GND PAR AD15 3V3 AD13 AD11 GND AD9 CON1 RESERVED GND CLK GND REQ VIO AD31 AD29 GND AD27 AD25 3V3 C/BE3 AD23 GND AD21 AD19 3V3 AD17 C/BE2 GND IRDY 3V3 DEVSEL GND LOCK PERR 3V3 SERR 3V3 C/BE1 AD14 GND AD12 AD10 M66EN AD6 AD4 GND AD2 AD0 100nF/50V C5 1K B14 GND B15 PCICLK B16 B17 GND REQ# B18 B19 B20 AD31 B21 AD29 B22 GND B23 AD27 B24 AD25 B25 C/BE3# B26 B27 AD23 B28 GND AD21 B29 B30 AD19 B31 B32 AD17 C/BE2# B33 B34 GND B35 IRDY# B36 DEVSEL# B37 B38 GND LOCK# B39 B40 PERR# B41 SERR# B42 B43 C/BE1# B44 B45 AD14 B46 GND AD12 B47 AD10 B48 B49 AD8 AD7 100nF/50V C3 R26 R25 C4 10nF/50V B1 B2 B3 B4 B5 V5V0_PCI B6 B7 B8 B9 B10 1K B11 V3V3_PCI V3V3_PCI V3V3_PCI V3V3_PCI V3V3_PCI V3V3_PCI 100nF/50V C1 C2 10nF/50V TPREQ#1 100nF/50V AD5 AD3 GND AD1 V5V0_PCI R40 10K R41 V3V3 V3V3 V3V3 V3V3 VSS LD31 LD30 LD29 LD28 LD27 LD26 LD25 LD24 LD23 LD22 LD21 LD20 LD19 LD18 LD17 VDD VSS LD16 LD15 LD14 LD13 LD12 VDD VSS LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 VDD LD3 LD2 LD1 LD0 LA31 LA30 TSIZ0 TSIZ1 RD/WR VDD EECS EESK EEDI 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 U2 PCI9054 V3V3 GND GND V3V3 10K LD15 LD14 LD13 LD12 V3V3 GND LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 V3V3 LD3 LD2 LD1 LD0 LA31 LA30 TSIZ0 TSIZ1 LW/R# V3V3 1 2 3 4 VCC NC ORG GND U1 u93LC56C CS SK DI DO V3V3 V3V3 V3V3 TSIZ0 TSIZ1 LW/R# V3V3 8 7 R20 6 R21 5 V3V3 10K 10K V3V3 V3V3 V3V3 V3V3 C31 R45 0R 0.1u F MH2 MECHOLE R46 0R LHOLD LHOLDA LREADY# LA31 LA30 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LRESET# LINT# LSERR# 39 40 41 42 43 J1 DNM 767130-1 LHOLD LHOLDA LREADY# LRESET# LINT# LSERR# LA31 LA30 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 Adapter board pin number 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 0R LA19 LA19 0R LA18 LA18 0R LA17 LA17 0R LA16 LA16 LHOLD LHOLD LHOLDA LHOLDA LREADY# LREADY# LRESET# LRESET# LINT# LINT# LSERR# LSERR# LA31 LA30 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA31 LA30 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LW/R# ADS# BLAST# LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD8 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 R1 R2 DNM R3 DNM R24 DNM 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 Female socket to attach test probe MH1 MECHOLE LW/R# 1 1 LW/R# ADS# 3 ADS# 2 BLAST# 5 BLAST# 3 7 LD0 LD0 4 9 LD1 LD1 5 11 LD2 LD2 6 13 LD3 LD3 7 15 LD4 LD4 8 17 LD5 LD5 9 19 LD6 LD6 10 21 LD7 LD7 11 LD8 23 LD8 12 LD9 25 LD9 13 LD10 27 LD10 14 LD11 29 LD11 15 LD12 31 LD12 16 LD13 33 LD13 17 LD14 35 LD14 18 LD15 37 LD15 19 Adapter board pin number V3V3 V3V3 V3V3 V3V3 V3V3 LA[31.. 16] LW/R# ADS# BLAST# LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 (c) Copyright ST-Ericsson, 2010. All rights reserved. 100nF/50V A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 10K 10K 100nF/50V C/BE0 3V3 AD6 AD4 GND AD2 AD0 VIO REQ64 +5V +5V 0R Rev 2 10K R33 LW/R # 100nF/50V 1K 1K 1K 1K 22 (29) CD00257207 LHOLDA 10K 10K ISP1763A PCI 2010-04-05 Figure 17 10K R30 TS IZ1 R44 100nF/50V AD8 AD7 3V3 AD5 AD3 GND AD1 VIO ACK64 +5V +5V R39 note: TEST should be 0 1 LHOLD 10K 10nF/50V B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 V3V3 TEST 1 10K 10K R23 R28 R22 BLAST# R32 10K LR EADY# R31 10K LINT# R29 LS ERR# ADS# R27 R19 LS ERR# ADS# LHOLDA LHOLD LC LK 146 LSERR# 145 ADS# 144 LHOLDA 143 LHOLD 142 LCLK 141 V3V3 140 GND 139 R14 R15 138 R16 137 R17 136 135 LREADY# R18 134 133 V3V3 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 GND 100nF/50V TEST GND V3V3 100nF/50V V5V0_PCI DNM GND V3V3 100nF/50V x86 Mode 10K 10K R42 R43 TS IZ0 100nF/50V 176 GND 175 AD29 174 AD30 100nF/50V 173 AD31 172 REQ# 171 GNT# 170 PCICLK 100nF/50V 169 RST# 168 INTA# 167 PME# DACK0# 166 EEDI DACK0# DR EQ0# 165 EESK DR EQ0# 164 EECS R4 10K 163 162 V3V3 161 GND R5 10K 160 159 DACK0# R6 10K 158 DR EQ0# R7 10K R8 1K 157 R9 1K 156 155 TEST TEST 154 LINT# LINT# R10 10K 153 152 LRESET# LRESET# 151 R11 10K R12 10K 150 R13 510R 149 148 BLAST# BLAST# 147 V3V3 VS S AD29 AD30 AD31 REQ GNT PCLK RST INTA PME EEDI/EEDO EESK EECS BIGEND/WAIT VDD VS S CCS USERi/DACK0/LLOC Ki USERo/DREQo/LLOC Ko MODE1 MODE0 TEST LINT MDREQ/DMPAF/EOT LR ESETo BDIP BB/BREQi RETRY/BR EQo BURST/BLAST VDD TEA TS /ADS BG BR/LHOLD LCLK VDD VS S DP3 DP2 DP1 DP0 TA BI/BTERM VDD VDD AD5 AD4 AD3 AD2 AD1 AD0 ENUM LEDon/LEDin LA0 LA1 LA2 LA3 LA4 LA5 LA6 VS S VDD LA7 LA8 LA9 LA10 LA11 LA12 VS S VDD LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 VS S 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 V3V3 AD5 AD4 AD3 AD2 AD1 AD0 100nF/50V R36 1K R37 1K Schematics User manual ISP1763A PCI evaluation board UM0865 LD[15..0] + TP6 C120 10uF/25V V12V0_ext DNM V5V0 0R 100nF/50V V1V2 R141 33K C122 2 100nF/50V 1 3 5 4 C121 0R R140 + TP10 Vref=1.25v 2 4 R151 DNM TP11 U12 REF VL FB SHDN OUT + 3 VP DH CS DL GND IN C123 10 9 8 7 6 R142 10R 2 DL_P 100nF/50V OUT U16 LD1086D2T18TR MAX1791EUB+ V5V0 C129 10uF/25V V2V5 GND DL_P 1 2 3 4 TP12 U13 S1 G1 S2 G2 D1 D1 D2 D2 FDS8958A V1V8 C124 220uF/10V L1 CDRH104RNP-7R0NC + C130 10uF/25V + LED5 LED RED 0603_LF R147 3R 0603 1/10W 1%_LF 8 7 6 5 V5V0 100NF/50V 0603 10%_LF C125 TP7 C126 C133 22UF/25V 20% TAN-D_LF + 3 main power V5V0 IN JP7 V3V3 R150 0R + C134 10uF/25V R153 V3V3 1 2 3 0R R149 TP8 0R R145 0R R146 VIO VCC(IO)_Chip VCC(3V3)_Chip R148 0R V3V3_PCI DNM R154 33R 0603 1/16W 1%_LF LED7 LED GREEN 0603, SML312ECT Super Pure Green V3V3 R144 200R 0603 1/16W 1%_LF V5V0 TP13 LED4 LED BLUE 0603_LF +5V_usb_Chip 0R HEADER1X3_LF V1V8 2 PCI power V5V0_PCI OUT U17 LD1086D2T33TR V5V0 JP6 HEADER1X3_LF 1 2 3 Take care the orientation of this connector PS1 Vin GND OUT 2 C128 10uF/25V Vout Tab U14 LD1117S12TR IN U15 LD1086D2T25TR + LED6 LED YELLOW 0603_LF 100NF/50V 0603 10%_LF 1 PC5V R139 2 GND 3 GND 4 DP04PR 12V IN THE CENTRE AND GND ON THE SHEILD DC POWER SOCKET 2.5MM DIA PS2 3 PD1 BYG22D TP9 + 3 C132 10uF/25V (c) Copyright ST-Ericsson, 2010. All rights reserved. 1 2 3 DC POWER SOCKET 2.5MM DIA V5V0 + C127 10uF/25V V5V0 C131 10uF/25V R152 51R 0603 1/16W 1%_LF Rev 2 DNM 23 (29) CD00257207 GND 1 10K R143 240R 0603 1/8W 1%_LF ISP1763A Power 2010-04-05 Figure 18 GND 1 1 GND 1 Schematics User manual ISP1763A PCI evaluation board UM0865 ISP1763A PCI evaluation board User manual Schematics UM0865 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 DNM 2K 0603 1/10W 1%_LF ALE_1 R155 0R DREQ R156 R157 3K 0603 1/16W 1%_LF CN1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 BSQUARE PXA320 SRAM INTERFACE 3V3 3V3 D0_BUF D1_BUF D2_BUF D3_BUF D4_BUF D5_BUF D6_BUF D7_BUF D8_BUF D9_BUF D10_BUF D11_BUF D12_BUF D13_BUF D14_BUF D15_BUF NONMUX_A0_BUF NONMUX_A1_BUF NONMUX_A2_BUF NONMUX_A3_BUF A0_BUF A1_BUF A2_BUF A3_BUF A4_BUF A5_BUF A6_BUF A7_BUF A8_BUF A9_BUF A10_BUF A11_BUF A12_BUF A13_BUF A14_BUF A15_BUF A16_BUF A17_BUF A18_BUF A19_BUF A20_BUF A21_BUF A22_BUF A23_BUF A24_BUF TP27 3V3 3V3 SFM-150-02-S-D-A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FLASH_HDR_nCS2 FLASH_HDR_nCS3_63MB SCLK_BUF nLLA TP26 nBE0 nBE1 TP25 PC_BVD1 PC_nCD nXCVREN nPWAIT nIOIS16 RDnWR nPCE1 nPCE2 nPIOW ALE_nWE nPREG nPIOR CLE_nOE FLASH_HDR_nIRQ FLASH_HDR_RESET GPIO_OUT5 GPIO_IN5 I2C_SCL I2C_SDA PER_nRESET nRESET_OUT FLASH_HDR_RDY GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 VCC(IO)_Chip R160 DNM 0R R161 DNM 0R R163 R164 CS# R158 R159 10K 0R DACK# DNM ALE_1 DNM 0R 0R DNM R162 DNM 0R ALE NOR Flash WE# RD# R165 IRQ 0R RESET# DNM R166 R167 DNM 0R RESET# 0R RESET# DNM CONN, 0.50"SQ Shr ouded Header, SMT, 100pin. 0.465" BTB 1 3 5 7 9 11 13 15 17 19 21 23 ALE 25 27 29 31 WE# 33 35 37 39 D15 41 D13 43 D11 45 47 D9 49 D7 D5 51 53 55 D3 57 D1 CS# 59 DNM 0R 61 RESET# R168 63 65 67 69 DC1 DAVINCI DM357 NAND 2 1 2 4 3 4 6 5 6 8 7 8 10 9 10 12 11 12 14 13 14 16 15 16 18 17 18 20 19 20 22 21 22 24 CLE 23 24 26 25 26 28 27 28 30 29 30 32 31 32 34 RD# 33 34 36 IRQ 35 36 38 37 38 40 D14 39 40 42 D12 41 42 D10 44 43 44 46 45 46 D8 48 47 48 D6 50 49 50 D4 52 51 52 54 53 54 D2 56 55 56 D0 58 57 58 60 59 60 62 61 62 64 63 64 66 65 66 68 67 68 70 69 70 TFM-135-32-S-D-A INTERFACE Samtec connector CONN,SMT,VERTICAL,PLUG,35X2 T FM-135-32-S-D-A Figure 19 Connectors CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 24 (29) ISP1763A PCI evaluation board User manual List of materials UM0865 5 Table 7 List of materials List of materials Part type Designator Footprint Description 0 R80, R81, R83, R82, R77, R76, R79, R78, R93, R92, R95, R94, R85, R84, R91, R90, R75, R64, R63, R66, R65, R39, R38, R62, R61, R72, R71, R74, R73, R68, R67, R70, R69, R155, R148, R162, R158, R149, R146, R153, R150, R167, R166, R160, R168, R164, R161, R165, R163, R145, R89, R88, R123, R109, R97, R96, R98, R99, R138, R126, R140, R139, R133, R124, R132, R134, R3, R2, R1, R45, R46, R24 R0603 Resistor SMD 0603 1/16W 1% 0 , lead free 1 k R25, R37, R26, R9, R8, R14, R15, R16, R36, R17 R0603 Resistor SMD 0603 1/10W 1% 1 k lead free 2 k R156 R0603 Resistor SMD 0603 1/10W 1% 2 k, lead free 3 k R157 R0603 Resistor SMD 0603 1/16W 1% 3 k, lead free 3 R147 R0603 Resistor SMD 0603 1/10W 1% 3 , lead free 4.7 k R107, R110, R106, R101 R0603 Resistor SMD 0603 1/10W 1% 4K7 lead free 4.7 F C108, C112 TAN SMD-A Capacitor tan SMD-A 4u7F/10 V +/-20%, lead free 4.7 F C96, C97 C0603 Capacitor SMD 0603 4u7F/10 V Y5V +80%-20%, lead free 4.7 F C117 ELE SMD-B Capacitor Ele SMD-B 4u7F/35 V +/-20%, lead free 10 k R59, R60, R57, R56, R58, R43, R118, R44, R130, R49, R47, R117, R55, R111, R42, R121, R113, R50, R114, R112, R52, R53, R54, R51, R119, R122, R120, R6, R7, R143, R5, R12, R135, R10, R11, R41, R40, R34, R35, R159, R48, R4, R22, R32, R27, R28, R29, R131, R33, R127, R30, R18, R19, R129, R128, R23, R31, R20, R21 C0603 Resistor SMD 0603 1/16W 1% 10 k lead free 10 nF C80, C75, C70, C104, C42, C37, C65, C45, C40, C35, C60, C55, C50, C102, C82, C77, C72, C106, C98, C100,C52, C47, C57, C67, C62, C24, C12, C14, C26, C10, C30, C28, C8, C4, C2,C22, C20, C6, C16, C18 C0603 Capacitor SMD 0603 10 nF/50 V 10% X7R CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 25 (29) ISP1763A PCI evaluation board User manual List of materials UM0865 Part type Designator Footprint Description 10 R147 C0603 Resistor SMD 0603 1/16W 1% 10 , lead free 10 F C128, C130, C120, C127, C129, C134, C132, C131 ELE SMD-B Capacitor Ele SMD-B 10uF/25 V +/-20%, lead free 12 k R115, R116 C0603 Resistor SMD 0603 1/16W 1% 12 k, lead free 15 pF C94 C0603 Capacitor SMD 0603 15 pF/50 V 5%, lead free 18 pF C110, C111 C0603 Capacitor SMD 0603 18 pF / 50 V 5% 22 R86, R87 C0603 Resistor SMD 0603 1/16W 1% 22 , lead free 22 F C133 TAN SMD-D Capacitor tan SMD-D 22 F/25 V +/-20%, lead free 33 k R141 C0603 Resistor SMD 0603 1/16W 1% 33 k, lead free 33 R154 C0603 Resistor SMD 0603 1/16W 1% 33 lead free 51 R152 C0603 Resistor SMD 0603 1/16W 1% 51 , lead free 68 R100 C0603 Resistor SMD 0603 1/16W 1% 68 100 k R136 C0603 Resistor SMD 0603 1/10W 1% 100 k lead free 100 nF C61, C23, C51, C21, C15, C56, C66, C49, C59, C76, C58, C71, C68, C63, C46, C19, C34, C44, C36, C64, C41, C39, C11, C73, C69, C74, C13, C78, C79, C33, C38, C5, C7, C48, C53, C9, C43, C17, C54, C25, C31, C29, C3, C1, C27, C95, C81, C87, C88, C83, C85, C86, C92, C84, C93, C89, C90, C91 C0603 Capacitor SMD 0603 100 nF/50 V +80-20%, lead free 100 nF C126, C125, C121, C122, C115, C118, C101, C103, C107, C99, C105, C123, C116, C113, C109 C0603 Capacitor SMD 0603 100 nF/50 V 10%, lead free 100 pF C32 C0603 Capacitor SMD 0603 100 pF/50 V 5% NPO 100 R103, R102, R105, R104 C0603 Resistor SMD 0603 1/10W 1% 100 lead free 100 F C114 ELE SMD-D Capacitor Ele SMD-D 100 F/16 V 20%, lead free 120 R108 C0603 Resistor SMD 0603 1/10W 1% 120 lead free 200 R144 C0603 Resistor SMD 0603 1/16W 1% 200 , lead free 220 F C124 ELE SMD-E Capacitor Ele SMD 220 F/10 V FK series, low ESR, +/-20%, lead free CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 26 (29) ISP1763A PCI evaluation board User manual List of materials UM0865 Part type Designator Footprint Description 240 R151 C0603 Resistor SMD 0603 1/8W 1% 240 , lead free 510 R13 C0603 Resistor SMD 0603 1/10W 1% 510 lead free 560 R125, R137 C0603 Resistor SMD 0603 1/16W 1% 560 , lead free 767130-1 J1 767130-1 Connector recept 38Pos 0.025CL 767130-1 B3S-1000 SW1 B3S-1000 Switch tact SMD 6 mm x 6 mm white BLM31A260S FB1, FB2 R1206 Murata ferrite bead, 1206 case, 0.05 DC resistance CDRH104RNP7R0NC L1 CDRH104RNP Inductor SMD 7 H/4.5 A DR1040-7R0-R CS10 12.000MABJ- X2 UT CS10 Crystal 12 MHz 6 x 3.5 mm CS10-12.000MABJ-UT DC power socket 2.5 mm DIA PS2 DC power socket Socket DC jack 2.5 mm PCB Mt DP04PR PS1 DP04PR Power disk drive RA 4-way FD2X20_LF J2 FD2X20 Connector PCB Mt 0.100" 2 x 20-way FDS8958A U13 SOIC-8_4 x 5 mm Transistor FDS8958A NP SO8 Header1 x 2_LF JP2, JP4, JP5 Header1 x 2 Header pin 0.100" 1 x 2-way gold, lead free Header1 x 3_LF JP1, JP6, JP7 Header1 x 3 Header pin 0.100" 1 x 3-way gold, lead free Header1 x 6_LF JP3 Header1 x 6 Header pin 0.100" 1 x 6-way gold, lead free Header2 x 8_LF J3, J4, J5, J6 Header2 x 8 Header pin 0.100" 2 x 8-way gold, lead free ISP1763 VFQFPN U6 VFQFPN-64 - LD1086D2T18TR U16 D2PAK IC reg LDO POS 1.8 V 1.5 A D2PAK LD1086D2T25TR U15 D2PAK IC reg LDO POS 2.5 V 1.5 A D2PAK LD1086D2T33TR U17 D2PAK IC reg LDO positive 3.3 V D2PAK LD1117S12TR U14 SOT-223 IC reg LDO POS 800MA 1.2 V SOT223 LED blue 0603_LF LED4 LED0603 LED blue 0603 LED green 0603, SML312ECT LED7 LED0603 Chip LED, green, SMD, 0603 package, 0.8 x 1.6 x 0.8 mm LED orange 0603_LF LED1 LED0603 LED orange 0603 LED red 3MM_LF LED2, LED3 LED3mm LED 3 mm red diffused LED red 0603_LF LED5 LED0603 LED red 0603 CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 27 (29) ISP1763A PCI evaluation board User manual List of materials UM0865 Part type Designator Footprint Description LED yellow 0603_LF LED6 LED0603 LED yellow 0603 MAX1791EUB+ U12 MSOP-10_3 x 3 mm IC MAX1791EUB+ MIC2026-2 U8 SOIC-8_4 x 5 mm IC MIC2026-2YM PCI9054 U2 F-QFP176/P.5N - SFM-150-02-S-D-A CN1 SFM-150-02-S-D-A Connector SMT 0.5" 2x50 SFM-150-02-S-D-A SMB PCB VERT S1 SMB SMB jack 50 PCB Mt ST SN74LVT244BPW U4 TSSOP20_4.4 x 6.5 mm IC 74LVT244BPW 20-TSSOP SPXO018044 X1 SPXO018044 Oscillator 50.000 MHz HCMOS 3.3 V 1/2 size Test point 1.8 TPREQ#1, TPGNT#1, TP11, TP12, TP13, TP10, TP7, TP6, TP9, TP4, TP1, TP2, TP3, TP8, TP5 TP18 Test point TFM-135-32-S-D-A DC1 TFM-135-32-S-D-A Samtec connector SMT, vertical, plug, 35 x 2, TFM135-32-S-D-A USB con type A receptacle S2 USB_A USB type A RA 4-way 875200010B USBULC6-2F3 U7, U9, U10, U11 USBULC6-2F3 ESD protection diode USB_AB_MICRO S3 USB micro type AB Micro USB type AB SMD R/A ZX62-AB-5P XC3S500E U3 PQ208 IC Spartan XC3S500E4PQG208C PQFP XCF04S U5 TSSOP20_4.4 x 6.5 mm IC programmable XCF04SVOG20C 20-TSSOP u93LC56C U1 DIP8 IC 93LC56C-I/P, EEPROM DIP-8, lead free CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 28 (29) ISP1763A PCI evaluation board User manual Glossary UM0865 Glossary EEPROM Electrically Erasable Programmable Read-Only Memory FPGA Field-Programmable Gate Array NAND Not AND NOR Nor OR OS Operating System OTG On-The-Go PCI Peripheral Component Interconnect PIO Parallel Input/Output RAM Random-Access Memory SRAM Static Random Access Memory USB Universal Serial Bus CD00257207 Rev 2 2010-04-05 (c) Copyright ST-Ericsson, 2010. All rights reserved. ISP1763A 29 (29)