G2R-1-SNDI 24DC - OMRON - Datasheet.Support

BU4209G

TSZ02201-0R7R0G300050-1-2

TSZ22111･14･001 1/12

08.Aug.2012 Rev.004

Datasheet

Voltage Detector IC Series

Low Volt age Free Delay T ime Setting

CMOS Voltage Detector IC Series

BU42xx series BU43xx series

●General Description

ROHM CMOS reset IC series with adjustable output

delay is a high-accuracy low current consumption reset

IC series with a built-in delay circuit. The lineup was

established with two output types (Nch open drain and

CMOS output) and detection voltages range from 0.9V to

4.8V in increments of 0.1V, so that the series may be

selected according to the application at hand.

●Features

 Free delay time setting by external capacitor

 Two output types (Nch open drain and CMOS output)

 Ultra-low current consumption

 Wide operating temperature range

 Very small and low height package

 Package SSOP5 and SOP4 is similar to SOT-23-5

and SC-82 respectively (JEDEC)

●Key Specifications

 Detection voltage: 0.9V to 4.8V (Typ.)

0.1V steps

 High accuracy detection voltage: ±1.0%

 Ultra-low current consumption: 0.55µA (Typ.)

 Operating temperature range: -40°C to +125°C

●Package

SSOP5: 2.90mm x 2.80mm x 1.15mm

SOP4: 2.00mm x 2.10mm x 0.95mm

VSOF5: 1.60mm x 1.60mm x 0.60mm

●Applications

All electronic devices that use micro controllers and logic

circuits

●Typical A pplication Circuit

●Connection Diagram & Pin Descriptions

SSOP5 SOP4 VSOF5

No. Symbol Function PIN

No. Symbol Function

1 VOUT Reset output 1 GND GND 1 VOUT Reset output

2 VDD Power supply voltage 2 VDD Power supply voltage 2 SUB Substrate*

3 GND GND

3 CT

Capacitor connection

terminal for output

delay time

3 CT

Capacitor connection

terminal for output

delay time

4 N.C. Unconnected terminal 4 VOUT Reset output 4 VDD Power supply voltage

5 CT

Capacitor connection

terminal for output

delay time

5 GND GND

VDD1

BU42xx

VDD2

GND

(Capacitor for

noise filtering)

CIN

RST Micro

controller

Open Drain Output type

BU42xx series

VDD1

BU43xx

CIN

GND

(Capacitor for

noise filtering)

RST Micro

controller

CMOS Output type

BU43xx series

TOP VIEW TOP VIEW TOP VIEW

*Connect the substrate to VDD

GND VDD

CTVOUT

1 2

3 4

Marking Lot. No

○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays.

VOUT VDD GND

N.C.

Lot. No

Marking

VDD

VOUT SUB CT

GND

Marking Lot. No

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 2/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

●Ordering Information

●Lineup

Making Detection

voltage

Part

Number Making Detection

voltage

Part

Number Making Detection

voltage

Part

Number Making Detection

voltage

Part

Number

ZR 4.8V BU4248 YV 2.8V BU4228 1H 4.8V BU4348 0M 2.8V BU4328

ZQ 4.7V BU4247 YU 2.7V BU4227 1G 4.7V BU4347 0L 2.7V BU4327

ZP 4.6V BU4246 YT 2.6V BU4226 1F 4.6V BU4346 0K 2.6V BU4326

ZN 4.5V BU4245 YS 2.5V BU4225 1E 4.5V BU4345 0J 2.5V BU4325

ZM 4.4V BU4244 YR 2.4V BU4224 1D 4.4V BU4344 0H 2.4V BU4324

ZL 4.3V BU4243 YQ 2.3V BU4223 1C 4.3V BU4343 0G 2.3V BU4323

ZK 4.2V BU4242 YP 2.2V BU4222 1B 4.2V BU4342 0F 2.2V BU4322

ZJ 4.1V BU4241 YN 2.1V BU4221 1A 4.1V BU4341 0E 2.1V BU4321

ZH 4.0V BU4240 YM 2.0V BU4220 0Z 4.0V BU4340 0D 2.0V BU4320

ZG 3.9V BU4239 YL 1.9V BU4219 0Y 3.9V BU4339 0C 1.9V BU4319

ZF 3.8V BU4238 YK 1.8V BU4218 0X 3.8V BU4338 0B 1.8V BU4318

ZE 3.7V BU4237 YJ 1.7V BU4217 0W 3.7V BU4337 0A 1.7V BU4317

ZD 3.6V BU4236 YH 1.6V BU4216 0V 3.6V BU4336 ZZ 1.6V BU4316

ZC 3.5V BU4235 YG 1.5V BU4215 0U 3.5V BU4335 ZY 1.5V BU4315

ZB 3.4V BU4234 YF 1.4V BU4214 0T 3.4V BU4334 ZX 1.4V BU4314

ZA 3.3V BU4233 YE 1.3V BU4213 0S 3.3V BU4333 ZW 1.3V BU4313

YZ 3.2V BU4232 YD 1.2V BU4212 0R 3.2V BU4332 ZV 1.2V BU4312

YY 3.1V BU4231 YC 1.1V BU4211 0Q 3.1V BU4331 ZU 1.1V BU4311

YX 3.0V BU4230 YB 1.0V BU4210 0P 3.0V BU4330 ZT 1.0V BU4310

YW 2.9V BU4229 YA 0.9V BU4209 0N 2.9V BU4329 ZS 0.9V BU4309

(Unit : mm)

SOP4

2.1±0.2

0.05

1.3

2.0±0.2

1.25 +0.2

–0.1

4°+6°

0.27±0.15

–4°

0.13 +0.05

–0.03

0.9±0.050.05±0.05

1.05Max.

0.32 +0.05

–0.04

0.42 +0.05

–0.04

0.1 S

(Unit : mm)

VSOF5

1.2±0.05

1.0±0.05

0.6MAX

0.22±0.05

0.5

1.6±0.05

0.13±0.05

0.2MAX

1.6±0.05

(MAX 1.28 include BURR)

(Unit : mm)

SSOP5

2.9±0.2

0.13

4°+6°

−4°

1.6

2.8±0.2

1.1±0.05

0.05±0.05

+0.2

−0.1

+0.05

−0.03

0.42+0.05

−0.04

0.95

123

1.25Max.

0.2Min.

0.1

Direction of feed

Reel

∗

Order quantity needs to be multiple of the minimum quantity.

Embossed carrier tapeTape

Quantity

Direction

of feed

The direction is the 1pin of product is at the upper right when you hold

reel on the left hand and you pull out the tape on the right hand

3000pcs

()

1pin

BUxxxx x-TR

Part Output Type Reset Voltage Value Package Packageing and

Number 42 : Open Drain 09 : 0.9V G : SSOP5 forming specification

43 : CMOS 0.1V step F : SOP4 TR : Embossed tape

48 : 4.8V FVE : VSOF5 and reel

(SOT-23-5)

(SC-82)

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 3/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

●Absolute Maximum Ratings (Ta=25°C)

Parameter Symbol Limit Unit

Power Supply Voltage VDD -0.3 to +7 V

Output Voltage Nch Open Drain Output VOUT GND-0.3 to +7 V

CMOS Output GND-0.3 to VDD+0.3

Power

Dissipation

SSOP5(SOT-23-5) *1*4

540

SOP4(SC-82) *2*4 400

VSOF5 *3*4 210

Operation Temperature Range Topt -40 to +125 °C

Ambient Storage Temperature Tstg -55 to +125 °C

*1 When used at temperatures higher than Ta=25°C, the power is reduced by 5.4mW per 1°C above 25°C.

*2 When used at temperatures higher than Ta=25°C, the power is reduced by 4.0mW per 1°C above 25°C.

*3 When used at temperatures higher than Ta=25°C, the power is reduced by 2.1mW per 1°C above 25°C.

*4 When a ROHM standard circuit board (70mm×70mm×1.6mm, glass epoxy board)is mounted.

●Electrical Characteristics (Un l ess Otherwise Specified Ta=-25 to 125°C)

Parameter Symbol Condition Limit Unit

Min. Typ. Max.

Detection Voltage VDET VDD=HÆL, Ta=25°C, RL=470kΩ

VDET(T)

×0.99 VDET(T) VDET(T)

×1.01 V

Circuit Current when ON IDD1 VDD=VDET-0.2V

VDET =0.9 to 1.3V - 0.15 0.88

µA

VDET =1.4 TO 2.1V - 0.20 1.05

VDET =2.2 TO 2.7V - 0.25 1.23

VDET =2.8 to 3.3V - 0.30 1.40

VDET =3.4 to 4.2V - 0.35 1.58

VDET =4.3 to 4.8V - 0.40 1.75

Circuit Current when OFF IDD2 VDD=VDET+2.0V

VDET =0.9 TO 1.3V - 0.30 1.40

µA

VDET =1.4 TO 2.1V - 0.35 1.58

VDET =2.2 to 2.7V - 0.40 1.75

VDET =2.8 to 3.3V - 0.45 1.93

VDET =3.4 to 4.2V - 0.50 2.10

VDET =4.3 to 4.8V - 0.55 2.28

Operating Voltage Range VOPL VOL≤0.4V, Ta=25 to 125°C, RL=470kΩ 0.70 - -

VOL≤0.4V, Ta=-40 to 25°C, RL=470kΩ 0.90 - -

‘High’ Output Current (Pch) IOH VDS=0.5V VDD=6.0V VDET=4.0 to 4.8V 2.0 4.0 - mA

‘Low’ Output Current (Nch) IOL

VDS=0.05V VDD=0.85V 20 100 - µA

VDS=0.5V VDD=1.5V VDET=1.7 to 4.8V 1.0 3.3 - mA

VDS=0.5V VDD=2.4V VDET=2.7 to 4.8V 3.6 6.5 -

Leak Current when OFF Ileak VDD=VDS=7V Ta=-40 to 85°C - 0 0.1 µA

VDD=VDS=7V Ta=85 to 125°C - 0 1

‘High’ Output Current (Pch) IOH VDS=0.5V VDD=4.8V VDET=0.9 to 3.9V 1.7 3.4 - mA

VDS=0.5V VDD=6.0V VDET=4.0 to 4.8V 2.0 4.0 -

CT pin Threshold Voltage VCTH

VDD=VDET×1.1, VDET=0.9 to 2.5V Ta=25°C

RL=470kΩ

VDD

×0.35

VDD

×0.45

VDD

×0.55 V

VDD=VDET×1.1, VDET=2.6 to 4.8V Ta=25°C

RL=470kΩ

VDD

×0.40

VDD

×0.50

VDD

×0.60

Output Delay Resistance RCT VDD=VDET×1.1 VCT=0.5V Ta=25°C *1 9 10 11 MΩ

CT pin Output Current ICT VCT=0.1V VDD=0.85V 5 40 - µA

VCT=0.5V VDD=1.5V VDET=1.7 to 4.8V 200 400 -

Detection Voltage

Temperature coefficient VDET/∆T Ta=-40°C to 125°C - ±30 - ppm/°C

Hysteresis Voltage ∆VDET

VDD=LÆHÆL

Ta=-40 to 125°C

RL=470kΩ

VDET≤1.0V VDET

×0.03

VDET

×0.05

VDET

×0.08 V

VDET≥1.1V VDET

×0.03

VDET

×0.05

VDET

×0.07

*1: Designed guarantee. (Outgoing inspection is not done all products.)

VDET(T) : Standard Detection Voltage(0.9V to 4.8V, 0.1V step)

RL: Pull-up resistor to be connected between VOUT and power supply.

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 4/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

●Block Diagrams

Vref

VOUT

VDD

GND CT

Fig.1 BU42xx Series

Vref

VOUT

VDD

GND CT

Fig.2 BU43xx Series

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 5/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

●Typical Performan ce Curves

Fig.3 Circuit Current

0.0

0.1

0.2

0.3

0.4

0.5

0.6

01 23 45 67

VDD SUPPLY VOLTAGE ：VDD[V]

CIRCUIT CURRENT ： IDD [μA]

0.0 0.5 1.0 1.5 2.0 2.5

DRAIN-SOURCE VOLTAGE ： VDS

[V]

"LOW" OUTPUT CURRENT ： IOL[mA]

VDD=1.2

【BU4216F】

Fig.4 “LOW” Output Current

0123456

DRAIN-SOURCE VOLTAGE ： VDS

[V]

"HIGH" OUTPUT CURRENT ： IOH[mA]

【BU4318G】

VDD=6.0V

VDD=4.8V

Fig.5 “High” Output Current Fig.6 I/O Characteristics

01234567

VDD SUPPLY VOLTAGE ：VDD[V]

OUTPUT VOLTAGE

　： VOUT [V]

【BU4216F】

【BU4216】

【BU4316】

【BU4318】【BU4216】

【BU4316】

【BU4216】

【BU4316】

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 6/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

0.0

0.1

0.2

0.3

0.4

0.5

-40 0 40 80 120

TEMPERATURE ： Ta[℃]

CIRCUIT CURRENT WHEN ON ： IDD1 [μA]

【BU4216F】

Fig.10 Circuit Current when ON

Fig.9 Detecting Voltage

Release Voltage

1.0

1.5

2.0

-40 0 40 80 120

TEMPERATURE ： Ta[℃]

DETECTION VOLTAGE

　： VDET[V]

Low to hi g h(VDET+ΔVDET)

High to low(VDET)

【BU4216F】

0.0

0.2

0.4

0.6

0.8

1.0

0.0 0.5 1.0 1.5 2.0 2.5

VDD SUPPLY VOLTAGE ： VDD[V]

OUTPUT VOLTAGE

　： VOUT[V]

【BU4216F】

Fig.7 Operating Limit Voltage

100

200

300

400

500

600

700

00.5 11.5 22.5

VDD SUPPLY VOLTAGE ： VDD[V]

CT OUTPUT CURRENT ： ICT[μA]

【BU4216F】

Fig.8 CT Terminal Current

【BU4216】

【BU4316】

【BU4216】

【BU4316】

【BU4216】

【BU4316】

【BU4216】

【BU4316】

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 7/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

0.0

0.5

1.0

-40 0 40 80 120

TEMPERATURE ： Ta[℃]

MINIMUM OPERATING VOLTAGE ： VOPL[V]

【BU4216F】

Fig.12 Operating Limit Voltage

-40 0 40 80 120

TEMPERATURE ： Ta[℃]

RESISTANCE OF CT ： RCT[MΩ]

【BU4216F】

Fig.13 CT Terminal Circuit Resistance

0.001

0.01

0.1

100

1000

10000

0.0001 0.001 0.01 0.1

CAPACITANCE OF CT ： CCT[μF]

DELAY TIME ： TPLH[ms]

【BU4216F】

Fig.14 Delay Time (tPLH) and CT Terminal External Capacitance

0.0

0.2

0.4

0.6

0.8

1.0

-40 0 40 80 120

TEMPERATURE ： Ta[℃]

CIRCUIT CURRENT WHEN OFF ： IDD2 [μA]

【BU4216F】

Fig.11 Circuit Current when OFF

【BU4216】

【BU4316】

【BU4216】

【BU4316】

【BU4216】

【BU4316】

【BU4216】

【BU4316】

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 8/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

●Applic at ion Informa tion

Explanation of Operation

For both the open drain type(Fig.15)and the CMOS output type(Fig.16), the detection and release voltages are used as

threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VouT terminal

voltage switches from either “High” to “Low” or from “Low” to “High”. BU42xx and BU43xx series have delay time function

which set tPLH (Output “Low”Æ”High”) using an external capacitor (CCT). Because the BU42xx series uses an open drain

output type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage (VOUT) in

this case becomes VDD or the voltage of the other power supply].

Fig.15 BU42xx type internal block diagram Fig.16 BU43xx type internal block diagram

Setting of Detector Delay Time

This detector IC can be set delay time at the rise of VDD by the capacitor connected to CT terminal.

Delay time at the rise of VDD t

PLH:Time until when VouT rise to 1/2 of VDD after VDD rise up and beyond the release

voltage(VDET+∆VDET)

TPLH=-1×CCT×RCT×ln

CCT: CT pin Externally Attached Capacitance VCTH: CT pin Threshold Voltage(P.3 VCTH refer.)

RCT: CT pin Internal Impedance(P.3 RCT refer.) ln: Natural Logarithm

Reference Data of Falling Time (tPHL) Output

Examples of Falling Time (tPHL) Output

Part Number tPHL [µs]

BU4245 275.7

BU4345 359.3

* This data is for reference only.

The figures will vary with the application, so please confirm actual operating conditions before use.

Timing Wa veforms

Example: the following shows the relationship between the input voltage VDD, the CT Terminal Voltage VCT and the output

voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in

Fig.15 and 16).

① When the power supply is turned on, the output is unsettled from

after over the operating limit voltage (VOPL) until tPHL. There fore it is

possible that the reset signal is not outputted when the rise time of

VDD is faster than tPHL.

② When VDD is greater than VOPL but less than the reset release

voltage (VDET+∆VDET), the CT terminal (VCT) and output (VOUT)

voltages will switch to L.

③ If VDD exceeds the reset release voltage (VDET+VDET), then VOUT

switches from L to H (with a delay to the CT terminal).

④ If VDD drops below the detection voltage (VDET) when the power

supply is powered down or when there is a power supply fluctuation,

VOUT switches to L (with a delay of tPHL).

⑤ The potential difference between the detection voltage and the

release voltage is known as the hysteresis width (VDET). The system

is designed such that the output does not flip-flop with power supply

fluctuations within this hysteresis width, preventing malfunctions due

to noise.

Vref

VDD

GND

VOUT

RESET

VDD

Vref

VDD

GND

VOUT

RESET

VDD

VDD-VCTH

VDD

VDET+ΔVDET

VDET

VOPL

1/2 VDD

tPHL

①

tPLH

tPHL

tPLH

② ③ ④

⑤

VCT

VOUT

Fig.17 Timing Waveforms

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 9/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

●Circuit Applic ations

1) Examples of a common power supply detection reset circuit

Application examples of BU42xx series

(Open Drain output type) and BU43xx series

(CMOS output type) are shown below.

CASE1:The power supply of the microcontroller (VDD2)

differs from the power supply of the reset detection

(VDD1).

Use the Open Drain Output Type (BU42xx series)

attached a load resistance (RL) between the output and

VDD2. (As shown Fig.18)

CASE2:The power supply of the microcontroller (VDD1) is

same as the power supply of the reset detection (VDD1).

Use CMOS output type (BU43xx series) or Open Drain

Output Type (BU42xx series) attached a load

resistance (RL) between the output and VDD1.

(As shown Fig.19)

When a capacitance CL for noise filtering is connected to

the VouT pin (the reset signal input terminal of the

microcontroller), please take into account the waveform

of the rise and fall of the output voltage (VouT).

VDD1

BU43xx

CIN

GND

RST

(Capacitor for

noise filtering)

Micro

controller

Fig.19 CMOS Output type

VDD1

BU42xx

VDD2

GND

RST

(Capacitor for

noise filtering)

CIN

Micro

controller

Fig.18 Open Drain Output type

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 10/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

2) Examples of the power supply with resistor dividers

In applications where the power supply input terminal (VDD) of an IC with resistor dividers, it is possible that a through

current will momentarily flow into the circuit when the output logic switches, resulting in malfunctions (such as output

oscillatory state).

(Through-current is a current that momentarily flows from the power supply (VDD) to ground (GND) when the output level

switches from “High” to “Low” or vice versa.)

Fig.20

A voltage drop of [the through-current (I1)] × [input resistor (R2)] is caused by the through current, and the input voltage

to descends, when the output switches from “Low” to “High”. When the input voltage decreases and falls below the

detection voltage, the output voltage switches from “High” to “Low”. At this time, the through-current stops flowing through

output “Low”, and the voltage drop is eliminated. As a result, the output switches from “Low” to “High”, which again

causes the through current to flow and the voltage drop. This process is repeated, resulting in oscillation.

Consider the use of BD52xx when the power supply input it with resistor dividers.

Fig.21 Current Consumption vs. Power Supply Voltage

* This data is for reference only.

The figures will vary with the application, so please confirm actual operating conditions before use.

VOUT

BU42xx

BU43xx

GND

CIN

IDD

VDD

VDET

Through

Current

VDD - IDD Peak Current Ta=25°C

0.001

0.01

0.1

345678910

VDD[V]

IDD-peak[mA]

BU49xx,BU43xx

BU48xx,BU42xx

BD52xx

BD53xx

Temp - IDD(BU42xx)

0.0

0.5

1.0

1.5

2.0

2.5

-50 -30 -10 10 30 50 70 90 110 130

Temp

IDD peak Current[mA]

VDD3V

VDD6V

VDD7V

VDD4V

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 11/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

●Operational Notes

1. Absolute Maximum Range

Absolute Maximum Ratings are those values beyond which the life of a device may be destroyed. We cannot be defined

the failure mode, such as short mode or open mode. Therefore a physical security countermeasure, like fuse, is to be

given when a specific mode to be beyond absolute maximum ratings is considered.

2 . GND Potential

GND terminal should be a lowest voltage potential every state.

Please make sure all pins that are over ground even if include transient feature.

3 . Electrical Characteristics

Be sure to check the electrical characteristics, that are one the tentative specification will be changed by temperature,

supply voltage, and external circuit.

4 . Bypass Capacitor for Noise Rejection

Please put into the to reject noise between VDD pin and GND with 1uF over and between VOUT pin and GND with 1000pF.

If extremely big capacitor is used, transient response might be late. Please confirm sufficiently for the point.

5 . Short Circuit between Terminal and Soldering

Don’t short-circuit between Output pin and VDD pin, Output pin and GND pin, or VDD pin and GND pin. When soldering the

IC on circuit board please is unusually cautious about the orientation and the position of the IC. When the orientation is

mistaken the IC may be destroyed.

6 . Electromagnetic Field

Mal-function may happen when the device is used in the strong electromagnetic field.

7. The VDD line inpedance might cause oscillation because of the detection current.

8. A VDD -GND capacitor (as close connection as possible) should be used in high VDD line impedance condition.

9. Lower than the mininum input voltage makes the VOUT high impedance, and it must be VDD in pull up (VDD) condition.

10. Case of needless Delay time, recommended to insert more 470kΩ resister between VDD and CT.

Recommended value of RL Resistar is over 50kΩ (VDET=1.5 to 4.8V),over 100kΩ (VDET=0.9 to 1.4V).

11. This IC has extremely high impedance terminals. Small leak current due to the uncleanness of PCB surface might cause

unexpected operations. Application values in these conditions should be selected carefully. If 10MΩ leakage is assumed

between the CT terminal and the GND terminal, 1MΩ connection between the CT terminal and the VDD terminal would be

recommended. Also, if the leakage is assumed between the VOUT terminal and the GND terminal, the pull up resistor

should be less than 1/10 of the assumed leak resistance.

The value of RCT depends on the external resistor that is connected to CT terminal, so please consider the delay time that

is decided by τ × RCT × CCT changes.

12. Delay time (tPLH)

PLH = τ × RCT × CCT (sec)

τ: time constant

CT : 10MΩ (typ.) (built-in resistor)

CT : capacitor connected CT pin.

Recommended value of C

CT capacitor is over 100pF.

The reference value

(τ × RCT) ×106

DET = 0.9 to 2.5V

Ta = 25°C (min. = 5.1 × 10

6 typ.= 6.0 × 106 max = 6.9 × 106)

Ta = -25 to 125°C (min. = 3.3 × 10

6 typ. = 6.0 × 106 max = 8.7 × 106)

DET = 2.6 to 4.8V

Ta = 25°C (min. = 5.9 × 10

6 typ.= 6.9 × 106 max = 7.9 × 106)

Ta = -25 to 125°C (min. = 3.8 × 10

6 typ.= 6.9 × 106 max = 10.0 × 106)

13. External parameters

The recommended parameter range for CT is 100pF to 0.1µF. For RL, the recommended range is 50kΩ to 1MΩ. There

are many factors (board layout, etc) that can affect characteristics. Please verify and confirm using practical applications.

14. CT pin discharge

Due to the capabilities of the CT pin discharge transistor, the CT pin may not completely discharge when a short input

pulse is applied, and in this case the delay time may not be controlled. Please verify the actual operation.

15. Power on reset operation

Please note that the power on reset output varies with the VDD rise up time. Please verify the actual operation.

Datasheet

TSZ02201-0R7R0G300050-1-2

TSZ22111･15･001 12/12

08.Aug.2012 Rev.004

BU42xx series BU43xx series

16. Precautions for board inspection

Connecting low-impedance capacitors to run inspections with the board may produce stress on the IC.

Therefore, be certain to use proper discharge procedure before each process of the test operation.

To prevent electrostatic accumulation and discharge in the assembly process, thoroughly ground yourself and any

equipment that could sustain ESD damage, and continue observing ESD-prevention procedures in all handing, transfer

and storage operations. Before attempting to connect components to the test setup, make certain that the power supply is

OFF. Likewise, be sure the power supply is OFF before removing any component connected to the test setup.

17. When the power supply, is turned on because of in certain cases, momentary Rash-current flow into the IC at the logic

unsettled, the couple capacitance, GND pattern of width and leading line must be considered.

Status of this document

The Japanese version of this document is formal specification. A customer may use this translation version only for a reference

to help reading the formal version.

If there are any differences in translation version of this document formal version takes priority.

Datasheet

Notice - Rev.003

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Datasheet

Notice - Rev.003

●Precaution for Mounting / Circuit board design

1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

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For details, please refer to ROHM Mounting specification

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Datasheet

Notice - Rev.003

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