intel. 8255A/8255A-5 PROGRAMMABLE PERIPHERAL INTERFACE @ MCS-85 Compatible 8255A-5 wg Direct Bit Set/Reset Capability Easing m 24 Programmable I/O Pins Control Application Interface = Completely TTL Compatible m Reduces System Package Count ma Fully Compatible with Intel @ Improved DC Driving Capability Microprocessor Families @ Available in EXPRESS w Improved Timing Characteristics Standard Temperature Range Extended Temperature Range @ 40 Pin DIP Package (See Intel Packaging: Order Number: 240800-001, Package Type P) The Intel 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It has 24 !/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In the first mode (MODE 0), each group of 12 I/O pins may be programmed in sets of 4 to be input or output. In MODE 1, the second mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for handshaking and interrupt control signals. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8 lines for a bidirectional bus, and 5 lines, borrowing one from the other group, for handshaking. ma7-Ph0 maa Ch NA 20 [7 oma oaz ]? wT) ms mai q 3 a0 7] as. oso (Js a7 wr mC] Pen! as 38 = oc ow CT] + ey Do rer arCye aP]o a0 q oy 3 TJ 2 eC passa eco (hs oT} v0 rcs q W n a} Os, Pea-PCo ve 9 Py a] O eco (} 4 wv Do ei] s 2D) vee vczC] 2s [7] ver vatly 20 [7] vee veo] p ros vo ves (J is 22) em P87-PEo ot 20 210) 231308-2 Figure 2. Pin Configuration 231308-t Figure 1. 8255A Block Diagram www.DataSheet.inintel: 8255A/8255A-5 8255A FUNCTIONAL DESCRIPTION General The 8255A is a programmable peripheral interface (PPI) device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configu- ration of the 8255A is programmed by the system software so that normally no external logic is neces- sary to interface peripheral devices or structures. Data Bus Buffer This 3-state bidirectional 8-bit buffer is used to inter- face the 8255A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A low on this input pin enables the communication between the 8255A and the CPU. (RD) Read. A low on this input pin enables the 8255A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to read from the 8255A. (WR) Write. A tow on this input pin enables the CPU to write data or controt words into the 8255A. (Ag and Aj) Port Select 0 and Port Select 1. These input sig- nals, in conjunction with the RD and WR inputs, con- trol the selection of one of the three ports or the control word registers. They are normally connected to the least significant bits of the address bus (Ao and Aj). ___+ sv POWER SUPPLIES > GNo @1 DIRECTIONAL DATA BUS Oats Dy Dy Bus BUFFER a = al ? > RESET GROUP A CONTROL v0 PA? Pag BBIT INTERNAL DATA BUS to PCy PCy "0 PB; PAy 231308-3 Figure 3. 8255A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions www.DataSheet.inintel. 8255A/8255A-5 8255A BASIC OPERATION A; | Ao | RD | WR | CS | Input Operation (READ) 1 PortA Data Bus 0 0 1 0 1 0 | PortB Data Bus 0 0 | PortC Data Bus Output Operation (WRITE) 0;0O] 1 0 | 0 | DataBus PortA o;1)] 1 0 | O | DataBus PortB 1] 0] 1 0 | O | DataBus PortC 1717] 4 50 |] 0 | DataBus Control Disable Function x {xX x 1 | DataBus 3-State Oo; 1 0 | Illegal Condition xX |X 1 Data Bus 3-State (RESET) Reset. A high on this input clears the control reg- ister and all ports (A, B, C) are set to the input mode. Group A and Group B Controls The functional configuration of each port is pro- grammed by the systems software. In essence, the CPU outputs a contro! word to the 8255A. The control word contains information such as mode, bit set, bit reset, etc., that initializes the func- tional configuration of the 8255A. Each of the Control blocks (Group A and Group B) accepts commands from the Read/Write Control Logic, receives control words from the internal data bus and issues the proper commands to its as- sociated ports. Control Group APort A and Port C upper (C7C4) Control Group BPort B and Port C lower (C3-C0) The Controt Word Register can Only be written into. No Read operation of the Control Word Register is allowed. Ports A, B, and C The 8255A contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 8255A. Port A. One 8-bit data output fatch/buffer and one 8-bit data input latch. Port B. One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no jatch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit jatch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. 3-1028255A/8255A-5 +ov POWER SUPPLIES BI-DMREC TIONAL DATA BUS - DATA 07-09 Cts BUFFER % __+-___e-a READ _- we WRITE CONTROL a1] Logic Ao -_____+| RESET __-] a ___ Group a _| ok Kt KY Su CONTROL (a) GROUP Khe KE a uPren Perea co) 4 TERNAL nour ATA BUS ponte KC e399 ia ---_$ GROUP GROUP 8 . 8 cana Ff) we 4 231308-4 Figure 4. 8225A Block Diagram Showing Group A and Group B Control Functions Pin Configuration pas} 1 \/ aot) eae paz (2 a0) Pas par (3 set) Pas wao(le 37[ ear aOC)s 337 we es 35) RESET eno (]7 lo, aiCle af o, ao(j 321] Db, ec7 (10 311) 0, pce []tt 8255A wT, pcs (12 231) og Pca [113 zl") D, pcol| 1 aria por [495 260) Vee ec2 716 2s opr ca }17 2a[] vas peo (418 23[7) pes Pei, 19 227) pee 82 <7] 20 217) pas Pin Names D7-Do Data Bus (Bi-Directional) RESET Reset Input cs Chip Select RD Read Input WAR Write Input AO, At Port Address PA7~PAO Port A (BIT) PB7-PBO Port 8 (BIT) PC7-PCO Port C (BIT) Voc +5 Volts GND 0 Volts 8255A OPERATIONAL DESCRIPTION 231308-5 Mode Selection There are three basic modes of operation that can be selected by the system software: 3-103intel. 8255A/8255A-5 Mode 0Basic Input/Output Mode 1Strobed Input/Output Mode 2Bi-Directional Bus When the reset input goes high all ports will be set to the input mode ({i.e., all 24 lines will be in the high impedance state). After the reset is removed the 8255A can remain in the input mode with no addi- tional initialization required. During the execution of the system program any of the other modes may be selected using a single output instruction. This al- lows a single 8255A to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be tailored to almost any |/O structure. For instance; Group B can be programmed in Mode 0 to monitor simple switch closings or display computa- tional results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. t ADDAESS BUS _1 I { CONTROL BUS lf LI iq DATA BUS MODE 1 8 PB, PB, CONTROL CONTROL PA, OR 1/0 OR 1/0 7 Pho MODE 2 5 A Jeite JefBrovecrionat PBL PB, vo 4_ pa, _ CONTROL 7PAg 231308-6 CONTROL WORD , { Og | Dg | OB, | Oy | DZ | DB, | O% GROUP & PORT C (LOWER) 1 = INPUT O* OUTPUT PORTS += INPUT Q= OUTPUT MODE SELECTION 0= MODE O 1=MOOE1 GROUP A PORT C (UPPER) T= INPUT 0 OUTPUT PORTA 1 = INPUT O= OUTPUT MODE SELECTION 00 = MODE 0 Ot = MODE 1 1X = MODE 2 MODE SET FLAG 1 = ACTIVE 231308-7 Figure 5. Basic Mode Definitions and Bus interface Figure 6. Mode Definition Format The mode definitions and possible mode combina- tions may seem confusing at first but after a cursory review of the complete device operation a simple, logical |/O approach will surface. The design of the 8255A has taken into account things such as effi- cient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. Single Bit Set/Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. This feature re- duces software requirements in Control-based appli- cations. 3-104intel. 8255A/8255A-5 CONTROL WORD D, | Dg | Dg | Dy D3 2 | oy BIT SET/RESET 1=SET O= RESET BIT SELECT BIT SET/RESET FLAG O= ACTIVE 231308-8 Figure 7. Bit Set/Reset Format When Port C is being used as status/control for Port Aor B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports. Interrupt Control Functions When the 8255A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The in- terrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. MODE 0 (BASIC INPUT) This function allows the Programmer to disallow or allow a specific |/O device to interrupt the CPU with- out affecting any other device in the interrupt struc- ture. INTE flip-flop definition: (BIT-SET)INTE is setinterrupt enable (BIT-RESET)INTE is RESETInterrupt disable NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset. Operating Modes MODE 0 (Basic Input/Output). This functional con- figuration provides simple input and output opera- tions for each of the three ports. No handshaking is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions: Two 8-bit ports and two 4-bit ports. e Any port can be input or output. Outputs are latched. inputs are not latched. 16 different Input/Output configurations are pos- sible in this Mode. INPUT CS, a1, A0 0,0) 231308-9 3-105intel. 8255A/8255A-5 MODE 0 (BASIC OUTPUT) D,-Dy CS, At, Ao OUTPUT 231308-10 MODE 0 PORT DEFINITION A B Group A Group B D, | D3 | Dy Do Port A Upper # Port B Lower) 0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT 0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT 0 0 1 0 OUTPUT OUTPUT 2 INPUT OUTPUT 0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT 0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT 0 1 0 1 OUTPUT INPUT 5 OUTPUT INPUT 0 1 1 0 OUTPUT INPUT 6 INPUT OUTPUT 0 1 1 1 OUTPUT INPUT 7 INPUT INPUT 1 0 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT 1 0 0 1 INPUT OUTPUT 9 OUTPUT INPUT 1 0 1 0 INPUT OUTPUT 10 INPUT OUTPUT 1 0 1 1 INPUT OUTPUT 11 INPUT INPUT 1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT 1 1 0 1 INPUT INPUT 13 OUTPUT INPUT 1 1 1 0 INPUT INPUT 14 INPUT OUTPUT 1 1 1 1 INPUT INPUT 15 INPUT INPUT 3-106. intel. 8255A/8255A-5 MODE CONFIGURATIONS CONTROL WORD #0 CONTROL WORD #2 D, Dg Dy 0, Dz D, D, Dy 8 8 PAS? PA,-PA, 7 PAG 4 4 PC, PC, PC, PC, D;-Dy D,-Dy 4 4 PC -PC, PC3PCy 8 8 PB, -PB, PB, PB, 231308-11 231308-12 CONTROL WORD #1 CONTROL WORD #3 Dr Dg Ds 0, 0, Dy, DB, Dy BD, De Ds 0, Dy Dz 0, Dy PA,-PAy PA, PAy 4 PC, PC, PC, PC, 07D 4 Poy Pey ry PC, 8 PB, PB, PB; PB, 231308~-13 231308-14 CONTROL WORD #4 CONTROL WORD #8 0, Og Dg O, Dy, Dz DB, O D, Dg Ds 0% D3 DB, Dy Dy 8 PA,-PAy PA,-PAy 4 PC, PC, PC, PC, D,-Dy D7 Dy 4 PC3-PC, PC3PCy 8 PB, PB, PB, PB, 231308-15 2313086-16 3-107intel. 8255A/8255A-5 CONTROL WORD #5 PA, PAY CONTROL WORD #9 0, PA;-PAy PA,-PAy PC,-PC, 0,Dy PC, PCy PB, Py 231308-21 PC,-PC, PC, -PC, PC,-PCy PC-PCy PB,-PB, PB,-PBy 231308-17 231908-18 CONTROL WORD #6 CONTROL WORD =10 D, De Ds 0, 03 OB, 0, OD D, 0, Ds O, Dz DB, D, Dy 8 PA,-P 7 PAy PA, PA, 4 PC, PC, 4 PC, -PC, D,-Dy D,-Dy 4 PC4-PC, PC, PCy 8 PB, -PBy PB, -PB, 231308-19 231308-20 CONTROL WORD #7 CONTROL WORD #11 BD, De 05 Dy Dz Oy Dy Dy Dd, PA,-PA, PC,-PC, D,Dy PC, PC, PB, PB, 231308-22 3-108intel. 8255A/8255A-5 CONTROL WORD #12 DB, Dg Ds Dy D3 D0, DB, Oy CONTROL WORD #14 D, Dg Os O Ds DB, D, dy PA, PAY PA, -PAy 8255A S255A 4 PC; PC, PC, PC, D,-D, c 0;-Dy c { 4 / PC3-PCy PC3-PCy 8 PB, PB PB, PB, 231308-23 231308-24 CONTROL WORD #13 CONTROL WORD #15 D, Dg Ds Dy Dz D, D, Dy D, Dg DOs Dy Dy DB, D, Dy Pieler tT fed ed | CEEEEELL PA,-PA, PA, PAy 8255A 8255A 4 PC, PC, PC, PC, 07D, c { D,-Dy c { 4 PC, PCy PC, -PCy PB, PB, PB, PB, 231308-25 231308-26 Operating Modes Input Control Signal Definition MODE 1 (Strobed Input/Output). This functional configuration provides a means for transferring 1/O data to or from a specified port in conjunction with strobes or handshaking signals. In mode 1, port A and port B use the lines on port C to generate or accept these handshaking signals. Mode 1 Basic Functional Definitions: Two Groups (Group A and Group B) * Each group contains one 8-bit data port and one 4-bit control/data port. The 8-bit data port can be either input or output. Both inputs and outputs are latched. The 4-bit port is used for control and status of the 8-bit data port. STB (Strobe Input). A tow on this input loads data into the input latch. IBF (Input Buffer Full F/F) A high on this output indicates that the data has been loaded into the input latch; in essence, an ac- knowledgement. IBF is set by STB input being low and is reset by the rising edge of the RD input. INTR (Interrupt Request) A high on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the STB is a one, IBF is a one and INTE is a one. It is reset by the falling edge of RD. This procedure allows an input device to re- quest service from the CPU by simply strobing its data into the port. 3-109intel. 8255A/8255A-5 INTE A Controlled by bit set/reset of PC4. INTE B Controlled by bit set/reset of PCo. MODE 1 (PORT A) CONTROL WORD Pay Phy D, Dg Dg Dg Dy D2 0, Oy lire t wre | ec 5TB Tel] odd | Ag LEP PCe7 Pc, > 18F, = INPUT = OUTPUT PC, f> INTR, 2 C, 7 be 1/0 231308-27 MODE 1 (PORT 8) CONTROL WORD D, Dg Dz Dy 0; D2 D, Dy Lt PDDDI + | DX (BF, INTR, 231308-28 Figure 8. MODE 1 Input INTR = * pig _} we tat | C |___/- wget = =. Wott n nnn nana 231308-29 Figure 9. MODE 1 (Strobed Input) 3-110intel. 8255A/8255A-5 Output Control Signal Definition OBF (Output Buffer Full F/F). The OBF output will go low to indicate that the CPU has written data out to the specified port. The OBF F/F will be set by the rising edge of the WR input and reset by ACK input being low. ACK (Acknowledge Input). A low on this input informs the 8255A that the data from port A or port B has been accepted. In essence, a response from the peripheral device indicating that it has received the data output by the CPU. | INTR (Interrupt Request). A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set when ACK is a one, OBF is a one, and INTE is a one. It is reset by the falling edge of WR. INTE A Controlled by bit set/reset of PCg. INTE B Controlled by bit set/reset of PCo. MODE 1 (PORT A) Pa,PAy| & > CONTROL WORD D, Dg Dg Dg D, D, D, Dy Le] [oJ PC, s 1= INPUT 0 = OUTPUT Plas bee 231308-30 MODE 1 (PORT B) CONTROL WORD D; Dg Ds Dy 0; BD, D, Dy LU PDPDT To XI 231308-31 Figure 10. MODE 1 Output wr \ f be twor INTR \ \ twit tak 1 tart we 231308-32 Figure 11. MODE 1 (Strobed Output) 3-1118255A/8255A-5 PA,PAy KC AD +q PC, [+ STB, PC; ;-> leF, CONTROL WORD 0, Dg Ds Dy Dy O, D, Dy PC, INTA, Pr fot sts fol [oD ry; /e~ > v0 PCe 7 sr | he WReo PC, }> OBF, PC, |-<__ ACK, PCy} _- INTRg 231308-33 PORT A{STROBED INPUT) PORT B{STROBED OUTPUT) PA, PAy{ 8 > WR*O PC,;- OBF, PC, |-_- ACK, CONTROL WORD D, M, Ds 0 D3 0, BD, Dy PC; F-+ INTR, fe fo] fo fuels x 2 PCy sf 0 Plas 1* INPUT 0 = OUTPUT PB, PBo RD PC, {-_ STB, PC, }-> IBF, PCy L-- INTR, 231308-34 PORT A{STROBEO OUTPUT) PORT B(STROBED INPUT) Figure 12. Combinations of MODE 1 Combinations of MODE 1 Port A and Port B can be individually defined as in- put or output in MODE 1 to support a wide variety of strobed I/O applications. Operating Modes MODE 2 (Strobed Bidirectional Bus 1/0). This functional configuration provides a means for com- municating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus 1/0). Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions: Used in Group A only. One 8-bit, bi-directional bus Port (Port A) and a 5- bit contro! Port (Port C). Both inputs and outputs are latched. e The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A). Bidirectional Bus 1/O Control Signal Definition INTR (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations. Output Operations OBF (Output Buffer Full). The OBF output will go low to indicate that the CPU has written data out to port A. ACK (Acknowledge). A low on this input enables the tri-state output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 (The INTE Flip-Flop Associated with OBF). Controlled by bit set/reset of PCg. Input Operations STB (Strobe Input). A low on this input loads data into the input latch. 3-112intel. IBF (Input Buffer Full F/F). A high on this output indicates that data has been loaded into the input latch. 8255A/8255A-5 INTE 2 (The INTE Flip-Flop Associated with IBF). Controlled by bit set/reset of PCy. CONTROL WORD D, Og Dy OD, D, DB, 0, Dy 1 V0 | 170 | 1/0 Plrg : 1 INPUT @=- OUTPUT * PORT B 1 = INPUT 0*= OUTPUT a <<<---= GROUP 8 MODE O= MODE CO 1= MODE 1 231308-35 Figure 13. MODE Contro! Word INTR, 231308-36 Figure 14. MODE 2 DATA FROM J > o 4 = 'wos INTR ACK Wh [~~ 'aon wD, i NOTE: 231308-37 Any sequence where WR occurs before ACK and STB occurs before AD is permissible. (INTR = IBF e MASK STB RD + OBF MASK e CK WR) Figure 15. MODE 2 (Bidirectional) 3-1132 intel. 8255A/8255A-5 MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT) PC, e INTR, Pc, }-> INTR, Pay Phy Phy Ph Pc, | 68F, Pc; -#> 8F, CONTROL WORD pc, |j~_ ACK, CONTROL WORD Pc, > ack, D, Dg DO, Dy Dy D, D, Dy D, Og Dy Dy Dz D, 0, Dy SANS PT RODE T Ta ef, CLR re 7, PC. Ee PC. Pc, -}>_ IBF, Poza = PCs 18F, veikrur ; a 0+ OUTPUT 3 uw 3 PC,9 + 1/0 PCz9 ;*7-> 1/0 a _-+d RD _+q PB, PBy 8 > 78, PB CONTROL WORD D, Dg Dg Dy Dy Dy D, Dy UT PD fof) 231308-38 MODE 2 AND MODE 1 (OUTPUT) PC, INTA, STB, IBF, INTRg 231308-40 WA +d MODE 2 AND MODE 1 (INPUT) 231308-39 CONTROL WORD D, Dg Dy Dy 0, Dz 9, Dy UL DDE TX RO ___ed wa ___-d PCy PA,-PAy PC, PB, -PBy Pe, PC, PCy r> INTR, > O@F, j+ ack, -_--_. 578, | IBF, + 578, p IBF, [> INTR, 231308-41 Figure 16. MODE 1/4, Combinationsintel. 8255A/8255A-5 Mode Definition Summary MODE 0 MODE 1 MODE 2 IN OUT IN OUT GROUP A ONLY PAg IN OUT IN OUT _ PA, IN OUT IN OUT PAp IN OUT IN OUT PA3 IN OUT IN OUT _ PAy IN OUT IN OUT PAs IN OUT IN OUT PAg IN OUT IN OUT _ PA IN OuT |- iN OUT PBo IN OUT IN OUT __ PB, IN | OUT IN OUT _ PBo IN OUT IN ~ OUT __ PB3 IN OUT iN OUT __ MODE 0 PB, IN OUT IN OUT __ OR MODE 1 PBs iN OUT IN OUT __ ONLY PBs iN OUT IN OUT _ PB7 iN OUT rN OUT __ PC IN OUT INTRe INTRs /0 PC, iN OUT IBF OBFg vO PCa IN OUT STBa ACKg 0 PCy IN OUT INTRa INTRA INTRa PC, IN OUT STB, 1/0 STB, PC5 IN OUT IBF, 1/0 IBF, PCg IN OUT 1/0 ACKa ACKa PC7 IN OUT 0 OBFa OBFa This feature allows the 8255 to directly drive Darling- ton type drivers and high-voltage displays that re- quire such source current. Special Mode Combination Considerations There are several combinations of modes when not ail of the bits in Port C are used for control or status. The remaining bits can be used as follows: lf Programmed as Inputs Alt input lines can be accessed during a normal Port C read. lf Programmed as Outputs Bits in C upper (PC7-PC,) must be individually ac- cessed using the bit set/reset function. Bits in C lower (PC3-PCo) can be accessed using the bit set/reset function or accessed as a three- some by writing into Port C. Source Current Capability on Port B and Port C Any set of eight output buffers, selected randomly from Ports B and C can source 1 mA at 1.5 voits. Reading Port C Status In Mode 0, Port C transfers data to or from the pe- ripheral device. When the 8255 is programmed to function in Modes 1 or 2, Port C generates or ac- cepts hand-shaking signals with the peripheral de- vice. Reading the contents of Port C allows the pro- grammer to test or verify the status of each pe- ripheral device and change the program flow ac- cordingly. There is no special instruction to read the status in- formation from Port C. A normal read operation of Port C is executed to perform this function. 3-1158255A/8255A-5 INPUT CONFIGURATION DB, De Os % 2 0, 2% W/o INTE, | INTR, vo | (BF, aaa T GROUP A GRouP 8 OUTPUT CONFIGURATION D, De OO O& OD, DB, D, GBF, | INTE,| 1/0 | vo | wre, wre,| OBF, |INTRg GROUP A GRouP B 231308-59 INTERRUPT REQUEST | PG, Figure 17. MODE 1 Status Word Format O, 03; Dz 1, Oy " X = GROUP B oo {DEFINED BY MODE 0 OR MODE 1 SELECTION) 231308-42 Figure 18. MODE 2 Status Word Format Ob, OO 2% | ORF, | INTE, | (BF, t T GROUP A APPLICATIONS OF THE 8255A The 8255A is a very powerful tool for interfacing pe- ripheral equipment to the microcomputer system. It represents the optimum use of available pins and is flexible enough to interface almost any !/O device without the need for additional external logic. Each peripheral device in a microcomputer system usually has a service routine associated with it. The routine manages the software interface be- tween the device and the CPU. The functional defini- tion of the 8255A is programmed by the !/O service routine and becomes an extension of the system software. By examining the I/O devices interface characteristics for both data transfer and timing, and matching this information to the examples and ta- bles in the detailed operational description, a control word can easily be developed to initialize the 8255A to exactly fit the application. Figures 19 through 25 represent a few examples of typical applications of the 8255A. 3-116 INTERRUPT REQUEST PA p> PA, -+] PA, -| HIGH-SPEED os |__| PRINTER i } | PAs -* MODE 1 _| Pg }$-w }__- (OUTPUT Pay | HAMMER RELAYS Pc, L-+] pata neapy | +| Cg [~-4 ack tt | PC, -] PAPER FEED =} + | PC, F>] FORWARD/REV }#1 | 82550 |_| [es, -e 8, /- 8, /K+ 8, -+ >} DATA READY pa, }-1 L$ ack MODE1 | pa, |! |__i PAPER FEED fourpur) " es, | | }-+| FoRWARD/REV 8, | + p+| RIBBON }+ CARRIAGE SEN. Pc, -}=] DATA READY Pc, J>J ack PCy CONTROL LOGIC AND DRIVERS 231308-43 Figure 19. Printer Interface INTERRUPT REQUEST MOD! MOD! E1 (INPUT) | E1 (ouTPuT) | PCy 2 FULLY DECODED 3 KEYBOARD Ry Ry SHIFT CONTROL STROBE ACK PC, Pc, PCy Pc, INTERRUPT REQUEST By By p, BURROUGHS 2 SELF-SCAN 8, _OISPLAY B, Bs, BACKSPACE CLEAR DATA READY ACK BLANKING CANCEL WORD 231308-44 Figure 20. Keyboard and Display Interfaceintel. 8255A/8255A-5 INTERRUPT INTERRUPT REQUEST REQUEST PC Pp, R Ms [Pag Dy Ag 0 PAY 0, PA, a, PA. D. 2 iz PA, A, PA; D; FLOPPY DISK Pa. A FULLY P, D. CONTROLLER MODE 1 | PAs 3 pecoven Aa a AND DRIVE UNPUT) | p, R, KEYBOARD Pas , Ay a 's Pay Rs MODE 2 PAg Dd, PA, D, PAG SHIFT 82554 Pa, CONTROL PCy DATA sta Pc, ACK LIN} PC, STROBE FC, DATA READY , ACK touT) PCs ACKNOWLEDGE PCy UsY LT PC, TRACK "0" SENSOR Pc, TEST LT PCy SYNC READY L Pc, INDEX Tre, 7 Tp, PBo Le TERMINAL PB, . PB ENGAGE HEAD PB, Pe, . wove | : maou INPUT) | PB, 7 move o _| P83 w nN > {ouTPUT} | PBs OVse SELECT PBs, _ PBs ENABLE CRC PB. PBs Test Pe, so PB, BUSY LT > = 231308-47 231308-45 Figure 23. Basic Flo Disk Interface Figure 21. Keyboard and 9 PPy Terminal Address interface INTERRUPT Request * r PA, ise PCT PA, Ry PA, Pa, Ry CRT CONTROLLER PA, PA, R, CHARACTER GEN. PA, PA; Ry REFRESH BUFFER PA, PA, Rr CURSOR CONTROL MODE 0 _| PAs PAs Ay (oureut) | pa, 12-81T MODE 1 | PA, SHIFT Pa DA (OUTPUTI| pa, CONTROL 7 converter [> ANALOG OUTPUT 7 PCy (DAC) PCS, Pc, DATA READY Pee PCy ACK 02580 rc, use PCs, BLANKED ~ Pc, BLACK WHITE ezssa L [ PCy STB DATA Pc, OUTPUT EN air PC, Row STs, SET/RESET | PC, COLUMN STS PC, SAMPLE EN Py CURSOR H/V STB PCy stB Pe [ #8, tse move o_| PB, 6, son toureuT) | Ps, Nv PB, CONVERTER [= ANALOG INPUT Pay eos Um MODE O | PB; 8, + HaV (INPUT) ~] PB, Pa, PB, Pa, PB, PB, 6 LL PB, MsB 231308-48 231308 -46 Figure 24. Basic CRT Controller Interface Figure 22. Digital to Analog, Analog to Digital 9 3-117. intel. 8255A/8255A-5 INTERRUPT REQUEST ~ mo 3 PA, Ay PA, ay PA. R 8 LEVEL 2 2 PAPER Pay Ry TAPE PA, rn, READER e R move 1 _| ne tweut) | PAs 6 Pa, A, PC, sT6 PC, Ack PC, stToP/Go G285A MACHINE TOOL move 0 PCy START/STOP tneuts 7] PC LIMIT SENSOR {(H/V) PC, OUT OF FLUID L FB, CHANGE TOOL PB, LEFT/AIGHT 8, UP/DOWN MODE 0 | PB; HOR. STEP STROBE toureuTl | PB, VERT. STEP STROBE PB, SLEW/STEP PB, FLUID ENABLE 8, |; + | EMERGENCY STOP 231308-49 Figure 25. Machine Tool Controller Interface ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias ...... 0C to 70C NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. Storage Temperature Voltage on Any Pin with Respect to Ground.......... 0.5V to +7V Power Dissipation *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. D.C. CHARACTERISTICS Ta = 0C to 70C, Veg = +5V 10%, GND = OV* Symbol Parameter Min Max | Unit Test Conditions ViL Input Low Voltage 0.5 0.8 Vv Vin Input High Voltage 2.0 Voc Vv Vo (DB) Output Low Voltage (Data Bus) 0.45* Vv lo. = 2.5mA Vor (PER) | Output Low Voltage (Peripheral Port) 0.45* Vv lop = 1.7mA Von (DB) Output High Voltage (Data Bus) 2.4 Vv lon = 400 pA Von (PER) | Output High Voltage (Peripheral Port) 2.4 v lon = 200 pA Iban) Darlington Drive Current 1.0 | 4.0 | mA | Rext = 7509; Vex7 = 1.5V loc Power Supply Current 120 mA hie input Load Current +10 | pA | Vin = Voc to OV loFL Output Float Leakage +10 | BA | Vout = Voc to 0.45V NOTE: 1. Available on any 8 pins from Port B and C. 3-118intel. 8255A/8255A-5 CAPACITANCE T, = 25C, Voc = GND = OV Symbol Parameter Min Typ Max Unit Test Conditions Cin Input Capacitance 10 pF fe = 1 MHz(4) Cio 1/O Capacitance 20 pF Unmeasured pins returned to GND(4) A.C. CHARACTERISTICS T, = 0C to 70C, Vog = +5V 10%, GND = OV* Bus Parameters READ Symbol , Parameter 8255A 8255A-5 Unit Min Max Min Max tan Address Stable before READ 0 0 ns tra Address Stable after READ 0 0 ns tar READ Pulse Width 300 300 ns tro Data Valid from READ(1) 250 200 ns tor Data Float after READ 10 150 10 100 ns try Time between READs and/or WRITEs 850 850 ns WRITE Symbol Parameter 8255A S255A-5 Unit Min Max Min Max taw Address Stable before WRITE 0 0 ns twa Address Stable after WRITE 20 20 ns tww WRITE Pulse Width 400 300 ns tow Data Valid to WRITE (T.E.) 100 100 ns twp Data Valid after WRITE 30 30 ns OTHER TIMINGS Symbol Parameter 8255A 8255A-5 Unit : Min Max Min Max twe WR = 1 to Output(1) 350 350 ns tin Peripheral Data before RD 0 0 ns tur Peripheral Data after RD 0 0 ns tak ACK Pulse Width 300 300 ns tst STB Pulse Width 500 500 ns tps Per. Data before T.E. of STB 0 0 ns tpH Per. Data after T.E. of STB 180 180 ns tap ACK = 0 to Output(1) 300 300 ns tkp ACK = 1 to Output Float 20 250 20 250 ns 3-119ntel. 8255A/8255A-5 A.C. CHARACTERISTICS (Continued) OTHER TIMINGS (Continued) Symbol Parameter 8255A 8255A-5 Unit Min Max Min Max twos WR = 1 to OBF = 0(1) 650 650 ns taos ACK = 0 to OBF = 1(1) 350 350 ns tsi STB = 0to IBF = 1(1) 300 300 ns trie RD = 1 to IBF = ott) 300 300 ns trait RD = Oto INTR = 001) 400 400 ns tsit STB = 1 to INTR = 1) 300 300 ns taiT ACK = 1 to INTR = 1(1) 350 350 ns twit WR = Oto INTR = 0(1,3) 850 850 ns NOTES: 1. Test Conditions: CL = 150 pF. 2. Period of Reset pulse must be at least 50 ,.s during or after power on. Subsequent Reset pulse can be 500 ns min. 3. INTR T may occur as early as WR I. 4. Sampled, not 100% tested. *For Extended Temperature EXPRESS, use M8255A electrical parameters. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT Input/Output 24 20 20 > TEST POINTS < C, = 150 pF oe 08 0.45 231308 -50 A.C. Testing: Inputs are driven at 2.4V for a Logic 1 and 0.45V for a Logic 0. Timing measurements are made at 2.0V for a Logic 1 and 0.8V for a Logic 0. pO ext" te 231308-51 Vext is set at various voltages during testing to guarantee the specification. GC, includes jig capacitance. 3-120intel. 8255A/8255A-5 WAVEFORMS MODE 0 (BASIC INPUT) INPUT CS. At, AO Dy Dy ee eee ee 231308-52 MODE 0 (BASIC OUTPUT) D,-05 CS, A1, AO OUTPUT 231308-53 3-121intel. 8255A/8255A-5 WAVEFORMS (Continued) MODE 1 (STROBED INPUT) 7 /__+_ f INPUT FROM Wo ee ee eee ee ee ee oe oe PERIPHERAL - ee wee ee 231308-54 MODE 1 (STROBED OUTPUT) = v | ~ oN ZY oureur Ze 231308-55 3-122intel. 8255A/8255A-5 WAVEFORMS (Continued) MODE 2 (BIDIRECTIONAL) DATA FROM $080 TO 8255 INTR \ / t { Lp | N\ L ACK 18F PERIPHERAL BUS *|tanfe - -*) ko ~lf \ iii ee ATA FROM DATA FROM PERIPHERAL TO 8255. 8255 TO PERIPHERAL | DATA FROM 8255 TO 8060 NOTE: _ 231308-56 Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF * MASK STB RD + OBF MASK @ ACK WR) WRITE TIMING READ TIMING Ag. 08 Ap.4. S t | jwtae DATA BUS RD N . eltaoie ftp be wR DATA BUS HIGH IMPEDANCE VALID | HIGH IMPEDANCE 231308 -58 231308-57 3-123