FB
LM25085A
PGATE
ISEN
GND
VCC
ADJ
4.5V to 42V
Input
VIN
GND
SHUTDOWN
CIN
RT
CVCC
CADJ
RADJ
Q1
D1
L1
Cff COUT
RFB2
RFB1
VOUT
GND
VIN
RT
LM25085A
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SNVS601B –JANUARY 2009–REVISED MARCH 2013
LM25085A 42V Constant On-Time PFET Buck Switching Controller with 0.9V Reference
Check for Samples: LM25085A
1FEATURES DESCRIPTION
The LM25085A is a functional variant of the LM25085
2• Wide 4.5V to 42V Input Voltage Range COT PFET Buck Switching Controller. The functional
• Adjustable Current Limit using RDS(ON) or a differences of the LM25085A are: The feedback
Current Sense Resistor reference voltage is 0.9V, the forced off-time after
• Programmable Switching Frequency to 1MHz current limit detection is longer, and the soft-start time
is shorter (1.8 ms).
• No Loop Compensation Required The LM25085A is a high efficiency PFET switching
• Ultra-Fast Transient Response regulator controller that can be used to quickly and
• Nearly Constant Operating Frequency with easily develop a small, efficient buck regulator for a
Line and Load Variations wide range of applications. This high voltage
• Adjustable Output Voltage from 0.9V controller contains a PFET gate driver and a high
voltage bias regulator which operates over a wide
• Precision ±2% Feedback Reference 4.5V to 42V input range. The constant on-time
• Capable of 100% Duty Cycle Operation regulation principle requires no loop compensation,
• Internal Soft-Start Timer simplifies circuit implementation, and results in ultra-
• Integrated High Voltage Bias Regulator fast load transient response. The operating frequency
remains nearly constant with line and load variations
• Thermal Shutdown due to the inverse relationship between the input
voltage and the on-time. The PFET architecture
PACKAGE allows 100% duty cycle operation for a low dropout
• HVSSOP-PowerPAD-8 voltage. Either the RDS(ON) of the PFET or an external
sense resistor can be used to sense current for over-
• VSSOP-8 current detection.
• WSON-8 (3 mm x 3 mm)
Typical Application, Basic Step Down Controller
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
8
7
6
5
4
3
2
1
Exposed Pad on Bottom
Connect to Ground
FB
GND
ADJ
PGATE
ISEN
VCC
RT
VIN
1
2
3
4 5
8
7
6
Exposed Pad on Bottom
Connect to Ground
FB PGATE
ISEN
GND
VCC
ADJ
RT
VIN
1
2
3
4 5
8
7
6
FB PGATE
ISEN
GND
VCC
ADJ
RT
VIN
LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
Connection Diagram
Figure 1. Top View Figure 2. Top View
8-Lead HVSSOP 8-Lead VSSOP
Figure 3. Top View
8-Lead WSON
PIN DESCRIPTIONS
Pin Name Description Application Information
No.
1 ADJ Current Limit Adjust The current limit threshold is set by an external resistor from VIN to ADJ in
conjunction with the external sense resistor or the PFET’s RDS(ON).
2 RT On-time control and shutdown An external resistor from VIN to RT sets the buck switch on-time and switching
frequency. Grounding this pin shuts down the controller.
3 FB Voltage Feedback from the Input to the regulation and over-voltage comparators. The regulation level is 0.9V.
regulated output
4 GND Circuit Ground Ground reference for all internal circuitry
5 ISEN Current sense input for current Connect to the PFET drain when using RDS(ON) current sense. Connect to the PFET
limit detection. source and the sense resistor when using a current sense resistor.
6 PGATE Gate Driver Output Connect to the gate of the external PFET.
7 VCC Output of the gate driver bias Output of the negative voltage regulator (relative to VIN) that biases the PFET gate
regulator driver. A low ESR capacitor is required from VIN to VCC, located as close as
possible to the pins.
8 VIN Input supply voltage The operating input range is from 4.5V to 42V. A low ESR bypass capacitor must be
located as close as possible to the VIN and GND pins.
EP Exposed Pad Exposed pad on the underside of the package (HVSSOP-PowerPAD-8 and WSON
only). This pad is to be soldered to the PC board ground plane to aid in heat
dissipation.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1)(2)
VIN to GND -0.3V to 45V
ISEN to GND -0.3V to VIN + 0.3V
ADJ to GND -0.3V to VIN + 0.3V
RT, FB to GND -0.3V to 7V
VIN to VCC, VIN to PGATE -0.3V to 10V
ESD Rating (3)
Human Body Model 2kV
Storage Temperature Range -65°C to +150°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin.
Operating Ratings (1)
VIN Voltage 4.5V to 42V
Junction Temperature −40°C to + 125°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 24V, RT= 100 kΩ.
Symbol Parameter Conditions Min Typ Max Units
VIN Pin
IIN Operating current Non-switching, FB = 1.05V (1) 1.25 1.75 mA
IQShutdown current RT = 0V (1) 175 300 µA
VCC Regulator (2)
VCC(reg) VIN - VCC Vin = 9V, FB = 1.05V, ICC = 0 mA 6.9 7.7 8.5 V
Vin = 9V, FB = 1.05V, ICC = 20 mA 7.7 V
Vin = 42V, FB = 1.05V, ICC = 0 mA 7.7 V
UVLOVcc VCC under-voltage lock-out VCC increasing 3.8 V
threshold
UVLOVcc hysteresis VCC decreasing 260 mV
VCC(CL) VCC Current Limit FB = 1.05V 20 40 mA
PGATE Pin
VPGATE(HI) PGATE High voltage PGATE Pin = Open VIN -0.1 VIN V
VPGATE(LO) PGATE Low voltage PGATE Pin = Open VCC VCC+0.1 V
VPGATE(HI)4.5 PGATE High Voltage at Vin = 4.5V PGATE Pin = Open VIN -0.1 VIN V
VPGATE(LO)4.5 PGATE Low Voltage at Vin = 4.5V PGATE Pin = Open VCC VCC+0.1 V
IPGATE Driver Output Source Current VIN = 12V, PGATE = VIN - 3.5V 1.75 A
Driver Output Sink Current VIN = 12V, PGATE = VIN - 3.5V 1.5 A
RPGATE Driver Output Resistance Source current = 500 mA 2.3 Ω
Sink current = 500 mA 2.3 Ω
Current Limit Detection
IADJ ADJUST pin current source VADJ = 22.5V 32 40 48 µA
VCL OFFSET Current limit comparator offset VADJ = 22.5V, VADJ - VISEN -9 09mV
(1) Operating current and shutdown current do not include the current in the RTresistor.
(2) VCC provides self bias for the internal gate drive.
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Electrical Characteristics (continued)
Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 24V, RT= 100 kΩ.
Symbol Parameter Conditions Min Typ Max Units
RT Pin
RTSD Shutdown threshold RT Pin voltage rising 0.73 V
RTHYS Shutdown threshold hysteresis 50 mV
On-Time
tON – 1 On-time VIN = 4.5V, RT= 100 kΩ3.5 57.15 µs
tON – 2 VIN = 24V, RT= 100 kΩ560 720 870 ns
tON - 3 VIN = 42V, RT= 100 kΩ329 415 500 ns
tON - 4 Minimum on-time in current limit (3) VIN = 24V, 25 mV overdrive at ISEN 55 140 235 ns
Off-Time
tOFF(CL1) Off-time (current limit) (3) VIN = 12V, VFB = 0V 5.56 810.96 µs
tOFF(CL2) VIN = 12V, VFB = 0.75V 2.59 3.7 5.16 µs
tOFF(CL3) VIN = 24V, VFB = 0V 9.03 13.2 18.1 µs
tOFF(CL4) VIN = 24V, VFB = 0.75V 4.29 68.54 µs
Regulation and Over-Voltage Comparators (FB Pin)
VREF FB regulation threshold 0.882 0.9 0.918 V
VOV FB over-voltage threshold Measured with respect to VREF 350 mV
IFB FB bias current 10 nA
Soft-Start Function
tSS Soft-start time 1.16 1.8 3.15 ms
Thermal Shutdown
TSD Junction shutdown temperature Junction temperature rising 170 °C
THYS Junction shutdown hysteresis 20 °C
Thermal Resistance(4)
θJA Junction to ambient, 0 LFPM air VSSOP-8 package 126 °C/W
flow (5) HVSSOP-PowerPAD-8 package 46
WSON-8 package 54
θJC Junction to case, 0 LFPM air flow VSSOP-8 package 29 °C/W
(5) HVSSOP-PowerPAD-8 package 5.5
WSON-8 package 9.1
(3) The tolerance of the minimum on-time (tON-4) and the current limit off-times (tOFF(CL1) through (tOFF(CL4)) track each other over process
and temperature variations. A device which has an on-time at the high end of the range will have an off-time that is at the high end of its
range.
(4) For detailed information on soldering plastic VSSOP and WSON packages visit www.ti.com/packaging.
(5) Tested on a 4 layer JEDEC board. Four vias provided under the exposed pad. See JEDEC standards JESD51-5 and JESD51-7.
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Typical Performance Characteristics
Unless otherwise specified the following conditions apply: TJ= 25°C, VIN = 24V.
Input Operating Current
vs.
Efficiency (Circuit of Figure 28) VIN
Figure 4. Figure 5.
Shutdown Current VCC
vs. vs.
VIN VIN
Figure 6. Figure 7.
VCC On-Time
vs. vs.
ICC RTand VIN
Figure 8. Figure 9.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ= 25°C, VIN = 24V.
Off-Time
vs.
VIN and VFB Voltage at the RT Pin
Figure 10. Figure 11.
ADJ Pin Current Input Operating Current
vs. vs.
VIN Temperature
Figure 12. Figure 13.
Shutdown Current VCC
vs. vs.
Temperature Temperature
Figure 14. Figure 15.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ= 25°C, VIN = 24V.
On-Time Minimum On-Time
vs. vs.
Temperature Temperature
Figure 16. Figure 17.
Off-Time Current Limit Comparator Offset
vs. vs.
Temperature Temperature
Figure 18. Figure 19.
ADJ Pin Current PGATE Driver Output Resistance
vs. vs.
Temperature Temperature
Figure 20. Figure 21.
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ= 25°C, VIN = 24V.
Feedback Reference Voltage Soft-Start Time
vs. vs.
Temperature Temperature
Figure 22. Figure 23.
RT Pin Shutdown Threshold
vs.
Temperature
Figure 24.
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-
+
QR
+
S
Negative Bias
Regulator
Thermal
Shutdown
ON Time
One-Shot
Soft-Start Gate Driver
Control Logic
VCC
UVLO Gate
Driver
REGULATION
COMPARATOR
OVER-VOLTAGE
COMPARATOR
CURRENT
LIMIT
COMPARATOR
OFF Time
One-Shot
FB
LM25085A
PGATE
ISEN
GND
VCC
ADJ
4.5V to 42V
Input
VIN
GND
SHUTDOWN
RT
CVCC
CADJ
RADJ
Q1
D1
L1
0.9V
RFB1
RFB2
CBYP
RSEN
VCC VOUT
COUT
R3 C1
C2
1.25V
+
-
+
-
7.7V
40 PA
+
-
0.73V
+
-
RT
CIN
VIN
VIN
VIN
LM25085A
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SNVS601B –JANUARY 2009–REVISED MARCH 2013
Block Diagram
Sense resistor method shown for current limit detection.
Minimum output ripple configuration shown.
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Duty Cycle = tON
tON + tOFF
== tON x FS
VOUT
VIN
LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
FUNCTIONAL DESCRIPTION
OVERVIEW
The LM25085A is a PFET buck (step-down) DC-DC controller using the constant on-time (COT) control principle.
The input operating voltage range of the LM25085A is 4.5V to 42V. The use of a PFET in a buck regulator
greatly simplifies the gate drive requirements and allows for 100% duty cycle operation to extend the regulation
range when operating at low input voltage. However, PFET transistors typically have higher on-resistance and
gate charge when compared to similarly rated NFET transistors. Consideration of available PFETs, input voltage
range, gate drive capability of the LM25085A, and thermal resistances indicate an upper limit of 10A for the load
current for LM25085A applications. Constant on-time control is implemented using an on-time one-shot that is
triggered by the feedback signal. During the off-time, when the PFET (Q1) is off, the load current is supplied by
the inductor and the output capacitor. As the output voltage falls, the voltage at the feedback comparator input
(FB) falls below the regulation threshold. When this occurs Q1 is turned on for the one-shot period which is
determined by the input voltage (VIN) and the RTresistor. During the on-time the increasing inductor current
increases the voltage at FB above the feedback comparator threshold. For a buck regulator the basic relationship
between the on-time, off-time, input voltage and output voltage is:
(1)
where Fs is the switching frequency. Equation 1 is valid only in continuous conduction mode (inductor current
does not reach zero). Since the LM25085A controls the on-time inversely proportional to VIN, the switching
frequency remains relatively constant as VIN is varied. If the input voltage falls to a level that is equal to or less
than the regulated output voltage Q1 is held on continuously (100% duty cycle) and VOUT is approximately equal
to VIN.
The COT control scheme, with the feedback signal applied to a comparator rather than an error amplifier,
requires no loop compensation, resulting in very fast load transient response.
The LM25085A is available in both an 8 pin HVSSOP-PowerPAD package and an 8 pin WSON package with an
exposed pad to aid in heat dissipation. An 8 pin VSSOP package without an exposed pad is also available.
REGULATION CONTROL CIRCUIT
The LM25085A buck DC-DC controller employs a control scheme based on a comparator and a one-shot on-
timer, with the output voltage feedback compared to an internal reference voltage (0.9V). When the FB pin
voltage falls below the feedback reference, Q1 is switched on for a time period determined by the input voltage
and a programming resistor (RT). Following the on-time Q1 remains off until the FB voltage falls below the
reference. Q1 is then switched on for another on-time period. The output voltage is set by the feedback resistors
(RFB1, RFB2 in Block Diagram). The regulated output voltage is calculated as follows:
VOUT = 0.9V x (RFB2+ RFB1)/ RFB1 (2)
The feedback voltage supplied to the FB pin is applied to a comparator rather than a linear amplifier. For proper
operation sufficient ripple amplitude is necessary at the FB pin to switch the comparator at regular intervals with
minimum delay and noise susceptibility. This ripple is normally obtained from the output voltage ripple attenuated
through the feedback resistors. The output voltage ripple is a result of the inductor’s ripple current passing
through the output capacitor’s ESR, or through a resistor in series with the output capacitor. Multiple methods are
available to ensure sufficient ripple is supplied to the FB pin, and three different configurations are discussed in
Applications Information.
When in regulation, the LM25085A operates in continuous conduction mode at medium to heavy load currents
and discontinuous conduction mode at light load currents. In continuous conduction mode the inductor’s current
is always greater than zero, and the operating frequency remains relatively constant with load and line variations.
The minimum load current for continuous conduction mode is one-half the inductor’s ripple current amplitude. In
discontinuous conduction mode, where the inductor’s current reaches zero during the off-time, the operating
frequency is lower than in continuous conduction mode and varies with load current. Conversion efficiency is
maintained at light loads since the switching losses are reduced with the reduction in load and frequency.
If the voltage at the FB pin exceeds 1.25V due to a transient overshoot or excessive ripple at VOUT the internal
over-voltage comparator immediately switches off Q1. The next on-time period starts when the voltage at FB falls
below the feedback reference voltage.
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RT
Input
Voltage
STOP
RUN
LM25085A
RT
VIN
RT = VOUT x 6 x 106
FS - 8.6
FS = VOUT x (VIN - 1.56V + RT/3167)
VIN x [(1.45 x 10-7 x (RT + 1.4)) + (tD x (VIN - 1.56V + RT/3167))]
tON = (VIN - 1.56V + RT/3167)
1.45 x 10-7 x (RT + 1.4) + 50 ns
LM25085A
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SNVS601B –JANUARY 2009–REVISED MARCH 2013
ON-TIME TIMER
The on-time of the PFET gate drive output (PGATE pin) is determined by the resistor (RT) and the input voltage
(VIN), and is calculated from:
(3)
where RTis in kΩ. The minimum on-time, which occurs at maximum VIN, should not be set less than 150 ns (see
CURRENT LIMITING). The buck regulator effective on-time, measured at the SW node (junction of Q1, L1, and
D1) is typically longer than that calculated in Equation 3 due to the asymmetric delay of the PFET. The on-time
difference caused by the PFET switching delay can be estimated as the difference of the turn-off and turn-on
delays listed in the PFET data sheet. Measuring the difference between the on-time at the PGATE pin versus the
SW node in the actual application circuit is also recommended.
In continuous conduction mode, the inverse relationship of tON with VIN results in a nearly constant switching
frequency as VIN is varied. The operating frequency can be calculated from:
(4)
where RTis in kΩ, and tDis equal to 50 ns plus the PFET’s delay difference. To set a specific continuous
conduction mode switching frequency (FS), the RTresistor is determined from the following:
(5)
where RTis in kΩ. A simplified version of Equation 6 at VIN = 12V, and tD= 100 ns, is:
For VIN = 42V and tD= 100 ns, the simplified equation is:
SHUTDOWN
The LM25085A can be shutdown by grounding the RT pin (see Figure 25). In this mode the PFET is held off,
and the VCC regulator is disabled. The internal operating current is reduced to the value shown in the graph
“Shutdown current vs. VIN”. The shutdown threshold at the RT pin is ≊0.73V, with ≊50 mV of hysteresis.
Releasing the pin enables normal operation. The RT pin must not be forced high during normal operation.
Figure 25. Shutdown Implementation
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'I = (VOUT + VFD + VESR) x tOFF
L
'I = (VIN - VOUT) x tON
L
tOFF(CL) = 8 x 10-6 x ((VIN/31) + 0.15)
(VFB x 0.93) + 0.56V
LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
CURRENT LIMITING
The LM25085A current limiting operates by sensing the voltage across either the RDS(ON) of Q1, or a sense
resistor, during the on-time and comparing it to the voltage across the resistor RADJ (see Figure 26). The current
limit function is much more accurate and stable over temperature when a sense resistor is used. The RDS(ON) of a
MOSFET has a wide process variation and a large temperature coefficient.
If the voltage across RDS(ON) of Q1, or the sense resistor, is greater than the voltage across RADJ, the current limit
comparator switches to turn off Q1. Current sensing is disabled for a blanking time of ≊100 ns at the beginning of
the on-time to prevent false triggering of the current limit comparator due to leading edge current spikes.
Because of the blanking time and the turn-on and turn-off delays created by the PFET, the on-time at the PGATE
pin should not be set less than 150 ns. An on-time shorter than that may prevent the current limit detection circuit
from properly detecting an over-current condition. The duration of the subsequent forced off-time is a function of
the input voltage and the voltage at the FB pin, as shown in Figure 10. The longer-than-normal forced off-time
allows the inductor current to decrease to a low level before the next on-time. This cycle-by-cycle monitoring,
followed by a forced off-time, provides effective protection from output load faults over a wide range of operating
conditions.
The voltage across the RADJ resistor is set by an internal 40 µA current sink at the ADJ pin. When using Q1’s
RDS(ON) for sensing, the current at which the current limit comparator switches is calculated from:
ICL = 40 µA x RADJ/RDS(ON) (6)
When using a sense resistor (RSEN) the thrshold of the current limit comparator is calculated from:
ICL = 40 µA x RADJ/RSEN (7)
When using Equation 6 or Equation 7, the tolerances for the ADJ pin current sink and the offset of the current
limit comparator should be included to ensure the resulting minimum current limit is not less than the required
maximum switch current. Simultaneously increasing the values of RADJ and RSEN decreases the effects of the
current limit comparator offset, but at the expense of higher power dissipation. When using a sense resistor, the
RSEN resistor value should be chosen within the practical limitations of power dissipation and physical size. For
example, for a 10A current limit, setting RSEN = 0.005Ωresults in a power dissipation as high as 0.5W. Current
sense connections to the RSEN resistor, or to Q1, must be Kelvin connections to ensure accuracy.
The CADJ capacitor filters noise from the ADJ pin, and helps prevent unintended switching of the current limit
comparator due to input voltage transients. The recommended value for CADJ is 1000 pF.
CURRENT LIMIT OFF-TIME
When the current through Q1 exceeds the current limit threshold, the LM25085A forces an off-time longer than
the normal off-time defined by Equation 1. See Figure 10, or calculate the current limit off-time from the following
equation:
(8)
where VIN is the input voltage, and VFB is the voltage at the FB pin at the time current limit was detected. This
feature is necessary to allow the inductor current to decrease sufficiently to offset the current increase which
occurred during the on-time. During the on-time, the inductor current increases an amount equal to:
(9)
During the off-time the inductor current decreases due to the reverse voltage applied across the inductor by the
output voltage, the freewheeling diode’s forward voltage (VFD), and the voltage drop due to the inductor’s series
resistance (VESR). The current decrease is equal to:
(10)
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LM25085A
PGATE
ISEN
VCC
ADJ
CADJ
RADJ
Q1
D1
L1
LM25085A
CURRENT LIMIT
COMPARATOR
GATE
DRIVER
40 PAADJ RADJ
CADJ
40 PA
Q1 L1
D1
GATE
DRIVER
CURRENT LIMIT
COMPARATOR
ISEN
PGATE
VCC
RSEN
+
-+
-
USING Q1 RDS(ON) USING SENSE RESISTOR RSEN
VIN
VIN
VIN VIN
VIN x tON
tOFF
VFD + VESR t
LM25085A
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SNVS601B –JANUARY 2009–REVISED MARCH 2013
The on-time in Equation 9 is shorter than the normal on-time since the PFET is shut off when the current limit
threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 10) is less than
the current increase (Equation 9), the current levels are higher at the start of the next on-time. This results in a
further decrease in on-time, since the current limit threshold is crossed sooner. A balance is reached when the
current changes in Equation 9 and Equation 10 are equal. The worst case situation is that of a direct short circuit
at the output terminals, where VOUT = 0 volts, as that results in the largest current increase during the on-time,
and the smallest decrease during the off-time. The sum of the diode’s forward voltage and the inductor’s ESR
voltage must be sufficient to ensure current runaway does not occur. Using Equation 9 and Equation 10, this
requirement can be stated as:
(11)
For tON in Equation 11 use the minimum on-time at the SW node. To determine this time period add the
“Minimum on-time in current limit” specified in Electrical Characteristics (tON-4) to the difference of the turn-off
and turn-on delays of the PFET. For tOFF use the value in Figure 10, or use Equation 8, where VFB is equal to
zero volts. When using the minimum or maximum limits of those specifications to determine worst case
situations, the tolerance of the minimum on-time (tON-4) and the current limit off-times (tOFF(CL1) through tOFF(CL4))
track each other over the process and temperature variations. A device which has an on-time at the high end of
the range will have an off-time that is at the high end of its range.
Figure 26. Current Limit Sensing
VCC REGULATOR
The VCC regulator provides a regulated voltage between the VIN and the VCC pins to provide the bias and gate
current for the PFET gate driver. The 0.47 µF capacitor at the VCC pin must be a low ESR capacitor, preferably
ceramic as it provides the high surge current for the PFET’s gate at each turn-on. The capacitor must be located
as close as possible to the VIN and VCC pins to minimize inductance in the PC board traces.
Referring to the Figure 7, the voltage across the VCC regulator (VIN – VCC) is equal to VIN until VIN reaches
approximately 8.5V. At higher values of VIN, the voltage at the VCC pin is regulated at approximately 7.7V below
VIN. The VCC regulator has a maximum current capability of at least 20 mA. The regulator is disabled when the
LM25085A is shutdown using the RT pin, or when the thermal shutdown is activated.
PGATE DRIVER OUTPUT
The PGATE pin output swings between VIN (Q1 off) and the VCC pin voltage (Q1 on). The rise and fall times
depend on the PFET gate capacitance and the source and sink currents provided by the internal gate driver. See
Electrical Characteristics for the current capability of the driver.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
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LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
P-CHANNEL MOSFET SELECTION
The PFET must be rated for the maximum input voltage, with some margin above that to allow for transients and
ringing which can occur on the supply line and the switching node. The gate-to-source voltage (VGS) normally
provided to the PFET is 7.7 volts for VIN greater than 8.5V. However, if the circuit is to be operated at lower
values of VIN, the selected PFET must be able to fully turn-on with a VGS voltage equal to VIN. The minimum
input operating voltage for the LM25085A is 4.5V.
Similar to NFETs, the case or exposed thermal pad for a PFET is electrically connected to the drain terminal.
When designing a PFET buck regulator the drain terminal is connected to the switching node. This situation
requires a trade-off between thermal and EMI performance since increasing the PC board area of the switching
node to aid the PFET power dissipation also increases radiated noise, possibly disrupting the circuit operation.
Typically the switching node area is kept to a reasonable minimum and the PFET peak current is derated to stay
within the recommended temperature rating of the PFET. The RDS(ON) of the PFET determines a portion of the
power dissipation in the PFET. However, PFETs with very low RDS(ON) usually have large values of gate charge.
A PFET with a higher gate charge has a corresponding slower switching speed, leading to higher switching
losses and affecting the PFET power dissipation.
If the PFET RDS(ON) is used for current limit detection, note that it typically has a positive temperature coefficient.
At 100°C the RDS(ON) may be as much as 50% higher than the value at 25°C which could result in incorrect
current limiting if not accounted for when determining the value of the RADJ resistor. The PFET Total Gate
Charge determines most of the power dissipation in the LM25085A due to the repetitive charge and discharge of
the PFET’s gate capacitance by the gate driver (powered from the VCC regulator). The LM25085A’s internal
power dissipation can be calculated from the following:
PDISS = VIN x ((QGx FS) + IIN) (12)
where QGis the PFET's Total Gate Charge obtained from its datasheet, FSis the switching frequency, and IIN is
the LM25085A's operating current obtained from Figure 5. Using the Thermal Resistance specifications in the
Electrical Characteristics, the approximate junction temperature can be determined. If the calculated junction
temperature is near the maximum operating temperature of 125°C, either the switching frequency must be
reduced, or a PFET with a smaller Total Gate Charge must be used.
SOFT-START
The internal soft-start feature of the LM25085A allows the regulator to gradually reach a steady state operating
point at power up, thereby reducing startup stresses and current surges. Upon turn-on, when Vcc reaches its
under-voltage lockout threshold, the internal soft-start circuit ramps the feedback reference voltage from 0V to
0.9V, causing VOUT to ramp up in a proportional manner. The soft-start ramp time is typically 1.8 ms.
In addition to controlling the initial power up cycle, the soft-start circuit also activates when the LM25085A is
enabled by releasing the RT pin, and when the circuit is shutdown and restarted by the internal Thermal
Shutdown circuit.
If the voltage at FB is below the regulation threshold value due to an over-current condition or a short circuit at
Vout, the internal reference voltage provided by the soft-start circuit to the regulation comparator is reduced
along with FB. When the over-current or short circuit condition is removed, VOUT returns to the regulated value at
a rate determined by the soft-start ramp. This feature helps prevent the output voltage from over-shooting
following an overload event.
THERMAL SHUTDOWN
The LM25085A should be operated such that the junction temperature does not exceed 125°C. If the junction
temperature increases above that, an internal Thermal Shutdown circuit activates at 170°C (typical) to disable
the VCC regulator and the gate driver, and discharge the soft-start capacitor. This feature helps prevent
catastrophic failures from accidental device overheating. When the junction temperature falls below 150°C
(typical hysteresis = 20°C), the gate driver is enabled, the soft-start circuit is released, and normal operation
resumes.
14 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM25085A
L1 = tON(min) x (VIN(max) - VOUT)
IOR(max) = 5.79 PH
RT = 1 x (12 - 1.56V)
1.45 x 10-7 x 12 x 200 kHz - 1.4= 20.9
(50 ns + 57 ns) x (12 - 1.56V)
1.45 x 10-7
-
LM25085A
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SNVS601B –JANUARY 2009–REVISED MARCH 2013
Applications Information
EXTERNAL COMPONENTS
The procedure for calculating the external components is illustrated with the following design example. Referring
to Block Diagram, the circuit is to be configured for the following specifications:
• VOUT = 1.0V
• VIN = 4.5V to 24V, 12V Nominal
• Maximum load current (IOUT(max)) = 5A
• Minimum load current (IOUT(min)) = 500 mA (for continuous conduction mode)
• Switching Frequency (FSW) = 200 kHz
• Maximum allowable output ripple (VOS) = 10 mVp-p
• Selected PFET: Vishay Si7465
•RFB1 and RFB2:These resistors set the output voltage. The ratio of these resistors is calculated from:
RFB2/RFB1 = (VOUT/0.9V) - 1
For this example, RFB2 / RFB1 = 0.111. Typically, RFB1 and RFB2 should be chosen from standard value
resistors in the range of 1 kΩto 20 kΩwhich satisfy the above ratio. For this example, RFB2 = 1.1 kΩ, and
RFB1 = 10 kΩ.
RT, PFET: Before selecting the RTresistor, the PFET must be selected as its turn-on and turn-off delays
affect the calculated value of RT. For the Vishay Si7465 PFET, the difference of its typical turn-off and turn-on
delays is 57 ns. Using Equation 5 at nominal input voltage, RTcalculates to be:
A standard value 21 kΩresistor is selected. Using Equation 3 the minimum on-time at the PGATE pin, which
occurs at maximum input voltage (24V), is calculated to be 195 ns. This minimum one-shot period is
sufficiently longer than the minimum recommended value of 150 ns. The minimum on-time at the SW node is
longer due to the delay added by the PFET (57 ns). Therefore the minimum SW node on-time is 252 ns at
24V. At the SW node the maximum on-time is calculated to be 1.21 µs at 4.5V.
•L1: The main parameter controlled by the inductor value is the current ripple amplitude (IOR). See Figure 27.
The minimum load current for continuous conduction mode is used to determine the maximum allowable
ripple such that the inductor current’s lower peak does not fall below 0 mA. Continuous conduction mode
operation at minimum load current is not a requirement of the LM25085A, but serves as a guideline for
selecting L1. For this example, the maximum ripple current is:
IOR(max) = 2 x IOUT(min) = 1.0 Amp (13)
If an application’s minimum load current is zero, a good initial estimate for the maximum ripple current
(IOR(max)) is 20% of the maximum load current. The ripple calculated in Equation 13 is then used in the
following equation to calculate L1:
(14)
A standard value 6.8 µH inductor is selected. Using this inductance value, the maximum ripple current
amplitude, which occurs at maximum input voltage, calculates to 0.85 Ap-p. The peak current (IPK) at
maximum load current is 5.43A. However, the current rating of the selected inductor must be based on the
maximum current limit value calculated below.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM25085A
COUT = 0.85A
8 x 200 kHz x 0.01V = 53.1 PF
COUT = IOR(max)
8 x FS x VRIPPLE
ICL(min) = 0.01:
(2.05 k: x 32 PA) - 9 mV = 5.66A
ICL(max) = 0.01:
(2.05 k: x 48 PA) + 9 mV = 10.7A
ICL(nom) = 0.01:
(2.05 k: x 40 PA) = 8.2A
RADJ = 32 PA
6.33A x 0.01: = 1.98 k:
SW Node
IPK
Inductor Current
IOUT
IOR
1/FS
LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
Figure 27. Inductor Current Waveform
•RSEN, RADJ:To achieve good current limit accuracy and avoid over designing the power stage components,
the sense resistor method is used for current limiting in this example. A standard value 10 mΩresistor is
selected for RSEN, resulting in a 50 mV drop at maximum load current, and a maximum 0.25W power
dissipation in the resistor. Since the LM25085A uses peak current detection, the minimum value for the
current limit threshold must be equal to the maximum load current (5A) plus half the maximum ripple
amplitude calculated above:
ICL(min) = 5A + 0.85A/2 = 5.43A
At this current level the voltage across RSEN is 54.3 mV. Adding the current limit comparator offset of 9 mV
(max) increases the required current limit threshold to 6.33A. Using Equation 7 with the minimum value for
the ADJ pin current (32 µA), the required RADJ resistor calculates to:
A standard value 2.05 kΩresistor is selected. The nominal current limit threshold calculates to:
Using the tolerances for the ADJ pin current and the current limit comparator offset, the maximum current limit
threshold calculates to:
The minimum current limit thresholds calculate to:
The load current in each case is equal to the current limit threshold minus half the current ripple amplitude.
The recommended value of 1000 pF for CADJ is used in this example.
•COUT:Since the maximum allowed output ripple voltage is very low in this example (10 mVp-p), the minimum
ripple configuration (R3, C1, and C2 in the Block Diagram) must be used. The resulting ripple at VOUT is then
due to the inductor’s ripple current passing through COUT. This capacitor’s value can be selected based on the
maximum allowable ripple voltage at VOUT, or based on transient response requirements. The following
calculation, based on ripple voltage, provides a first order result for the value of COUT:
where IOR(max) is the maximum ripple current calculated above, and VRIPPLE is the allowable ripple at VOUT.
A 68 µF capacitor is selected. Typically the ripple amplitude will be higher than the calculations indicate due
to the capacitor’s ESR.
•R3, C1, C2: The minimum ripple configuration uses these three components to generate the ripple voltage
required at the FB pin since there is insufficient ripple at VOUT. A minimum of 25 mVp-p must be applied to
the FB pin to obtain stable constant frequency operation. R3 and C1 are selected to generate a sawtooth
waveform at their junction, and that waveform is AC coupled to the FB pin via C2. The values of the three
16 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM25085A
CIN + CBYP = IOUT(max) x tON(max)
'V= 24.2 PF
5A x 1.21 Ps
0.25V
=
R3 x C1 = (4.5V ± 0.49V) x 1.21 Ps
0.03V = 1.62 x 10-4
R3 x C1 = (VIN(min) - VA) x tON
'V
LM25085A
www.ti.com
SNVS601B –JANUARY 2009–REVISED MARCH 2013
components are determined using the following procedure:
Calculate VA= VOUT - (VSW x (1 – (VOUT/VIN(min))))
where VSW is the absolute value of the voltage at the SW node during the off-time, typically 0.5V to 1V
depending on the diode D1. Using a typical value of 0.65V, VAcalculates to 0.49V. VAis the nominal DC
voltage at the R3/C1 junction, and is used in the next equation:
where tON is the maximum on-time (at minimum input voltage), and ΔV is the desired ripple amplitude at the
R3/C1 junction, typically 30 mVp-p. For this example
R3 and C1 are then selected from standard value components to produce the product calculated above.
Typical values for C1 are 3000 pF to 10,000 pF, and R3 is typically from 10 kΩto 300 kΩ. C2 is then chosen
large compared to C1, typically 0.1 µF. For this example, 3300 pF is chosen for C1, requiring R3 to be 48.9
kΩ. A standard value 48.7 kΩresistor is selected.
•CIN, CBYP:These capacitors limit the voltage ripple at VIN by supplying most of the switch current during the
on-time. At maximum load current, when Q1 is switched on, the current through Q1 suddenly increases to the
lower peak of the inductor’s ripple current, then ramps up to the upper peak, and then drops to zero at turn-
off. The average current during the on-time is the load current. For a worst case calculation, these capacitors
must supply this average load current during the maximum on-time, while limiting the voltage drop at VIN. For
this example, 0.25V is selected as the maximum allowable droop at VIN. Their minimum value is calculated
from:
A 33 µF electrolytic capacitor is selected for CIN, and a 1 µF ceramic capacitor is selected for CBYP. Due to
the ESR of CIN, the ripple at VIN will likely be higher than the calculation indicates, and therefore it may be
desirable to increase CIN to 47 µF or 68 µF. CBYP must be located as close as possible to the VIN and GND
pins of the LM25085A. The voltage rating for both capacitors must be at least 24V. The RMS ripple current
rating for the input capacitors must also be considered. A good approximation for the required ripple current
rating is IRMS > IOUT/2.
•D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW pin may affect the regulator’s operation due to the diode’s reverse recovery transients.
The diode must be rated for the maximum input voltage, and the worst case current limit level. The average
power dissipation in the diode is calculated from:
PD1 = VFx IOUT x (1-D)
where VFis the diode’s forward voltage drop, and D is the on-time duty cycle. Using Equation 1, the minimum
duty cycle occurs at maximum input voltage, and is calculated to be ≊4.2% in this example. The diode power
dissipation calculates to be:
PD1 = 0.65V x 5A x (1- 0.042) = 3.11W
•CVCC:The capacitor at the VCC pin (from VIN to VCC) provides not only noise filtering and stability for the
VCC regulator, but also provides the surge current for the PFET gate drive. The typical recommended value
for CVCC is 0.47 µF. A good quality, low ESR, ceramic capacitor is recommended. CVCC must be located as
close as possible to the VIN and VCC pins. If the selected PFET has a Total Gate Charge specification of
100 nC or larger, or if the circuit is required to operate at input voltages below 7 volts, a larger capacitor may
be required. The maximum recommended value for CVCC is 1 µF.
•IC Power Dissipation: The maximum power dissipated in the LM25085A package is calculated using
Equation 12 at the maximum input voltage. The Total Gate Charge for the Si7465 PFET is specified to be 40
nC (max) in its data sheet. Therefore the total power dissipation within the LM25085A is calculated to be:
PDISS = 24V x ((40 nC x 200 kHz) + 1.25 mA) = 222 mW
Using an HVSSOP-PowerPAD-8 package with a θJA of 46°C/W produces a temperature rise of 10°C from
junction to ambient.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM25085A
4.5V to 24V
Input
VIN
GND
SHUTDOWN
CIN
33 PF
CBYP
1 PF
RT
21 k:
GND FB
PGATE
ISEN
ADJ
VCC
CVCC
0.47 PF
CADJ 1000 pF
RADJ
2.05 k:
RSEN
0.01:
L1 6.8 PH
Q1
D1
VOUT
COUT
GND
C1
3300 pF
C2
0.1 PF
R3
48.7 k:
1.0V
68 PF
RFB1
10 k:
RFB2
1.1 k:
RT
VIN
LM25085A
LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
Final Design Example Circuit
The final circuit is shown in Figure 28, and its performance is presented in Figure 29 through Figure 32. The
measured efficiencies shown in Figure 29 are typical for a buck converter producing a low output voltage (1V).
Figure 28. Example Circuit
Figure 29. Efficiency vs. Load Current and VIN (Circuit of Figure 28)
18 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM25085A
LM25085A
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SNVS601B –JANUARY 2009–REVISED MARCH 2013
Figure 30. Frequency vs. VIN (Circuit of Figure 28)
Figure 31. Current Limit vs. VIN (Circuit of Figure 28)
Figure 32. LM25085A Power Dissipation (Circuit of Figure 28)
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM25085A
R4 = VRIP(min)
IOR(min)
FB
LM25085A
PGATE
GND
Q1 L1
Cff
COUT
RFB2
RFB1
VOUT
GND
D1 R4
Cff = 3 x tON(max)
(RFB1//RFB2)
R4 = 25 mV
IOR(min)
LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
Alternate Output Ripple Configurations
The minimum ripple configuration, using C1, C2 and R3, used in the example circuit Figure 28, results in a low
ripple amplitude at VOUT determined mainly by the characteristics of the output capacitor and the ripple current in
L1. This configuration allows multiple ceramic capacitors to be used for VOUT if the output voltage is provided to
several places on the PC board. However, if a slightly higher level of ripple at VOUT is acceptable in the
application, and distributed capacitance is not used, the ripple required for the FB comparator pin can be
generated with fewer external components using the circuits shown below.
Reduced ripple configuration: In Figure 33, R3, C1 and C2 are removed (compared to Figure 28). A low value
resistor (R4) is added in series with COUT, and a capacitor (Cff) is added across RFB2. Ripple is generated at
VOUT by the inductor’s ripple current flowing through R4, and that ripple voltage is passed to the FB pin via Cff.
The ripple at VOUT can be set as low as 25 mVp-p since it is not attenuated by RFB2 and RFB1. The minimum
value for R4 is calculated from:
where IOR(min) is the minimum ripple current, which occurs at minimum input voltage. The minimum value for Cff
is determined from:
where tON(max) is the maximum on-time, which occurs at minimum VIN. The next larger standard value capacitor
should be used for Cff.
Figure 33. Reduced Ripple Configuration
b) Lowest cost configuration: This configuration, shown in Figure 34, is the same as Figure 33 except Cff is
removed. Since the ripple voltage at VOUT is attenuated by RFB2 and RFB1, the minimum ripple required at VOUT is
equal to:
VRIP(min) = 25 mV x (RFB2 + RFB1)/RFB1
The minimum value for R4 is calculated from:
where IOR(min) is the minimum ripple current, which occurs at minimum input voltage.
20 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM25085A
FB
LM25085A
PGATE
GND
Q1 L1
COUT
RFB2
RFB1
VOUT
GND
D1 R4
LM25085A
www.ti.com
SNVS601B –JANUARY 2009–REVISED MARCH 2013
Figure 34. Lowest Cost Ripple Generating Configuration
PC Board Layout
In most applications, the heat sink pad or tab of Q1 is connected to the switch node, i.e. the junction of Q1, L1
and D1. While it is common to extend the PC board pad from under these devices to aid in heat dissipation, the
pad size should be limited to minimize EMI radiation from this switching node. If the PC board layout allows, a
similarly sized copper pad can be placed on the underside of the PC board, and connected with as many vias as
possible to aid in heat dissipation.
The voltage regulation, over-voltage, and current limit comparators are very fast and can respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible with all the components as close as possible to their associated pins. Two
major current loops conduct currents which switch very fast, requiring the loops to be as small as possible to
minimize conducted and radiated EMI. The first loop is that formed by CIN, Q1, L1, COUT, and back to CIN. The
second loop is that formed by D1, L1, COUT, and back to D1. The connection from the anode of D1 to the ground
end of CIN must be short and direct. CIN must be as close as possible to the VIN and GND pins, and CVCC must
be as close as possible to the VIN and VCC pins.
If the anticipated internal power dissipation of the LM25085A will produce excessive junction temperatures during
normal operation, a package option with an exposed pad must be used (HVSSOP-PowerPAD-8 or WSON-8).
Effective use of the PC board ground plane can help dissipate heat. Additionally, the use of wide PC board
traces, where possible, helps conduct heat away from the IC. Judicious positioning of the PC board within the
end product, along with the use of any available air flow (forced or natural convection) also helps reduce the
junction temperature.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM25085A
LM25085A
SNVS601B –JANUARY 2009–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 21
22 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM25085A
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM25085AMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVZA
LM25085AMME/NOPB ACTIVE VSSOP DGK 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVZA
LM25085AMMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVZA
LM25085AMY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVYA
LM25085AMYE/NOPB ACTIVE HVSSOP DGN 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVYA
LM25085AMYX/NOPB ACTIVE HVSSOP DGN 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SVYA
LM25085ASD/NOPB ACTIVE WSON NGQ 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L246A
LM25085ASDE/NOPB ACTIVE WSON NGQ 8 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L246A
LM25085ASDX/NOPB ACTIVE WSON NGQ 8 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L246A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM25085AMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085AMME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085AMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085AMY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085AMYE/NOPB HVSSOP DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085AMYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM25085ASD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LM25085ASDE/NOPB WSON NGQ 8 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LM25085ASDX/NOPB WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM25085AMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM25085AMME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0
LM25085AMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LM25085AMY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0
LM25085AMYE/NOPB HVSSOP DGN 8 250 210.0 185.0 35.0
LM25085AMYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0
LM25085ASD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0
LM25085ASDE/NOPB WSON NGQ 8 250 210.0 185.0 35.0
LM25085ASDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
8X 0.3
0.2
2 0.1
8X 0.5
0.3
2X
1.5
1.6 0.1
6X 0.5
0.8
0.7
0.05
0.00
B3.1
2.9 A
3.1
2.9
(0.1) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1.6)
6X (0.5)
(2.8)
8X (0.25)
8X (0.6)
(2)
(R0.05) TYP ( 0.2) VIA
TYP
(0.75)
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
SYMM
1
45
8
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
8X (0.25)
8X (0.6)
6X (0.5)
(1.79)
(1.47)
(2.8)
(R0.05) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
45
8
SYMM
METAL
TYP
9
www.ti.com
PACKAGE OUTLINE
C
6X 0.65
2X
1.95
8X 0.38
0.25
5.05
4.75 TYP
SEATING
PLANE
0.15
0.05
0.25
GAGE PLANE
0 -8
1.1 MAX
0.23
0.13
1.88
1.58
2.0
1.7
B3.1
2.9
NOTE 4
A
3.1
2.9
NOTE 3
0.7
0.4
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
1
4
5
8
0.13 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
PowerPAD is a trademark of Texas Instruments.
TM
A 20
DETAIL A
TYPICAL
SCALE 4.000
EXPOSED THERMAL PAD
1
45
8
9
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(2)
NOTE 9
(3)
NOTE 9
(1.22)
(0.55)
( 0.2) TYP
VIA
(1.88)
(2)
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SYMM
SYMM
1
45
8
SOLDER MASK
DEFINED PAD
METAL COVERED
BY SOLDER MASK
SEE DETAILS
9
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(1.88)
BASED ON
0.125 THICK
STENCIL
(2)
BASED ON
0.125 THICK
STENCIL
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
1.59 X 1.690.175 1.72 X 1.830.15 1.88 X 2.00 (SHOWN)0.125 2.10 X 2.240.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
SYMM
SYMM
1
45
8
METAL COVERED
BY SOLDER MASK SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
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