DS80C410-FNY+ - Maxim Integrated

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Note: Some revisi ons of this device may incorporate deviations from published specificat i ons known as errata. Multi pl e revisi ons of any device

may be simultaneously avail abl e through various sal es channels. For information about device errata, click here: www.maxim-ic.com/errata.

GENERAL DESCRIPTION

The DS80C410/DS80C411 network microcontrollers offer

the highest integration available in an 8051 device.

Peripherals include a 10/100 Ethernet MAC, three serial

ports, an optional CAN 2.0B controller, 1-Wire® Master,

and 64 I/O pins. The DS80C410 and DS80C411 also

include 64kBytes internal SRAM for user application

storage and network stack.

To enable access to the network, a full application-

accessible TCP IPv4/6 network stack and OS are provided

in the ROM. The network stack supports up to 32

simultaneous TCP connections and can transfer up to

5Mbps through the Ethernet MAC. Its maximum system-

clock frequency of 75MHz results in a minimum instruction

cycle time of 54ns. Access to large program or data

memory areas is simplified with a 24-bit addressing

scheme that supports up to 16MB of contiguous memory.

To accelerate data transfers between the microcontroller

and memory, the DS80C410 and DS80C411 provide four

data pointers, each of which can be configured to

automatically increment or decrement upon execution of

certain data pointer-related instructions. High-speed shift,

normalization, accumulate functions and 32-bit/16-bit

multiply and divide operations are optimized by the

DS80C410/DS80C411 hardware math accelerator.

The High-Speed Microcontroller User’s Guide and the Hi gh-Speed

Microcontrol l er User’s Guide: Netw ork Mic rocontroller Supplement

should be used in conjunction with this data sheet. Download

both at: www.maxim-ic.com/user_guides.

APPLICATIONS

Industrial Control/Automation

Data Converters (Serial-to-

Ethernet, CAN-to-

Ethernet)

Environmental Monitoring

Network Sensors

Vending

Remote Data-Collection

Equipment

Home/Office Automation

Transaction/Payment

Terminals

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

Magic Packet is a registered trademark of Advanced Mic ro

Devices, Inc.

FEATURES

 High-Performance Architecture

Single 8051 Instruction Cycle in 54ns

DC to 75MHz Clock Rate

Flat 16MB Address Space

Four Data Pointers with Auto-Increment/

Decrement and Sele ct-Accelerate Data Movement

16/32-Bit Math Accelerator

 Multitiered Networking and I/O

10/100 Ethernet Media Access Controller (MAC)

Optional CAN 2.0B Controller

1-Wire Net Controller

Three Full-Duplex Hardware Serial Ports

Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O Pins)

 Robust ROM Firmware

Supports Network Boot Over Ethernet Using DHCP and

TFTP

Full, Application-Accessible TCP/IP Network Stack

Supports IPv4 and IPv6

Implements UDP, TCP, DHCP, ICMP, and IGMP

Preemptive, Priority-Based Task Scheduler

MAC Address can Optionally be Acquired from IEEE-

Registered DS2502-E48

 10/100 Ethernet Mac

Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC

(10Mbps) Interfaces Allow Selection of PHY

Low-Power Operation

Ultra-Low-Power Sleep Mode with Magic Packet®

and Wake-Up Frame Detection

8kB On-Chip Tx/Rx Packet Data Memory with Buffer

Control Unit Reduces Load on CPU

Half- or Full-Duplex Operation with Flow Control

Multicast/Broadcast Address Filtering with VLAN

Support

Features continued on page 34.

Pin Configuration appears at end of data sheet.

Selector Guide appears at end of data sheet.

ORDERING INFORMATION

PART TE MP RANGE PIN-PACKAGE

DS80C410-FNY -40°C to +85°C 100 LQFP

DS80C410-FNY+ -40°C to +85°C 100 LQFP

DS80C411-FNY -40°C to +85°C 100 LQFP

DS80C411-FNY+ -40°C to +85°C 100 LQFP

+Denotes a lead(Pb)-free/RoHS-compliant device.

19-4659; Rev 5; 4/15

DS80C410/DS80C411

Network Microcontrollers with

Ethern e t a nd CAN

DS80C41 0/D S80 C41 1 Net wor k Microcontroll ers with Ethernet and CAN

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Input Pin Relative to Ground………………………………………………………..-0.5V to +5.5V

Voltage Range on Any Output Pin Relative to Ground……………………………………………..-0.5V to (VCC3 + 0.5V)

Voltage Range on VCC3 Relative to Ground…………………………………………………………………..-0.5V to +3.6V

Voltage Range on VCC1 Relative to Ground…………………………………………………………………..-0.3V to +2.0V

Operating Temperature Range………………………………………………………………………………..-40°C to +85°C

Junction Temperature……………………………………………………………………………………………..+150°C max

Storage Temperature Range………………………………………………………………………………...-55°C to +160°C

Soldering Temperature………………………………………………………………See IPC/JEDEC J-STD-020 Standard

Stresses beyond those listed under “Abs ol ute Maximum Ratings” may caus e permanent damage to the device. Thes e are stress rati ngs only,

and functional operat i on of the device at these or any other conditions beyond t hose indic ated in the operational sections of the specifications is

not implied. Exposure to absolut e maximum rating conditions f or extended periods can affect device reliabil i ty .

DC ELECTRICAL CHARACTERISTICS

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL MIN TYP MAX UNITS

VCC3

Supply Voltage (VCC3) (Note 2)

VCC3

3.0

3.3

3.6

Power-F ail War ning (VCC3) (Note 3)

VPFW3

2.85

3.00

3.15

Power-Fail Reset Voltage (VCC3) (Note 3)

VRST3

2.76

2.90

3.05

Active Mode Current (VCC3) (Note 4)

ICC3

Idle Mode Current (VCC3) (Note 4)

IIDLE3

Stop Mode Current (VCC3) (Not 4)

ISTOP3

Stop Mode Current, Bandgap Enabled (V

CC3

) (Note 4)

SPBG3

100

150

VCC1

Supply Voltage (VCC1) (Note 2)

VCC1

1.62

1.8

1.98

Power-F ail War ning (VCC1) (Note 5)

VPFW1

1.52

1.60

1.68

Power-Fail Reset Voltage (VCC1) (Note 5)

VRST1

1.47

1.55

1.63

Active Mode Current (VCC1) (Note 4)

ICC1

Idle Mode Current (VCC1) (Note 4)

IIDLE1

Stop Mode Current (VCC1) (Note 4)

ISTOP1

Stop Mode Current, Bandgap Enabled (V

CC1

) (Note 4)

SPBG1

Input Low Level

VIL1

0.8

Input Low Level for XTAL1, RST, OW

VIL2

1.0

Input High Level

VIH1

2.0

Input High Level for XTAL1, RST, OW

VIH2

2.4

Output Low Current for Port 1, 3–7 at VOL = 0.4V

IOL1

Output Low Current for Port 0, 2, TX_EN, TXD[3:0], MDC, MDIO,

RSTOL, ALE, PSEN, and Ports 3–7 (when used as any of the following:

A21–A0,

CE0-7

PCE0-3

) at VOL = 0.4V (Note 6)

IOL2 12 20 mA

Output Low Current for OW,

OWSTP

at VOL= 0.4V

IOL3

Output High Current for Port 1, 3–7 at V

= V

CC3

- 0.4V (Note 7)

OH1

-75

-50

Output High Current for Port 1, 3–7 at VOH= VCC3 - 0.4V (Note 8)

IOH2

-8

-4

Output High Current for Port 0, 2, TX_EN, TXD[3:0], MDC, MDIO,

RSTOL, ALE, PSEN, and Ports 3–7 (when used as any of the following:

A21–A0, WR, RD, CE0-7, PCE0-3) at VOH = VCC3 - 0.4V (Notes 6, 9) IOH3 -16 -8 mA

Input Low Current for Port 1–7 at 0.4V (Note 10)

IIL

-50

-20

-10

Logic 1-to-0 Transition Current for Port 1, 3–7 (Note 11)

ITL

-650

-400

Input Leakage Current, Port 0 Bus Mode, V

= 0.8V (Note 12)

TH0

200

Input Leakage Current, Port 0 Bus Mode, V

= 2.0V (Note 12)

TL0

-200

-50

-20

Input Leakage Current, Input Mode (Note 13)

-10

RST Pulldown Resistance

RRST

100

200

Ω

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Note 1:

Specifications to -40°C are guaranteed by design and not production tested.

Note 2: The user should note that this part is t est ed and guaranteed t o operate down to VCC3 = 3.0V and VCC1 = 1.62V, while the reset

thresholds f or those supplies, VRST3 and VRST1 respectively, may be above or below those points. When the reset threshold for a

given supply is greater than the guaranteed minim um operat i ng voltage, that res et threshol d should be considered the minim um

operating point si nce executi on ceases once the part enters the reset stat e. When the reset threshold for a given suppl y is lower

than the guaranteed minimum operating vol t age, t here exists a range of voltages for either supply, ( VRST3 < VCC3 < 1.62V) or (VRST1

< VCC1 < 3.0V), where the processor’s operation is not guaranteed, and the reset trip point has not been reached. This should not

be an issue in most applications, but should be considered when proper operation m ust be maintained at all times. For these

applicat i ons, it may be desirable to use a more accurate external reset.

Note 3: While t he s pecificati ons for VPFW3 and VRST3 overlap, the design of the hardware makes it such that this is not possible. W i thin the

ranges given, there is a guaranteed separat i on between these two voltages.

Note 4: Current measured with 75MHz clock s ource on XTAL1, VCC3 = 3.6V, VCC1 = 2.0V, EA and RST = 0V, Port0 = VCC3, all other pins

disconnected.

Note 5: While t he s pecificati ons for VPFW1 and VRST1 overlap, the design of the hardware makes it such that this is not possible. W i t hi n the

ranges given, there will be a guaranteed separat i on between these two voltages.

Note 6: Certain pins exhibit stronger dri ve c apabi l i t y when being used to address external m emory. These pins and ass oci ated memory

interfac e funct ion (in parentheses) are as follows: Port 3.6-3.7 (WR, RD), Port 4 (CE0-3, A16-A 19), Port 5. 4-5.7 (PCE0-3), Port 6.0-

6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).

Note 7: This measurement reflect s t he weak I/O pullup state that persists following the moment ary strong 0 to 1 port pin drive (VOH2). This

I/O pin state can be achieved by applying RST = VCC3.

Note 8: The measurement reflects the mom entary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot

circuit dri ves the ports hard for two clock cycles. A weak pullup device (VOH1) remains in effect following the strong two-cloc k cycle

drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contai ns a 1, changing the pin to an I/O

mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.

Note 9: Port 3 pins 3.6 (WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition

of either

from a 0 to a 1.

Note 10: This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set

to 1. This is only the current required to hold the low level; transiti ons from 1 to 0 on an I/O pin also have to overcome the transition

current.

Note 11: Following the 0 to 1 one-shot timeout, ports in I/O mode source transition c urrent when being pulled down externally. It reaches a

maximum at approximately 2V.

Note 12: During external addressing m ode, weak latc hes are used to maintain the previous l y driven state on the pin until such time that the

Port 0 pin is driven by an external memory source.

Note 13: The OW pin (when configured to output a 1) at VIN = 5.5V, EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],

CRS, COL, MDIO ) at VIN = 3.6V.

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AC ELECTRICAL CHARACTERISTICS (MULTIPLEXE D AD DRESS/DATA BUS)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL

75MHz

VARIABLE CLOCK

UNITS

MIN

MAX

MIN

MAX

External Crystal Frequency 1 / tCLK

4 40 MHz

Clock Mutliplier 2X Mode

Clock Multiplier 4X Mode 16 37.5

11 18.75

External Clock Oscillator Frequency 1 / tCLK DC 75 MHz Clock Mutlip lier 2X Mode 16 37.5

Clock Multip lier 4X Mode 11 18.75

ALE Pulse Width tLHLL 15.0 tCLCL + tCHCL - 5 ns

Port 0 Instruction Address Valid to ALE Low tAVLL 1.7 tCHCL - 5 ns

Address Hold After ALE Low tLLAX 4.7 tCLCH - 2 ns

ALE Low to Valid Instruction In tLLIV 14.3 2tCLCL + tCLCH - 19 ns

ALE Low to PSEN Low tLLPL 3.7 tCLCH - 3 ns

PSEN Pulse Width tPLPH 21.7 2tCLCL - 5 ns

PSEN Low to Valid Instruction In tPLIV 8.7 2tCLCL -18 ns

Input Instruction Hold After PSEN tPXIX 0 0 ns

Input Instruction Float After PSEN tPXIZ 8.3 tCLCL - 5 ns

Port 0 Address to Valid Instruction In tAVIV0 21.0 3tCLCL - 19 ns

Port 2, 4, 6 Address or Port 4 CE to Valid

Instruction In tAVIV2 24.7 3tCLCL + tCLCH - 22 ns

PSEN Low to Address Float tPLAZ 0 0 ns

Note 1: AC electrical characteri st ic s assume 50% duty cycle for the oscill ator, osci l l ator frequency ≤ 75MHz, and are not 100% production

tested, but are guaranteed by design.

Note 2:

All parameters apply to both comm ercial and indust ri al tem perature operation, unless otherwise noted.

Note 3: tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external cl ock (tCLK) as defined in

the External Clock Oscil l ator (XTAL1) Charact erist ic s table.

Note 4:

The precalculat ed 75MHz MIN/MAX timi ng specific ati ons assume an exact 50% dut y cycle.

Note 5: All signals guaranteed with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following

signals, when configured f or memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7 (

PCE0-3

), Port 6.0–6.5 (

CE4-7,

A20, A21), Port 7 (demultiplexed mode A0–A7).

Note 6: For high-frequency operat i on, s pecial att ention shoul d be pai d to the float times of the interfaced memory devices so as to avoid

bus contention.

Note 7: References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determini ng the relative occurrence of events, not

for determing absol ute signal timing with respect to t he external clock.

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EXTERNAL CLOCK OSCILLATOR (XTAL1) CHARACTERISTICS

PARAMETER

SYMBOL

MIN

MAX

UNITS

Clock Oscillator Period tCLK

See External Clock

Oscillator Frequency

Clock Symmetry at 0.5 x VCC3

tCH

0.45 tCLK

0.55 tCLK

Clock Rise Time

tCR

Clock Fall Time

tCF

EXTERNAL CLOCK DRIVE

SYSTEM CLOCK TIME PERIODS (tCLCL, tCHCL, tCLCH)

SYSTEM CLOCK SELECTION SYSTEM CLOCK

PERIOD tCLCL

SYSTEM CLOCK HIGH (t

CHCL

) AN D

SYSTEM CLOCK LOW (tCLCH)

4X/2X

CD1

CD0

MIN

MAX

tCLK / 4

0.45 (tCLK / 4)

0.55 (tCLK / 4)

tCLK / 2

0.45 (tCLK / 2)

0.55 (tCLK / 2)

tCLK

0.45 tCLK

0.55 tCLK

256 tCLK

0.45 (256 tCLK)

0.55 (256 tCLK)

Note 1: Figure 21 shows a detailed descripti on and ill ust ration of t he system clock select i on.

Note 2: When an external clock oscillat or is used in conjuncti on with the default system clock sel ect i on (CD1:CD0 = 10b), the

minimum/maxi mum system clock high (tCHCL) and system clock low (tCLCH) periods are di rect l y related to clock oscillat or duty cycle.

MOVX CHARACTERISTICS (M ULTIPLEXED ADDRESS/DATA BUS) (Note 1)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40 °C to +85°C.)

PARAMETER SYMBOL MIN MAX UNITS

STRETCH VALUES

CST (MD2:0)

MOVX ALE Pulse Width tLHLL2

tCLCL + tCHCL - 5

CST = 0

2tCLCL - 5

1≤ CST ≤ 3

6tCLCL - 5

4 ≤ CST ≤ 7

Port 0 MOVX Address Valid

to ALE Low tAVLL2

tCHCL - 5

CST = 0

tCLCL - 6

1≤ CST ≤ 3

5tCLCL - 6

4 ≤ CST ≤ 7

Port 0 MOVX Address Hold

after ALE Low tLLAX2

and tLLAX3

tCLCH - 2

CST = 0

tCLCL - 2

1≤ CST ≤3

5tCLCL - 2

4 ≤ CST ≤ 7

RD Pulse Width (P3.7 or

PSEN)

tRLRH

2tCLCL - 5

CST = 0

(4 x CST) tCLCL - 3

1 ≤ CST ≤ 7

WR Pulse Width (P3.6) tWLWH

2tCLCL - 5

CST = 0

(4 x CST) tCLCL - 3

1 ≤ CST ≤ 7

RD (P3.7 or PSEN) Low to

Valid Data In

tRLDV

2tCLCL - 18

CST = 0

(4 x CST) tCLCL - 18

1 ≤ CST ≤ 7

Data Hold After RD (P3. 7 or

PSEN) High

tRHDX -2 ns

Data Float After RD (P3.7 or

tRHDZ

tCLCL - 5

CST = 0

CLK

XTAL1

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PARAMETER SYMBOL MIN MAX UNITS

STRETCH VALUES

CST (MD2:0)

PSEN) High

2tCLCL - 5

1≤ CST ≤ 3

6tCLCL - 5

4 ≤ CST ≤ 7

ALE Low to Valid Data In tLLDV

2tCLCL + tCLCH - 19

CST = 0

(4 x CST + 1) tCLCL - 19

1≤ CST ≤ 3

(4 x CST + 5) tCLCL - 19

4 ≤ CST ≤ 7

Port 0 Address to Valid Data

In tAVDV0

3tCLCL - 19

CST = 0

(4 x CST + 2)tCLCL - 19

1≤ CST ≤ 3

(4 x CST + 10)tCLCL - 20

4 ≤ CST ≤ 7

Port 2, 4, 6 Address, Port 4

CE, or Port 5 PCE to Valid

Data In tAVDV2

3tCLCL + tCLCH - 22

CST = 0

(4 x C

+ 2)t

CLCL

+ t

CLCH

1≤ CST ≤ 3

(4 x C

+ 10)t

CLCL

+ t

CLCH

4 ≤ CST ≤ 7

ALE Low to (RD or PSEN) or

WR Low tLLWL

tCLCH - 3

tCLCH + 6

CST = 0

tCLCL - 3

tCLCL + 6

1 ≤ CST ≤ 3

5tCLCL - 3

5tCLCL + 6

4 ≤ CST ≤ 7

Port 0 Address to (RD or

PSEN) or WR Low tAVWL0

tCLCL – 6.5

CST = 0

2tCLCL – 6.5

1 ≤ CST ≤ 3

10tCLCL – 7

4 ≤ CST ≤ 7

Port 2, 4 Address, Port 4 CE,

Port 5 PCE, to (RD or PSEN

)

Low

tAVWL2

tCLCL + tCLCH - 7

CST = 0

2tCLCL + tCLCH - 7

1 ≤ CST ≤ 3

10tCLCL + tCLCH - 7

4 ≤ CST ≤ 7

Data Valid to WR Transition

tQVWX

Data Hold After WR High tWHQX

tCLCL - 5

CST = 0

2CLCL - 8

1 ≤ CST ≤ 3

6tCLCL - 8

4 ≤ CST ≤ 7

RD Low to Address Float

tRLAZ

(Note 2)

0≤ CST ≤ 7

(RD or PSEN) or WR High to

ALE tWHLH

-2.5

CST = 0

tCLCL – 2.5

tCLCL + 6

1 ≤ CST ≤ 3

5tCLCL – 2.5

5tCLCL + 6

4 ≤ CST ≤ 7

(RD or PSEN) or WR High to

Port 4 CE or Port 5 PCE

High

tWHLH2

tCHCL -5

tCHCL + 13

CST = 0

tCLCL + tCHCL - 5

tCLCL + tCHCL + 13

1 ≤ CST ≤ 3

5tCLCL + tCHCL - 5

5tCLCL + tCHCL + 13

4 ≤ CST ≤ 7

Note 1: AC electrical characteristic s assume 50% duty cycle for the oscill ator, osci l l ator frequency ≤ 75MHz, and are not 100% production

tested, but are guaranteed by design.

Note 2:

For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.

Note 3:

All parameters apply to both comm ercial and indust ri al tem perat ure operation, unless otherwise noted.

Note 4: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL , tCLCH , tCHCL are time

periods associat ed with the internal system clock and are related to the external clock. See the System Clock Time Periods table.

Note 5: All signals characteri zed with load capac itance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. T he foll owing

signals, when configured f or memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7

(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demulti plexed mode A0–A7).

Note 6: References to the XTAL, XTAL1 or CLK signal in the timing diagrams are to assist in determi ning the relati ve occ urrence of events,

not for determining absol ute signal timing with respect to the external c l ock.

7 of 102

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MULTIPLEXED, 2-CYCLE DATA MEMORY

PCE0-3

READ

9 of 102

MULTIPLEXED, 2-CYCLE DATA MEMORY

CE0-7

READ

PO R T 4

–

3CE0−

PORT 4/6 ADDRESS

PO R T 6

–

7−

CE4

A16 -A21

PO R T 4

–

3CE0−

PO R T 6

–

7−

CE4

PORT 4/6 ADDRESS

A16 -A21

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MULTIPLEXED, 2-CYCLE DATA MEMORY

CE0-7

WRITE

MULTIPLEXED, 3-CYCLE DATA MEMORY

PCE0-3

READ OR WRITE

PO R T 4 –

3CE0−

PO R T 6

–

−

CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 4

–

3CE0−

PO R T 6 –

7−CE4

PORT 4/6 ADDRESS

A16 -A21

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MULTIPLEXED, 3-CYCLE DATA MEMORY

CE0-7

READ

MULTIPLEXED, 3-CYCLE DATA MEMORY

CE0-7

WRITE

PO R T 4

–

3CE0−

PO R T 6

–

−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 4

–

CE0−

PO R T 6

–

7−CE4

PORT 4/6 ADDRESS

A16 -A21

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MULTIPLEXED, 9-CYCLE DATA MEMORY

PCE0-3

READ OR WRITE

MULTIPLEXED, 9-CYCLE DATA MEMORY

CE0-7

READ

PO R T 4

–

3CE0−

PO R T 6

–

7−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 4 –

CE0−

PO R T 6

–

7−CE4

PO R T 4/6

ADDRESS

A16 -A21

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MULTIPLEXED, 9-CYCLE DATA MEMORY

CE0-7

WRITE

PO R T 4

–

3CE0−

PO R T 6 –

−

CE4

PORT 4/6

ADDRESS

A16 -A21

14 of 102

ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL

75MHz

VARIABLE CLOCK

UNITS

MIN

MAX

MIN

MAX

External Crystal Frequency 1 / tCLK 4 40 MHz Clock Mutliplier 2X Mode 16 37.5

Clock Multiplier 4X Mode 11 18.75

External Oscillator Frequency 1 / tCLK DC 75 MHz Clock Mutliplier 2X Mode 16 37.5

Clock Multiplier 4X Mode 11 18.75

PSEN Pulse Width tPLPH 21.7 2tCLCL - 5 ns

PSEN Low to Valid Instruction In tPLIV 8.7 2tCLCL - 18 ns

Input Instruction Hold After PSEN tPXIX 0 0 ns

Input Instruction Float After PSEN tPXIZ See MOVX

Characteristics ns

Port 7 Address to Valid Instruction In tAVIV1 21.0 3tCLCL - 19 ns

Port 2, 4, 6 Address or Port 4 CE to Valid

Instruction In tAVIV2 24.7 3tCLCL + tCLCH - 22 ns

Note 1: AC electrical characteristic s assume 50% duty cycle for the oscill ator, osci l l ator frequency ≤ 75MHz, and are not 100% production

tested, but are guaranteed by design.

Note 2:

All parameters apply to both comm ercial and indust ri al tem perat ure operation, unless otherwise noted.

Note 3: tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external cl ock (tCLK) as defined in

the System Clock Time Periods table.

Note 4:

The precalculat ed 75MHz min/max tim i ng specifications assume an exact 50% duty cycle.

Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following

signals, when configured f or memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7

(

PCE0-3

), Port 6.0–6.5 (

CE4-7

, A20, A21), Port 7 (demul t i plexed mode A0–A7).

Note 6: References to the XTAL, XTAL1, or CLK signal in the timing diagrams are to assist in determining the relative occurrenc e of events,

not for determining absol ute signal timing with respect to the external c l ock.

15 of 102

MOVX CHARACTERISTICS (NONM ULTIPLEX ED ADDRESS/D ATA BUS)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V +±10%, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL MIN MAX UNITS

STRETCH

VALUES

CST (MD2:0)

Input Instruction Float After PSEN tPXIZ

2tCLCL - 5

CST = 0

3tCLCL - 5

1≤ CST ≤ 3

11tCLCL - 5

4 ≤ CST ≤ 7

PSEN High to Data Address, Port 4 CE,

Port 5 PCE Valid tPHAV tCHCL - 3 ns

RD Pulse Width (P3.7 or PSEN) tRLRH

2tCLCL - 5

CST =0

(4 x CST) tCLCL - 3

1 ≤ CST ≤ 7

WR Pulse Wid th (P3.6) tWLWH

2tCLCL - 5

CST =0

(4 x CST)tCLCL - 3

1 ≤ CST ≤ 7

RD (P3.7 or PSEN) Low to Valid Data In tRLDV

2tCLCL - 17

CST = 0

(4 x CST)tCLCL - 17

1 ≤ CST ≤ 7

Data Hold After RD (P3. 7 or PSEN) High tRHDX -2 ns

Data Float After RD (P3.7 or PSEN) High

tRHDZ

tCLCL - 5

CST = 0

2tCLCL - 5

1≤ CST ≤ 3

6tCLCL - 5

4 ≤ CST ≤ 7

PSEN High to WR Low tPHWL

2tCLCL - 3

CST = 0

3tCLCL - 3

1≤ CST ≤ 3

11tCLCL - 3

4 ≤ CST ≤ 7

PSEN High to (RD or PSEN) Low tPHRL

2tCLCL - 3

CST = 0

3tCLCL - 3

1≤ CST ≤ 3

11tCLCL - 3

4 ≤ CST ≤ 7

Port 7 Address to Valid Data In tAVDV1

3tCLCL - 19

CST = 0

(4 x CST + 2)tCLCL- 19

1≤ CST ≤ 3

(4 x C

+ 10)t

CLCL

4 ≤ CST ≤ 7

Port 2, 4, 6 Address, Port 4 CE or Port 5

PCE to Valid Data In tAVDV2

3tCLCL + tCLCH - 22

CST = 0

(4 x C

+ 2)t

CLCL

tCLCH - 22

1≤ CST ≤ 3

(4 x C

+ 10)t

CLCL

tCLCH - 22

4 ≤ CST ≤ 7

Port 7 Address to (RD or PSEN) or WR

Low tAVWL1

tCLCL – 6.5

CST = 0

2tCLCL – 6.5

1 ≤ CST ≤ 3

10tCLCL - 7

4 ≤ CST ≤ 7

Port 2, 4, 6 Address, Port 4 CE or Port 5

PCE to (RD or PSEN) or WR Low tAVWL2

tCLCL + tCLCH - 7

CST = 0

2tCLCL + tCLCH - 7

1 ≤ CST ≤ 3

10tCLCL + tCLCH - 7

4 ≤ CST ≤ 7

Data Valid to WR Transition tQVWX 0 ns

Data Hold After WR High tWHQX

tCLCL - 5

CST = 0

2CLCL - 8

1 ≤ CST ≤ 3

6tCLCL - 8

4 ≤ CST ≤ 7

(RD or PSEN) or WR High to Port 4 CE

or Port 5 PCE High tWHCEH

tCHCL - 5

tCHCL + 13

CST = 0

tCLCL + tCHCL - 5

tCLCL + tCHCL +12

1 ≤ CST ≤ 3

5tCLCL + tCHCL -5

5tCLCL + tCHCL +12

4 ≤ CST ≤ 7

16 of 102

Note 1:

AC electrical characteri st ics ass um e 50% duty cycle for the oscillator, oscil l ator frequency ≤ 75MHz, and are not 100% production

tested, but are guaranteed by design.

Note 2:

All parameters apply to both comm ercial and indust ri al tem perat ure operation, unless otherwise noted.

Note 3: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL, tCLCH, tCHCL are time

periods associat ed with the internal system clock and are related to the external clock. See the System Clock Time Periods table.

Note 4: All signals characterized with load capacitance of 80pF except Port 0, P ort 2, ALE, PSEN, RD, and WR with 100pF. The foll owing

signals, when configured f or memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7

(

PCE0-3

), Port 6.0–6.5 (

CE4-7

, A20, A2), Port 7 (demultiplexed mode A0–A7).

Note 5: References to the XTAL or CLK signal in the timing diagrams are to assist in determining the relative occurrence of events, not for

determining absolute signal timing with respect to the external clock.

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18 of 102

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NONMULTIPLEXED, 2-CYCLE DATA MEMORY

PCE0-3

READ OR WRI T E

NONMULTIPLEXED, 2-CYCLE DATA MEMORY

CE0-7

READ

PO R T 4

–

3CE0−

PO R T 6

–

7−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 4

–

3CE0−

PO R T 6

–

7−

CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 7

20 of 102

NONMULTIPLEXED, 2-CYCLE DATA MEMORY

CE0-7

WRITE

NONMULTIPLEXED, 3-CYCLE DATA MEMORY

PCE0-3

READ OR WRI T E

PO R T 4

–

3CE0−

PORT

6 –

7−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 7

PO R T 4

–

3CE0−

PO R T 6 –

7−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 7

21 of 102

NONMULTIPLEXED, 3-CYCLE DATA MEMORY

CE0-7

READ

NONMULTIPLEXED, 3-CYCLE DATA MEMORY

CE0-7

WRITE

PO R T 4

–

3CE0−

PO R T 6

–

−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 7

PO R T 4

–

3CE0−

PO R T 6

–

7−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 7

22 of 102

NONMULTIPLEXED, 9-CYCLE DATA MEMORY

PCE0-3

READ OR WRI T E

NONMULTIPLEXED, 9-CYCLE DATA MEMORY

CE0-7

READ

PO R T 4

–

CE0−

PO R T 6

–

7−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 7

PO R T 4

–

3CE0−

PO R T 6

–

7−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 7

23 of 102

NONMULTIPLEXED, 9-CYCLE DATA MEMORY

CE0-7

WRITE

OW PIN TIMING CHARACTERISTICS (Note 1)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.)

PARAMETER SYMBOL

STANDARD

OVERDRIVE

LONGLINE

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

Transmit Reset Pulse Low Time

(Note 2)

tRSTL 500.8 626 50.4 63 500.8 626 µs

Transmit Reset Pulse High Time

(Note 2)

tRSTH 508.8 636 59.2 74 508.8 636 µs

Wait Time for Transmit of Presence

Pulse (Notes 2, 3)

tPDH 15 60 2 6 15 60 µs

Wait Time for Absence of Presence

Pulse (Notes 2, 4)

tPDHCNT 60 75 6.4 8 60 75 µs

Presence Pulse Width (Note 2)

tPDL

240

µs

Presence Pulse Sampling Time

(Note 2)

tPDS 24 31 2.4 4 30.4 38 µs

Read/Write Data Time Slot

tSLOT

68.8

µs

Low Time for Write 1

tLOW1

4.8

0.8

7.2

µs

Low Time for Write 0

tLOW0

62.4

µs

Write Data Sampling Time

tWDV

µs

Read Data Sampling Time

tRDV

1.6

µs

Note 1:

AC electrical characteri st ics ass um e 50% duty cycle for the oscillator, oscil l ator frequency ≤ 75MHz, and are not 100% production

tested, but are guaranteed by design.

Note 2:

In PMM mode, the master pulls the line low after the first 15µs for the remainder of the standard speed 1-Wire routine.

Note 3:

This parameter quant ifi es the wait time for the slave devic es to respond to the reset pulse and is dependent on the slave device

timing.

Note 4:

This parameter quant ifi es the wait time for the case when no presence pulse detected.

Note 5:

The maximum timing figures shown apply only when an exact 1-Wire clock frequency can be achieved from the microcontroller

input clock.

PO R T 4

–

3CE0−

PO R T 6

–

7−CE4

PORT 4/6 ADDRESS

A16 -A21

PO R T 7

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OW PIN TIMING

25 of 102

OWSTP

PIN TIMING CHARACTERISTICS

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL

STANDARD

OVERDRIVE

UNITS

MIN

MAX

MIN

MAX

Active Time for Presence Detect tON1 6.4 8 0.8 1 µs

Active Time for Presence Detect Recovery tON2 8 10 8 10 µs

Active Time for Write 1 Recovery (Notes 2, 3) tON3 51.2 64 7.2 9 µs

Active Time for Write 0 Recovery (Notes 2, 3) tON4 6.4 8 0.8 1 µs

Delay Time for Presence Detect tDLY1 0.8 1 0.8 1 µs

Delay Time for Presence Detect Recovery (Note 4) tDLY2 399.2 499 31.2 39 µs

Delay Time for Write 1/Write 0 Recovery tDLY3 0.8 1 0.8 1 µs

Turn-Off Time for 1-Wire Reset tOFF1 1.6 2 1.6 2 µs

Turn-Off Time for Write 1/Write 0 (Note 5) tOFF2 0.8 1 0.8 1 µs

Note 1:

AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production

tested, but are guaranteed by design.

Note 2: There is no OWSTP t imi ng diff erence for sendi ng out and receiving bits withi n a byt e. The differenc e comes when the last bit of the

byte has been completely sent. At this point, the signal is either enabled cont i nuousl y until the next reset or time slot begins, or

enabled only for active tim e write 1 or write 0.

Note 3:

When performing a read versus a write time slot, the master provides the same active time for write 1 and write 0. However, the

Schmitt-triggered input from the OW line is sensed every 1µs for a high value. If OW is high, the OWSTP si gnal is enabl ed. If the OW

line is low, the

OWSTP

signal remains disabled until a high state is sensed. In all write time slots, a high is sensed immedi ately.

Note 4:

This parameter is the time delay until the master begins to monitor the OW pin level. If the line is already high, then

OWSTP

enabled. If not, it waits to enable

OWSTP

until the next state machine clock (1

s or 50ns) after the OW line recovers.

Note 5:

The very first bit in a byte has an extended turn-off time of 4µs because of the order of states that the 1-Wire master state machine

must go through.

OWSTP

PIN TIMING

26 of 102

ETHERNET MII INTERFACE TIMING CHARACTERISTICS

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL

100Mbps

10Mbps

UNITS

MIN

MAX

MIN

MAX

TXClk Duty Cycle tTDC 14 26 140 260 ns

TXD, TX_EN Data Setup to TXClk tTSU 10 25 ns

TXD, TX_EN Data Hold from TX Clk tTHD 2 2 ns

RXC lk Pulse Width tRDC 14 26 140 260 ns

RXClk to RXD, RX_DV, RX_ER Valid tRDV 10 30 190 210 ns

MDC Period tMCLCL 400 400 ns

MDC to Input Data Valid tMDV 300 300 ns

MDIO Output Data Setup to MDC tMOS 10 10 ns

MDIO Output Data Hold from MDC tMOH 10 10 ns

Note 1:

AC electrical characteristic s ass um e 50% duty cycle for the oscillator, oscil l ator frequency ≤ 75MHz, and are not 100% production

tested, but are guaranteed by design.

MII INTERFACE TIMING

27 of 102

SERIAL PORT MODE 0 TIMING CHARACTERISTICS

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Serial Port Clock Cycle Time tXLXL SM2 = 0:12 clocks per cycle 12 tCLCL ns

SM2 = 1:4 clocks per cycle 4 tCLCL

Output Data Setup to Clock

Rising tQVXH SM2 = 0:12 clocks per cycle 10 tCLCL -

10 ns

SM2 = 1:4 clocks per cycle

3 t

CLCL

Output Data Hold from Clock

Rising tXHQX SM2 = 0:12 clocks per cycle 2 tCLCL -

10 ns

SM2 = 1:4 clocks per cycle

CLCL

Input Data Hold After Clock

Rising tXHDX SM2 = 0:12 clocks per cycle 0 ns

SM2 = 1:4 clocks per cycle 0

Clock Rising Edge to Input

Data Valid tXHDV SM2 = 0:12 clocks per cycle 11 tCLCL -

20 ns

SM2 = 1:4 clocks per cycle

3 t

CLCL

Note 1:

AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production

tested, but are guaranteed by design.

28 of 102

SERIAL PORT 0 (SYNCHRONOUS MODE)

TRADITIONAL 8051 OPERATION, TXD CLOCK = XTAL/12 (SM2 = 0)

HIGH-SPEED OPERA TION, TXD CLK = SYSCLK/4 (SM2 = 1)

29 of 102

POWER-CYCLE TIMING CHARACTERISTICS

PARAMETER SYMBOL MIN TYP MAX UNITS

Crystal Startup Time (Note 1) tCSU 1.8 ms

Power-On Reset Delay (Note 2) tPOR 65,536 tCLCK

Note 1: Startup time for crystals varies with l oad capacit ance and manufact urer. Time shown is for an 11.0592MHz crystal manuf act ured by Fox

Electronics.

Note 2: Reset delay is a synchronous counter of crystal oscillat i ons during crys tal startup. Counting begins when the level on the XTAL1 input

m eet s the VIH2 crit eri a. At 40MHz, this time is approximatel y 1. 64ms.

POWER-CYCLE TIMING

30 of 102

BLOCK DIAGRAM

OWSTP

CC1

(1)

VCC3 (4)

VSS (4)

RST

RSTOL

MUX

PSEN

ALE

XTAL1

XTAL2

ADDRESS BUS

DATA BUS

PORT 1

PORT 7

PORT LATCH

PORT 6

PORT LATCH

PORT 3

PORT LATCH

PORT 5

MII

MANAGEMENT

MII

I/O

SERIAL

PORT 1

SERIAL

PORT 0

SERIAL

PORT 2

TIMER 2

TIMER 0

TIMER 1

TIMER 3

CAN 0

CONTROLLER

CAN

SRAM

256 x 8

BUFFER CONTROL UNIT

ACCUMULATOR

PORT LATCH

PORT 4

OSCILLATOR

PORT 2

PORT LATCH

PORT 0

1-WIRE

CONTROLLER

PORT LATCH

SRAM

73k x 8

POWER

MONITOR

RESET

CONTROL

OSCILLATOR-

FAIL DETECT

PSW

STACK

POINTER

SFRs/ SRAM

256 x 8

INTERRUPT

LOGIC

MATH

ACCELERATOR

TIMED

ACCESS

DPTR0

DPTR1

DPTR2

DPTR3

PROGRAM

COUNTER

ONE’S COMP.

ADDER

INTRUCTION

BOOT

ROM

64k x 8

WATCHDOG

P6.0–P6.7

P4.0– 4.7

P2.0–P2.7

P7.0–P7.7

P3.0–P3.7

P5.0–P5.7

P1.0–P1.7

P0.0–P0.7

CLOCK AND

MEMORY

CONTROL

MDC MDIO

MII I/O (15)

B

DS80C410

DS80C411

31 of 102

PIN DESCRIPTION

PIN NAME FUNCTION

70 VCC1 +1.8V Core Supply Voltage

12, 36, 62,

VCC3 +3.3V I/O Supply Voltage

13, 39, 63,

VSS Digital Circuit Ground

68 ALE

Add ress L atch E n able, Outp u t. When the MUX pin is low, this pin outputs a clock to latch the external address

LSB from the multiplexed address/dat a bus on Port 0. This signal is commonly connect ed to the latch enable of

an external transparent l atc h. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles.

When the MUX pin is high, the pin toggles continuously if the ALEOFF bit is cleared. ALE is forced high when

the device is in a reset condition or if the ALEOFF bit is set while the MUX pin is high.

67 PSEN

Program Store Enab le, Output. This signal is the chip enable for external program or m erged program / data

memory. PSEN provides an active-low pulse and is driven high when external memory is not being accessed.

69 EA

External Access Enable, Input. Connect to GND to use external program memory. Connect t o V

to use

internal ROM.

40 MUX

Multiplex/Demultiplex Select, Input. This pin selects if the address/data bus operat es i n multiplexed (MUX =

0) or demultiplexed (MUX = 1) mode. The MUX pin is sampled only on a power-on reset.

97 RST

Reset, Input. The RST input pin contains a Schmitt volt age input to recognize external active-high reset inputs.

The pin also employs an internal pulldown resistor to all ow for a combination of wired-OR external-reset

sources. An RC circuit is not required for power-up, as the device provides this funct i on internall y.

98 RSTOL

Reset Output Low, Output. This active-low signal is asserted when the microcontroller has entered reset

through the RST pin; during crystal warm-up period following power-on or stop mode; during a watchdog tim er

reset; during an oscillator failure (if OFDE = 1); whenever VCC1 ≤ VRST1 or VCC3 ≤ VRST3.

XTAL2

XTAL1, XTAL2. Cry stal oscillator pins support fundamental mode, parallel resonant, AT cut crystals. XTAL1 is

the input if an external clock source is used in place of a crystal. XTAL2 is the output of the crystal amplifier.

XTAL1

86 AD0/D0

AD0–7 (Port 0), I/O. When the MUX pin is connected low, Port 0 is the multiplexed address/data bus. While

ALE is high, the LSB of a memory address is presented. While ALE falls, the port transitions to a bidirectional

data bus. When the MUX pin is connected high, Port 0 functions as the bidirectional dat a bus. Port 0 cannot be

modified by software. The res et condition of Port 0 pins is high. No pullup resist ors are needed.

Port Alt ernat e Function

P0.0 AD0/D0 ( A d dress )/Data 0

P0.1 AD1/D1 (Address )/Data 1

P0.2 AD2/D2 (Address )/Data 2

P0.3 AD3/D3 (Address )/Data 3

P0.4 AD4/D4 (Address )/Data 4

P0.5 AD5/D5 (Address )/Data 5

P0.6 AD6/D6 (Address )/Data 6

P0.7 AD7/D7 (Address )/Data 7

85 AD1/D1

84 AD2/D2

83 AD3/D3

82 AD4/D4

81 AD5/D5

80 AD6/D6

79 AD7/D7

89 P1.0

Port 1, I/O. Port 1 can function as either an 8-bit, bidirectional I/O port or as an alternate interface for internal

resources. T he reset conditi on of Port 1 is all bits at logic 1 through a weak pullup. The logic 1 state also serves

as an input mode, since external circuits writing to the port can override the weak pullup. When software cl ears

any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written to the port pin or a

reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver, followed by a weaker

sustaining pul l up. Once the momentary strong dri ver turns off, the port once again becomes the output (and

input) high state.

Port Alternate Function

P1.0 T2 External I/O for Timer/Count er 2

P1.1 T2EX Timer/Counter 2 Capture/ Reload Trigger

P1.2 RXD1 Serial Port 1 Receive

P1.3 TXD1 Serial Port 1 Transmit

P1.4 INT2 External Interrupt 2 (Posit i ve Edge Detect)

P1.5 INT3 External I nterrupt 3 (Negative Edge Detect)

P1.6 INT4 External Interrupt 4 (Posit i ve Edge Detect)

P1.7 INT5 External I nterrupt 5 (Negative Edge Detect)

90 P1.1

91 P1.2

92 P1.3

93 P1.4

94 P1.5

95 P1.6

96 P1.7

66 A8

A15–A8 (Port 2), Output. Port 2 serves as the MSB for external addressi ng. The port automat ic al l y asserts t he

address MSB during external ROM and RAM access. Although the Port 2 SFR exists, the SFR value never

appears on the pins (due to memory access). Theref ore, acc essing the Port 2 SFR is only useful for MOVX A,

@Ri or MOVX @Ri, A instructions, which use the Port 2 SFR as the external address MSB.

Port Alt ernat e Function

P2.0 A8 Program/Data Memory Address 8

P2.1 A9 Program/Data Memory Address 9

P2.2 A10 Program/Data Memory Address 10

P2.3 A11 Program/Data Memory Address 11

P2.4 A12 Program/Data Memory Address 12

P2.5 A13 Program/Data Memory Address 13

65 A9

64 A10

61 A11

60 A12

59 A13

58 A14

32 of 102

PIN NAME FUNCTION

57 A15

P2.6 A14 Program/Data Memory Address 14

P2.7 A15 Program/Data Memory Address 15

20 P3.0

Port 3, I/O. Port 3 funct ions as an 8-bit, bidirectional I/O port, and as an alternate interface for several resourc es

found on the traditional 8051. The reset condi tion of Port 3 is all bits at logic 1 through a weak pullup. The logic

1 state also serves as an input mode, since external circuits writing to t he port c an override the weak pullup.

When software clears any port pin to 0, the device activates a strong pulldown that remai ns on until either a 1 is

written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition

driver, foll owed by a weaker sustaining pullup. Once the momentary st rong dri ver t urns off, the port once again

becomes the output (and input) high state.

Port Alt ernat e Function

P3.0 RXD0 Serial Port 0 Receive

P3.1 TXD0 Serial Port 0 Transmit

P3.2 INT0 External I nterrupt 0

P3.3 INT1 External I nterrupt 1

P3.4 T0 Timer 0 External Input

P3.5 T1/CLKO Timer 1 External Input/External Clock O utput

P3.6 WR External Data Memory W rite St robe

P3.7

External Data Memory Read Strobe

21 P3.1

22 P3.2

23 P3.3

24 P3.4

25 P3.5

26 P3.6

27 P3.7

48 P4.0

Port 4, I/O. Port 4 can function as an 8-bit, bidirect i onal I/O port, and as the source for external address and

chip-enable signals f or program and data memory. Port pins are configured as I/O or memory signals through

the P4CNT register. The reset condition of Port 4 is all bits at logic 1 through a weak pullup. The logic 1 state

also serves as an input mode, since external circuits writing to the port can override the weak pullup. When

software clears any port pin to 0, the device acti vat es a strong pulldown that remains on until either a 1 is written

to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver,

followed by a weaker sustaining pullup. Once the momentary strong driver turns off , the port once again

becomes the output (and input) high state.

Port Alt ernat e Function

P4.0 CE0 Program Memory Chip Enable 0

P4.1 CE1 Program Memory Chip Enable 1

P4.2 CE2 Program Memory Chip Enable 2

P4.3 CE3 Program Memory Chip Enable 3

P4.4 A16 Program/Data Memory Address 16

P4.5 A17 Program/Data Memory Address 17

P4.6 A18 Program/Data Memory Address 18

P4.7 A19 Program/Data Memory Address 19

47 P4.1

46 P4.2

45 P4.3

44 P4.4

43 P4.5

42 P4.6

41 P4.7

35 P5.0

Port 5, I/O. Port 5 can function as an 8-bit, bidirect i onal I/O port, the CAN interface, Timer 3 input, and/or as

peripheral-enable signal s. The reset condition of Port 5 is all bits at logic 1 through a weak pull up. The logic 1

state also serves as an input mode, since external circuits writing to the port can override the weak pullup.

When software clears any port pin to 0, the device activates a strong pulldown that remai ns on until either a 1 is

written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition

driver, foll owed by a weaker sustaining pullup. Once the momentary st rong dri ver t urns off, the port once again

becomes the output (and input) high state.

Port Alt ernat e Function

P5.0 C0TX CAN0 Transmit Output – Unavailable on DS80C411

P5.1 C0RX CAN0 Receive Input – Unavailable on DS80C411

P5.2 T3 Timer 3 External Input

P5.3 None

P5.4 PCE0 Peripheral Chip Enable 0

P5.5 PCE1 Peripheral Chip Enable 1

P5.6 PCE2 Peripheral Chip Enable 2

P5.7 PCE3 Peripheral Chip Enable 3

34 P5.1

33 P5.2

32 P5.3

31 P5.4

30 P5.5

29 P5.6

28 P5.7

56 P6.0

Port 6, I/O. Port 6 can function as an 8-bit, bidirect i onal I/O port, as program and data memory address/chi p-

enable signals, and/or a third serial port. The reset c onditi on of Port 6 is all bits at logic 1 through a weak pullup.

The logic 1 state also serves as an input mode, since external circuits writing to the port can override the weak

pullup. When software clears any port pin to 0, the device activates a strong pulldown that remai ns on until

either a 1 is written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong

transition dri ver, fol lowed by a weaker sustaini ng pul l up. Once the momentary strong driver turns off, the port

once again becomes the output (and input) high state.

Port Alt ernat e Function

P6.0 CE4 Program Memory Chip Enable 4

P6.1 CE5 Program Memory Chip Enable 5

P6.2 CE6 Program Memory Chip Enable 6

P6.3 CE7 Program Memory Chip Enable 7

P6.4 A20 Program/Data Memory Address 20

P6.5 A21 Program/Data Memory Address 21

P6.6 RXD2 Serial Port 2 Receive

P6.7 TXD2 Serial Port 2 Transmit

55 P6.1

54 P6.2

53 P6.3

52 P6.4

51 P6.5

50 P6.6

49 P6.7

33 of 102

PIN NAME FUNCTION

78 A0

Port 7, I/O. Port 7 can function as either an 8-bit, bidirectional I/O port or the nonmultiplexed A0–A7 signals

(when the MUX pin = 1). The reset condition of Port 7 is all bits at logic 1 through a weak pullup. The logic 1

state also serves as an input mode, since external circuits writing to the port can override the weak pullup.

When software clears any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written

to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver,

followed by a weaker sustaining pullup. Once the momentary strong driver turns off , the port once again

becomes the output (and input) high state.

Port Alt ernat e Function

P7.0 A0 Program/Data Memory Address 0

P7.1 A1 Program/Data Memory Address 1

P7.2 A2 Program/Data Memory Address 2

P7.3 A3 Program/Data Memory Address 3

P7.4 A4 Program/Data Memory Address 4

P7.5 A5 Program/Data Memory Address 5

P7.6 A6 Program/Data Memory Address 6

P7.7 A7 Program/Data Memory Address 7

77 A1

76 A2

75 A3

74 A4

73 A5

72 A6

71 A7

8 TXClk

Transmit Clock, Input. The transmit clock is a continuous clock sourced from t he Ethernet PHY controller. It is

used to provide timing reference for transf erring of TX_EN and TXD[3:0] signals from the MAC to the external

Ethernet PHY controller. The i nput clock frequency of TXClk shoul d be 25MHz for 100Mbps operation and

2.5MHz for 10Mbps operation. For ENDEC operation, TXClk serves the same funct i on, but the input clock

frequency shoul d be 10MHz.

7 TX_EN

Transmit Enable, Output. The transmit enable is an active-high output and is synchronous with respect to the

TXClk signal. TX_EN is used to indicate valid nibbles of data for transm ission on the MII pins TXD.3–TXD.0.

TX_EN is asserted with the first nibble of the preamble and remains assert ed while all nibbles to be transmitted

are presented on the TXD.3–TXD.0 pins. TX_EN negates prior t o the first TXClk foll owing the final nibble of the

frame. TX_EN serves the same function for ENDEC operation.

TXD.3

Transmit Data, Output. The transmit data outputs provide 4-bit nibbles of data for transmiss i on over the MII.

The transmit data is synchronous with respec t t o the TXClk signal. For each TXClk period when TX_EN is

asserted, TXD.3–TXD.0 provides the data for transmission to the Ethernet PHY controller. When TX_EN is

deassert ed, the TXD data should be ignored. For ENDEC operation, only TXD.0 is used for transmission of

frames.

TXD.2

TXD.1

6 TXD.0

10 RXClk

Receive Clock, Input. The receive clock is a continuous clock sourced from the Ethernet PHY controller. It is

used to provide timing reference for transf erri ng of RX_DV, RX_ER, and RXD[3:0] signals from the external

Ethernet PHY controller to t he MAC. The input clock frequency of RXClk should be 25MHz for 100Mbps

operation and 2.5MHz for 10Mbps operation. For ENDEC operation, RXClk serves the sam e function, but t he

input clock frequency should be 10MHz.

11 RX_DV

Receive Data Valid, Input. The receive dat a valid is an active-high input from t he external Ethernet PHY

controll er and is synchronous with respec t t o the RXClk signal. RX_DV is used to indicate valid nibbl es of data

for reception on the MII pins RXD.3–RXD.0. RX_DV is asserted continuously from the fi rst nibble of the frame

through the final nibbl e. RX_DV negates pri or to the first RXClk foll owing the final ni bbl e. RX_DV serves the

same function for ENDEC operation.

9 RX_ER

Receive Error, Input. The recei ve error is an active-high input from the external Ethernet PHY controller and is

synchronous with respect to the RXClk signal. RX_ER is used to indicate to the MAC that an error (e.g., a

coding error, or any error detect able by the PHY) was detected somewhere in the frame presentl y bei ng

transmitted by the PHY. RX_ER has no effect on the MAC while RX_DV is deasserted. RX_ER should be low

for ENDEC operation.

RXD.3

Receive Data, Input. The receive data inputs provide 4 -bit nibbl es of data for rec eption over t he MII. The

receive data is synchronous with respect to t he RXClk signal. For each RXClk period when RX_DV is asserted,

RXD.3–R XD.0 have the dat a to be received by the MAC. When RX_DV is deasserted, the RXD data should be

ignored. For ENDEC operation, only RXD.0 is used for recepti on of frames.

RXD.2

RXD.1

RXD.0

1 CRS

Carrier Sense, Input. The carrier sense signal is an active-high input and should be asserted by the external

Ethernet PHY controller when either the t ransmit or receive m edium is not idl e. CRS should be deasserted by

the PHY when the transmit and receive mediums are idle. The PHY should ensure that the CRS signal remains

assert ed throughout the durat i on of a collision condition. The transiti ons on the CRS signal need not be

synchronous to TXClk or RXClk. CRS serves t he same function for ENDEC operati on.

2 COL

Collision Detec t , Input . The collision detect signal is an active-high input and should be asserted by the

external Ethernet P HY controll er upon detecti on of a collis i on on the medium. The PHY should ensure that COL

remains asserted while the col lis i on conditi on pers ists. The transitions on the COL signal need not be

synchronous to TXClk or RXClk. The COL signal is ignored by the MAC when operating in full-duplex mode.

COL serves the same function for ENDEC operation.

18 MDC

MII Management Clock, Output. The MII management clock is generated by the MAC for use by the external

Ethernet PHY controller as a timing referenced for t ransf erring i nformation on the MDIO pin. MDC is a periodic

signal that has no maximum high or low times. The minimum high and low times are 160ns each. The minimum

period for MDC is 400ns independent of the period of TXClk and RXClk.

19 MDIO

MII Management Input/ O utput . The MII management I/O is the data pin for serial communication with the

external Ethernet P HY controll er. In a read cycle, dat a is driven by the PHY to the MAC synchronously with

respect to the MDC clock. In a write cycle, data from the MAC is output to the external PHY sync hronously with

respect to the MDC clock.

99 OW

1-Wire Da t a , I/O. The 1-W i re data pin is an open-drain, bidirectional data bus for the 1-Wire Bus Master.

External 1-Wire slave devic es are connec t ed to this pin. This pin must be pulled high by an external resistor,

34 of 102

PIN NAME FUNCTION

normall y 2.2kΩ.

100 OWSTP

Strong Pull up Enable, Output. Thi s 1-Wire pin is an open-drain active-low output used t o enable an external

strong pull up for the 1-Wire bus. This pin must be pulled high by an external resistor, normall y 10kΩ. This

functionali t y hel ps recovery tim es when the 1-Wire bus is operated in overdrive and long-line standard

communication m odes. It can optionally be enabled while the bus master is in the idle state for slave devices

requiring sustai ned hi gh-current operation.

FEATURES (continued)

 Full-Function CAN 2.0B Controller

15 Message Centers

Supports Standard (11-Bit) and Extended (29-Bit)

Identifiers and Global Masks

Media Byte Filtering to Support DeviceNet™, SDS,

and Higher Layer CAN Protocols

Auto-Baud Mode and SIESTA Low-Power Mode

 Integrated Primary System Logic

16 Total Interrupt Sources with Six External

Four 16-Bit Timer/Counters

2x/4x Clock Multiplier Reduces Electromagnetic

Interference (EMI)

Programmable Watchdog Timer

Oscillator-Fail Detection

Programmable IrDA Clock

 Advanced Power Management

Energ y Saving 1.8 V Core

3.3V I/O Operation, 5V Tolerant

Power-Management, Idle, and Stop Mode

Operations with S witc hback Feature

Ethernet and CAN Shutdown Control for Power

Conservation

Early Warning Power-Fail Interrupt

Power-F a il R es et

 Enhanced Memory Architecture

Selectab le 8/1 0-Bit Stack Pointer for High-Level

Language Sup por t

64kBytes Additional On-Chip SRAM Usable as

Program/Data Memory

16-Bit/24-Bit Paged/24-Bit Contiguous Modes

Selectable Multiplexed/Nonmultiplexed External

Memory Interface

Merged Program/Data Memory Space Allows In-

System Programming

Defaults to True 8051-Memory Compatibility

DeviceNet is a trademark of Open DeviceNet Vendor Associ ation, Inc.

DS80C41 0/D S80 C41 1 Net wor k Microcontroll ers with Ethernet and CAN

35 of 102

TERMINOLOGY

The term DS80C410 is used in the remainder of the document to refer to the DS80C410 and DS80C411 unless

otherwise specified.

DETAILED DESCRIPTION

The DS80C410 network microcontroller offers the highest integration available in an 8051 device. Peripherals

include a 10/ 100 E thern et MAC , thre e s er ial por ts , an opti ona l CAN 2. 0B c ontro l l er , 1-Wire Mas ter , and 64 I/O pins.

To enable access to the network, a full application-accessible TCP IPv4/6 network stack and OS are provided in

ROM. The network stack supports up to 32 simultaneous TCP connections and can transfer up to 5Mbps through

the Ethernet MAC. Its maximum system-clock frequency of 75MHz results in a minimum instruction cycle time of

54ns. Access to large program or data memory areas is simplified with a 24-bit addressing scheme that supports

up to 16MB of contiguous memory. To accelerate data transfers between the microcontroller and memory, the

DS80C410 provides four data pointers, each of which can be configured to automatically increment or decrement

upon execution of certain data pointer-related instructions. The DS80C410’s hardware math accelerator further

increases the speed of 32-bit and 16-bit multiply and divide operations as well as high-speed shift, normalization,

and accumulate functions.

With extensive networking and I/O capabilities, the DS80C410 is equipped to serve as a central controller in a

multitiered network. The 10/100 Ethernet media access controller (MAC) enables the DS80C410 to access and

communicate over the Internet. While maintaining a presence on the Internet, the microcontroller can actively

control lower tier networks with dedicated on-chip hardware. These hardware resources include a full CAN 2.0B

controller, a 1-Wire net controller, three full-duplex serial ports, and eight 8-bit ports (up to 64 digital I/O pins).

Instant connectivity and networking support are provided through an embedded 64kB ROM. This ROM contains

firm ware to per form a netw ork boot over an Ethernet connec tion using DHC P in conjunc tion with TF TP. The ROM

firm ware reali zes a f ull, ap plicat ion-accessible T CP/IP s tack , suppor ting bot h IPv 4 and IPv6, an d implem ents UDP,

TCP, DHCP, ICMP, and IGMP. In addition, a priority-based, preemptive task scheduler is also included. The

firm ware has been structur ed so that a MA C address c an optionall y be acquired f rom an IEEE-r egistere d DS2502-

E48.

The 10/100 Ethernet MAC featured on the DS80C410 complies with both the IEEE 802.3 MII and ENDEC PHY

interface standards. The MII interface supports 10/100Mbps bus operation, while the ENDEC interface supports

10Mbps operation. The MAC has been designed for low-power standard operation and can optionally be placed

into an ultr a-low-power slee p mode, to be a wak ened m anua lly or by detec tio n of a Mag ic Pac ket or wake-up frame.

Incorporating a buffer control unit reduces the burden of Ethernet traffic on the CPU. This unit, after initial

configurat ion through an SFR interface, m anages all T x/Rx pack et activity and status repor ting through a n on-chip

8kB SRAM. To further reduce host (DS80C410) software intervention, the MAC can be set up to generate a

hardware interrupt following each transmit or receive status report. The DS80C410 MAC can be operated in half-

duplex or full-duplex mode with flow control, and provides multicast/broadcast-address filtering modes as well as

VLAN tag-recognition capability.

The DS80C 410 featur es a f ull-function C AN 2.0B con troller. The DS8 0C411 does not incl ude this periphera l. This

controller provides 15 total message centers, 14 of which can be configured as either transmit or receive buffers

and one that can serve as a receive double buffer. The device supports standard 11-bit or 29-extended message

identifiers , a nd of fers two s epar at e 8-b it media m asks and m edia arbitr a tio n f ields to s upp or t th e us e of hi ghe r -level

CAN protocols such as DeviceNet and SDS. A special auto-baud mode allows the CAN controller to quickly

determ ine required bus tim ing when insert ed into a new net work . A SIESTA sleep m ode has been m ade available

for times when the CAN controller can be placed into a power-saving mode.

The DS80C410 has resources that far exceed those normally provided on a standard 8-bit microcontroller. Many

functions, which might exist as peripheral circuits to a microcontroller, have been integrated into the DS80C410.

Some of the integrated fun c tions of the DS80C 410 i nc lud e 16 int err upt s ourc es (six ex ter nal), f our timer/c ounters , a

programmable watchdog timer, a programmable IrDA output clock, an oscillator-fail detection circuit, and an

internal 2X/4X clock multiplier. This frequency multiplier allows the microcontroller to operate at full speed with a

reduced crystal frequency, reducing EMI.

Advanced power-management support positions the DS80C410 for portable and power-conscious applications.

The low-voltage microcontroller core runs from a 1.8V supply while the I/O remains 5V tolerant, operating from a

3.3V supp l y. A power-management mode (PMM) al lows s of t ware t o switch fr om the standar d machine c ycl e rate of

36 of 102

4 clocks per cycle to 1024 clocks per cycle. For example, 40MHz standard operation has a machine cycle rate of

10MHz. In P MM, at the sa me external c lock speed, sof tware can selec t a 39kHz m achine cycle rate, c onsiderabl y

reducing po wer cons umpti on. The m icrocontroller c an be conf igured to aut om atically switc h back f rom PMM to the

faster mode in res ponse to ex ternal i nter rupts or ser ia l port ac t iv ity. The DS80 C 41 0 pro vi des th e a bi lit y to pla c e th e

CPU into an idle state or an ultra-low-power stop-mode state. As protection against brownout and power-fail

conditions, the microcontroller is capable of issuing an early warning power-fail interrupt and can generate a power-

fail reset.

When the internal ROM is disabled, the DS80C410 defaults to true 8051-memory compatibility on power up.

However, the microcontroller is most powerful when taking advantage of its enhanced memory architecture. The

DS80C410 has a selectable 10-bit stack pointer that can address up to 1kB of on-chip SRAM stack space for

increased code efficiency. It can be operated in a 24-bit paged or 24-bit contiguous address mode, giving access t o

a much larger address range than the standard 16-bit address mode. Support for merged program and data

memory access allows in-system programming, and it can be configured to internally demultiplex data and the

lowest address byte, thereby eliminating the need for an external latch and potentially allowing the use of slower

memory devices.

80C32 COMP ATIBILITY

The DS80C410 is a CMOS 80C32-compatible microcontroller designed for high performance. Every effort has

been made to k eep the c ore de v ic e f amiliar to 80C32 us ers whi le add in g many enhanc e d f eatures. T he D S 8 0C41 0

provides the sam e timer/counter res ources, f ull duplex ser ial port, 256 Bytes of s cratchpad RA M, and I/O por ts as

the standar d 80C 32. T im ers default t o 12 os cillat or clo cks per tick operation to k eep tim ing compatible with o riginal

8051 systems. New hardware functions are accessed using special function registers (SFRs) that do not overlap

with standar d 80 C32 l oc ati ons. Al l instr uc ti ons per f or m exac tl y the same functions as their 8051 counterparts. Their

effect on bits, flags, and other status functions is identical. Because the device r uns the standard 8051 inst ruction

set, in gener al, softw are wri tten for existing 80C 32-bas ed system s work on the DS80C410. The pr imar y exceptions

are related to timing-critical issues, since the high-performance core of the microcontroller executes instructions

much faster than the original, both in absolute and relative number of clocks.

The relative time of two DS80C410 instructions might differ from the traditional 8051. For example, in the original

architecture the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction required the sam e amount

of tim e: two m achine c ycles or 24 osc illator c ycles. I n its def ault c onfig uration ( m achine c ycl e = 4 oscillator c ycles),

the DS8 0C41 0 ex ecutes th e “MO VX A, @DPT R ” ins tr uc tion in as litt le as t wo machine cycles or 8 osc illat or cycles,

but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their

origina l co unterp arts, th ey now ha ve dif fer ent execu tion tim es . Exam ine t he tim ing of eac h i nstruc tion f or f am iliarity

with the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle.

Most instruc t ions req uir e o nly one or two c yc les, bu t some requir e as man y as four or five. Refer to t he High-Speed

Microcontroller User’s Guide and the High-Speed Microcontroller User’s Guide: Network Microcontroller

Supplement for individual instruction-timing details and for calculating the absolute timing of software loops. Also

remember that the counter/timers default to run at the traditional 12 clocks per increment. This means that timer-

based events still occur at the standard intervals, but that code now executes at a higher speed relative to the

timers. Timers optionally can be conf igured to run at the faster 4 clocks per increment to take advantage o f faster

controller operation.

Memor y interfacing can be performed identically to the standard 80C32. The h igh-speed nature of the DS80C410

core slightly changes the interface timing, and designers are advised to consult the timing diagrams in this data

sheet for more information.

This data s heet pr o v ides o nly a summary and over view of the DS80C41 0. D et ai led des c ript io ns ar e avai lab l e in th e

corresponding user’s guide. This data sheet assumes a familiarity with the architecture of the standard 80C32. In

addition to the basic features of that device, the DS80C410 incorporates many new features.

PERFORMANCE OVERVIEW

The DS80C410’s higher performance comes not just from increasing the clock frequency but also from a more

efficient design. This updated core removes the dummy memory cycles that are present in a standard, 12 clock-

per-machine cycle 8051. In the DS80C41 0, a machine c ycle requires only 4 clocks. Thus the fastest instruction, 1

machine c ycle in duration, executes three times faster for the sam e crystal f requency. The m ajority of instructions

on the DS80C 410 experien ce a 3-to-1 speed impr ovement, while a fe w execute between 1. 5 and 2.4 tim es faster.

37 of 102

One instruction, INC DPTR, actually executes in fewer machine cycles (1 machine cycle vs. 2 machine cycles

originally required), thus it sees a 6X throughput improvement over the original 8051. Regardless of specific

performance improvements, all instructions are faster than the original 8051.

Improvement of individual programs depends on the actual mix of instructions used. Speed-sensitive applications

should make the m os t us e of instr uc tions that are at leas t thr ee times f ast er. H owever, g i ven the lar g e number of 3-

to-1 impr oved op c odes, dram atic speed im provements are lik ely for any arbitr ary combinat ion of instruc tions. The

core arc hitectural improve ments and the subm icron-CMOS design res ult in a peak instructio n cycle of 54ns (18.75

million instructions per second, i.e., MIPS). To further increase performance, auto-increm ent/decrement and auto-

toggle enhancements have been implemented for the quad data pointer to allow the user to eliminate wasted

instructions when moving blocks of memory .

SPECIAL FUNCTION REGISTERS (SFRS)

SFRs control most special features of the microcontroller. They allow the device to have many new features but

use the standard 8051 instruction set. When writing software to use a new feature, an equate statement defines the

SFR to the assembler or compiler. This is the only change needed to access the new function. The DS80C410

duplicat es the SF Rs cont ained in th e stand ard 80C 32. Table 1 shows the r egister addres ses and bit location s. The

High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement contains a full description of all

SFRs.

Bits that are related to the CAN module become read-only bits on the DS80C411, returning logic 1 when read.

Exceptions to this are:

 C0_I/O (P5CNT.3) is a general-purpose read/write bit on the DS80C411, but it has no effect on processor

operation.

 CAN0BA (P5CNT.6) has the same operation as on the DS80C400.

 C0BPR6 (COR.3) is a general-purpose read/write bit on the DS80C411, but is has no effect on processor

operation.

 C0BPR7 (COR.4) is a general-purpose read/write bit on the DS80C411, but is has no effect on processor

operation.

 C0IE (EIE.6) is a general-purpose read/write bit on the DS80C411, but is has no effect on processor operation.

 C0IP (IEP.6) is a general-purpose read/write bit on the DS80C411, but is has no effect on processor operation.

38 of 102

Table 1. SFR Address es and Bit Locations

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ADDRESS

P4.7/A19

P4.6/A18

P4.5/A17

P4.4/A16

P4.3/CE3

P4.2/CE2

P4.1/CE1

P4.0/CE0

80h

SP 81h

DPL

82h

DPH 83h

DPL1

84h

DPH1 85h

DPS

ID1

ID0

TSL

AID

SEL1

—

SEL0

86h

PCON SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLE 87h

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

88h

TMOD

GATE

C/T

GATE

C/T

89h

TL0

8Ah

TL1

8Bh

TH0

8Ch

TH1

8Dh

CKCON WD1 WD0 T2M T1M T0M MD2 MD1 MD0 8Eh

P1.7/INT5

P1.6/INT4

P1.5/INT3

P1.4/INT2

P1.3/TXD

P1.2/RXD1

P1.1/T2EX

P1.0/T2

90h

EXIF IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGS 91h

P4CNT

—

P4CNT.5

P4CNT.4

P4CNT.3

P4CNT.2

P4CNT.1

P4CNT.0

92h

DPX 93h

DPX1

95h

C0RMS0 96h

C0RMS1

97h

SCON0 SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h

SBUF0

99h

ESP

—

ESP.1

ESP.0

9Bh

9Ch

ACON

—

MROM

BPME

BROM

AM1

AM0

9Dh

C0TMA0

9Eh

C0TMA1

9Fh

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

A0h

P5.7/PCE3

P5.6/PCE2

P5.5/PCE1

P5.4/PCE0

P5.3

P5.2/T3

P5.1/C0RX

P5.0/C0TX

A1h

P5CNT

—

CAN0BA

—

C0_I/O

P5CNT.2

P5CNT.1

P5CNT.0

A2h

C0C

ERIE

STIE

PDE

SIESTA

CRST

AUTOB

ERCS

SWINT

A3h

C0S BSS EC96/128 WKS RXS TXS ER2 ER1 ER0 A4h

C0IR

INTIN7

INTIN6

INTIN5

INTIN4

INTIN3

INTIN2

INTIN1

INTIN0

A5h

C0TE A6h

C0RE

A7h

IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h

SADDR0

A9h

SADDR1 AAh

C0M1C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

ABh

C0M2C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

ACh

C0M3C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

ADh

C0M4C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

AEh

C0M5C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

AFh

P3.7/RD

P3.6/WR

P3.5/T1

P3.4/T0

P3.3/INT1

P3.2/INT0

P3.1/TXD0

P3.0/RXD0

B0h

P6.7/TXD2

P6.6/RXD2

P6.5/A21

P6.4/A20

P6.3/CE7

P6.2/CE6

P6.1/CE5

P6.0/CE4

B1h

P6CNT

—

P6CNT.5

P6CNT.4

P6CNT.3

P6CNT.2

P6CNT.1

P6CNT.0

B2h

C0M6C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

B3h

C0M7C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

B4h

C0M8C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP B5h

C0M9C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

B6h

39 of 102

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ADDRESS

C0M10C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

B7h

—

PS1

PT2

PS0

PT1

PX1

PT0

PX0

B8h

SADEN0

B9h

SADEN1

BAh

C0M11C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

BBh

C0M12C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP BCh

C0M13C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

BDh

C0M14C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP BEh

C0M15C

MSRDY

ETI

ERI

INTRQ

EXTRQ

MTRQ

ROW/TIH

DTUP

BFh

SCON1 SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 C0h

SBUF1

C1h

PMR CD1 CD0 SWB CTM 4X/2X ALEOFF — — C4h

STATUS

PIP

HIP

LIP

—

SPTA1

SPRA1

SPTA0

SPRA0

C5h

MCON

—

PDCE3

PDCE2

PDCE1

PDCE0

C6h

C7h

T2CON

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2 CP/RL2

C8h

T2MOD

—

D13T1

D13T2

—

T2OE

DCEN

C9h

RCAP2L

CAh

RCAP2H

CBh

TL2

CCh

TH2

CDh

COR

IRDACK

—

C0BPR7

C0BPR6

COD1

COD0

CLKOE

CEh

PSW

RS1

RS0

D0h

MCNT0

LSHIFT

CSE

SCE

MAS4

MAS3

MAS2

MAS1

MAS0

D1h

MCNT1 MST MOF SCB CLM — — — — D2h

D3h

MB D4h

D5h

MCON1 IRAMD PRAME — — PDCE7 PDCE6 PDCE5 PDCE4 D6h

WDCON

SMOD_1

POR

EPFI

PFI

WDIF

WTRF

EWT

RWT

D8h

SADDR2 D9h

BPA1

DAh

BPA2

DBh

BPA3

DCh

ACC

E0h

OCAD

E1h

CSRD

E3h

CSRA E4h

EBS

FPE

RBF

—

BS4

BS3

BS2

BS1

BS0

E5h

BCUD E6h

BCUC

BUSY

EPMF

TIF

RIF

BC3

BC2

BC1

BC0

E7h

EIE EPMIE C0IE EAIE EWDI EWPI ES2 ET3 EX2-5 E8h

MXAX

EAh

DPX2 EBh

DPX3

EDh

OWMAD — — — — — A2 A1 A0 EEh

OWMDR

EFh

F0h

SADEN2

F1h

DPL2

F2h

DPH2

F3h

DPL3

F4h

DPH3

F5h

40 of 102

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ADDRESS

DPS1

ID3

ID2

—

F6h

STATUS1

—

V1PF

V3PF

SPTA2

SPRA2

F7h

EIP

EPMIP

C0IP

EAIP

PWDI

PWPI

PS2

PT3

PX2-5

F8h

P7.7/A7

P7.6/A6

P7.5/A5

P7.4/A4

P7.3/A3

P7.2/A2

P7.1/A1

P7.0/A0

F9h

TL3

FBh

TH3 FCh

T3CM

TF3

TR3

T3M

SMOD_2

GATE

FDh

SCON2 SM0/FE_2 SM1_2 SM2_2 REN_2 TB8_2 RB8_2 TI_2 RI_2 FEh

SBUF2

FFh

Note: Shaded bits are timed-acces s prot ect ed.

41 of 102

Table 2. SFR Reset Values

80h

81h

DPL

82h

DPH

83h

DPL1

84h

DPH1

85h

DPS

86h

PCON

Special

87h

TCON

88h

TMOD

89h

TL0

8Ah

TL1

8Bh

TH0

8Ch

TH1

8Dh

CKCON

8Eh

90h

EXIF

Special

91h

P4CNT

92h

DPX

93h

DPX1

95h

C0RMS0

96h

C0RMS1

97h

SCON0

98h

SBUF0

99h

ESP

9Bh

9Ch

ACON

Special

9Dh

C0TMA0

9Eh

C0TMA1

9Fh

A0h

A1h

P5CNT

A2h

C0C

A3h

C0S

A4h

C0IR

A5h

C0TE

A6h

C0RE

A7h

A8h

SADDR0

A9h

SADDR1

AAh

C0M1C

ABh

C0M2C

ACh

C0M3C

ADh

C0M4C

AEh

C0M5C

AFh

B0h

B1h

P6CNT

B2h

C0M6C

B3h

C0M7C

B4h

C0M8C

B5h

C0M9C

B6h

C0M10C

B7h

B8h

SADEN0

B9h

SADEN1

BAh

C0M11C

BBh

C0M12C

BCh

C0M13C

BDh

C0M14C

BEh

C0M15C

BFh

SCON1

C0h

SBUF1

C1h

PMR

C4h

STATUS

C5h

42 of 102

MCON

C6h

C7h

T2CON

C8h

T2MOD

C9h

RCAP2L

CAh

RCAP2H

CBh

TL2

CCh

TH2

CDh

COR

CEh

PSW

D0h

MCNT0

D1h

MCNT1

D2h

D3h

D4h

D5h

MCON1

D6h

WDCON

Special

D8h

SADDR2

D9h

BPA1

DAh

BPA2

DBh

BPA3

DCh

ACC

E0h

OCAD

E1h

CSRD

E3h

CSRA

E4h

EBS

E5h

BCUD

E6h

BCUC

E7h

EIE

E8h

MXAX

EAh

DPX2

EBh

DPX3

EDh

OWMAD

EEh

OWMDR

EFh

F0h

SADEN2

F1h

DPL2

F2h

DPH2

F3h

DPL3

F4h

DPH3

F5h

DPS1

F6h

STATUS1

F7h

EIP

F8h

F9h

TL3

FBh

TH3

FCh

T3CM

FDh

SCON2

FEh

SBUF2

FFh

Note: Shaded bits are timed-acces s prot ect ed. “Speci al ” bits are affect ed only by cert ain types of reset. Refer t o the user’s guide for details.

43 of 102

TIMED-ACCESS PROTECTION

Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write

operatio n. The t imed-ac cess pr ocedure prev ents er rant beha vior f rom accidentall y alteri ng bits that woul d seri ousl y

affect microcontroller operation. The timed-access procedure requires that the write of a protected bit be

immediately preceded by the following two instructions:

MOV 0C7h, #0AAh

MOV 0C7h, #55h

Writing an AAh followed by a 55h to the timed access register (location C7h), opens a three-cycle window that

allows software to modify one of the protected bits. The protected bits are:

SFR BIT(S) NAME FUNCTION

EXIF (91h)

EXIF.0

BGS

Bandgap Select

P4CNT (92h)

P4CNT.5–0

—

Port 4 Pin Configuration Control Bits

ACON (9Dh) ACON.5 MROM Merge ROM

—

ACON.4

BPME

Breakpoint Mode Enable

—

ACON.3 BROM By-Pass ROM

—

ACON.2 SA Stack Address Mode

—

ACON.1–0

AM1–AM0

Address Mode Select Bits

P5CNT (A2h)

P5CNT.2–0

—

Port 5 Pin Configuration Control Bits

C0C (A3h) C0C.3 CRST CAN 0 Reset

P6CNT (B2h)

P6CNT.5–0

—

Port 6 Pin Configuration Control Bits

—

MCON.5

CAN

CMA Data Memory Assignment

— MCON.3–0 PDCE3–PDCE0 Program/Data-Chip Enables

COR (CEh)

COR.7

IRDACK

IRDA Clock-Output Enable

— COR.4–3 C0BPR7–C0BPR6 CAN 0 Baud Rate Prescale Bits

— COR.2–1 COD1–COD0 CAN Clock-Output Divide Bits

—

COR.0

CLKOE

CAN Clock-Output Enable

MCON1 (D6h)

MCON1.3–0

PDCE7–PDCE4

Program/Data Chip Enable

MCON2 (D7h) MCON2.6–4 WPR2–WPR0 Write-Protect Range Bits

MCON2.3–0

WPE3–WPE0

Write-Protect Enable Bits

WDCON (D8h)

WDCON.6

POR

Power-On Reset Flag

— WDCON.3 WDIF Watchdog Inter r upt Flag

—

WDCON.1

EWT

Watchdog Reset Enable

— WDCON.0 RWT Reset Watchdo g Timer

EBS (E5h) EBS.7 FPE Flush Filter Failed-Packet Enable

—

EBS.4–0

BS4-BS0

Buffer Size Configuration Bits

MEMORY ARCHITE CTURE

The DS80C410 incorporates six internal memory areas:

• 256 Bytes of scratchpad (or direct) RAM

• 8kB of SRAM for Ethernet MAC transmit/receive buffer memory

• 64kB SRAM configurable as a combination of MOVX data memory and code memory

• 1kB SRAM configurable as extended stack memory or MOVX data memory

• 256 Bytes of RAM reserved for the CAN message centers (not available on the DS80C411)

• 64kB embedded ROM firmware

Up to 16MB of external code memory can be addressed through a multiplexed or demultiplexed 22-bit address

bus/8-bit d ata bus thr ough eight a vailab le chip enabl es . Up to 4M B of exter nal d ata m em or y can be acces sed o ver

the same address/data buses through peripheral-enable signals. The DS80C410 also permits a 16MB merged

program/data memory map.

44 of 102

ADDRESSING MODES

Three dif ferent addr essing m odes are s upported, as s elected b y the AM1, AM0 bits in t he address control (ACO N;

9Dh) SFR.

AM1:0 ADDRESS MODE

00b

16-bit (default when internal ROM disabled)

01b

24-bit paged

1xb

24-bit contiguous (default if internal ROM enabled)

16-Bit Address Mode

The 16-bit ad dress mode a cces ses m emor y in a similar m anner as a tr aditio nal 8051. It is op-c ode com patib le with

the 8051 m icroprocess or and ident ical to the byte and cycle count of the Maxim high-speed m icrocontroller f amily.

A device operating in this mode can access up to 64kB of program and data mem ory. The DS80C41 0 defaults to

this mode following any reset.

24-Bit Paged Address Mode

The 24-bit paged address mode retains binary-code compatibility with the 8051 instruction set, but adds one

machine cycle to the ACALL, LCALL, RET, and RETI instructions with respect to the Maxim high-speed

microc ontroller fam ily tim ing. This is trans parent to standar d 8051 com pilers. Interrupt l atency is also i ncreased b y

one machine cycle. In this mode, interrupt vectors are fetched from 0000xxh.

24-Bit Contiguous Address Mode

The 24-bit con tiguous addr essing mode us es a full 24-bit pr ogram c ounter, and all modif ied branching ins tructions

automatically save and restore the entire program counter. The 24-bit branching instructions such as ACALL,

AJMP, LCALL, LJMP, MOV DPTR, RET, and RETI instructions require an assembler, compiler, and linker that

specifically supports th ese f eatures. T he INC DPTR is lengthe ned b y one cycle b ut remains byte-count com patibl e

with the standard 8051 instruction set.

Visit www.maxim-ic.com/microcontrollers for a list of tools that support the DS80C410.

Extended Address Generation

FUNCTION ADDRESS BITS 23–16 ADDRESS BITS 15–8 ADDRESS BITS 7–0

MOVX Instructions Using DPTRn DPXn DPHn DPLn

MOVX Instructions Using @Ri MXAX;EAh P2;A0h Ri

Addressing Program Memory In 24-Bit

Paged Mode

AP;9Ch — —

10-Bit Stack Pointer Mode — ESP;9Bh SP;81h

External Program Memory Addressing

Since the DS80C410 is not bound to the 8051’s traditional 16-bit address mode, on-chip hardware enhancem ents

were made to accommodate the larger memory interfaces associated with 24-bit addressing. The DS80C410

provides SFR bits to configure certain port pins as upper address lines and chip enables. The Port 4 control

and the maximum amount of program memory that can be accessed per chip enable. Tables 3 and 4 illustrate

which port pins are converted to address lines or chip enables as a result of the P4CNT and P6CNT bit settings.

45 of 102

Table 3. Extended Address Gener at io n

P4CNT.5–3 P6.5 P6.4 P4.7 P4.6 P4.5 P4.4

MAX MEMORY ACCESSIBLE

per CE

000

I/O

32kB (Note 1)

001

I/O

A16

128kB

010

I/O

A17

A16

256kB

011

I/O

A18

A17

A16

512kB

100

I/O

A19

A18

A17

A16

1MB

101

I/O

A20

A19

A18

A17

A16

2MB (Note 4)

110 or 111(default)

A21

A20

A19

A18

A17

A16

4MB (Note 2)

Table 4. Chip-Enable Generation

P6CNT.2–0

PORT 6 PIN FUNCTION

P4CNT.2–0

PORT 4 PIN FUNCTION

P6.3

P6.2

P6.1

P6.0

P4.3

P4.2

P4.1

P4.0

000 (Note 3)

I/O

000

I/O

100

I/O

CE4

100

I/O

CE0

101

I/O

CE5

CE4

101

I/O

CE1

CE0

110

I/O

CE6

CE5

CE4

110

I/O

CE2

CE1

CE0

111 (Note 4)

CE7

CE6

CE5

CE4

111(default)

CE3

CE2

CE1

CE0

Note 1: Only 32kB of memory is accessible per chip enable for the P4CNT.5-3 = 000b setting, which means at least two chip enables are

needed in order to address the standard 16-bit (0–FFF F h) address range.

Note 2: The default P 4CNT.5-3 = 111b setting (4MB access ible per CE) requires only f our chip enables in order to acc ess the maximum 24-bit

(0–FFFFFFh) address range.

Note 3: Default condition when the internal ROM is disabled.

Note 4: W hen the internal ROM i s enabled, the defaul t memory map is reconfigured to 2MB per CE, P4CNT.5-3 = 101b, and CE4 to CE7 are

enabled, P6CNT.2-0 = 111b.

External Data Memory Addressing

Using a s imilar im plementation as was us ed to expan d program mem ory access, the D S80C410 al lows up t o 4MB

of data m emory acces s through f our peripheral chip enables (PCE). The Port 5 control r egister (P5CN T; A2h) and

Port 6 c ontro l r e gister (P6C NT; B2h) des ig nate th e n um ber of periphera l ch ip ena bles and the maxim um amount of

addressable data memory per peripheral chip enable. Table 5 shows which port pins are converted to peripheral

chip enab les, along with th e maxim um m em or y access ible t hrough eac h peri pheral chip en abl e f or P5CNT, P6CNT

bit settings.

Table 5. Peripher al Chip-Enable Generation

P5CNT.2–0

P5.7

P5.6

P5.5

P5.4

P6CNT.5–3

MAX MEMORY ACSESSIBLE per PCE

000 (default)

I/O

000 (default)

32kB

100

I/O

PCE0

001

128kB

101

I/O

PCE1

PCE0

010

256kB

110

I/O

PCE2

PCE1

PCE0

011

512kB

111

PCE3

PCE2

PCE1

PCE0

100

1MB

Demultiplexed External Memory Addressing

On power-up or followin g any reset, t he DS80C 410 def aults to the tradit ional 805 1 external m emor y interf ace, wit h

the addres s MSB pr esente d on Por t 2 and th e addr es s LSB a nd data m ultip lexed on Port 0. The m ultiplexe d m ode

requires an external latch to demultiplex the address LSB and data. The DS80C410 provides an external pin (MUX)

that, when pulled h igh during a p ower-on rese t, dem ultiplexes the a ddress LS B and data. If dem ultiplexed m ode is

enabled, the address LSB is provided on Port 7 and the data on Port 0. At the expense of consuming Port 7,

demultiplexed mode eliminates the external demultiplexing latch and the delay element associated with the latch. In

some cases, the removal of this timing delay allows use of slower, less expensive external memory devices.

Table 6 shows pin assignments for the multiplexed (traditional 8051) and demultiplexed external addressing

modes.

46 of 102

Table 6. External Memory Addressing Pin Assignments

ADDRESS

SIGNAL MULTIPL EXED (

MUX

= 0) DEMULTIPLEXED (

MUX

= 1)

A21

P6.5

A20

P6.4

A19

P4.7

A18

P4.6

A17

P4.5

A16

P4.4

A15–A8

P2.7–P2.0

A7–A0

P0.7–P0.0

P7.7–P7.0

DATA D7–D0 P0.7–P0.0 P0.7–P0.0

CHIP ENABLES

CE7

P6.3

CE6

P6.2

CE5

P6.1

CE4

P6.0

CE3

P4.3

CE2

P4.2

CE1

P4.1

CE0

P4.0

PERIPHERAL CHIP

ENABLES

PCE3

P5.7

PCE2

P5.6

PCE1

P5.5

PCE0

P5.4

Combined Program/Data Memory Access

The DS80C410 can be configured to allow data memory access (MOVX) to the program memory area. This feature

might be useful, for example, when modifying lookup tables or supporting in-application programming of code

space. Setting any of the PDCE7-4 (MCON1.3-0) or PDCE3-0 (MCON.3-0) bits enables combined program/data

memory access and causes the corresponding chip-enable (CE) signal to function for both MOVC and MOVX

operations. When combined program/data memory access is enabled, the peripheral chip-enable (PCE) signals

previous ly assig ned to that data m emor y space are d isabled. W rite ac cess to combin ed progr am and data mem or y

blocks is controlled by the WR signal, and read access is controlled by the PSEN signal. This feature is especially

useful if the design ac hieves in-s ystem reprogramm ability throug h external f lash mem ory, in which a single dev ice

is accessed through both MOVC instructions (program fetch) and MOVX write operations (updates to code

memory). Figure 1 demonstrates how setting PDCE bits can alter external memory data access.

W hen combined pro gram /data m em or y access is ena bled, there is the pot ential to ina dvertent l y modify code that a

user meant to leave fixed. For this reason, the DS80C410 provides the ability to write protect the first 0–16kB of

memory accessible through each of the chip enables CE3, CE2, CE1, and CE0. The write-protection feature for

each chip enable is invoked by setting the appropriate W PE3–0 (MCON2.3-0) bit. The protected range is defined

by the WPR2–0 (MCON2.6–4) bit settings as shown in Table 7. Any MOVX instructions attempting to write to a

protected area are disallowed and set the write-protected interrupt flag (W PIF–MCON2.7), causing a write-protect

interrupt if enabled.

Table 7. Write-Protection Range

MCON2.6–4 RANGE PROTECTED (kB)

000

0 to 2

001

0 to 4

010

0 to 6

011

0 to 8

100

0 to 10

101

0 to 12

110

0 to 14

111

0 to 16

47 of 102

Figure 1. Example External Memory Map—Merged P r ogr am/Data

Enhanced Quad Da ta Pointe r s

The DS80C410 of fers enhanced features for accelerating the access and movement of data. It contains four data

pointers (DPTR0, DPTR1, DPTR2, and DPTR3), in comparison to the single data pointer offered on the original

8051, and allows the user to define, for each data pointer, whether the INC DPTR instruction increments or

decrements the selected pointer. Also, realizing that many data accesses occur in large contiguous blocks, the

DS80C410 can be configured to automatically increment or decrement a data pointer on execution of certain

instructions. This improvement greatly speeds access to consecutive pieces of data since hardware can now

accom plish a task (advanc ing the data pointer) that previousl y requ ired software execution t ime. Finall y, eac h pair

of data pointer s (D PT R0, D PT R1 or DPT R 2, DPT R 3) can be conf igure d f or an auto-togg le mode. W hen plac ed into

this mode, certain data pointer-relat ed ins tr uct ions tog gle the acti ve data-pointer selection to the other pointer in the

pair. Enabling the auto-toggle feature, with one pointer to source data and a second pointer to destination data,

greatly speeds the copying of large data blocks.

DPTR0 is located at the same address as the original 8051 data pointer, allowing the DS80C410 to execute

standard 8051 code with n o modificat ions. T he registers m aking up the seco nd, third, and f ourth data p ointers are

located at SFR address locations not used in the original 8051. To access the extended 24-bit address range

supported by the DS80C410, a third, high-order byte (DPXn) has been added to each pointer so that each data

pointer is now composed of the SFR combination DPXn+DPHn+DPLn. Table 8 summarizes the SFRs that make

up each data pointer.

CE0

=2M x 8

PCE0

= 1M x 8

PCE1

= 1M x 8

PCE2

= 1M x 8

PCE3

= 1M x 8

CE1

=2M x 8

CE7

= 2M x 8

CE6

= 2M x 8

CE5

= 2M x 8

CE4

= 2M x 8

CE3

= 2M x 8

CE2

=2M x 8

PROGRAM

MEMORY

DATA

MEMORY

NONADDRESSABLE

CE0

= 2M x 8

PCE2

= 1M x 8

PCE3

= 1M x 8

CE1

= 2M x 8

CE7

= 2M x 8

CE6

= 2M x 8

CE5

= 2M x 8

CE4

= 2M x 8

CE3

= 2M x 8

CE2

= 2M x 8

PROGRAM

MEMORY

DATA

MEMORY

NONADDRESSABLE

PROGRAM/

DATA

MEMORY

PDCE3

= 1

PDCE0

= 1

BEFORE

AFTER

48 of 102

Table 8. Data Pointer SFR Locations

DATA POI NTER

DPX+DPH+DPL COMBINATION

DPTR0

DPX (93h) + DPH (83h) + DPL (82h)

DPTR1

DPX1 (95h) + DPH1 (85h) + DPL1 (84h)

DPTR2

DPX2 (EBh) + DPH2 (F3h) + DPL2 (F2h)

DPTR3

DPX3 (EDh) + DPH3 (F5h) + DPL3 (F4h)

The act ive data pointer is select ed with the dat a pointer select bi ts SEL1 (DPS. 3) and SEL (D PS.0). For the SEL 1

and SEL bits , the 00b stat e selec ts DPT R0, 01b selec ts DPTR1, 10b s elects D PTR2, and 11b s elects DPT R3. An y

instructio ns that refer ence the DPT R (i.e., MOVX A, @DPTR) use th e data pointer s electe d by the SEL1, SEL bit-

pair c ombination. T o allow f or code compatibil ity wit h previous dua l data pointer microcontroller s, the bits adj acent

to SEL are not implemented so that the INC DPS instruction can still be used to quickly toggle between DPTR0 and

DPTR1 or between DPTR2 and DPTR3.

Unlike the standard 8051, the DS80C410 has the ability to decrement as well as increment the data pointers

without additional instructions. Each data pointer (D PTR0, DPTR1, DPTR2, DPTR3) has an associated control bit

(ID0, ID1, ID2, ID3) that determines whether the INC DPTR operation results in an increment or decrement of the

pointer. When the active data pointer ID (increment/decrement) control bit is clear, the INC DPTR instruction

increments the pointer, whereas a decrement occurs if the active pointer’s ID bit is set when the INC DPTR

instruction is performed.

ID0 = DPS.6

ID1 = DPS.7

ID2 = DPS1.6

ID3 = DPS1.7

Another usef ul feature of the device is its abi lit y to autom atically switch th e active data p ointer after certain DPT R-

based instructions are executed. This feature can greatly reduce the software overhead associated with data

memory block m oves , whic h tog gl e be t ween t he s our ce and des t ina tion r eg is ters . The auto-togg le f eat ur e do es not

toggle between all four data pointers, nor does it allow the user to select which data pointers to toggle between.

When the toggle select bit (TSL;DPS.5) is set to 1, the SEL bit (DPS.0) is automatically toggled every time one of

the DPT R instructi ons belo w is execu ted. T hus, depe nding upo n the stat e of the SEL1 bi t (DPS.3), the act ive dat a

pointer toggles the DPTR0, DPTR1 pair or the DPTR2, DPTR3 pair.

Auto-Toggle (if TSL = 1)

INC DPTR

MOV DPTR, #data16

MOV DPTR, #data24

MOVC A, @A+DPTR

MOVX A, @DPTR

MOVX @DPTR, A

As a brief example, if TSL is set to 1, then both data pointers can be updated with two INC DPTR instructions.

Assume that SEL1 = 0 and SEL = 0, making DPTR0 the active data pointer. The first INC DPTR increments

DPTR0 and toggles SEL to 1. The second instruction increments DPTR1 and toggles SEL back to 0.

INC DPTR

As a furt her enh anc ement, the D S80C 410 pr o vides th e abi l it y to au tomaticall y increment/decrem ent t he act iv e data

pointer after certain DPTR-based instructions are executed. Copying large blocks of data generally requires that

the source an d des t ina ti on poi nter s i ndex b yte-by-byte throu gh t heir r es pec ti ve da t a ran ges . The trad it ional metho d

for incrementing each pointer is by using the INC DPTR instruction. When the auto-increment/decrement bit

(AID:DPS. 4) is set to 1, the act ive data po inter is autom atically increm ented or decrem ented every time one of the

DPTR instructions below is executed.

49 of 102

Auto-Increment/Decrement (if AID = 1)

MOVC A, @A+DPTR

MOVX A, @DPTR

MOVX @DPTR, A

When used in conjunction, the auto-toggle and auto-increment/decrement features can produce very fast and

efficient routines for copying or moving data. For example, suppose you want to copy three bytes of data from a

source location (pointed to by DPTR2) to a destination location (pointed to by DPTR3). Assuming that DPTR2 is

the active pointer (SEL 1 = 1, SEL = 0), with TSL = 1 and AID = 1, the i nstructio n sequence below copies the three

bytes:

MOVX A, @DPTR

MOVX @DPTR, A

MOVX A, @DPTR

MOVX @DPTR, A

MOVX A, @DPTR

MOVX @DPTR, A

Stretch Memory Cycles

The DS80C410 allows user-application software to select the number of machine cycles it takes to execute a

MOVX instruction, allowing access to both fast and slow off-chip data memory and/or peripherals without glue

logic. High-speed systems often include memory-mapped peripherals such as LCDs or UARTs with slow access

times, so it may not be necessary or desirable to access external devices at full speed. The microprocessor can

perform a MOVX instruction in as little as two machine cycles or as many as 12 machine cycles. Accesses to

internal MOVX SRAM always use two cycles. Note that stretch cycle settings affect external MOVX memory

operatio ns on ly an d t her e i s no wa y to slow the ac c ess es to pr o gram m em ory other than to us e a s lo wer cr ystal ( or

external clock).

External MOVX timing is governed by the selection of 0-to-7 stretch cycles, controlled by the MD2–MD0 SFR bits in

the clock contr ol register (CKCO N.2–0). A stretc h of 0 res ults in a 2-machine cycle MOVX ins truc tion. A st retc h of 7

results in a MOVX of 12 machine cycles. Software can dynamically change the stretch value depending on the

particular memory or peripheral being accessed. The default of one stretch cycle allows the use of commonly

available SRAMs without dramatically lengthening the memory access times.

Stretch c ycle settin gs aff ect ext ernal MOVX tim ing in th ree gradat ions. Changin g the stretc h value fr om 0 to 1 adds

an additional clock cycle each to the data setup and hold times. Stretch values of 2 and 3 each stretch the WR or

RD signal by an additional machine cycle. When a stretch value of 4 or above is selected, the interface timing

changes dram atically to allow for very slow peripher als. First, the ALE signal is lengthened by one machine c ycle.

This increases the address setup time into the peripheral b y this am ount. Next, the address is held on the bus for

one additional machine cycle, increasing the address hold time by this amount. The WR and RD signals are then

lengthened by a machine cycle. Finally, during a MOVX write the data is held on the bus for one additional machine

cycle, thereby increasing the data hold time by this am ount. For every stretch value greater than 4, the setup and

hold tim es rem ain consta nt, and o nly the width of the read or write s ignal is incre ased. Thes e three gr adati ons are

reflected in the AC Electrical Characteristics section, where the eight MOVX timing specifications are represented

by only three timing diagrams.

The res et default of one s tr etch c ycle res ults in a three -c ycle MOVX f or an y external acces s. T heref ore, the def ault

off-chip RAM access is not at full speed. This is a convenience to existing designs that use slower RAM. When

maxim um s peed is des ired, sof tware s hould select a st retch v alue of 0. When us ing ver y slo w RAM or per ipher als,

the application software can select a larger stretch value.

The s pecific timing of MO VX instructions as a f unction of stretc h settings is pr ovided in the Elec trical Specific ations

section of this data sheet. As an exam ple, Table 9 shows the read and write strobe widths corresponding to each

stretch value.

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Table 9. Data Memory Cycle Stretch Values

MD2 MD1 MD0 STRETCH

VALUE

MOVX

MACHINE

CYCLES

APPROXIMATE RD, WR PULSE WIDTH

(IN OSCILLATOR CLOCKS)

(4X/2X =

CD1:0 = 00)

(4X/2X =

CD1:0 = 00)

(4X/2X =

CD1:0 = 10)

(4X/2X =

CD1:0 = 11)

0 (Note 1)

0.5 tCLK

1 tCLK

2 tCLK

512 tCLK

1 (Note 2)

1 tCLK

2 tCLK

4 tCLK

1024 tCLK

2 tCLK

4 tCLK

8 tCLK

2048 tCLK

3 tCLK

6 tCLK

12 tCLK

3072 tCLK

4 tCLK

8 tCLK

16 tCLK

4096 tCLK

5 tCLK

10 tCLK

20 tCLK

5120 tCLK

6 tCLK

12 tCLK

24 tCLK

6144 tCLK

7 tCLK

14 tCLK

28 tCLK

7168 tCLK

Note 1: All internal MOVX operations execute at the 0 stretch setting.

Note 2: Default stretch setting for external MOVX operations f ol l owing reset, pri or to execution of internal ROM.

Internal MOVX SRAM

The DS80C410/411 incorporates 73.25kBytes on-chip SRAM for MOVX memory. The on-chip SRAM is physicall y

divided into four memory blocks: a dedicated 64Kx8 data or program/data memory, a 1Kx8 memory block for

extended stack or data memory, and 256 bytes of dual port RAM for control and storage of CAN messages. The

address locations of these four blocks are fixed and cannot be altered. Figure 2 shows the default memory

configuration of the DS80C410.

Figure 2. Internal Data Memory

The 8k B (2kx32) block is us ed by the Et hernet M AC as f rame-buffer m emory for inc oming or outg oing pac ket data

and can, at the same time, be accessed by the DS80C410 as MOVX data memory. While the MAC is in use,

special care should be taken by user software to prevent undesirable MOVX writes from corrupting frame-buffer

memory. Note: that when the SA bit (ACON.2) is set, 1kB of the MOVX data memory is accessed by the 10-bit

extended s tack pointer . Th e ad ditional 256 Bytes of inter nal S RAM are used to c onfigure an d operate the 1 5 CA N-

controller message centers.

2Kx32 SRAM

(DATA ME MORY OR

NETWORK BUFFER

MEMORY)

1Kx8 SRAM

(DATA ME MORY OR

OPTIO N AL STACK)

256x8 DPSRAM

(CAN DATA MEMORY)

64Kx8 SRAM

(DATA MEMORY)

INTERNAL DATA MEMOR Y

FFFFFF

FFDC00

FFDBFF

FFDB00

00FFFF

000000

FFE000

FFDFFF

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Extended Sta ck Po int er

The DS80C410 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the

performance of large programs written in high-level languages such as C. To enable the 10-bit stack pointer, set

the stack-address mode bit, SA (ACON.2). The bit is cleared following a reset, forcing the device to use an 8-bit

stack located in the scratchpad RAM area. When the SA bit is set, the device addresses up to 1kB of internal

MOVX memory for stack purposes. The 10-bit stack pointer address is generated by concatenating the lower two

bits of the extended stack pointer (ESP;9Bh) and the traditional 8051 stack pointer (SP;81h).

On-Chip Arithmetic Accelerator

An on-c hip m ath accelerator all ows the micr ocontroller to perf orm 32-bit and 16-bit m ultiplic ation , divisio n, shift ing,

and norm alization using dedicated hardware. Math operations are performed by sequentiall y loading three special

registers . T he m at hem atica l oper at io n is deter mined by the sequence in w hich three dedicat e d SFRs ( MA, M B, and

MCNT0) are accessed, eliminating the need for a special step to choose the operation. The normalize function

facilitates the conversion of 4-Byte unsigned binary integers into floating point format. Table 10 shows the

operations supported by the math accelerator and their time of execution.

Table 10. Arithmetic Accelerator Execution Times

OPERATION

RESULT

EXECUTION TIM E

32-Bit/16-Bit Divide

32-Bit Quotient, 16-Bit Remainder

36 tCLCL

16-Bit/16-Bit Divide

16-Bit Quotient, 16-Bit Remainder

24 tCLCL

16-Bit/16-Bit Multiply

32-Bit Product

24 tCLCL

32-Bit Shift Left/Right

32-Bit Result

36 tCLCL

32-Bit Normalize

32-Bit Mantissa, 5-Bit Exponent

36 tCLCL

Table 11 demonstrates the procedure to perform mathematical operations using the hardware math accelerator.

The MA and M B register s must be loaded an d read in the order show n for proper operat ion, although acc esses to

any other registers can be performed bet ween accesses to the MA or MB registers. An access to the MA, MB, or

MC regis ters out of s equence corr upt the operat ion, requiring t he software t o clear the MST bit to restart t he math

accelerator state machine. See the descriptions of the MCNT0 and MCNT1 SFRs for details about how the shift

and normalize functions operate.

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Table 11. Arithmetic Accelerator Sequencing

DIVIDE (32/16 or 16/16) MULTIPLY (16 x 16)

Load MA with dividend LSB.

Load MA with dividend LSB + 1*.

Load MA with dividend LSB + 2*.

Load MA with dividend MSB.

Load MB with divisor LSB.

Load MB with divisor MSB.

Poll the MST bit until cleared.

(9 machine cyc le s for 32-bit numerator)

(6 machine cyc le s for 16-bit numerator)

Read MA to retrieve the quotient MSB.

Read MA to retrieve the quotient LSB + 2*

Read MA to retrieve the quotient LSB + 1*

Read MA to retrieve the quotient LSB.

Read MB to retrieve the remainder MSB.

Read MB to retrieve the remainder LSB.

Load MB with multiplier LSB.

Load MB with multiplier MSB.

Load MA with multiplicand LSB.

Load MA with multiplicand MSB.

Poll the MST bit until cleared (6 machine cycles).

Read MA for product MSB.

Read MA for product LSB + 2.

Read MA for product LSB + 1.

Read MA for product LSB.

SHIFT RIGHT/LEFT NORMALIZE

Load MA with data LSB.

Load MA with data LSB + 1.

Load MA with data LSB + 2.

Load MA with data MSB.

Configure MCNT0/MCNT1 registers as required.

Poll the MST bit until cleared (9 machine cycles).

Read MA for result MSB.

Read MA for result LSB + 2.

Read MA for result LSB + 1.

Read MA for result LSB.

Load MA with data LSB.

Load MA with data LSB + 1.

Load MA with data LSB + 2.

Load MA with data MSB.

Configure MCNT0.4–0 = 00000b.

Poll the MST bit until cleared (9 machine cycles).

Read MA for mantissa MSB.

Read MA for mantissa LSB + 2.

Read MA for mantissa LSB + 1.

Read MA for mantissa LSB.

Read MCNT0.4–MCNT0.0 for exponent.

*Not performed for 16-bit numerator.

40-Bit Accumulator

The accelerator also incorporates an automatic accumulator function, permitting the implementation of multiply-

and-accumulate and divide-and-accumulate functions without any additional delay. Each time the accelerator is

used for a multiply or divide operation, the result is transparently added to a 40-bit accumulator. This can greatly

increase speed of DSP and other high-level math operations.

The accumulator can be accessed any time the multiply/accumulate status flag (MCNT1;D2h) is cleared. The

accumulator is initialized by performing five writes to the multiplier C register (MC;D5h), LSB first. The 40-bit

accumulator can be read by performing five reads of the multiplier C register, MSB first.

Ethernet Controlle r

The DS80C410 incorporates a 10/100Mbps Ethernet controller, which supports the protocol requirements for

operating an Ethernet/IEEE 802.3-compliant PHY device. It provides receive, transmit, and flow control

mechanis ms thr ough a media-ind ependent in terface ( MII), which inc ludes a seri al m anagement bus for configurin g

external PH Y devices. T he MII can be co nfigured t o operate i n half-duplex or full-dupl ex mode at either 10Mbps or

100Mbps, or can support 10Mbps ENDEC mode operation. The system clock (external clock source after internal

multiplication or division) must be a minimum of 25MHz for use of the Ethernet 100Mbps mode.

For half-duplex mode operation, the DS80C410 shares the Ethernet physical media with other stations on the

network. The DS80C410 follows the IEEE 802.3 carrier-sens e multiple-access with collision detection (CSMA/CD)

method for accessing the physical media. The MAC waits until the physical carrier is idle before attempting a

transmission. Having multiple stations on the network results in the possibility of transmissions from different

stations colliding. When a c ollisio n is detec ted, th e MAC waits som e num ber of tim e slots (ac cording to a n interna l

back-off timer) before attempting retransmission. Unless instructed otherwise, the MAC automatically attempts to

retransmit collided frames up to 16 times before aborting the transmit frame. As a means of flow control when

receiving data, the MAC uses a back-pressure scheme, transmitting a jamming signal to force collisions on

incoming frames transmitted by other stations. Using this back-pressure scheme gives the DS80C410 control of

the network or time to free up needed receive data buffers.

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For full-duplex mode operation, the physical media connects the DS80C410 directly to only one other station,

allowing simultaneous transmit and receive activity between the two without risk of collision. Hence, no media-

access method (i.e., CSMA/CD) needs to be used. For full-duplex operation, the flow control mechanism is the

PAUSE control frame. When needing time to free additional receive data buffers, the DS80C410 can initiate a

PAUSE control frame, requesting that the other station suspend transmission attempts for a specified number of

time slots.

Figure 3. Ethernet Controller Bl ock Diagram

MII MA NAGEMENT

BLOCK

<SERIAL

INTERFACE BUS TO

EXTERNAL PHY(s)>

MII I/O BLOCK

(TRANSMIT,

RECEIVE, AND

FLOW CONTROL)

CSR REGIS TERS

ADDRESS CHECK

BLOCK

POWER MANAGEMENT

BLOCK

MAC HOST INTERF ACE

BCU

Tx/Rx BUFFE R

MEMORY

(8kB)

EXTERNAL

PHY(s)

DS80C400 ON-CHIP ETHERNET CONTROLLER

DS80C400

CPU

NOTE: WHEN CONNECTING THE DS80C400 TO AN EXTERNAL PHY, DO NOT CONNECT THE RSTOL TO THE RESET OF THE PHY. DOING SO MAY

DISABLE THE ETHERNET TRANSMIT.

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Buffer Control Unit

The buff er contr ol unit (BCU) serves as the centr al co ntroller of all DS80C 410 Et hernet ac tivit y. The BCU regulates

CPU read/ write acti vit y to the Ether net c ontroll er bloc ks thr ough a seri es of SFRs: BCU contr ol (BCU C; E7h), BCU

data (BCUD ; E6h), C SR ad dress (CSRA; E4h), and C SR d ata (CSR D; E3h). T hes e SFRs allows the CPU to issue

commands to the BCU, exchange packet size/location information with the BCU, configure the on-chip Ethernet

MAC, and even communicate with external PHYs through the MII serial-management bus.

Table 12 outlines the comm ands that can be issued thr ough the BCUC regist er. Prior to issuing a write ( 1000b) or

read (1001b) CSR register command, the CSRA SFR must be configured to address a valid CSR register. For

each CSR register write, the CSRD SFR must be loaded with the data to be written prior to issuing the write

comm and, w hereas o n a r e ad, C SRD r et ur ns the CSR r egister d ata f ol lo wing the read com mand. Table 13 lists t he

CSR register addresses and functions.

Table 12. Buffer Control Unit Commands

COMMAND

(BCUC.3:BCUC.0)

OPERATION

0000

No Operation (default)

0010

Invalidate Current Receive Packet

0011

Flush Receive Buffer

0100

Transmit Request (normal)

0101

Transmit Request (disable padding)

0110

Transmit Request (disable CRC)

1000

Write CSR Register

1001

Read CSR Register

1100

Enable Sleep Mode

1101

Disable Sleep Mode

Other

Reserved

Table 13. CSR Registers

CSR REGISTER ADDRESS

(CSRA)

FUNCTION

00h

MAC Control

04h

Ethernet MAC Physical Address [47:32]

08h

Ethernet MAC Physical Address [31:0]

0Ch

Multicast Address Hash Table [63:32]

10h

Multicast Address Hash Table [31:0]

14h

MII Address

18h

MII Data

1Ch

Flow Control

20h

VLAN1 Tag

24h

VLAN2 Tag

28h

Wake-Up Frame Filter

2Ch

Wake-Up Events Control and Status

Other

Reserved

The BCU is respons ible for coor dinating a nd reporti ng status f or all data-p acket tr ansactions between the Ethernet

MAC and the 8kB packet-buff er memory. The si ze of t he transmit and r eceive buf fers within the 8k B packet-buffer

memory is user-configurable through the EBS (E5h) register. During transmit and receive operations, the BCU

operates acc or di ng to the u s er -def ined buf f er alloc ati o n an d tr ac k s c ons umption of r eceiv e b uf f er m em or y so th at a

receive-buffer-full condition can be signaled.

For a rec eive oper ation, the BCU f irst m ust ass ess whether there ar e any op en pages in rec eive buf fer m emory to

accommodate an incoming packet. If there are not open pages, the receive-buffer-full (RBF; EBS.6) flag is set.

Until the RBF condition is cleared, all incoming frames are missed. If receive buffer memory has open pages, the

received data is stored in the first open page starting at byte offset 4, leaving the first 4 bytes open for packet status

reporting. Receive packets requiring multiple pages are stored in consecutive pages. Note that the receive buffer

operates as a circ ular que u e, with pa ge 0 be ing the c onsec utive p age to f ollow th e final (n - 1) rece ive buff er page.

The BCU stores incoming data to receive buffer memory until the transaction is complete or until the reception is

aborted. T he BCU i ncorpor ates a 31 x 8 firs t-in-first-out receive pac ket r egister ( receive F IFO) s o that the C PU c an

55 of 102

access information for the next receive packet in queue. Upon reception of each valid packet into receive buffer

mem ory, the BCU writes a receive status word into the first word of the r eceive packet starting page, updates the

receive FIFO, and notifies the CPU by setting an interrupt flag. The CPU can ac cess the receive FIFO by read ing

the BCUD SFR. Bits 4–0 of the data read f rom BCUD contain th e start ing page a ddress and bits 7, 6, 5 reflec t the

number of pages occupied by the packet.

For a transmit operation, the tasks performed by the BCU are similar. The CPU first provides size/location

inform ation of the transm it pac k et to the BCU. T his is ac complishe d b y three c onsec utive writes to t he BCU D SFR.

The first write specifies the MSB of the 11-bit byte count for the transmit packet, the second gives the LSB of the

11-bit byte count, and the third provides the starting page address for the packet. Note that at page 31 of the

transm it buffer, the next c onsecutive page is page (n). The CPU issues a tr ansmit request t o the BCU, w hich then

comm unicates this request to the MAC. Once started , the BCU reads data f rom transm it buffer memory and f eeds

the data to the MAC for presentation on the MII. This process continues until the transaction is complete or the

transmission is aborted. The BCU then writes a transmit status word back to transmit buffer memory and notifies

the CPU by setting the interrupt flag. Transmit buffer management should be handled by the application code.

Command/Status (CSR) Registers

The CSR registers are essential in defining the operational characteristics of the Ethernet controller. The CSR

registers contain the following key items:

• MAC physical address

• Transmit, receive, and flow control settings for the MAC

• Multicast hash table used by the address check block

• Filter mode and good/bad frame controls for the address check block

• VLAN tag identifiers

• Wake-up frame filter

• Register interface for serial MII PHY management bus

Each CSR reg ister is 32-b its wide and is acc essibl e using the BCUC , CSR A, CSRD SFR interf ace desc ribed in the

Buffer Control Unit section. To program a CSR register, the application code must provide data (CSRD) and

address (CSRA) for the target register before issuing the ‘Write CSR Register’ command to the BCU. When

performing a CSR register read, the application code provides the address (CSRA), issues the ‘Read CSR

procedures for writing an d read ing the CSR regis ter s.

CSR Register Write

Load CSRD with MSB of 32-bit word to be written.

Load CSRD with LSB + 2 of the 32-b it word to be writt en.

Load CSRD with LSB + 1 of the 32-b it word to be writt en.

Load CSRD with LSB of the 32-bit word to be written.

Load CSRA with address of the CSR register to be written.

Issue the ‘Write CSR Register’ command to the BCU by writing BCUC.3–BCUC.0 = 1000b.

CSR Register Read

Load CSRA with address of the CSR register to be read.

Issue the ‘Read CSR Register’ command to the BCU by writing BCUC.3–BCUC.0 = 1001b.

Wait until the BCU busy bit (BCUC.7) = 0.

Unload CSRD for the MSB of the 32-b it word.

Unload CSRD for the LSB + 2 of the 32-bit word.

Unload CSRD for the LSB + 1 of the 32-bit word.

Unload CSRD for the LSB of the 32-b it word.

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Each CSR register is documented as follows:

CSR Register: MAC Control

Bit Names:

BLE

—

HBD

—

DRO

OM[1:0]

—

LCC

DBF

DRTY

—

ASTP

BLOMT[1:0]

—

Reset State:

RA, Receive All. This bit overrides the flush-filter failed-packet function if that function has been enabled

(EBS.7 = 1).

0 = default frame handling (default)

1 = all error-free frames are received with packet filter bit set (= 1) in the receive status word

BLE, Big/Little Endian Mode

0 = data buffers are operated in little Endian mode (default)

1 = data buffers are operated in big Endian mode

HBD, Heart-Beat Disable. This bit is only useful in ENDEC mode and has no affect on MII mode operation.

0 = heart-beat signal quality-generator function enabled (default)

1 = heart-beat signal quality-generator function is disabled

PS, Port Select

0 = MII mode (default)

1 = ENDEC mode

DRO, Disable Receive Own. This bit should always be cleared to a logic 0 for full-duplex operation and any

loopback operating modes other than “normal mode.”

0 = MAC receives all packets given by the PHY (default)

1 = MAC disables reception of frames during frame transmission (TX_EN = 1)

OM[1:0], Loopback Operating Mode

00 = normal mode, no loopback (default)

01 = internal loopbac k thro ugh MII

10 = external loopb ac k through PHY

11 = reserved

F, Full-Duplex Mode

0 = half-duplex mode (default)

1 = full-duplex mode

PM, Pass All Multicast

0 = multicast frames filtered according to current multicast filter mode (default)

1 = pass all multicast frames; filter-fail bit is reset (= 0) for all multicast frames received

PR, Promiscuous Mode

0 = promiscuous mode disabled

1 = promiscuous mode enabled (default)

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IF, Inverse Filtering

0 = inverse filtering disabled (default)

1 = inverse filtering by the address check block enabled

PB, Pass Bad Frames

0 = packet filter bit in the receive status word is set (= 1) only when error-free frames received (default)

1 = packet filter bit in the receive status word is set (= 1) for frames that pass the destination address filter even

when they contain errors. Promiscuous mode should always be used when this bit is set.

HO, Hash-Only Filtering Mode

This bit should only be set when HP = 1.

0 = filter unicast frames according to filter mode configuration (default)

1 = hash filtering of unicast and multicast frames by the address check block

HP, Hash/Perfect Filtering Mode

0 = perfect filtering by the address check block for unicast and multicast frames (default)

1 = hash filtering by the address check block for multicast frames and perfect filtering of unicast frames

LCC, Late Collis ion Control

0 = transmission is aborted if a late collision is encountered (default)

1 = allows frame retransmission attempts even when a late collision is encountered

DBF, Disable Broadcast Frames

0 = packet filter bit in the receive status word is set (= 1) for each broadcast frame received (default)

1 = packet filter bit in the receive status word is reset (= 0) for each broadcast frame received

DRTY, Disable Retry

0 = MAC attempts to transmit a frame 16 times before signaling a retry error (default)

1 = MAC attempts to transmit a frame only once before signaling a retry error

ASTP, Automatic Pad Stripping

0 = receive frames are transferred to the BCU without modification (default)

1 = zero padding and CRC are stripped for receive frames, which specify a data length less than 46 Bytes

BOLMT[1:0], Back-Off Limit. The back -off pr otoc ol requ ires that the MAC wait s ome number of tim e s lots (512b its

/ time s lot) bef ore resc hedulin g a transm is sion attem pt. A 10-bit f re e-running c ount er is us ed to gener ate th is bac k-

off delay. The BOLMT[1:0] bits select the number of bits to be used from the 10-bit counter.

00 = 10 bits (0 to 1024 time slots, default)

01 = 8 bits (0 to 256 time slots)

10 = 4 bits (0 to 16 time slots)

11 = 1 bit (none or 1 time slot)

DC, Deferral Check

0 = MAC can defer indefinitely while waiting to transmit (default)

1 = MAC aborts a transmission attempt if it has deferred for more than 24,288 consecutive bit times

TE, Transmitter Enable

0 = transmitter disabled (default)

1 = transmitter enabled

RE, Receiver Enable

0 = receiver disabled (default)

1 = receiver enabled

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CSR Register: MAC Address High

Bit Names:

—

PADR [47:40]

PADR [39:32]

Reset State:

PADR [47:32]m MAC Physical Address [47:32]. These two bytes represent the 16 most significant bits of the

MAC physical address.

CSR Register: MAC Address Low

Bit Names:

PADR [31:24]

PADR [23:16]

PADR [15:8]

PADR [7:0]

Reset State:

PADR [31:0], M AC Physical Address [31:0]. T hese four bytes represent the 32 least significant bits of the MAC

physical address .

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CSR Register: Multicast Address High

Bit Names:

HT[63]

HT[62]

HT[61]

HT[60]

HT[59]

HT[58]

HT[57]

HT[56]

HT[55]

HT[54]

HT[53]

HT[52]

HT[51]

HT[50]

HT[49]

HT[48]

HT[47]

HT[46]

HT[45]

HT[44]

HT[43]

HT[42]

HT[41]

HT[40]

HT[39]

HT[38]

HT[37]

HT[36]

HT[35]

HT[34]

HT[33]

HT[32]

Reset State:

HT [63:32], Hash Table [63:32]. These bits represent the upper 32 bits of the 64-bit hash table that are used for

hash table filtering. The multicast hash-filtering mode is detailed later in the data sheet.

CSR Register: Multicast Address Low

Bit Names:

HT[31]

HT[30]

HT[29]

HT[28]

HT[27]

HT[26]

HT[25]

HT[24]

HT[23]

HT[22]

HT[21]

HT[20]

HT[19]

HT[18]

HT[17]

HT[16]

HT[15]

HT[14]

HT[13]

HT[12]

HT[11]

HT[10]

HT[9]

HT[8]

HT[7]

HT[6]

HT[5]

HT[4]

HT[3]

HT[2]

HT[1]

HT[0]

Reset State:

HT [ 31:0] , Hash T ab le [31: 0] . These bits r epres ent t he lo wer 3 2 bi ts of the 64-b it has h tab le t hat are used f or has h

table filtering. The multicast hash-filtering mode is detailed later in the data sheet.

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CSR Register: MII Address

Bit Names:

—

PHYA [4:0]

PHYR [4:2]

7 PHYR [1:0] — — — —

BUSY 0

Reset State:

PHYA[4:0], PHY Address [4:0]. This 5-bit address specifies the PHY address for 2-wire MII serial-management

bus communication.

PHYR[4:0], PHY Register Select [4:0]. This 5-bit field specifies the PHY register to be accessed in 2-wire MII

serial-management bus communication.

, Write/Read. This bit is used to indicate whether a write or read operation is to be requested of the addressed

PHY/PHY register.

0 = read

1 = write

BUSY, Busy. This status bit indicates when PHY communication is currently taking place on the MII serial-

management bus. The application must wait until BUSY = 0 before modifying the MII address and MII data

registers prior to each read/write operation.

0 = MII serial-management bus idle

1 = MII serial-management bus busy (write/read in progress)

CSR Register: MII Data

Bit Names:

—

PHYD [15:8]

PHYD [7:0]

Reset State:

PHYD[15:0], PHY Data [15:0]. These 16 bits contain the data read from the PHY register following a read

operation, or the data to be written to the PHY register prior to a write operation.

61 of 102

CSR Register: Flow Control

Bit Names:

PAUSE [15:8]

PAUSE [7:0]

—

PCF

FCE

BUSY

Reset State:

PAUSE[15:0], Pause Time [15:0]. These bits are only valid in full-duplex mode. These 16 bits contain the value

that is passed in the pause time field when a pause-control frame is generated. The format for the pause-control

frame is shown in Figure 4.

PCF, Pas s Pause-Control Frame. This bit is valid for full-duplex mode only. This bit instructs the MAC whether or

not to set the packet filter bit for pause-control frames.

0 = MAC decodes (if FCE = 1) but does not set the receive status word packet-filter bit (default)

1 = MAC decodes (if FCE = 1) and sets the packet-filter bit = 1 for pause-control frames

FCE, Flow Control Enable

0 = MAC flow control is disabled (default)

1 = MAC flow control enabled; pause-control frame for full-duplex , bac k -pressure for half-duplex

BUSY, Flow Control Busy. The BUSY bit is only valid in full-duplex mode. The BUSY bit should read logic 0

before initiating a pause-control frame. The BUSY bit should be set to logic 1 to initiate a pause-control frame.

Upon successful transmission of a pause-control frame, the BUSY bit returns to logic 0.

0 = no pause-control frame currently being transmitted (default)

1 = initiate a pause-control f r am e

Figure 4. Pause-Control Frame

ETHERNET FRAME

PREAMBLE SFD 01 80 C2 00 00 01 SOURCE ADDRESS 88 08 00 01 PAUSE TIME (2) PAD (42) CRC-32

(7)

(1)

(6)

(2)

(46)

(4)

62 of 102

CSR Register: VLAN1 Tag

Bit Names:

—

VLAN1 [15:8]

VLAN1 [7:0]

Reset State:

VLAN1 [15:0], VLAN1 Tag Identifier [15:0]. These 16 bits contain the VLAN1 tag that is compared against the

13th and 14th bytes of the incoming frame to determ ine whether it is a VLAN1 frame. If a non-zero match occurs,

the max frame length is extended from 1518 Bytes to 1522 Bytes.

CSR Register: VLAN2 Tag

Bit Names:

—

VLAN2 [15:8]

VLAN2 [7:0]

Reset State:

VLA N2 [15:0], VLAN2 Tag Identifier [15:0]. These 16 bits contain the VLAN2 tag that is compared against the

13th and 14th bytes of the incoming frame to determine whether it is a VLAN2 frame. If a non-zero match occurs,

the max frame length is extended from 1518 Bytes to 1538 Bytes.

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CSR Register: Wake-Up Frame Filter

Bit Names:

WUFD [31:24]

WUFD [23:16]

WUFD [15:8]

WUFD [7:0]

Reset State:

WUFD [31:0], Wake-Up Frame Filter Data [31:0]. These 32 bits are used to access the four available network

wake-up frame filters. Eight accesses to the wake-up frame filter register are needed to read or write all four wake-

up frame filters.

CSR Register: Wake-Up Events Control and Status

Bit Names:

—

WUFF

MPF

—

WUFE

MPE

—

Reset State:

*Power-on reset only. Unaff ect ed by other reset sources.

GU, Global Unicast

0 = frames must pass the destination address filter as well as the wake-up frame filter criteria in order to generate a

wake-up event (default)

1 = frames must pass only the wake-up frame filter criteria to generate a wake-up eve nt

WUFF, Wake-U p Frame R eceived Flag. T his bit is s et to log ic 1 to indic ate when a wak e-up event was gene rated

due to the reception of a network wake-up frame. Application software must clear this flag by writing a 1 to this bit.

MPF, Magic Packet Recei ved Flag. T his bit is s et to logic 1 to indicat e when a wak e-up even t was ge nerate d due

to the reception of a Magic Packet. Application software must clear this flag by writing a 1 to this bit.

WUFE, Wake-Up F r ame E nab le. S ett ing this b it t o l og ic 1 in vokes sleep mode an d al lo ws th e r eception of ne twork

wake-up frame to generate a wake-up event.

MPE, Magic Packet Enable. Setting this bit to logic 1 invokes sleep mode and allows the reception of a Magic

Packet to generate a wake-up event.

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Media Independent Interface (MII)

The DS80C41 0 conta ins a n IEEE 802.3 MII -com pliant PH Y interf ace. T his interf ace contains t wo basic bloc ks. T he

MII I/O block provides independent transmit and receive data-path I/O and PHY network-status signal inputs. The

MII management block implements a 2-wire serial communication bus to facilitat e PHY register access. The block

diagram in Figure 5 shows the signals associated with the DS80C410 MII.

Figure 5. MII Block Diagram

MII Management Block

The MII m anagement block allows the host to write control d ata to and read s tatus from an y of 32 reg isters in an y

of 32 PHY controllers. The MII management block communicates with external PHY(s) over a 2-wire serial

interfac e compos ed of the MD C serial-c lock output pin and the MDIO pin t hat serves as the I/O l ine for all a ddress

and dat a trans actio ns. Dat a (MDIO) is v alid on the risi ng edge of c lock (MDC) . The M II a ddress (14h) and MII data

(18h) CSR registers, outlined previously in the CSR Register section, are used by the CPU to monitor and control

the 2-wire MII serial bus. A write to the CSR register MII address triggers the read or write operation. Figure 6

shows the MII management frame format.

Figure 6. MII Management Fram e Format

PREAMBLE

(32 bits) START

(2 bits) OP CODE

(2 bits) PHY ADDRESS

(5 bits)

PHY

(5 bits)

TURN

AROUND

(2 bits)

DATA

(16 bits) IDLE

(1 bit)

READ 111…111 01 10 PHYA [4:0] PHYR[4:0] ZZ* ZZ….ZZ* Z

WRITE 111…111 01 01 PHYA [4:0] PHYR[4:0] 10 PHYD[15:0] Z

*During a read operation, the external PHY driv es the MDIO line low for the second bit of the turnaround field to indicate proper synchronization,

and then drives the 16-bits of read data requested.

MDC

MII

MANAGEMENT

BLOCK

(SERIAL INTERFACE

BUS TO PHY)

MDIO

MII I/O BLOCK

(TRANSMIT,

RECEIVE, AND FLO W

CONTROL)

EXTERNAL

PHY

DEVICE

TX_EN

TXD[3:0]

RXCLK

RX_DV

RX_ER

RXD[3:0]

CRS

COL

TXCLK

DS80C410

65 of 102

MII I/O Block

The MII I/O block supports all of the tra nsmit and receive data transactions between the DS80C410 MAC and the

external PHY device as well as monitoring network status signals provided by the PHY.

The transmit interface is composed of TXCLK, TX_EN, and TXD[3:0]. The TXCLK input is the transmit clock

provided b y the PHY. For 10Mbps operation, the tr ansmit clock (TXCLK) should be run at 2.5 MHz. For 100Mbps,

TXCLK should be run at 25MHz. The TXD[3:0] outputs provide the 4-bit (nibble) data bus for transmitting frame

data to th e external PHY. Each tr ansm ission begins when t he TX_EN o utput is driven act ive high, in dicating t o the

PHY that valid data is present on the TXD[3:0] bus.

The receive interface is composed of RXCLK, RX_DV, RX_ER, and RXD[3:0]. The RXCLK input is the receive

clock provided by the external PHY. This clock (RXCLK) should be run at 2.5MHz for 10Mbps operation and at

25MHz for 100Mbps operation. The RXD[3:0] inputs serve as the 4-bit (nibble) data bus for receiving frame data

from the external PHY. The reception begins when the external PHY drives the RX_DV input high, signaling that

valid data is present on the RXD[3:0] bus. During reception of a frame (RX_DV = 1), the RX_ER input indicates

whether the external PHY has detected an error in the current frame. The RX_ER input is ignored when not

receiving a frame (RX_DV = 0).

The MII also monitors two net work status signals that are provided by the external PHY. The CRS (carrier sense)

input is used to ass ess wh en the ph ysical media is idle. T he COL (c ollision detect) inp ut is requ ired for ha lf-duplex

operation to signal when a collision has occurred on the physical media.

Ethernet Fram es

The basic purpose of the MII I/O block is to deliver and receive Ethernet frames to and from an external PHY,

which controls the physical carrier. The format of the IEEE 802.3 Ethernet frame is shown in Figure 7.

The preamble (7 Bytes) and start-of-frame delimiter (1 Byte) precede the Ethernet frame as a means of

synchronizing to the start of the frame. The first two fields of the Ethernet frame are the destination address and the

source address, each made up of 6 octets (bytes). The destination address field is the field examined by the

address check block to determine whether the applied address filter criteria is m et or not. The two bytes following

the source addr ess contain the Length or T ype of fram e. For Ethernet II (DIX) f rames, these two b ytes con tain the

Type field and the protocol for that specific frame type is embedded in the Data field. For fram es where Length is

specif ied in these two byte s, a header wou ld typica lly follo w in the D at a f ield to conve y t ype/ pr otocol infor m atio n f or

the fram e (i.e., 802.2 or S NAP). Since the m aximum Data fie ld length for an Et hernet fram e is 1500 Bytes, and a ll

assigned frame types are greater than this value (1500d = 05DCh), one can easily distinguish whether the field

holds Type or Length, allowing both kinds of frames to co-exist on the network. A special case occurs when the

VLAN tag prot ocol ID (= 8100h) is encoun tered where the Len gth or Type is normall y expecte d. The fram e is then

considered to be VLAN tagged. The VLAN frame format is described later.

Figure 7. IEEE 802.3 Ethernet Frame

ETHERNET FRAME

PREAMBLE SFD DESTINATION ADDRESS SOURCE ADDRESS TYPE/LENGTH DATA CRC-32

(7)

(1)

(6)

(2)

(46-1500)

(4)

66 of 102

Address Check Block

The address check block of the Ethernet controller monitors the destination address of all incoming packets and

determines whether the address passes or fails the filter criteria conf igured b y CPU. T he outcome of this address

filter test, along with b its si gnaling wheth er the f ram e is a broadc ast or m ultic ast f ram e, is repor ted b y the BCU in a

packet’s receive status word.

All incoming frames can be classified as one of three types: unicast, multicast, or broadcast (a special type of

multicast). A unicast frame contains a 0 in the first received bit of the destination address and is intended for a

singl e node on t he net work. A m ulticast f rame contain s a 1 in the f irst rec eived bi t of the des tinati on addr ess and is

intended for multiple devices on the network. A broadcast frame is a multicast frame containing all 1’s in the

destination address field and is intended for all network devices. Unless specifically disabled through the disable

broadcast frame (DBF) bit in the CSR MAC control register (00h), broadcast frames are always received by the

DS80C410 MAC.

The addres s filter cr iteria are estab lished usin g five bits found in the CSR MAC c ontrol register ( 00h). Thr ee basic

filter possibilities exist: perfect, inverse, and hash. Perfect filtering requires that the destination address perfectly

match the MAC physical address that has been assigned in CSR registers MAC address high (04h) and MAC

address lo w (08h). Inverse filtering req uires that t he de stination ad dress be a nything ot her than t he assigne d MAC

physical address. Perfect and inverse filtering is only applied to unicast fram es. Hash filtering uses a user-defined

hash table contained in CSR registers multicast address high (0Ch) and multicast address low (10h) to detect a

succes sful ad dress m atch. Figure 8 sho ws the f ive bits c ontro lling th e des tinati on address f ilter . Table 14 gives the

valid bit com binations and r esulta nt filter m odes. Note that som e of the addres s filter m ode control bits c an instruct

the address check block to automatically pass or fail certain types of frames.

Figure 8. Address Filter Mode Control Bits

CSR Register MAC Control (00h)

31 0

HP (MAC Control.13) Hash/Perfect Filtering Mode

HO (MAC Control.15) Hash-Only Filtering Mode

IF (MAC Control.17) Inverse Filtering

PR (MAC Control.18) Promiscuous Mode

PM (MAC Control.19) Pass All Multicast

Table 14. Address Filter Modes

FILTER MODE CONT ROL BITS

DESTINATION ADDRESS FILTER CRITERIA

UNICAST

MULTICAST

PERFECT

FAIL

INVERSE

FAIL

PERFECT

HASH

PERFECT

PASS

HASH

PASS

x 1 0 x x PASS (reset default state = 01000b)

67 of 102

Multicast Hash Filter

Hash filtering of destination addresses requires that a hash table be established. The hash table must be

programmed into the CSR multicast address low and multicast address high registers. When hash filtering has

been selected, the 6 bytes of the destination address are passed through the internal CRC-32 logic. The most

significant 6 bits of the resultant CRC-32 are used to index into the hash table. From those 6 bits, the most

significan t bit d eterm ines wheth er m ulticast addres s high or lo w is use d, wh ile the lower 5 bits prov ide the bit index

into the selected CSR register. If the multicast address high or low register bit indexed by the upper 6 bits of the

CRC-32 is programmed to 1, then the destination address passes. Figure 9 shows the hash filtering process.

Figure 9. Hash Table Index Generation

VLAN Support

The DS80C410 offers VLAN support through recognition of frames that are tagged as such. Each VLAN tag

provides ta g c ontr o l infor m atio n ( T CI) c ontaining a tag prot ocol ID ( TPID) and VLAN I D. The incom ing TPID occupy

the 13th a nd 14th byte pos i tions, those th at wou ld norm all y contai n e ith er th e len gth or type field for the f rame. The

TPID is compared against the VLAN1 (20h) and VLAN2 (24h) CSR registers.

If a non-zero match occurs between the TPID and VLAN1 register setting, the frame is recognized as having a

VLAN1 tag. For VLAN1 tagged frames, the TPID is followed by 2 Bytes containing the VLAN ID; therefore, the

MAC extends the maximum legal frame length by a total of 4 Bytes (TPID = 2 Bytes, VLAN ID = 2 Bytes).

If a non-zero match occurs between the TPID and VLAN2 register setting, the frame is recognized as having a

VLAN2 tag. For VLAN2 tagged frames, the TPID is followed by 18 Bytes containing the VLAN ID; therefore, the

MAC extends the maximum legal frame length by a total of 20 Bytes (TPID = 2 Bytes, VLAN ID = 18 Bytes).

Figure 10. VLAN Ta gged Frame

ETHERNET FRAME

CRC-32 OF DESTINATION ADDRESS BYTES

PREAMBLE SFD DESTINATION ADDRESS SOURCE ADDRESS TYPE/LENGTH DATA CRC-32

CRC-32 GENERATOR

POLYNOMIAL

. . . . . .

BIT INDEX

00000b: bit 0

00001b: bit 1

11110b: bit 30

11111b: bit 31

MULTICAST REGISTER SELECT

0: Multicast Address Low

1: Multicast Address High

TCI

ETHERNET FRAME

PREAMBLE SFD DESTINATION ADDRESS SOURCE ADDRESS TYPE/LENGTH DATA CRC-32

(7)

(1)

(6)

(2)

(46-1500)

(4)

TPID VLAN ID

(2)

(2: VLAN1)

(18: VLAN2)

68 of 102

Transmit/Receive Packet Buffer Memory (8kB)

The DS80C410 Ethernet controller uses 8kB of internal SRAM as transmit/receive packet buffer memory. This

SRAM is re ad/ wri te ac c ess i ble as data m em ory by the CPU using the MOVX i ns truc tion. The BCU also has a c c ess

to this SR AM, and autom atic ally writ es/reads pac ket buf f er memor y whenever it needs to stor e or retr ieve Et hernet

packet information. The logical MOVX address range of the 8kB SRAM is fixed at FFE000h to FFFFFFh.

When used for Ethernet packet buffer memory, the 8kB SRAM is logically configured into (32) pages of 64 words

each, where a word consists of 4 Bytes. These 32 pages can be dynamically allocated between Ethernet transmit

and receive buffer memory. The five least significant bits of the Ethernet buffer size (EBS; E5h) SFR specify how

many pages are allocated for receive buffer memory. The remaining pages of the 32 are used as transmit buffer

memory. Note that transmit and receive data packets can span multiple pages. The reset default state of the

Ethernet buffer size select bits (EBS.4–EBS.0) is 00000b, which configures all 32 pages as transmit buffer

mem ory. As an example, setting EBS.4–EBS.0 = 10 000b would result in pages 0–15 ( 16 pages) b eing conf igured

as receive buffer memory and pages 16–31 (16 pages) being configured as transmit buffer memory. A setting of

11111b leaves a single page (page 31) for transmit buffer memory and configures pages 0–30 (31 pages) as

receive buffer memory. Changing the transmit/receive buffer-size settings flush the contents of the receive buffer

and the receive FIFO. Figure 11 is an illustration of the 8kB buffer memory map and addressing scheme.

Figure 11. Transmit/Receive Data Buffer Memor y

EXAMPLE: PAGE 1, WORD 2, BYTE 3

WORD 2

WORD 63

STATUS WORD (WORD 0)

WORD 1

PAGE 31

PAGE (n - 2)

PAGE (n - 1)

PAGE n

PAGE 0

PAGE 1

RECEIVE

BUFFER

(n PAGES)

TRANSMIT

BUFFER

(32 - n PAGES)

BUFFER SIZE

SETTING

(EBS.4–EBS.0)

FIXED PAGE WORD BYTE

8kB INTERNAL SR AM

PAGE 1

11111111 111 00001 000010 11

69 of 102

Transmit/Receive Status Words

For each attempt m ade b y the MAC to recei ve or tran smit pack et data, the BCU wri tes a 32-b it transm it or rec eive

status word back to the f irs t word of the st arting page f or the pack et. T his word pr ov ides st atus inform ation n eeded

by the CPU to determine when and what action should be taken.

Transmit Status Word

Bit Names:

RETRY

—

HBF

COL_CNT [3:0]

OLTCOL

DFR

NODAT

XCOL

LTCOL

XDFR

LSCRS

NOCRS

JABTO

ABORT

RETRY, Pack et Ret r y. This bit indica tes tha t t he cur rent transmit packet has to b e r etrie d bec a us e of a c ollision on

the bus. T he ap plicati on ha s to res tart t he tra nsm iss ion of the f ram e when t his bit is set t o 1. W hen this bit is reset,

it indicates that the transmission of the current frame is completed. The success or failure to transmit a frame is

indicated by the framed aborted (ABORT) bit.

HBF, Heart-Beat Fail. This bit is only meaningful for ENDEC mode. This bit is not valid if the NODAT or XFDR bit

is set .

0 = heart-beat collision check successful

1 = heart-beat collision check failed

COL_CNT [3:0], Collision Count. These four bits indi cate the num ber of collisions that oc curred b efore the f rame

was transmitted. Collision count is valid only in half-duplex mode and it is not valid when the excessive collisions

(XCOL) bit is set.

OLTCOL, Late Collision Observed. This bit is onl y valid in half -duplex m ode and is alwa ys set if the late collision

abort (LTCOL) bit is set in the status word.

0 = no late collisions observed

1 = late collision (collision after the first time slot) observed.

DFR, Deferred. This bit is only valid in half-duplex mode.

0 = no deferral required for the frame transmission attempt

1 = MAC had to defer while waiting to transmit because the carrier was not idle

NODAT, Underrun

0 = transmit frame was not aborted due to data underrun

1 = transmit frame aborted because the MAC did not have sufficient data to complete the current frame

transmission

XCOL, Excessive Collisions. This bit is only valid in half-duplex mode.

0 = transmit frame was not aborted due to excessive collisions

1 = transmit frame aborted because of excessive collisions (16 transmit attempts unless DRTY = 1)

LTCOL, Late Collision. This bit is only valid in half-duplex mode.

0 = transmit frame was not aborted due to a late collision

1 = transmit frame aborted due to collision occurring after the collision window of 64 Bytes. This bit is not valid if the

NODAT bit is set.

XDFR, Excessive Deferral. This bit is only val id in half-duplex mode when the MAC control register bit DFR is set.

0 = transmit frame was not aborted due to excessive deferral

1 = transmit frame aborted due to deferral of over 24,288 bit times

LSCRS, Loss of Carrier. This bit is only valid in half-duplex mode.

0 = transmit frame was not aborted due to loss of carrier

1 = transmit frame aborted due to loss of carrier (CRS = 0 during the frame transmission)

70 of 102

NOCRS, No Carrier. This bit is onl y valid in half-duplex mode.

0 = transmit frame was not aborted due to lack of carrier

1 = transmit frame aborted due to lack of carrier (CRS = 0 when transmit frame initiated)

JABTO, Jabber Timeout

0 = transmit frame was not aborted due to jabber timeout

1 = transmit frame aborted due to jabber timeout (MAC transmitter has been active for twice the Ethernet max

frame length)

ABORT, Frame Aborted

0 = transmit frame was not aborted

1 = transmit frame was aborted by the MAC due to one of the following conditions: jabber timeout, no carrier, loss

of carrier, excessive deferral, late collision, retry count exceeds the attempt limit, and data underrun

Receive Status Word

Bit Names:

BCF

MCF

UCTRL

CTRL

LEN

VLAN2

VLAN1

CRC

DRIB

MII_ER

TYPE

COL

LONG

RUNT

WDOG

FLEN [13:8]

FLEN [7:0]

MF, Missed Frame

0 = receive frame was not missed

1 = receive frame missed

PF, Packet Filter

0 = current frame failed the packet filter

1 = current frame passed the packet filter

FF, Filter Fail

0 = destination address of the current receive frame passed the applied address filter

1 = destination address of the current receive frame failed the applied address filter

BCF, Broadcast Frame

0 = receive frame is not a broadcast frame

1 = receive frame is a broadcast frame (i.e., destination address is all ones)

MCF, Multicast Frame

0 = receive frame is not a multicast frame

1 = receive frame is a multicast frame (i.e., first bit of the destination address is a 1)

UCTRL, Unsupported Control Frame. This bit is only valid in full-duplex mode.

0 = receive frame is not an unsupported control frame

1 = receive frame is a control frame that is not supported (i.e., one that contains an op code field that is not

supported or one that is not equal to the 64-Byte minimum frame size)

CTRL, Control Fr ame. This bit is only valid in full-duplex mode.

0 = receive frame is not a control frame

1 = receive frame is a control frame

LEN, Length Error. The f ram e length check is per formed onl y when t ype/leng th field co ntains fram e length ( TYPE

= 0). W hen the data field c ontains m ore b ytes than spec ified in the le ngth f ield, thes e bytes ar e assum ed to be pad

bytes.

0 = receive frame passed the frame length check

1 = receive frame contained fewer bytes than specified in the length field

71 of 102

VLAN2, Two_Level VLAN Frame

0 = receive frame did not contain a VLAN tag that matched the VLAN2 register

1 = receive frame 13th and 14th bytes matched the two-level VLAN tag register (VLAN2)

VLAN1, One_Lev el VLAN Frame

0 = receive frame did not contain a VLAN tag that matched the VLAN1 register

1 = receive frame 13th and 14th bytes matched the one-level VLAN tag register (VLAN1)

CRC, CRC Error. This bit is also set to 1 if the RX_ER pin is asserted by the PHY during a reception, even if the

CRC-32 for the frame is correct.

0 = CRC-32 error was not detected for the receive frame

1 = CRC-32 error was detected for the receive frame

DRIB, Dribbling Bit. This bit is not valid if the COL or RUNT bits are set to 1. If DRIB = 1 and CRC = 0, then the

packet is valid.

0 = receive frame did not contain any dribbling bits

1 = receive frame contained dribbling bits (a noninteger multiple of 8 bits)

MII_ER, MII Error

0 = PHY did not assert the RX_ER signal during reception of the frame

1 = PHY asserted the RX_ER signal (indicating an error was detected) during the receive frame

TYPE, Frame Type. This bit is not valid for runt frames less than 14 Bytes.

0 = length specified in the length/type field (i.e., value equal or less than 1500)

1 = type specified in the length/type field (i.e., value greater than 1500)

COL, Collision Se en

0 = receive frame did not incur any collisions

1 = receive frame is damaged by a late collision (one that occurred after the first 64 bytes)

LONG, Frame Too Long. This bit only serves as a status indicator and does not cause frame truncation.

0 = receive frame did not exceed the maximum frame length check

1 = receive frame exceeded the maximum frame length (1518 Bytes, unless VLAN tagged)

RUNT, Runt Frame

0 = receive frame is not a runt frame (<64 Bytes)

1 = receive frame does not meet the minimum required frame size (64 Bytes = 1 time slot) due to a collision or

premature frame termination

WDOG, Watchdog Timeou t. The FLEN[13:0] field is not valid when this bit is set.

0 = MAC watchdog timer did not timeout during the receive frame

1 = MAC watchdog timer timed out during the receive frame. The watchdog timer is programmed to twice the

maximum frame length (3036 bit times).

FLEN [13:0], Frame Length [13:0]. This field indicates the receive frame length in bytes, including zero padding

pad (if applicable) and the CRC-32 field, unless automatic pad stripping has been enabled (ASTP = 1). When

ASTP = 1, the frame length includes only the data field.

72 of 102

Ethernet Interr upts

The DS80 C41 0 Ethernet c ontr ol ler s u pports t wo int err upt s o urc es : Et hernet power-mode interr upt and the Et hernet

activity interrupt. Each interrupt source has its own enable, priority, and flag bits. The locations of these bits are

documented in the interrupt vector table later in the data sheet (Table 26). Both interrupt sources are globally

enabled or disabled by the EA bit in the IE SFR and both require that the interrupt flags be manually cleared by

applicat ion sof tware. The E ther net po wer -mode interr u pt s ourc e, if enab le d, c an b e gen er ate d on th e r eception of a

Magic Packet or network wake-up frame while the Ethernet controller is in sleep mode. The Ethernet activity

interrupt can be triggered when the BCU reports the status of either a transmit or receive packet.

Power Management Block

The DS80C410 Ethernet controller contains a power management block that allows it to be put into a sleep mode

by the CPU, thus conserving power when not actively handling Ethernet traffic.

Sleep mode can be invoked in two different ways. The CPU can issue the ‘Enable Sleep Mode’ command to the

BCU by simply writing the BCUC SFR = 1100b. Alternatively, the Ethernet controller is put into sleep mode when

one or both of the possible wake-up frame sources are enabled. The enable bits for these two wake-up sources,

network wake-up fr am e an d Ma gic Packet f ram e, are l oc ated in th e C SR w ake-up frame control and s tatus re gis ter

(2Ch). If the network wak e-up frame is inten ded as a wake-up s ource, the CSR wak e-up fram e filter registe r (28h)

should be programmed accordingly prior to invoking sleep mode.

If sleep m ode is invok ed using the ‘E nable Slee p Mode’ c omm and, the Ether net cont roller c an be awak ened b y the

‘Disable Sleep Mode’ command or by either of the two special wake-up frames. If sleep mode is invoked by

enabling one or both wake-up frame sources, only the enabled wake-up frame(s) can remove the condition. To

resume normal Ethernet operation, all enable bits and flag bits (including EPMF of the BCUC SFR) should be

cleared an d if the ‘Enable Sleep Mode’ comm and was used to invoke sleep m ode, then the ‘Disable Sleep Mod e’

command must be issued.

Magic Packet and Network Wake-Up Frame

The power management block recognizes two types of frames, Magic Packet and network wake-up frame, as

capable of a wak enin g th e Ethernet con tr oller f r om sleep mode. In order f or eit her t ype of f r am e to s er ve as a wak e-

up source, it must be programmed to do so.

A Magic Packet is an err or -fr ee fram e t hat pass es the curr ent des tinat ion ad dr es s f ilter and that, anywhere af ter the

source address, contains a data sequence of FFFF_FFFF_FFFFh immediately followed by 16 iterations of the

MAC physical address. When a Magic Packet is detected by the power management block, the Magic Packet-

received bit (bit 5 of CSR wak e-up events c ontro l and status r egis ter) is s et, and an i nterrup t req uest t o the CPU is

generated if enabled (EPMI = 1).

A network wak e-up f ram e is one that pass es an y of th e f our user -defin ed fr am e filters th at hav e been progr am med

into the CSR wake-up f rame filter reg ister (28h) an d passes the dest ination addr ess filter (if GU = 0). Each filter is

composed of a command, an offset, a byte mask, and a CRC. The command nibble contains a bit (MSB of

comm and) to s elect whet her un icast ( = 0) or m ulticas t ( = 1) f ram es are to be c heck ed and a b it (LS B of c omm and)

used to dis able (= 0) or en able (= 1) t hat indi vidua l fram e filter. The off set def ines the loca tion of the f irst b yte to be

checked in each potential wake-up frame. Since the destination address is checked by the address check block,

the offset should always be greater than 12. The byte mask is used to define which of the 31 bytes, beginning at

the off set, are to be use d for the CRC c alculati on. Bit 31 of the byte m ask is alwa ys 0, but for eac h bit j of the byte

mask that is set to a logic 1, b yte (off set + j) is inc luded in t he CRC-16 calculat ion. T he CRC cont ains the CRC-16

of the pattern b ytes need ed to c ause a wake-up eve nt. W hen a network wak e-up fram e is recogni zed, the wak e-up

fram e received bit (bit 6 of CSR wake-up even ts control and status register) bec omes set and an i nterrupt request

to the CPU is generated if enabled (EPMI = 1). The wake-up frame-filter register structure is shown in Figure 12.

73 of 102

Figure 12. Wake-Up Frame-Filter Structure

31 0

FILTER 0 BYTE MASK

FILTER 1 BYTE MASK

FILTER 2 BYTE MASK

FILTER 3 BYTE MASK

RESERVED

FILTER 3

COMMAND

RESERVED

FILTER 2

COMMAND

RESERVED

FILTER 1

COMMAND

RESERVED

FILTER 0

COMMAND

FILTER 3 OFFSET

FILTER 2 OFFSET

FILTER 1 OFFSET

FILTER 0 OFFSET

FILTER 1 CRC-16

FILTER 0 CRC-16

FILTER 3 CRC-16

FILTER 2 CRC-16

Embedded ROM F irmware

The DS80C410 incorporates an embedded ROM specifically designed for hosting the MxTNI™ runtime

environm ent an d the MxTNI C librar ies. The RO M firm ware im plem ents three m ajor components : a ful l TCP/I Pv4/6

stack with industry-standar d Berkele y socket interfac e, a pr eemptive tas k s c hedul er, and NetBoot f unc t ion al it y. T he

NetBoot component uses the TCP/IP stack, socket layer, and task scheduler to provide automatic network boot

capability. NetBoot allows an application to be downloaded from the network and executed by the microcontroller.

To use the ROM firmware, the system is required to have the following hardware components:

• 64kB SRAM memory, internal on the DS80C410 and DS80C411, mapped (Note 1) at address locations

000000h–00FFFFh

• Memory (SRAM or flash) to store user-application code

• DS2502P-E48 1-Wire chip, to hold physical MAC address (Note 2)

• External crystal or oscillator (Note 3)

Note 1:

Merged program/data memory configurat i on is requi red.

Note 2:

Java applicati ons and NetBoot require a DS2502P-E48. Applications written in C can program the MAC address directly and do not

require the use of the DS2502P-E48.

Note 3:

NetBoot functi onal ity requires external c l ock frequency to be at least 7MHz. Clock doubler is not turned on until aft er NetBo ot. Thus,

100Mbps NetBoot is not possibl e unless the external clock sourc e is at least 25MHz. When not in NetBoot, the system clock

(external clock s ource after i nternal m ulti pl ication or division) must be a minim um of 25MHz for use of the Ethernet 100Mbps mode.

Selecting DS80C410 ROM Code Execution

The DS80C410, following each reset, begins execution of program code at address location 000000h. Since the

DS80C410 contains internal ROM and supports external program code, the user must select which of these two

program memory spaces should be accessed for initial program fetching. There are two mechanisms that control

selection of the internal DS80C410 ROM code. These two controls are the EA pin and the bypass ROM (BROM)

SFR bit. N o m atter the s tate of the BRO M bit, if the EA pin is held at a log ic low l evel, t he DS8 0C410 RO M c ode is

not entered and is not accessible to the user code. If the EA pin is at a logic high level, the BROM bit is then

examined to determine whether the internal DS80C410 ROM should be executed or bypassed. If BROM = 0, the

ROM code is executed. Otherwise (BROM = 1), the ROM code is bypassed and execution is transferred to external

user code at address 000000h. The BROM bit defaults to 0 on a power-on reset, but is unaffected by other reset

sources. This code selection process can be seen in Figure 13.

DS80C410 ROM Code Execution Flow

Once the internal DS80C4 10 ROM code has been selected (EA = 1, BROM = 0), it must first execute some basic

configurat ion code to provide functionality to subsequent ROM operations. Next, the ROM code reads the state of

port pin P1.7. The ROM associates the logic state of P1.7 with the user desire to invoke the serial loader function. If

the serial loader pin (P1.7) is a logic 1, the ROM monitors for activity on serial port 0 and tries to respond to the

external host with its own serial banner. Once serial communication has been established at a supported baud

rate, sign ified by correc t rec eptio n of the D S80C 4 10 l o ader ba nner a nd pr ompt, the us er c an iss ue comm ands. T he

serial load er com mands are desc ribed later in the d ata s heet. If the s erial loa der pin is pulled to a logic 0, the RO M

reads the state of port p in P5.3. Much l ike the associ ation made bet ween P1.7 and invocation of the serial loader ,

the ROM link s the logic s tate of P5.3 with the user des ir e to begin the N etBoot pr oc ess. If the N etBoot pi n (P5.3) is

asserted (logic 0), the ROM initiates the NetBoot process. If the NetBoot pin is not asserted (logic 1), the ROM

executes the find-user-code routine to identify executable user code. Figure 13 illustrates the ROM decisions

described above.

MxT NI is a trademark of Maxim Integrated Products, Inc.

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Figure 13. ROM Code Boot Sequence

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DS80C410 ROM Initialization Code

The DS80C410 firmware automatically executes Initialization Code (ROM_Init) to generate the memory map as

shown in Figure 14 and configure the hardware as follows:

Enables 24-bit contiguous address mode (ACON.1:0 = 11b)

Logically relocates ROM to addresses FF0000h–FF7FFFh (ACON.5 =1)

Enables CE0–3, 2MB/c h ip enab le (P4CNT = 2Fh)

Enables PCE0–3 (P5CNT = 07h)

Enables CE4–7, 1M/per i ph eral ch ip ena ble (P6CNT = 27h)

Merged program/data CE0–3, relocate internal XRAM (MCON = AFh)

Enables extended 1kB stack option (ACON.2 = 1)

Configure to maximum MOVX stretch value (CKCON.2:0 = 111b)

Configure UARTs for Mode 1 serial operation

Figure 14. Memory Map Following Execution of ROM_Init on DS80C410/DS80C411

00FFFFh

800000h -

A00000h -

C00000h -

E00000h -

FFFFFFh -

600000h -

400000h -

200000h -

000000h -

INTERNAL MEMORY

program data

EXTERNAL MEMORY

merged program/data space

CE7

CE6

CE5

CE4

CE3

CE2

CE1

CE0

DATA INACCESSIBLE

PROGRAM

INACCESSIBLE

ROM

CAN/B CU XRAM

FF0000h

FFDB00h

64kB Internal SRAM

76 of 102

Serial Loade r

The serial loader function implemented by the firmware can be invoked by leaving the serial loader pin (P1.7) at

logic 1 during the boot sequence. When this condition is found, the ROM monitors the RXD0 pin for reception of

the <CR> char acter (0Dh) at a s upport ed baud rat e. The s erial loa der func tion us es hard ware seria l port 0 in mode

1 (asynchronous, one start bit, eight data bits, no parity, and one stop bit in full duplex). The serial loader can

automatically detect certain baud rates and configure itself to that speed. The equation below is used to calculate

the nearest integer-reload value for Timer 2 (used for serial port 0 baud rate generation) based on the external

clock frequency and desired baud rate. The calculated (nearest integer) RCAP2H, RCAP2L reload value may not

result in an ex ac t b aud r ate match. The calculat ed reload va lue and cloc k frequen cy can be us ed in th e e qua tion t o

solve f or the bau d r ate c o nf igura bl e b y the DS80C41 0. It is ad vised that the baud rat e mism atc h be no gr eat e r than

±2.5% to maintain reliable communication. The functionality was designed to work for clock rates from 3.680MHz to

75.000MHz and baud rates from 2400 to 115,200.

RCAP2H, RCAP2L = 65,536 -

Rate Baud x 32 Frequency Clock Oscillator

For example, suppose an 18MHz crystal is being used and a 19,200 baud rate is desired. The above equation

yields a nearest integer reload value of FFE3h. This reload value results in a true baud rate of 19396.6 (+1% error).

Once a supported baud rate has been detected, the DS80C410 transmits an ASCII text banner containing

loader commands. A summary of the supported serial loader commands can be seen in Table 15. A detailed

description of each command and further information pertaining to the serial loader can be found in the High-Speed

Microcontroller User’s Guide: Network Microcontroller Supplement.

Table 15. Serial Loader Command Summary

COMMAND FUNCTION

Bank select

CRC-16 of memory range

Dump Intel hex data from selected ban k

Exit the loader and try to execute code

Fill selected bank memory with hex data

Go: Start executing code at offset 0 in the current bank

H, ?

Help: Display ROM version and current bank

Load Intel hex into memory

NetBoot

Verify memory against incoming hex

Enable clock doubler

Enable/Disable load of internal 64kByte RAM

Execute code at a given offset in the current bank

Zap: Erase/clear the current bank.

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NetBoot

The NetBoot process affords the user flexibility to download or update code remotely over the network. This

capability is quite powerful. Not only does it make firmware revisions trivial, but it also makes remote diagnostics

very practical. Also, since NetBoot can automatically reload the latest version of the user application code, the

system designer now has the option to select volatile SRAM for code storage.

For the NetBoot function to work, the DS80C410 ROM firmware must initialize certain hardware components and

create the environment needed to support the process. The NetBoot initialization code implements a primitive

mem ory manager, kicks off the task scheduler, and initializes the 1-W ire hardware, Ethernet driver, TCP/IP stack,

and socket layer.

Once the NetBoot initialization code has completed, the true network boot process can begin. The DS80C410

Ethernet MAC first must be assigned a physical address. Within the NetBoot process, the physical MAC address

can onl y be acquire d through an exter nal DS2502-(E48) 1-W ire chip. Hence, this 1-W ire chip, containing t he MAC

address, is required for successful NetBoot operation. Figure 15 shows the NetBoot code flow chart.

Figure 15. NetBoot Code Flow Chart

Next, the D S80 C41 0 RO M s earc hes the 1-Wire bus for an exter na l de vice (s ep ar ate f rom the device c onta in i ng the

MAC address) that contains an IP address and TFTP server IP address. In order to correctly acquire the IP and

TFTP server addresses from an external 1-W ire device, the data read from the device must conform to a specific

format. This format is shown in Figure 16.

Figure 16. 1-Wire IP and TFTP Server IP Address Format

IPv4 or IPv6

IPv4

‘TINI’

1Dh 54h,49h,4Eh,49h Address(4) Gateway(4) PrefixLength(1) TFTP Server Address(16) Checksum(2)

1’S COMPLEMENT

OF CRC-16 (LSB

FIRST)

29 (LENGTH)

IPV4

(BYTE

CONVERTED T O

SUBNET MASK)

NETBOOT

INITIALIZATION CODE

ACQUIRE MAC

ADDRESS F RO M DS2502

1-WIRE DEVICE

WITH IP

ADDRESS

FIND USER CODE

TFTP/FLASH WRITE

DHCP

GET IP ADDRESS FROM

1-WIRE DEVICE

NetBo ot PROCESS

78 of 102

If the IP and T FT P server addres ses c annot be acquir ed f rom a 1-W ire device, the NetB oot proc ess us es DHCP t o

get this information. The DS80C410 broadcasts its MAC address in a DHCP discover packet. A DHCP server, if

availab le, should then resp ond wit h an IP a ddress of fering. T he DS80C410 subseque ntly r equests the IP addr ess,

to which the DHCP server must acknowledge. In the DHCP acknowledge packet, the TFTP server IP address is

then read from the “next server IP” field. Because some DHCP servers do not allow configuration of the “next

server IP” f ield, the DS80C 410 recognizes th e site-specif ic option 150 (also us ed on Cisco IP ph ones to get T FTP

server IP addres s es) . When opt ion 150 is pres e nt i n t he ac knowledge pac ket, it wil l take precede nc e o ver t he “ nex t

server IP” field.

Now armed with an IP address and TFTP server IP address, the DS80C410 tries to find code to be loaded into

external pr ogram m emory. T he DS80C410 RO M firs t requests to r ead the f ile from the TFT P server c oincidi ng with

a “!” prepended t o its uniqu e ph ysical MAC addres s (e .g., ! 006035 AB9811) . If the reques t is s ucces sf ul, NetBoot is

immediately terminated. If the request is denied, it issues a second request for its unique MAC address (e.g.

006035AB9811). If this request is unsuccessful, it issues a third, less specific, request to read the filename

associated with t he ROM r evision (e. g. TIN I400-1.2.0). If this request is den ied, then lastly it attem pts to rea d from

the TFTP server the file ‘TINI400.’ Using this strateg y, the T FTP server operator can distinguish bet ween different

devices and/or different releases of the Maxim Network ed Microcontroller ROM firm ware (DS80C400, DS80C410,

and DS80C411).

After successfully locating the desired file on the TFTP server, the DS80C410 must transfer and program the file

into memory. Currently, the DS80C410 only offers programming support for internal/external SRAM and AMD

compatible flash memory devices. The NetBoot code expects the transferred file to be in the Maxim tbin2 format.

The tbin2 format consists of one or more records, allowing binary concatenation of multiple images into one file.

Figure 17 illustrates the tbin2 file format.

For each 64k B bank to be program m ed, the DS80C410 RO M first per forms a CRC -16 of the curr ent memory bank

contents. If the CRC-16 of the current memory matches the data to be programmed, the bank is left alone. If the

CRC-16 differs, it performs a couple of write/read-back operations to assess whether the bank is flash or SRAM

and then executes the erasure (if flash) and programming.

After completion of the TFTP server file transfer and programming of external memory, the NetBoot process

concludes by updating a ‘previous TFTP success’ flag and executing the ROM find-user-code routine.

If either DHC P or the T FTP transfer fail, the NetBoo t code check s whether the TFTP tr ansfer has been succ essful

in a previous attempt (note that this feature requires cooperation by the user application). If so, the DS80C410

ROM exits NetBoot and transfers execution to the find-user-code routine. If the TFTP transfer has not been

successful in the past, the DS80C410 ROM allows the watchdog timer to reset the DS80C410.

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Figure 17. Maxim tbin2 Record and File Format

Find-User Code

The DS80C410 ROM firmware attempts to find valid user code by searching for specific signature bytes. First, the

address C000h in the internal RAM is checked. If unsuccessful, the ROM starts a search at the beginning of each

64kB block of memory. The search begins at address location C00000h and continues downward through memory

in decrements of 64kB until executable code is located or failure occurs (search terminates at 000000h). For the

find-user-code routine to judge a block of memory as valid executable code, it must be tagged with the signature

bytes shown in Figure 18.

Figure 18. User Code Signature (Required by Find-User Code)

Once a valid signature is found , the signature byte at offset 6, referred to in Figure 18 as the segment address, is

exam ined to determine wh ether executio n control sho uld be transferr ed immediat ely or whether the s earch should

continue. If the segment ad dress byte equals 00h or matc hes the most signif icant address b yte for the 6 4kB block

being examined, execution is transferred to the user code. If the segment address byte does not match, that

segment address byte is used to determine the next memory block examined for a valid signature.

Exported ROM Functions

The DS80C410 ROM firmware implem ents many functions that are made accessible to the user application code.

In order for user application code to call a specific function, the location of that function must be known. The

absolute address location of each DS80C410 ROM function must be read from an export table (also found in the

ROM). To allow flexibility for future ROM firmware structural changes and improvements, the export table itself is

not connected to a specific address range, but instead a 3-Byte pointer to the start of the export table is fixed at

addresses FF0002h (XSB), FF0003h (MSB), and FF0004h (LSB). The first three bytes of the export t able contain

the quantity of function entries in the export table. In 3-Byte increments, following the first three bytes, the rest of

the table cont ains absolut e addres s locations f or the exported R OM functions . Thus, onc e the export table l ocation

has been discovered, the index for a given function/structure (Table 16) can be used to find its absolute address

(Function address = ExportTable[Index x 3]). Figure 19 illustrates the method for locating the export table and a

specif ic ROM func tion. Table 16 sho ws the conte nts of the RO M export table . Brief descr iptions of the func tionalit y

VERSION TARGET ADDR ESS (3) LENGTH-1 (2) CRC-16 (2)

BINARY DATA (LENGTH)

tbin2 record

tbin2 file

FIELD FORMAT (NOTES)

Version: 01h (versions other t han 01h reserved for future use)

Target Address: LSB, MSB, XSB (target address es > FF0000h reserved)

Length-1: LSB, MSB

CRC-16: LSB, MSB

SJMP xx

‘TINI’

80h,xxh 54h,49h,4Eh,49h Segment Address(1)

USER CODE

SIGNATURE B YTE S

80 of 102

provided b y the T CP/IP stack, s ocket layer, and task manager are included after the table, while the f ull det ails for

these and other exported ROM functions are covered in the High-Speed Microcontroller User’s Guide: Network

Microcontroller Supplement.

Figure 19. Finding the Location of an Exported ROM Function

DS80C410 ROM

(LOGICALLY LOCATED FF0000h–

FFFFFFh WHEN MROM = 1)

ROM Export Table

FF0000h

ROM FUNCTION EXPO RT TABLE

ROM Exported Function [3]

FFxxxxh

Export Table

Address

FFFFFFh

Number of Functions Exported (n)

Function [index=1] Address

Function [2] Address

Function [3] Address

Function [n] Address

FFxxxxh

FFxxxxh +03h

FFxxxxh +06h

FFxxxxh +09h

FFxxxxh +(n x 3)h

81 of 102

Table 16. ROM Export Table

INDEX

FUNCTION

DESCRIPTION/GROUP

Num_Fn,0,0

Number of functions following in the table

crc16

Utility functions

mem_clear

mem_copy

mem_compare

add_dptr0

add_dptr1

sub_dptr0

sub_dptr1

getpseudorandom

rom_kernelmalloc

Memory manager

rom_kernelfree

rom_malloc

rom_malloc_dirty

rom_free

rom_deref

rom_getfreeram

socket

Socket functions

closesocket

sendto

recvfrom

connect

bind

listen

recv

send

getsockopt

setsockopt

getsockname

getpeername

cleanup

avail

join

leave

ping

getnetworkparams

setnetworkparams

getipv6params

getethernetstatus

gettftpserver

settftpserver

eth_processinterrupt

Ethernet interrupt handler

arp_generaterequest

Generates ARP request

MAC_ID

Pointer to MAC ID

dhcp_init

DHCP functions

dhcp_setup

dhcp_startup

dhcp_run

dhcp_status

dhcp_stop

rom_dhcp_notify

tftp_init

TFTP functions

tftp_first

tftp_next

TFTP_MSG

task_genesis

Task scheduler functions

task_getcurrent

task_getpriority

task_setpriority

task_fork

task_kill

82 of 102

INDEX

FUNCTION

DESCRIPTION/GROUP

task_suspend

task_sleep

task_signal

rom_task_switch_in

rom_task_switch_out

EnterCritSection

Enter/Leav e critical section

LeaveCritSection

rom_init

Initialization functions

rom_copyivt

rom_redirect_init

mm_init

km_init

ow_init

network_init

eth_init

init_sockets

tick_init

WOS_Tick

Timer interrupt handler

BLOB

Start address of the memory area ignored by NetBoot

WOS_IOPoll

Asynchronous TCP/IP maintenance functions

IP_ProcessReceiveQueues

IP_ProcessOutput

TCP_RetryTop

ETH_ProcessOutput

IGMP_GroupMaintenance

IP6_ProcessReceiveQueues

IP6_ProcessOutput

PARAMBUFFER

Pointer to parameter buffer

RAM_TOP

Address of pointer to end of RAM used by NetBoot

BOOT_MEMBEGIN

BOOT_MEMEND

OWM_First

1-Wire master funct io ns

OWM_Next

OWM_Reset

OWM_Byte

OWM_Search

OWM_ROMID

Autobaud

Serial port 0 baud rate detection

100

tftp_close

Note: Index 101 and higher only available on DS80C410 or ROM 1.2.0 and newer

101

ROM_NetBoot

Entry point to NetBoot function

102

task_switcher

Address of default task switcher

103

Tick_CalculateReload

Function that computes values required for millisecond timer

104

OWM_ProbeClock

1-Wire master funct io ns

105

OWM_CalculateDivisor

106

Info_SendString

Debug port functions

107

Info_SendTwoHex

108

Info_ConvHex

109

Info_SendCRLF

110

Locations of copyright strings

111

AllRightsReserved

112

Util_PseudoRand

Pseudo random function

113

Flash_SectorErase

AMD Flash functions

114

Mem_WriteXRAM

115

ARP_GenerateRequest

ARP support for ZeroConf

116

ARP_CheckCache

117

NetNat_Subnet_to_Prefix

Calculates subnet length

118

unbind

Socket function

119

Math_Mul1024

Math functions

120

Math_Div2

121

Math_Div1024

122

Math_LongDiv1024

123

task_suspend_nc

Task scheduler functions

83 of 102

INDEX

FUNCTION

DESCRIPTION/GROUP

123

task_sleep_nc

124

UDP_TestReceive

Socket function

125

ETH_ReadMII

Ethernet MAC functions

126

ETH_WriteMII

127

ETH_ReadCSR

128

ETH_WriteCSR

129

IP_CheckHeader

IP stack functions

130

IP_PacketReceived

84 of 102

TCP/IP Stack and Berkeley Sockets

The ROM firmware implements TCP/IP Ethernet networking over an industry-standard/Berkeley socket interface.

The stack supports TCP and UDP transport protocols, allowing a maximum of 24 client/server sockets for either

IPv4 or I Pv6. Table 17 lists the sock et functions im plem ented and ac cessible in the ROM f irm ware. The full details

of each socket function are contained in the High-Speed Microcontroller User’s Guide: Network Microcontroller

Supplement.

Figure 20 illustrates the typical sequences for using TCP/UDP client/server sockets. The IPv4 implementation

supports multicasting, ICMP echo request (“ping”), DHCP client, and TFTP client. It does not, however, allow IP

packet fragmentation or reassembly, and it ignores the extended IP options field. The IPv6 implementation

supports ICMP and the TFTP client protocols.

Table 17. Socket Functions

FUNCTION

DESCRIPTION

socket

Creates the specified TCP or UDP network socket

closesocket

Closes the specified socket

sendto

Sends a UDP datagram to the specified address

recvfrom

Receives a UDP datagram

connect

Connects a TCP socket to the specified address

bind

Binds a socket to the specified address, port

listen

Listens for connect ions on the specified soc ket

Accepts a TCP connect ion on the spec ifi ed soc ket

recv

Reads data from the specified TCP socket connection

send

Sends data to the specified TCP socket connection

getsockopt

Gets options for the specified socket

setsockopt

Sets options for the specified socket

getsockname

Gets current local address for the specifi ed socket

getpeername

Gets current remote address for the specified TCP socket

cleanup

Closes all sockets associated with the specified task ID

avail

Returns the number of bytes available for reading on the specified TCP socket

join

Adds the specified UDP socket to a specified multicast group

leave

Removes the specified UDP socket from a specified multicast group

ping

Sends ICM P echo request to the specified address

setnetworkparams

Sets the IPv4 address and configuration parameters

getnetworkparams

Gets the IPv4 address and configuration parameters

getipv6params

Gets the IPv6 address

getethernetstatus

Gets the status of the Ethernet link

gettftpserver

Gets the IP address of the TFTP server

settftpserver

Sets the IP address of the TFTP server

Figure 20. Typical TCP/UDP Sockets

UDP UDP

Unicast Multicast

TCP TCP

Server Client

socket

bind, getsockopt, setsockopt (optional)

listen (max. 16)

connect

avail, send, recv

sendto, recvf rom

closesocket

join

leave

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Task Schedu l er

The DS80C410 ROM firmware implements a priority based preemptive task scheduler. Each task created is

represente d in a task ring by a correspond ing task control block (TCB). The T CB holds critica l inform ation spec ific

to the t ask, such as the ID, prior ity, event bit mask , wake-up time, and pointers t o state inf ormation and n ext task.

Using a timer, the scheduler is run approximately every 4ms (at 18.432MHz crystal frequency) unless deferred

because an other interr upt i s in pr ogr ess . The scheduler s upp ort s an unlimited nu mber of tasks and al lo ws a ddit ion,

deletion, or modificatio n on the f ly. Ho wever, one sho uld realize that increas ing t he number of tasks increas es the

time needed by the scheduler to search and prioritize the ring. The High-Speed Microcontroller User’s Guide:

Network Microcontroller Supplement provides greater detail about the task scheduler and its functionality.

Controller Area Network (CAN) Module

The DS80C410 incorporates one CAN controller that is fully compliant with the CAN 2.0B specification. On the

DS80C411, the CAN controller is not available. CAN is a highly robust, high-performance communication protocol

for serial communications. Popular in a wide range of applications including medical, heating, ventilation, and

industrial control, the CAN architecture allows for the construction of sophisticated networks with a minimum of

external hardware.

The CAN controller supports the use of 11-bit standard or 29-bit extended acceptance identifiers for up to 15

messages, with the standard 8-Byte data field, in each message. Fourteen of the 15 message centers are

programmable in either transmit or receive modes, with the 15th designated as an FIFO-buffered, receive-only

message center to help prevent data overruns. All message centers have two separate 8-bit media masks and

media arbitration fields for incoming message verification. This feature supports the use of higher-level protocols

that use t he first a nd/ or s econd b yte of data as a p art o f the ac ceptance la yer f or storing i ncoming messages . Eac h

mess age center can also be program m ed independent ly to test incom ing data w ith or without th e use of the global

masks.

Global contr ols an d status r egisters i n the CAN un it allo w the m icrocontr oller to eva luate err or m ess ages, generate

interrupts , locate and val idate new data, establis h the CAN bus tim ing, establ ish identif ication m ask bits, and verif y

the source of individual messages. Each message center is individually equipped with the necessary status and

control bits to establish d irection, i dentificat ion mode ( standard or extended), da ta f ield size, data s tatus, auto matic

remote frame request and acknowledgment, and perform masked or nonmasked identification-acceptance testing.

Communicating with the CAN Module

The m icrocontroller interf ace to the CAN modules is divided into two gr oups of register s. All the global CAN s tatus

and control bits as well as the individual m essage center control/status registers are located in the SFR map. The

remaining registers associated with the message centers (data identification, identification/arbitration masks, format

and data) are located in MOVX data space. For the DS80C410, the message centers are fixed from FFDB00h –

FFDBFFh. The internal architecture of the DS80C410 requires that the device be in one of the two 24-bit

addressin g modes when the CMA bit is s et to correctl y acc ess the CAN MO VX m emor y. A special lockout f eature

prevents the accidental software corruption of the control, status, and mask registers while a CAN operation is in

progress. Each CAN controller uses a total of 15 message centers. Each message center is composed of four

specific areas that include the following:

1) Four arbitration registers (C0MxAR0-3) that store either the 11-bit or 29-bit arbitration value. These registers

are located in the MOVX memory map.

2) A format register (C0MxF) that informs the CAN controller as to the direction (transmit or receive), the number

of data bytes in the message, the identification format (standard or extended), and the optional use of the

identification mask or media mask during message evaluation. This register is located in the MOVX memory

map.

3) Eight data bytes for storage of 0 to 8 Bytes of data (C0MxD0–7) are located in the MOVX memory map.

4) Message control registers (C0MxC) are located in the SFR memory for fast access.

Each of the message centers is identical with the exception of message center 15. Message center 15 has been

designed as a receive-only center and is also buffered through the use of a two-message FIFO to help prevent

mess age loss i n a m essage-overr un s ituat ion. T he re ceipt of a thir d m essage be f ore either of the f irst t wo a re read

overwrites the second message, leaving the first message undisturbed.

Modification of the CAN registers located in MOVX memory is protected through the SWINT bit. Consult the

description of this bit in the High-Speed Microcontroller User’s Guide: Networ k Micr ocontr ol ler Sup pl eme nt for more

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information. The CAN module contains a block of control/status/mask registers, 14 functionally identical message

centers, plus a 15th m essage center th at is receive-on ly and incor porates a buf fered FIFO. Table 18 desc ribes the

organization of the message centers located in MOVX space.

Table 18. CAN Controller MOVX Memory Map

CONTROL/ST ATUS/MASK REGISTERS

MO VX DATA

ADDRESS

C0MID0

MID07

MID06

MID05

MID04

MID03

MID02

MID01

MID00

FFDB00h

C0MA0

M0AA7

M0AA6

M0AA5

M0AA4

M0AA3

M0AA2

M0AA1

M0AA0

FFDB01h

C0MID1

MID17

MID16

MID15

MID14

MID13

MID12

MID11

MID10

FFDB02h

C0MA1

M1AA7

M1AA6

M1AA5

M1AA4

M1AA3

M1AA2

M1AA1

M1AA0

FFDB03h

C0BT0

SJW1

SJW0

BPR5

BPR4

BPR3

BPR2

BPR1

BPR0

FFDB04h

C0BT1

SMP

TSEG26

TSEG25

TSEG24

TSEG13

TSEG12

TSEG11

TSEG10

FFDB05h

C0SGM0

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

FFDB06h

C0SGM1

ID20

ID19

ID18

FFDB07h

C0EGM0

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

FFDB08h

C0EGM1

ID20

ID19

ID18

ID17

ID16

ID15

ID14

ID13

FFDB09h

C0EGM2

ID12

ID11

ID10

ID9

ID8

ID7

ID6

ID5

FFDB0Ah

C0EGM3

ID4

ID3

ID2

ID1

ID0

FFDB0Bh

C0M15M0

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

FFDB0Ch

C0M15M1

ID20

ID19

ID18

ID17

ID16

ID15

ID14

ID13

FFDB0Dh

C0M15M2

ID12

ID11

ID10

ID9

ID8

ID7

ID6

ID5

FFDB0Eh

C0M15M3

ID4

ID3

ID2

ID1

ID0

FFDB0Fh

CAN 0 MESSAGE CENTER 1

RESERVED

FFDB10h–11h

C0M1AR0

CAN 0 MESSAGE 1 ARBITRAT ION REGISTER 0

FFDB12h

C0M1AR1

CAN 0 MESSAGE 1 ARBITRAT ION REGISTER 1

FFDB13h

C0M1AR2

CAN 0 MESSAGE 1 ARBITRAT ION REGISTER 2

FFDB14h

C0M1AR3

CAN 0 MESSAGE 1 ARBITRAT ION REGISTER 3

WTOE

FFDB15h

C0M1F

DTBYC3

DTBYC2

DTBYC1

DTBYC0

T/R

EX/ST

MEME

MDME

FFDB16h

C0M1D0–7

CAN 0 MESSAGE 1 DA TA BYTES 0 to 7

FFDB17h–1Eh

RESERVED

FFDB1Fh

CAN 0 MESSAGE CENTERS 2 to 14

MESSAGE CENTER 2 REGISTERS (similar to Message Center 1)

FFDB20h–2Fh

MESSAGE CENTER 3 REGISTERS (similar to Message Center 1)

FFDB30h–3Fh

MESSAGE CENTER 4 REGISTERS (simi l ar to Message Center 1)

FFDB40h–4Fh

MESSAGE CENTER 5 REGISTERS (similar to Message Center 1)

FFDB50h–5Fh

MESSAGE CENTER 6 REGISTERS (similar to Message Center 1)

FFDB60h–6Fh

MESSAGE CENTER 7 REGISTERS (similar to Message Center 1)

FFDB70h–7Fh

MESSAGE CENTER 8 REGISTERS (similar to Message Center 1)

FFDB80h–8Fh

MESSAGE CENTER 9 REGISTERS (similar to Message Center 1)

FFDB90h–9Fh

MESSAGE CENTER 10 REGISTERS (similar to Message Center 1)

FFDBA0h–AFh

MESSAGE CENTER 11 REGISTERS (similar to Message Center 1)

FFDBB0h–BFh

MESSAGE CENTER 12 REGISTERS (similar to Message Center 1)

FFDBC0h–CFh

MESSAGE CENTER 13 REGISTERS (similar to Message Center 1)

FFDBD0h–DFh

MESSAGE CENTER 14 REGISTERS (similar to Message Center 1)

FFDBE0h–EFh

CAN 0 MESSAGE CENTER 1 5

—

Reserved

FFDBF0h–F1h

C0M15AR0

CAN 0 MESSAGE 15 ARBITRATION REGISTER 0

FFDBF2h

C0M15AR1

CAN 0 MESSAGE 15 ARBITRATION REGISTER 1

FFDBF3h

C0M15AR2

CAN 0 MESSAGE 15 ARBITRATION REGISTER 2

FFDBF4h

C0M15AR3

CAN 0 MESSAGE 15 ARBITRATION REGISTER 3

WTOE

FFDBF5h

C0M15F DTBYC3 DTBYC2 DTBYC1 DTBYC0 0 EX/ST MEME MDME FFDBF6h

C0M15D0—

C0M15D7

CAN 0 MESSAGE 15 DATA BYTE 0 to 7 FFDBF7h–FEh

Reserved

FFDBFFh

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CAN Inter rupts

The DS80 C41 0 pr o v ides o ne interru pt s ourc e f or the CAN c o ntr ol ler. The C AN i nterr upt s ourc e c an be tr i g gered by

a receive/transmit acknowledgment from one of the 15 message centers or an error condition.

Each m essage center has individua l ETI (tr ansmit) and ERI (receive) int errupt en able bits and INT RQ f lag bits that

are found in th e corr espo nding mes sage contr ol (C0 MxC) SFR. I f the ETI or ER I bits have be en set for a mes sage

center, the successful transmission or receipt of a message, respectively, sets the INTRQ bit for that message

center. The INTRQ bit can only be cleared through software. All message center interrupt flags (INTRQ) of the

CAN m odule are O Red tog ether to produce a sing le inter rupt sour ce f or the CAN cont roller. F or the micr ocontroll er

to ack nowledge an y individ ual mess age center int errupt r equest, th e global interrupt e nable bit ( IE.7) and t he CAN

0 interrupt enable bit, EIE.6, must both be set.

Interrupt assertion of error and status conditions associated with the CAN module is controlled by the ERIE and

STIE bits located in the CAN 0 control (C0C) SFR. These interrupt sources also require that the global interrupt

enable (EA = IE.7) and the CAN 0 interrupt enable (C0IE = EIE.6) bits be set in order to be acknowledged by the

microcontroller.

Arbi tration and Masking

After the CAN module has ascertained that an incoming message is bit error-free, the identification field of that

message is then com pared against one or m ore arbitration values to determine if they are loaded into a message

center. Each enabl ed mes sage center ( see the M SRDY b it in the C AN m essage cont rol regist er) is t ested in or der

from 1 to 15. T he first message center to successfully pass the test receives the incoming m essage and ends the

testing. The use of mask ing register s al lows t he us e of more c om plex identific at io n s c hem es, as tes ts c an be made

based on bit patterns rather than an exact match between all bits in the identification field and arbitration values.

The CAN controller also incorporates a set of five masks to allow messages with different IDs to be grouped and

successfully loaded into a message center; note that some of these masks are optional as per the bits shown in

Table 19.

There are several possible arbitration tests, varying according to which message center is involved. If all of the

enabled tes ts suc ceed, t he m ess age is loade d into th e r espectiv e m essage c enter. The m ost bas ic test, per form ed

on all m essages, c ompares eith er 11 (CAN 2.0 A) or 29 ( CAN 2.0B) b its of the id entificat ion field to the appropr iate

arbitration register, based on the EX/ST bit in the CAN 0 format register. The MEME bit (C0MxF.1) controls whether

the arbitration and ID registers are compared directly or through a mask register. A special set of arbitration

registers dedicated to message center 15 allows added flexibility in filtering this location.

If desired, further arbitration can be performed by comparing the first two bytes of the data field in each message

against two 8-bit media arbitration register bytes. The MDME bit in the CAN message center format registers

(C0MxF.0) either disables (MDME = 0) arbitration, or enables (MDME = 1) arbitration using the media ID mask

registers 0–1.

If the 1 1-bit or 29-bit arb itration and the optiona l media-byte arb itration are successful, th e message is loaded into

the respective message center. The format register also allows the microcontroller to program each message

center to function in a receive or transmit mode through the T/R bit and to use from 0 to 8 data bytes within the data

field of a m ess age. Note that message c enter 15 can onl y be used in a r eceive m ode. To avoid a pr iorit y inversio n,

the DS80C410 CAN controller is configured to reload the transmit buffer with the message of the highest priority

(lowest message center number) whenever an arbitration is lost or an error condition occurs.

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Table 19. Arbitration/Masking Feature Summary

TEST NAME

ARBITRATION

REGISTERS

MASK REGISTERS

CONTROL BITS

AND CONDITIONS

Standard 11-bit

Arbitration

(CAN 2.0A)

Message Center

Arbitration Registers 0–1

(Located in each message

center, MOVX memory)

Standard Global Mask

Registers 0–1 (Located in

CAN control/status/mask

memory)

EX/ST = 0

MEME = 0: Mask register ignored. ID and

arbitration register must match exactly.

MEME = 1: Only bits corresponding to 1 in

mask register are compared in ID and

arbitration registers.

Extended 29-bit

Arbitration

(CAN 2.0B)

Message Center

Arbitration Registers 0–3

(Located in each message

center, MOVX memory)

Extended Global Mask

Registers 0–3 (Located in

CAN control/status/mask

memory)

EX/ST = 1

MEME = 0: Mask register ignored. ID and

arbitration register must match exactly.

MEME = 1: Only bits corresponding to 1 in

mask register are compared in ID and

arbitration registers.

Media Byte

Arbitration

Media Arbitration Registers

0–3 (Located in CAN

control/status/mask

memory)

Media ID Mask Registers

0–1 (Located in CAN

control/status/mask

memory)

MDME = 0: Media byte arbitration disabled.

MDME = 1: Only bits corresponding to 1 in

Media ID mask register are compared

between data bytes 1 and 2 and Media

arbitration registers.

Message Center

15, Standard 11-

bit Arbitration

(CAN 2.0A)

Message Center 15

Arbitration Registers 0–1

(Located in message

center 15, MOVX memory)

Message Center 15 Mask

Registers 0–1 (Located in

CAN control/status/mask

memory)

EX/ST = 0

MEME = 0: Mask register ignored. ID and

arbitration register must match exactly.

MEME = 1: Message center 15 mask

registers are ANDed with Global Mask

resulting value are compared in ID and

arbitration registers.

Message Center

15, Extended

29-bit Arbitration

(CAN 2.0B)

Message Center 15

Arbitration Registers 0–3

(Located in message

center 15, MOVX memory)

Message Center 15 Mask

Registers 0–3 (Located in

CAN control/status/mask

memory)

EX/ST = 1

MEME = 0: Mask register ignored. ID and

arbitration register must match exactly.

MEME = 1: Message center 15 mask

registers are ANDed with Global Mask

resulting value are compared in ID and

arbitration registers.

Message Buffering/Overwrite

If a m ess age c enter is c o nf igured f or r eception (T/R = 0) and the prev io us mess age has not been rea d ( DTUP = 1),

then th e d ispos i tio n of an in c om ing message to that mess age c e nter is c ontr ol led b y the WTOE bit ( locat ed i n CAN

arbitration register 3 of each message center). When WTOE = 0, the incoming message is discarded and the

current message untouched.

If the W TOE bit is set, th e incom ing m essage is received a nd written o ver the exis ting data b ytes in t hat message

center. The receiver overwrite bit (ROW ) also is set in the corresponding message center control reg ister, located

in SFR memory.

Message ce nter 15 is un ique in that it incorporates a buffer that can receive u p to two mes sages without l oss. If a

message is received by message center 15 while it contains an unread message, the new incoming message is

held in a n internal buffer . W hen the CAN contr oller r eads the m essage c enter 15 m em ory location an d then c lears

DTUP = I NT RQ = EXT RQ = 0, the c ontents of the int er nal buf fer ar e autom atic ally loa ded in to the m es sage c enter

15 MOVX memory location.

The message center 15 WTOE bit controls what happens if a third message is received when both the message

center 15 MOVX memory location and the buffer contain unread messages. If WTOE = 0, the new message is

discarded, leaving the message center 15 MOVX memory location and the buffer untouched. If WTOE = 1, then

the third message writes over the buffered message but leaves the message center 15 MOVX memory location

untouched.

Error Counter Inter r upt Gene r ation

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The CAN module can be configured to alert the microcontroller when either 96 or 128 errors have been detected by

the transmit or receive error counters. The error-count select bit, ERCS (C0C.1), selects whether the limit is 96

(ERCS = 0) or 128 ( ERCS = 1) er rors. W hen the error lim it is exceed ed, the CAN error-count exceeded bit CECE

(C0S.6) is set. If the ERIE, C0IE, and EA SFR bits are c onfigured, an int errupt is generated . If the ERCS bit is set,

the device generates an interrupt when the CECE bit is set or cleared, if the interrupt is enabled.

Bit Timing

Bit tim ing of the CAN tr ansm ission can be adj usted pe r the CAN 2.0 B specific ation. T he CAN 0 bus tim ing regis ter

zero (C0BT 0), located in th e control/status /mask r egister block in MOVX memor y, controls t he PHASE_S EG1 and

PHASE_SEG2 time segments and the baud rate prescaler (BPR5–BPR0). The CAN 0 bus timing register one

(C0BT1) contains the controls for the sampling rate and the number of clock cycles assigned to the Phase

Segment 1 and 2 portions of the nom inal bit time. The values of both of the bus tim ing registers are autom atically

loaded into the CAN controller following each software change of the SWINT bit from a 1 to a 0 by the

microcontroller. The bit timing parameters must be set before starting operation of the CAN controller. These

registers are modifiable onl y duri ng a software initia lization, (SW INT = 1), when the CAN contro ller is not in a bus-

off mode, and after the removal of a system reset or a CAN reset. To avoid unpredictable behavior of the CAN

controller, the software cannot clear the SWINT bit when TSEG1 and TSEG2 are both cleared to 0.

1-Wire Bus Master

The DS80C410 incorporates a 1-Wire bus master to support communication to external 1-W ire devices. The bus

master provides complete control of the 1-Wire bus and coordinates transmit (Tx)/receive (Rx) activities with

minim al superv ision b y the CPU. A ll tim ing and co ntrol s equences f or the bus are generated within t he bus m aster.

Communication between the CPU and the bus master is accomplished through read/write access of the 1-Wire

master address (OWMAD; EEh) and 1-Wire master data (OWMDR; EFh) SFRs. When 1-Wire bus activity

generates a condition that requires servicing by the CPU, the bus master sets the appropriate status bit to create

an inter rupt re quest to th e C PU. If the 1-Wire bus m aster int errupt sourc e has been enabl ed, th e C PU ser vices the

request acc or d ing to t he priorit y tha t has b een as sign e d. The 1-Wire bus mast er supports b it b an gin g, s ear ch R OM

accelerator, and overdrive modes. Detailed operation of the 1-Wire bus is described in The Book of iButton

Standards (www.maxim-ic.com/iButtonBook).

Communicating with the Bus Master

The microcontroller interface to the 1-Wire bus master is through two SFRs, 1-Wire master address (OWMAD;

EEh), and 1-Wire master data (OWMDR; EFh). These two registers allow read/write access of the six internal

registers of the 1-Wire bus master. The internal registers provide a means for the CPU to configure and control

transmit/receive activity through the bus master.

The three least significant bits (A2:A0) of the OWMAD SFR specify the address of the internal register to be

accessed. The OWMDR SFR is used for read/write access to the implemented bits of the specified internal

only read access to interrupt status flags. It should also be noted that all writes to the Tx/Rx buffer register

(xxxxx001b) are directed to the Tx buffer and all reads retrieve data from the Rx buffer. The 1-Wire bus master

internal register map is shown in Table 20.

Table 20. 1-Wire Bus Master Internal Register Map

FUNCTION

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

000

Command

—

OW_IN

FOW

SRA

1WR

001

Tx/Rx Buffer

010

Interrupt Flag

OW_LOW

OW_SHORT

RSRF

RBF

TEMT

TBE

PDR

011

Interrupt Enable

EOWL

EOWSH

ERSF

ERBF

ETMT

ETBE

—

EPD

100

Clock Divisor

CLK_EN

—

DIV2

DIV1

DIV0

PRE1

PRE0

101

Control

EOWMI

BIT_CTL

STP_SPLY

STPEN

EN_FOW

PPM

LLM

*Logic states repres ented by A2:A0 other than those list ed in the table are considered t o be invalid addresses and are not support ed by the bus

master. When OWMAD contains an invalid address, reads of OWMDR return invalid data, and writes to OWMDR do not change the internal

Clock Control

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All 1-W ire timing patt erns ar e generated usi ng a base cloc k of 1.0MH z. To create this bas e clock frequency for the

1-Wire bus master, the microcontroller system clock must be internally divided down. The clock divisor internal

microcontroller system clock by 1, 3, 5, or 7 for settings of 00b, 01b, 10b, and 11b respectively. The divider bits

(DIV2:DI V0) contro l the circ uitry, whic h then di vides th e presc aler output c lock by 1, 2, 4, 8, 16, 32, 64, or 12 8. T he

CLK_EN bit (bit 7 of the clock divisor register) enables or disables the clock generation circuitry. Setting CLK_EN to

a logic 1 enables the clock generation circuitry while clearing the bit disables the clock generation circuitry. The

clock divisor register must be configured properly before any 1-Wire communication can take place. Table 21

shows the proper selections for the PRE1:PRE0 and DIV2:DIV0 register bits for a given microcontroller system

clock. Note that the clock generation circuitry requires that the microcontroller system clock be between 3.2MHz

and 75MHz, preferably with 50% duty cycle.

Table 21. Clock Divisor Register Settings

SYSTEM CLOCK

FREQUENCY (MHz)

DIVIDER

RATIO DIV2:DIV0 DIVIDE BI TS

SELECTION PRE1:PRE0

PRESCALER

BITS

SELECTION

MIN

MAX

4.0

< 5.0

010

5.0

< 6.0

000

6.0

< 7.0

001

7.0

< 8.0

000

8.0

< 10.0

011

10.0

< 12.0

001

12.0

< 14.0

010

14.0

< 16.0

001

16.0

< 20.0

100

20.0

< 24.0

010

24.0

< 28.0

011

28.0

< 32.0

010

32.0

< 40.0

101

40.0

< 48.0

011

48.0

< 56.0

100

56.0

< 64.0

011

64.0

75.0

110

Transmitting a nd Receiving Data

All data transmitted and received by the 1-Wire bus master passes through the transmit/receive data buffer

(internal register address xxxxx001b). The data buffer is double-buffered with separate transmit and receive

buffers. Writing to the data buffer connects the transmit buffer to the data bus while reading connects the receive

buffer to the data bus.

The data buf fer com bination f or the tr ansm it interf ace is c omposed of the trans m it buffer and transm it s hift register.

Each of these regis ters has a flag that can be used as an int errupt so urce. T he transm it buff er empt y (T BE) flag is

set when the transmit buffer is empty and ready to accept a new byte of data from the user. As soon as the data

byte is writte n i nto the tr ans mit buff er, TBE is cleare d. The tr ans mit shif t regis ter e mpt y (TEMT ) flag is s et when th e

shift register has no data and is ready to load a new data byte from the transmit buffer. When a byte of data is

transferred into the transmit shift register, TEMT is cleared and TBE becomes set.

To s end a b yte of data on t he 1-Wire bus, the user writes the des ired d ata to the transmit buff er. T he data is moved

to the transmit shift register, where it is shifted serially onto the 1-Wire bus, least significant bit first. When the

transm it shift r egister is empt y, new dat a is trans ferred f rom the trans mit buff er (if availab le) and th e serial process

repeats. Note that the 1-Wire protocol requires a reset before any bus communication.

The data buffer combination for the receive interface is composed of the receive buffer and the receive shift

start of data being shifted into the register, and is cleared when the receive shift register is empty. The receive

buffer full (RBF) flag is set when data is transferred from the receive shift register into the receive buffer and is

cleared after the CPU reads the register. If RBF is set, and another byte of data is received in the receive shift

register, th e receive shif t register holds th e new byte and waits until the user reads the rec eive buffer , clearing the

RBF flag. T hus , if both RS R F and RBF are s et, n o f ur ther trans miss ions s hould b e m ade on the 1-Wire bus, or else

data can be lost, as the byte in the receive shift register is overwritten by the next received data.

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To read d ata from a slave device, the bus m aster must f irst be ready to transmit dat a depending on comm ands in

the command register already set up by the CPU. Data is retrieved from the bus in a similar fashion to a write

operation. The CPU initiates a read operation by writing FFh data to the transmit buffer. The data that is then

shifted into the receive shift register is the wired-AND of the bus master write data (FFh) and the data from the

slave de vice. W hen the rec eive shif t register is full, the data is tra nsfer red to the r eceive buf fer ( if RBF = 0), w here

it can be rea d by the CPU. Additional b ytes can be read by sending FFh again. If the slave device is not ready to

respond to read request, the data received the by the bus master is identical to that which was transmitted (FFh).

Bus Master Commands

The 1-W ir e bus master can genera te speci al com m ands on the 1-Wire bus in ad dition to tr ansm itting and r ec eiving

data. These commands are generated through the setting of a corresponding bit in the command register

(xxxxx000h). These operational modes are defined in The Book of iButton Standards available on our website at

www.maxim-ic.com/iButtonBook.

1WR (Bit 0): 1-Wire Reset. Setting this bit to logic 1 causes a reset of the 1-Wire bus, which must precede any

command given on the bus. Setting this bit also automatically clears the SRA bit. The 1WR bit is automatically

cleared as soon as the 1-Wire bus reset completes. The bus master sets the presence-detect interrupt flag (PD)

when the reset is completed and sufficient time for a 1-Wire reset to occur has passed. The result of the 1-Wire

reset is placed in the interrupt register bit PDR. If a presence-detect pulse was received, PDR is cleared; otherwise,

it is set.

SRA (Bit 1): Search ROM Accelerator. Setting this bit to logic 1 places the bus master into search-ROM-

accelerat or mode in order t o expedite the sear ch ROM proc ess. The general principle of the s earch ROM proc ess

is to des e lect on e device af ter an oth er at e very confl icting R OM ID bit p os ition of the attac h ed slave de vices. Us ing

the search ROM process, the b us master can ultimately learn the ROM ID for each device attach ed to the 1-Wire

bus. To prevent the CPU from having to perform many bit manipulations during a search ROM process, the search-

ROM-accelerator mode can be invoked, allowing the CPU to send 16 bytes of data to complete a single search

ROM pass. Details about the search ROM algorithm can be found in The Book of iButton Standards or the High-

Speed Microcontroller User’s Guide: Network Microcontroller Supplement.

FOW (Bit 2): Force OW Line Low. Setting this bit to l ogic 1 f or c es the OW line to a lo w va lue if the EN_FOW bit in

the control register is also set to logic 1. The FOW bit has no affect on the OW line when the EN_FOW bit is

cleared to logic 0.

OW_IN (Bit 3): OW Line Input. This bit always reflects the current logic state of the OW line.

Bus Master Controls

The 1-Wire bus mas ter c an per f orm cer tain s pecia l f un c tions to sup port OW line oper ati on. These spec i al f un c tions

can be configured through the control register (xxxxx101h).

LLM (Bit 0): Long Line Mode. This bit is used to enable the long-line mode timing. Setting this bit to logic 1

effectively moves the ‘write one’ release and dat a-sample tim ing during standar d mode communication out to 8µs

and 22µs, res pecti vel y. The r ecover y tim e is ext end ed to 14µs. T his provid es a less stric t enviro nm ent for long line

transmissions. Clearing this bit to logic 0 leaves the ‘write one’ release, data sampling, and recovery time (during

standard mode communication) at 5µs, 15µs, and 10µs, respectively.

PPM (Bit 1): Presence Pulse Masking. This bit is used to enable/disable the presence pulse-masking function.

Setting this bit to logic 1 caus es the bus m aster to initiat e the beginn ing of a presence pu lse during a 1-Wire reset.

This enabl es the m as ter to preve nt the lar ger am ount of ringing c aused b y slave devices pu lling t he OW line lo w. If

the PPM bit is set, the PDR result bit in the interrupt flag register is always set, indicating that a slave device is

present on the OW line (even if there are none). Clearing the PPM bit to logic 0 disables the presence pulse-

masking function.

EN_FOW (Bit 2): Enable Force OW. Setting the EN_FOW bit to a logic 1 allows the bus master to force the OW

line low using FOW (bit 2 of the command register). Clearing the EN_FOW bit to a logic 0 d isables the use of the

FOW bit.

STPEN (Bit 3): Strong Pullup Enable. Setting the STPEN bit to a logic 1 enables functionality for the OWSTP

output pin. The OWSTP pin serves as the enable signal to an external strong pullup device. This functionality is

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used for meeting the recovery time requirement in overdrive mode and long-line standard communication. When

enabled ( ST PEN = 1), OWSTP goes ac ti ve-l o w an y ti me the mas ter is not pull ing the OW line low or wait ing to read

data f rom a slave during a comm unication s equence. Once the comm unication s equence is com plete, the OWSTP

output is rele ased. Note that w hen the master is in the idle state, the STP_S PLY bit must als o be set to logic 1 (in

addition to STPEN = 1) in order for the OWSTP pin to remain in the active-low state. Clearing the STPEN bit to

logic 0 disables all OWSTP pin functionality.

STP_SPLY (Bit 4): Strong Pullup Supply Mode. When the OWSTP pin is enabled (STPEN = 1), setting the

STP_SPLY bit to logic 1 results in an active-low output for the OWSTP pin being sustained when the master is in an

idle state. Thus, when the OWSTP signal gates an external P-channel pullup, STP_SPLY = 1 can be used to

enable a stiff supply voltage to slave devices requiring high current during operation. Clearing the bit to logic 0

disables t he s tr on g p ul lu p o n the OWSTP p in when the m aster is id le. T his bit has no affec t when the OWSTP pin is

disabled (STPEN = 0) .

BIT_CTL (Bit 5): Bit-Banging Mode. Setting this bit to logic 1 place the master into the bit-banging mode of

operation. In the bit-banging mode, only the least significant bit of the transmit/receive register is sent or received

before the associated interrupt flag occurs (signaling the end of the transaction). Clearing the bit leaves the bus

master operating in full-byte boundaries.

OD (Bit 6): Overdrive Mode. Setting this bit to a logic 1 places the master into overdrive mode, effectively

changing the bus master timing to match the 1-W ire timing for overdrive mode as outlined in The Book of iButton

Standards. Clearing the OD bit to a logic 0 leaves the master operating with standard mode timing.

EOWMI (Bit 7): Enable 1-Wire Master Interrupt. Setting this bit to a logic 1 enables the 1-W ire master interrupt

request to the CPU for any of the 1-Wire interrupt sources that have been individually enabled in the interrupt

enable register (xxxxx011b). Since the 1-Wire master interrupt and external interrupt 5 share the same interrupt

flag (IE5; EXIF.7), both cannot be used simultaneously. Thus, enabling the 1-Wire interrupt source effectively

disables the external interrupt 5 source.

1-Wire Interrupts

The 1-Wire bus master can be configured to generate an interrupt request to the CPU on the occurrence of a

number of 1-Wire-related e vent s or c ond itions . These inc lud e the f ol lo win g: pr esence-detect, t r ans mit buffer empty,

transmit shift-register empty, receive buffer full, receive shift-register full, 1-Wire short, and 1-Wire low. Each of

these potential 1-Wire interrupt sources has a corresponding enable bit and flag bit. Each flag bit in the interrupt

flag register (xxxxx010b) is set, independent of the interrupt enable bit, when the associated event or condition

occurs . In or d er for th e inte rr upt f lag to ge ner at e a n int er rupt r e ques t to the CPU, ho we ver, the i nd iv idual e nable b it

for the source along with the 1-Wire bus master interrupt enable bit (EOWMI; control register bit 7), and global

interrupt enable b it (EA; I E.7) m ust both be set t o a lo gic 1. T o clear th e 1-W ire bus m aster inter rupt, a read of the

interrupt flag reg is ter must always be per f ormed b y so f tware. Table 22 sum marizes the 1-Wire bus master interr upt

sources.

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Table 22. 1-Wire Bus Master Interrupt Sources

INTERRUPT

SOURCE MEANING

ENABLE/FLAG LOCATION

(Interrupt Flag Register.x

Interrupt Enable Register.x)

Presence Detect

After a 1-Wire reset has been issued, this flag is set after the amount

of time for a presence-detect pulse to have occurred. This bit is cleared

when the interrupt flag register is read.

Bit 0

Transmit Buffer

Empty

This flag is set when the transmit buffer is empty and ready to receive

the next byte. This bit is cleared when data is written to the transmit

buffer. A read of the interrupt flag register has no effect on this bit.

Bit 2

Transmit Shift

This flag is set when the transmit shift register is empty and is ready to

load a new byte from the transmit buffer. This bit is cleared when data

is transferred from the transmit buffer to the transmit shift register. A

read of the interrupt flag register has no effect on this bit.

Bit 3

Receive Buffer Full

This flag is set when there is a byte of data in the receive buffer waiting

to be read. This bit is cleared when the receive buffer is read.

Bit 4

Receive Shift

This flag is set when there is a byte of data in the receive shift register

waiting to be transferred to the receive buffer. This bit is cleared when

data in the receive shift register is transferred to the receive buffer.

Bit 5

1-Wire Short

This flag is set when the OW line was low before the bus master was

able to send out the beginning of a reset or a time slot. A read of the

interrupt flag register clears this bit.

Bit 6

1-Wire Low

This flag is set when the OW line is low while the bus master is idle,

signaling that a slave device has issued a presence pulse on the OW

line. A read of the interrupt flag register clears this bit if the OW line is

no longer low while the master is idle.

Bit 7

Peripheral Overview (Primary Integrated System Logic)

The DS80C410 provides several of the most commonly needed peripheral functions in microcomputer-based

systems. The DS80C410 offers three serial ports, four timers, a programmable watchdog timer, power-fail reset

detection, and a power-fail interrupt flag. Each of these peripherals is described below, and more details are

available in the High-Speed Microcontroller User’s Guide and the High-Speed Microcontroller User’s Guide:

Network Microcontroller Supplement.

Serial Ports

The microcontroller provides a serial port (UART) that is identical to the 80C52. Two additional hardware serial

ports are pr ovided th at are duplicates of the f irst one. This sec ond port opt ionally us es pins P1. 2 (RXD1) a nd P1.3

(TXD1) . The third port opt ionall y uses pins P6.6 (RXD2) and P6.7 (T XD2). The f unction of each of the three ser ial

ports is controlled by the SFRs and bits shown in Table 23.

Table 23. Serial Port SFRs

SERIAL PORT

FUNCTION CONTROL

SERIAL PORT 0 SERIAL PORT 1 SERIAL PORT 2

Control Register

SCON0

SCON1

SCON2

Input/Output Data Buffer

SBUF0

SBUF1

SBUF2

Baud Rate Doubler Bit

PCON.7

WDCON.7

T3CM.4

Framing Error-Detection Enable

PCON.6

Slave Address Mask Enable

SADEN0

SADEN1

SADEN2

Slave Address

SADDR0

SADDR1

SADDR2

All three serial ports can operate simultaneously and be configured for different baud rates or different modes.

When using a timer for the purpose of baud rate generation, serial port 1 must use timer 1, serial port 2 must use

timer 3, while serial por t 0 can use e ither timer 1 or tim er 2. Refer to the High-S peed Microcontr oller User ’s Guid e

for full descriptions of serial port operational modes.

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Timers

The microcontroller provides four general-purpose t imer/counters . Timers 0, 1, and 3 have thr e e comm on modes of

operation. Each of the t hree can be used as a 13-b it timer/c ounter, 16-bit timer/counter, or 8-bit tim er/counter with

auto-reloa d. Timer 0 can also oper ate as two 8-bit tim er/counters. W hen operated as a counter, tim ers 0, 1, and 3

count puls es on the c orres ponding T 0, T1, and T 3 ext ernal pins . Tim er 2 is a true 16-b it tim er/counter with severa l

additional operating modes. With a 16-bit reload register, timer 2 supports other features such as 16-bit auto-

reload, capture, up/down count, and output clock generation. All four timer/counters default to the standard

oscillator frequency divided by 12 input clock but can be configured to run from the system clock divided by 4.

Timers 1 and 2 can also be configured to operate with an input clock equal to the system clock divided by 13.

Table 24 shows the SFRs and bits associated with the four timer/counters.

Table 24. Timer/Counter SFRs

TIMER/COUNTER FUNCTION

TIMER/

COUNTER 0

TIMER/

COUNTER 1

TIMER/

COUNTER 2

TIMER/

COUNTER 3

Timer/Counter Mode Selection and

Control

TMOD, TCON TMOD, TCON T2MOD, T2CON T3CM

Count Registers TH0, TL0 TH1, TL1 TH2, TL2 TH3, TL 3

8-Bit Reload Register

TH0

TH1

—

TH3

16-Bit Reload/Capture Registers — — RCAP2H, RCAP2L —

Timer Input Clock-Select Bit CKCON.3 CKCON.4 CKCON.5 T3CM.5

Divide-by-13 Clock-Option Bit

—

T2MOD.4

T2MOD.3

—

Watchdog Timer

The watchdog is a free-running, programmable timer that can set a flag, cause an interrupt, and/or reset the

microcontroller if allowed to reach a preselected timeout. It can be restarted by software.

A typical application uses the watchdog timer as a reset source to prevent software from losing control. The

watchdog timer is initialized, selecting the timeout period and enabling the reset and/or interrupt functions. After

enabling the reset function, software must then restart the tim er before its expiration or hardware resets the CPU.

In this way, if the code execution goes awry and software does not reset the watchdog as scheduled, the

microcontroller is put in reset, a known good state.

Software c an s e lect o ne of four t imeout values as controlled by the W D1 and WD0 bits. Tim eout va lues are precis e

since the y are a func tion of the cr ystal fr equenc y. When the watchd og tim es out, the w atchdog in ter rupt f lag (W DIF

= W DCON.3) is s et. If the watchdog interrupt s ource has been enabled, program execution im mediate ly vectors to

the watchdog timer interrupt-service routine (code address = 63h). To enable the watchdog interrupt source, both

the EWDI (EIE.4) and EA (IE.7) bits must be set. Furthermore, setting the EWT (WDCON.1) bit allows the

watchdog t imer to generat e a reset exactly 512 system clocks following a tim eout. To prevent the watchdog reset

from occurring in such a situation, the watchdog timer count must be reset (RWT = 1) or the watchdog-reset

function itself must be disabled (EWT = 0). Both the enable watchdog timer (EWT) reset and the reset watchdog

timer (RWT) control bits are protected by timed-access circuitry. This prevents errant software from accidentally

clearing or disabling the watchdog. When a watchdog timer reset condition occurs, the watchdog timer reset flag

(WTRF = WDCON.2) is set by the hardware. This flag can then be interrogated following a reset to determine

whether the reset was caused by the watchdog timer.

The watchdog interrupt is useful for systems that do not require a reset circuit. It sets the WDIF (watchdog

interrupt) flag 512 system clocks before setting the r eset flag. Softw are can optional ly enable this interrupt source,

which is i ndependent of the watchdog-r eset functio n. The interrup t is comm only used durin g the debug process to

determine where watchdog reset commands must be located in the application software. The interrupt also can

serve as a convenient time-base generator or can wake up the microcontroller from power-saving modes.

The watchdog timer is controlled by the clock control (CKCON) and the watchdog control (WDCON) SFRs.

CKCON.7 and CKCO N.6 a re W D1 and W D0 r espectivel y, and th ey se lect the wat chdog t im eout peri od. Of c ourse,

the 4X/2X (PMR.3) and CD1:0 (PMR.7:6) s ystem clock control bits also affect the timeout period. Table 25 shows

the selection of timeout.

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Table 25 demonstrates that, for a 40MHz crystal frequency, the watchdog timer is capable of producing timeout

periods from 3.28ms (217 x 1/40MHz) to greater than one and a half seconds (1.68 = 226 x 1/40MHz) with the

default setting of CD1:0 (= 10). This wide variation in timeout periods allows very flexible system implementation.

In a typical initialization, the user selects one of the possible counter values to determine the timeout. Once the

counter chain has completed a full count, hardware sets the interrupt flag (WDIF = WDCON.3). Regardless of

whether the software makes use of this flag, there are then 512 system clocks left until the reset flag (WTRF =

WDCON.2) is set. Software can enable (1) or disable (0) the reset using the enable watchdog tim er reset (EWT =

WDCON.1) bit.

Table 25. Watchdog Timeout Values

4X/

CD1:0

WATCHDOG INTERRUPT TI MEOUT

WD1:0 = 00

WD1:0 = 01

WD1:0 = 10

WD1:0 = 11

215

218

221

224

216

219

222

225

217

220

223

226

217

220

223

226

225

228

231

234

IrDA Clock

The DS80C410 has the ability to generate an output clock (CLKO) as a secondary function on port pin P3.5.

Setting both the IrDA clock-output enable bit (IRDACK:COR.7) and external clock-output enable bit

(XCLKOE:COR.1) to a logic 1 produces an output clock of 16 times the programmed baud rate for serial port 0.

This 16X output clock used in conjunction with serial port 0 I/O (TXD0, RXD0) conveniently allows for direct

connection to common IrDA encoder/decoder devices. If the XCLKOE bit alone is set to logic 1, the CLKO pin

outputs the s yst em clock frequenc y divided b y 2, 4, 6, or 8 as def ined b y clock -output divi de bits ( COD1:0) . Sett ing

the IRDACK bit alone to logic 1 has no effect.

Interrupts

The microcontroller provides 16 interrupt sources with three priority levels. All interrupts, with the exception of the

power-fail i nterr up t, ar e cont roll ed by a series com binat ion of indi vidu al en ab le bits and a glob al i nterr up t enab le E A

(IE.7). Sett ing EA to a 1 al lows indiv idual inter rupts to be enabled. C learing EA disables all i nterrupts regardl ess of

their individual enable settings.

The three a vaila ble pri orit y levels ar e low , high, and h ighest. T he h ighest priorit y level is reser ved for the po wer -fail

interrupt only. All other interrupts have individual priority bits that when set to a 1 establish the particular interrupt

as high prior ity. In addit ion t o the user -s el ec tab le pri or ities , eac h i nterr u pt also has an inher e nt nat ur al pr iority, used

to determine the pr i ority of s imultaneous l y occ ur ring in ter rupts . The ava ilabl e interrupt sour c es, their f lags , e n abl es ,

natural pr iority, and a vailable prior ity selection bits are id entified in Table 26. N ote that exter nal interrup ts 2–5 and

the 1-Wire bus master share a common interrupt vector (43h). Also note that external interrupt 5 and the 1-Wire

bus master interrupt are multiplexed to form a single interrupt request. When the 1-Wire bus master interrupt is

enabled ( EOW MI = 1), it t ak es pr iority over ext ernal interr upt 5. I n or der f or exter nal i nterrupt 5 reques t to b e use d,

the 1-Wire bus master interrupt must be disabled (EOWMI = 0).

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Table 26. Interrupt Summary

NAME FUNCTION VECTOR

NATURAL

PRIORITY

FLAG BIT ENABLE BIT

PRIORITY

CONTROL BIT

PFI

Power-Fail Interrupt

33h

PFI (WDCON.4)

EPFI (WDCON.5)

N/A

INT0 External Interrupt 0 03h 1

IE0 (TCON.1)

(Note 2)

EX0 (IE.0) PX0 (IP.0)

TF0 Timer 0 0Bh 2

TF0 (TCON.5)

(Note 1)

ET0 (IE.1) PT0 (IP.1)

INT1 External Interrupt 1 13h 3

IE1 (TCON.3)

(Note 2)

EX1 (IE.2) PX1 (IP.2)

TF1 Timer 1 1Bh 4

TF1 (TCON.7)

(Note 1)

ET1 (IE.3) PT1 (IP.3)

TI0 or RI0 Serial Port 0 23h 5

RI_0(SCON0.0)

ES0 (IE.4) PS0 (IP.4)

TI_0(SCON0.1)

TF2

Timer 2

2Bh

TF2(T2CON.7)

ET2 (IE.5)

PT2 (IP.5)

TI1 or RI1 Serial Port 1 3Bh 7

RI_1(SCON1.0)

ES1 (IE.6) PS1 (IP.6)

TI_1(SCON1.1)

INT2

External Inter ru pts 2–

1-Wire Bus Master,

Interrupt 43h 8

IE2 (EXIF.4)

EX2-5 (EIE.0)

PX2-5 (EIP.0)

INT3

IE3 (EXIF.5)

—

INT4

IE4 (EXIF.6)

—

INT5/OWMI — — —

IE5 (EXIF.7)

(Note 3)

EOWMI (Note 3)

TF3

Timer 3

4Bh

TF3 (T3CM.7))

ET3 (EIE.1)

PT3 (EIP.1)

TI2 or RI2

Serial Port 2

53h

IE4 (EXIF.6)

ES2 (EIE.2)

PS2 (EIP.2)

WPI

Write Protect Interrupt

5Bh

WPIF (MCON2.7)

EWPI (EIE.3)

PWPI (EIP.3)

C0I

CAN0 Interrupt

6Bh

Various

C0IE (EIE.6)

C0IP (EIP.6)

EAI Ethernet Activity 73h 13

TIF (BCUC.5)

EAIE (EIE.5) EAIP (EIP.5)

RIF (BCUC.4)

WDTI

Watchdog Timer

63h

WDIF (WDCON.3)

EWDI (EIE.4)

PWDI (EIP.4)

EPMI

Ethernet Power Mode

7Bh

EPMF (BCUC.6)

EPMIE (EIE.7)

EPMIP (EIP.7)

Unless marked, all flags must be cleared by the applicati on software.

Note 1: Cleared automatic ally by hardware when the servic e routine is entered.

Note 2: If edge-triggered, the flag is cleared aut omatic al l y by hardware when the service routine is entered. If level-triggered, the flag follows the

state of the interrupt pin.

Note 3: The global 1-Wire interrupt-enable bi t (E OWMI) and individual 1-Wire interrupt source enables are located in the internal 1-Wire bus

master interrupt enable regi st er, and must be accessed through the OWMAD and OWMDR SFRs. Individual 1-Wire interrupt source

flag bits that are located in the internal 1-W ire bus master Interrupt flag regis t er are accessed in the sam e way.

One’s Compleme nt Adder

The DS80C410 implements a one’s complement adder to support the Internet checksum algorithm. The adder

contains a 16-bit accumulator and is accessed through the one’s complement adder data (OCAD) SFR.

W riting two b ytes to the O CAD register initiates a s ummation b etween the 16-b it accum ulator and the 16-bit value

entered. When entering a new 16-bit value for summation, the MSB should be loaded first and the LSB loaded

second. The calculation begins on the first machine cycle following the second write to the OCAD register and

executes in a single machine cycle. This allows back-to-back writes of 16-bit data to the OCAD register for

summation. The carry out bit from the high-order bit of the calculation is added back into the low-order bit of the

accumulator.

Reading two bytes from the OCAD register downloads the contents of the 16-bit accumulator. When reading the

16-bit accum ulator thr ough the OCAD reg ister , the MS B is unloade d firs t and the LSB is unlo aded s econd. T he 16-

bit accumulator is cleared to 0000h following the second read of the OCAD SFR.

The following is an example sequence for producing an Internet checksum for transmission.

• Read OCAD twice to make certain that the 16-bit accumulator = 0000h

• Write MSB of 16-bit value to OCAD

• Write LSB of 16-bit value to OCAD

• Repeat steps 2, 3 over the message data for which the checksum is to be computed

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• Read MSB of 16-bit value from OCAD

• One’s complement of the byte last read is the Internet checksum MSB

• Read LSB of 16-bit value from OCAD

• One’s complement of the byte last re ad is the Inter net c hec k sum LSB

Note that the computation of the Internet checksum over the message data and 16-bit checksum field should yield

0000h.

Clock Control and Power Management

The DS80C410 includes a number of unique features that allow flexibility in selecting system clock sources and

operating frequencies. To support the use of inexpensive crystals while allowing full speed operation, a clock

multiplier is included in the microcontroller’s clock circuit. Also, in addition to the standard 80C32 idle and power-

down (stop) modes, the DS80C410 provides a PMM. This mode allows the microcontroller to continue instruction

execution at a very low speed to significantly reduce power consumption (below even idle m ode). The DS80C410

also features several enha ncements to s top m ode that make this ex tremely low-power m ode more usef ul. Each of

these features is discussed in detail below.

System Clock Control

As mentioned previously, the microcontroller contains special clock-control circuitry that simultaneously provides

maximum timing flexibility and maximum availability and econom y in crystal selection. The logical operation of the

system clock divide control function is shown in Figure 21. A 3:1 multiplexer, controlled by CD1, CD0 (PMR.7-6),

selects one of three sources for the internal system clock:

• Crystal oscillator or external clock source

• (Crystal oscillator or external clock source) divided by 256

• (Crystal oscillator or external clock source) frequency multiplied by 2 or 4 times

The system clock control circuitry generates two clock signals that are used by the microcontroller. The internal

system clock provides the tim e base for timers and internal peripherals. The s ystem clock is run throug h a divide-

by-4 circuit to generate the machine cycle clock that provides the time base for CPU operations. All instructions

execute in one to five machine cycles. It is important to note the distinction between these two clock signals, as

they are sometimes confused, creating errors in timing calculations.

Setting CTM = 1 and CD1, CD0 = 00b enables the frequency multiplier, either doubling or quadrupling the

frequency of the crystal oscillator or external clock source. The 4X/2X bit controls the multiplying factor, selecting

twice or four times the frequency when set to 0 or 1, respectively. Enabling the frequency multiplier results in

apparent instruction exec ution speeds of 2 or 1 clock s. Regardless of the configur ation of the freque ncy multiplier,

the system clock of the microcontroller can never be operated faster than 75MHz. This means that the maximum

external clock source is 18.75MHz when using the 4X setting, and 37.5MHz when using the 2X setting.

The prim ary advantage of the clock multiplier is that it allows the microcontroller to use slower crystals to achieve

the sam e performanc e level. This red uces EMI and cost, as slower cr ystals are genera ll y mor e available and th us

less expensive.

Setting CD1, CD0 = 11b enables the PMM. When placed into PMM, the incoming crystal or clock frequency is

divided b y 256, resu lting in a m achine c ycle of 1024 cl ocks. Note tha t power c onsum ption in PMM is less tha n idle

mode. W hile both modes leave the p ower-hungry internal tim ers running, PMM runs all clocked functions such as

timers at the rate of crystal divided by 1024, rather than crystal divided by 4. Even though instruction execution

continues in PM M ( al be it at a reduc ed s p eed) , it sti ll co ns umes les s power th an i dl e mode. As a r esult, t her e i s little

reason to use idle mode in new designs.

The system clock and machine cycle rate changes one machine cycle after the instruction changing the control

bits. Note that the change affects all aspects of system operation, including timers and baud rates. Using the

switchback feature, described later, can eliminate many of the problems associated with the PMM.

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Changing the System Clock/Machine Cycle Clock Frequency

The microcontroller incorporates a special locking sequence to ensure “glitch-free” switching of the internal clock

signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-4) state. For example, to change

from 00 (frequency multiplier) to 11 (PMM), the software must change the bits in the following sequence: 00b =>

10b => 11b. Attempts to switch between invalid states fail, leaving the CD1, CD0 bits unchanged.

The following sequence must be followed when switching to the frequency multiplier as the internal time source.

This sequence can only be performed when the device is in divide-by-4 operation. The steps must be followed in

this order, alt hough it is po ss ible to have other instruct ions bet ween t hem . Any deviati on from this order causes the

CD1, CD0 bits to remain unchanged. Switching from frequency multiplier to nonm ultiplier mode requires no steps

other than the changing of the CD1, CD0 bits.

1) Ensure that the C D1, CD0 bits are set to 10, and the RG MD (EXIF .2) bit = 0.

2) Clear the crystal multiplier enable (CTM) bit.

3) Set the 4X/2X bit to the appropriate state.

4) Set the CTM bit.

5) Poll the CKRDY bit (EXIF. 3), waiting until it is set to 1. T his takes approxim ately 65,536 c ycles of the external

cry stal or clock sou rce.

6) Set CD1, CD0 to 00. The frequency multiplier is engaged on the machine cycle following the write to these bits.

Figure 21. System Clock Control Diagram

Switchback

As an alternative to software changing the CD1 and CD0 clock control bits to exit PMM, the microcontroller

provides hard ware a lternati ves for autom atic switchba ck to standar d spe ed (d ivide-by-4) operation. When enabl ed,

the switchb ack f eature allo ws seria l ports and int errup ts to autom aticall y switch b ack f rom divide-by-1024 (P MM) to

divide-by-4 (standard speed) operation. This feature makes it very convenient to use the PMM in real-time

applications.

The switchback feature is enabled by setting the SFR bit SWB (PMR.5) to a 1. Once it is enabled, and PMM is

selected , t wo pos s ible ev en ts c an caus e a n a utomatic s witc hbac k t o divi de-by-4 mode. Firs t, if an ex ter n al int err upt

occurs and is acknowledged, the system clock reverts from PMM to divide-by-4 mode. For example, if INT0 is

enabled and th e CPU is not servicin g a higher priorit y interru pt, then switchbac k occurs on INT0. Ho wever, if INT0

is not ena bl ed or t he CPU i s ser vicin g a hi gher pr iori t y interr u pt, t hen ac tivit y on INT0 does not cause switchb ac k to

occur.

A switchback can also occur when an enabled UART detects the start bit, indicating the beginning of an incom ing

serial character or when the SBUF register is loaded initiating a serial transmission. Note that a serial character’s

start bit does not generate an interrupt. The interrupt occurs only on reception of a complete serial word. The

autom atic switchback on detection of a start bit allo ws hardware to retur n to divide-by-4 operatio n (and the correc t

baud rate) in time for a proper serial reception or transmission.

99 of 102

Status

The ST ATUS (C5h) r egist e r and STATUS1 ( F7h) reg ister provide inf or mation abo ut i nter rupt and seri al port ac tiv ity

to assist in deter mining if it is pos sible to enter PMM. T he microcontr oller suppor ts three levels of interrupt priorit y:

power-fail, h ig h, and lo w. T he PI P (po wer-f ail pr ior ity interrupt stat us; STATU S.7), HI P (hig h prior ity interrupt status ;

STATUS.6), and LIP (low priority interrupt status; STATUS.5) status bits, when set to a logic 1, indicate the

corresponding level is in service.

Software s houl d not rel y on a lo wer-prior it y level inter rupt sour ce to rem ove PM M ( switchbac k ) when a hi gher level

is in service. Check the current priority service level before entering PMM. If the current service level locks out a

desired switchback source, then it would be advisable to wait until this condition clears before entering PMM.

Alternately, software can prevent an undesired exit from PMM by intentionally entering a low priority interrupt-

service level before entering PMM. This prevents other low priority interrupts from causing a switchback.

Entering PMM during an ongoing serial port transmission or reception can corrupt the serial port activity. To

prevent this, a hardware lockout feature ignores changes to the clock divisor bits while the serial ports are active.

Serial por t tr ansmit and receive act iv ity can be monitored thr o ugh the s erial port a c tivit y bits located i n th e STATU S

and STATUS1 registers.

Oscillator-Fail Detect

The m icrocontroller c ontains a safet y mechanism called an on-chip osc illator-fail detect c ircuit. W hen enabled, this

circuit causes the microcontroller to be held in reset if the oscillator frequency falls below ~100kHz. When

activated, this circuit complements the watchdog timer. Normally, the watchdog timer is initialized so that it times

out and causes a reset in the event that the microcontroller loses control. In the event of a crystal or external

oscillator fai lure, ho wever , the watchdo g tim er does not f unc tion, an d there is th e pote ntial to fai l in a n uncon troll ed

state. Using the oscillator-fail detect circuit forces the microcontroller to a known state (i.e., reset) even if the

oscillator stops.

The os cillator-f ail detec t cir cuitr y is enabl ed when s oft ware s ets the enabl e bit O FDE (PCO N.4) to a 1. Plea se note

that softw are must us e a tim ed-access procedure ( described earl ier) to write this bit. T he OFDF (PCO N.5) bit also

sets to a 1 when the circuitry detects an oscillator failure, and the microcontroller is forced into a reset state. This

bit can onl y be cleared to a 0 by a po wer-fail res et or by softw are. The osc illator-fail detec t circuitr y is not triggere d

when the oscillator is stopped upon entering stop mode.

Power-Fail Reset

The microcontroller incorporates an internal precision bandgap voltage reference and comparator circuit that

provide a power-on and power-fail reset function. This circuit monitors the incoming power supply voltages (VCC1

and VCC3) and holds the microcontroller in reset if either supply is below a minimum voltage level. When power

exceeds t he res et threshold, a full power -on res et is perf ormed. In this wa y, this int erna l v olt age monitoring c irc uitry

handles both power-up and power-down conditions without the need for additional external components.

Once VCC1 and VCC3 have risen above minimum voltages, VRST1 and VRST3 respectively, the device automatically

restarts the oscillator for the external crystal and counts 65,536 clock cycles before program execution begins at

location 0000h. This helps the system maintain reliable operation by only permitting operation when the supply

voltage is in a known good state. Software can determine that a power-on reset has occurred by checking the

power-on reset flag (POR;WDCON.6). Software should clear the POR bit after reading it.

Power-Fail Interrupt

The band gap volt age refer ence that se ts precis e rese t thresho lds also generates an option al earl y warning power-

fail interrupt (PFI). W hen enabled by software, the microcontroller vectors to code address 0033h if either VCC1 or

VCC3 drop below VPFW1 or VPFW3, respectively. PFI has the highest priority. The PFI enable is in the watchdog

control SFR (EPFI;WDCON.5). Setting this bit to logic 1 enables the PFI. Application software can also read the

PFI flag at W DCO N.4. A PFI condition sets this bit to a 1. The flag is inde pendent of the interrupt enable an d must

be cleared by software.

100 of 102

External Reset Pin s

The DS80C410 has both reset input (RST) and reset output (RSTOL) pins. The RSTOL pin supplies an active-low

reset output when the microcontroller is reset through a high on the RST pin, a timeout of the watchdog timer, a

crystal oscillator f ail, or an internally detected power-fail. The timing of the RSTOL pin is dependent on the source

of the reset.

RESET TYPE/SOURCE

RSTOL DURATION

Power-On Reset

65,536 tCLK (as described in Power Cycle Timing Characteristics)

External Reset

< 1.25 machine cycles

Power-Fail

65,536 tCLK (as described in Power Cycle Timing Characteristics)

Watchdog Timer Reset

Two machine cycle s

Oscillator-Fail Detect

65,536 tCLK (as described in Power Cycle Timing Characteristics)

Idle Mode

Setting the IDLE bit (PCON.0) invokes the idle mode. Idle leaves internal clocks, serial ports, and timers running.

Power consum ption drops because memory is not being accessed and instructions are not being executed. Since

clock s are r unning, the i dle power consum ption is a f u nction of cr ystal f reque ncy. T he CPU can exit i dle m ode with

any interrupt or a reset. Because PMM consumes less power than idle mode, and leaves the timers and CPU

operating, idle mode is no longer recommended for new designs, and is included for backward-software

compatibility only.

Stop Mode

Setting the STOP bit of the power-control register (PCON.1) invokes stop mode. Stop mode is the lowest power

state (besid es po wer of f ) s ince it turns of f all internal cl oc k ing. All microc ontrol ler o per ati on c eases at th e end of the

instruction that sets the STOP bit. The CPU invokes stop mode only when the CAN controller has been disabled

(through the SWINT or CRST bits in the C0C SFR) and when the Ethernet controller has been placed in sleep

mode. The CPU c an ex i t st op mode throug h an ext er n al i nter rupt , Et her net po w er -m ode inter ru pt , C AN in ter rupt, or

a reset con dit ion . Internally gener ated int err upts (t im er , s erial por t, watc hd og) cannot cause an ex it f r om stop m ode

because internal clocks are not active in stop mode. See the DC Electrical Specifications section for ICC1 and ICC3

maximum stop mode currents.

Bandgap Select

The DS80C410 provides two enhancements to stop mode. As described below, the device provides a bandgap

reference to determine power-fail interrupt and reset thresholds. The bandgap reference is controlled by the

bandgap select bit, BGS (EXIF.0). Setting BGS to a 1 keeps the bandgap reference enabled during stop mode.

The def ault or reset condit ion of the bit is logic 0, whic h disables the band gap during sto p mode. T his bit does not

enable/disable the internal reference during full power, PMM, or idle modes.

With the bandgap reference enabled, the power-fail reset and power-fail interrupt sources are valid means for

leaving st op mode. T his a ll o ws sof t ware t o det ec t an d c om pens ate f or a power su pply sag or browno ut, ev en when

in stop m ode. W hen BGS = 1, t he internal bandgap a nd associated c omparator circuitry cons ume a sm all amount

of addition al current d uring stop m ode. If a us er does not require a p ower-f ail reset or int errupt wh ile in stop m ode,

the bandgap can remain disabled. Only the most power-sensitive applications should disable the bandgap

reference in stop mode, as this results in an uncontrolled power-down condition.

Ring Oscillator

The second enhancement to stop mode reduces power consumption and allows the device to restart instantly

when exiting stop mode. The ring oscillator is an internal clock that can optionally provide the clock source to the

microcontroller when exiting stop mode in response to an interrupt.

During s top mode the cr ystal oscillat or is halted to m axim ize power s avings. Typicall y 1m s to 7ms are required for

an external crystal to begin oscillating again once the device receives the exit stimulus. The ring oscillator, by

contrast, is a free-running digital oscillator that has no startup delay. The ring oscillator feature is enabled by setting

the ring oscillator select bit, RGSL (EXIF.1). If enabled, the microcontroller uses the ring oscillator as the clock

source to exit stop mode, resuming operation in less than 100ns. After 65,536 oscillations of the external clock

source (not the ring oscillator), the device clears the ring oscillator mode bit, RGMD (EXIF.2), to indicate that the

device has switched from the ring oscillator to the external clock source.

101 of 102

The ring oscillator runs at approximately 15MHz, but varies over temperature and voltage. As a result, no serial

communication or precision timing should be attempted while running from the ring oscillator, since the operating

frequenc y is not pr ecise. Lik ewise, the Ethernet and CAN controll ers derive their t iming from the s ystem clock and

should no t be en abled until RGMD = 0. The r eset ( default) state of th e RGSL b it is logic 0, which does n ot res ult in

use of the ring oscillator to exit stop mode.

EMI Reduction

One of the major contributors to radiated noise in an 8051-based system is the toggling of ALE. The microcontroller

allows sof tware to disa ble ALE whe n not used b y setting the AL EOFF (PMR.2) bit to a 1. W hen ALEOFF = 1, ALE

automatically toggles during off-chip program and data memory accesses. However, ALE remains static when

performing on-chip memory access. The default state of ALEOFF is 0, so ALE normally toggles at a frequency of

XTAL/4.

Software Breakpoint Mode

The DS80C410 provides a special software-breakpoint mode for code-debug purposes. Breakpoint mode can be

enabled by setting the BPME bit (ACON.4) to a logic 1. Once enabled, the A5h op code can be used to create a

break in code execution. When the break op code (A5h) is executed, all clocks to the timer 0, 1, 2, 3, and watchdog

timer blocks are s topped and an y serial port oper ation (when derived f rom a tim er) is halted. Additional ly, the state

machine controlling access to timed-access-protected SFRs is suspended. Much like an interrupt, the CPU

generates a hardware LCALL and vector to address location 000083h. Unlike an interrupt, however, the return

address is not pushed onto the stack, but is placed into the BPA1 (LSB), BPA2 (MSB), and BPA3 (XSB) SFRs, and

the A5h op code is used to exit breakpoint mode and return to the address contained in the BPA3:1 SFRs.

PIN CONFIGURATION

SELECTOR GUIDE

PART CAN BUS ON-CHIP

SRAM

(kB)

MAX

CLOCK

SPEED

(MHz)

DS80C410-FNY 1 73.25 75

DS80C410+FNY 1 73.25 75

DS80C411-FNY 0 73.25 75

DS80C411+FNY 0 73.25 75

+Denotes a lead(Pb)-free/RoHS-compliant device.

PACKAGE INFORMATION

For the latest package outline information and land

patterns, go to www.maxim-ic.com/packages.

PACKAGE

TYPE

PACKAGE

CODE

DOCUMENT

NO.

100 LQFP — 21-0297

REVISION HISTORY

100

Maxim

DS80C410

DS80C411

TOP VIEW

LQFP

102 of 102

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim

reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 Rio Robles, San Jose, CA 95134 408-601-1000

REVISION HISTORY

REVISION

NUMBER

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

0 102204 New product release (DS80C410) —

1 010705 New product release (DS80C411) 1

2 060805

Added lead-free devices to O r dering Information and Selector Guide

tables.

1, 102

3 010907

Added notes explaining that the system clock must be > 25MHz to

support Eth ernet 100 Mbps m ode.

52, 73

Correct BCUD SFR address in Buffer Control Unit section.

Updated package drawing. 102

4 6/09 Corrected the SEL (DPS.3) bit reset state from 1 to 0 in Table 2. 41

5 4/15

Removed automotive reference from the Controller Area Network (CAN)

Module section