September 2013 Doc ID 17074 Rev 6 1/31
1
VNH5180A-E
Automotive fully integrated H-bridge motor driver
Features
• Output current: 8 A
• 3 V CMOS compatible inputs
• Undervoltage shutdown
• Overvoltage clamp
• Thermal shutdown
• Cross-conduction protection
• Current and power limitation
• Very low standby power consumption
• PWM operation up to 20 KHz
• Protection against loss of ground and loss of
V
CC
• Current sense output proportional to motor
current
• Output protected against short to ground and
short to V
CC
• Package: ECOPACK
®
Description
The VNH5180A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side driver and two low-side
switches. Both switches are designed using
STMicroelectronics’ well known and proven
proprietary VIPower
®
M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent
signal/protection circuitry. The three dies are
assembl ed in Pow er SS O-3 6 TP package on
electrically isolated leadframes. This package,
specifically designed for the harsh automotive
environment offers improved thermal
performance thanks to exposed die pads.
More over, its f ully sy mmetric al mec hanical desig n
allows superior manufacturability at board level.
The input signals IN
A
and IN
B
can directly
interface to the microcontroller to select the motor
direction and the brake condition. The
DIAG
A
/EN
A
or DIAG
B
/EN
B
, when connected to an
external pull-up resistor, enables one leg of the
bridge. Eac h DIAG
A
/EN
A
provides a feedback
digital diagnostic signal as well. The normal
operating condition is explained in the truth table.
The CS pin allows to monitor the motor current by
delivering a current proportional to its value when
CS_DIS pin is driven low or left open. When
CS_DIS is driven high, CS pin is in high
impedance condition. The PWM, up to 20 KHz,
allows to control the speed of the motor in all
possible conditions. In all cases, a low level state
on the PWM pin turns off both the LS
A
and LS
B
switches.
Type R
DS(on)
I
out
V
CCmax
VNH5180A-E 180 mΩ max
(per leg) 8A 41V
PowerSSO-36 TP
Table 1. Device summary
Package Order codes
Tube Tape and reel
PowerSSO-36 TP VNH5180A-E VNH5180ATR-E
www.st.com
Contents VNH5180A-E
2/31 Doc ID 17074 Rev 6
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Elect rical char acteristi c s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 W aveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-
state mode 23
4.1.2 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 ECOPACK
® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 PowerSSO-36 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 PowerSSO-36 TP packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VNH5180A-E List of tables
Doc ID 17074 Rev 6 3/31
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Pin functions description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Switching (VCC = 13 V, RLOAD = 5 W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12. Current sense (9 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 13. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 15. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 16. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 17. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 18. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 23
Table 19. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. PowerSSO-36 TP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of figures VNH5180A-E
4/31 Doc ID 17074 Rev 6
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 14
Figure 8. Definition of delay response time of sense current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Waveforms in full-bridge operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Waveforms in full-bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 19
Figure 12. Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. PowerSSO-36™ PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 23
Figure 18. Detailed chipset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 25
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 25
Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22. PowerSSO-36 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 23. PowerSSO-36 TP tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VNH5180A-E Block diagram and pin description
Doc ID 17074 Rev 6 5/31
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Block description
Name Description
Logic control Allows the turn-on a nd t he turn-of f of th e high-si de a nd the
low- side switches ac cording t o the truth table.
Undervoltage Shuts down the device for battery voltage lower than 5V.
High-side and low-side clamp voltage Protect the high-side and the low-side switches from the
high voltage on the battery line.
High-side and low-side driver Drive the gate of the concerned switch to allow a proper
R
DS(on)
for the leg of the bridge.
Current limitation Limits the motor current in case of short circuit.
High-side and low-side overtemperature
protection
In case of short-circuit with the increase of the junction
temperatu re, it shu ts down the conc erned d river to pre vent
degradation and to protect the die.
Low-si de overload detector Detec ts when low side current excee ds shutdown current
and latches off the concerned Low side.
Fault detectio n Signalizes the abnormal behaviour of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.
Power limitation Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
6285&(B+6
$
.
6,*1$/
&/$03
32:(5
/,0,7$7,21
)$8/7
'(7(&7,21
89
/6%B29(57(03(5$785(
+6%B29(57(03(5$785(+6$B29(57(03(5$785(
/6$B29(57(03(5$785(
/2*,&
&/$03B/6
$
'5,9(5
+6
$
&/$03B+6$
&855(17
/,0,7$7,21B$
+6$
'5,9(5
/6
$
/6$
*1'
$
29(5/2$'
'(7(&725B$
9&&
',$*
$
(1
$
,1
$
&6 &6B',6 3:0 ,1
%
',$*
%
(1
%
'5,9(5
+6
%
+6%
&/$03B+6%
&855(17
/,0,7$7,21B%
&/$03B/6
%
/6%
*1'
%
'5,9(5
/6
%
29(5/2$'
'(7(&725B%
6285&(B+6
%
.
'5$,1B/6
$
'5$,1B/6
%
("1($'5
Block diagram and pin description VNH5180A-E
6/31 Doc ID 17074 Rev 6
Figure 2. Conf iguration diagram (top view)
Table 3. Suggested connections for unused and not connected pins
Connection / pin Current sense N.C. SOURCE_HSx DRAIN_LSx INPUTx, PWM
DIAGx/ENx
CS_DIS
Floating Not allowed X X X X
To ground Through 1 kΩ
resistor XNot allowed X Through 10 kΩ
resistor
Table 4. Pin definitions and functions
Pin N° Symbol Function
13, 24 V
CC
, Heat Slug1 Drain of high-side switches and power supply voltage.
1, 5, 9, 14, 18, 23,
28, 32, 36 NC Not connected.
15 IN
A
Clockwise input
16 EN
A
/DIAG
A
Status of high-side and low-side switches A;
open drain output.
17 IN_PWM PWM input.
19 CS Output of current sense.
1
EN/DIAG
_
A
CS
19
IN_A
GND_B
GND_A
IN_B
EN/DIAG
_
B
18
NC
SOURCE HS
B
GND_B
Slug1
Slug2 Slug3
36
SOURCE HS
A
GND_A
GND_A
GND_A
DRAIN LS
A
SOURCE HS
A
SOURCE HS
A
V
CC
NC
V
CC
SOURCE HS
B
SOURCE HS
B
DRAIN LS
B
GND_B
GND_B
DRAIN LS
B
NC
NC
NC
IN_PWM
NC CS_DIS
NC
NC
NC
DRAIN LS
A
VNH5180A-E Block diagram and pin description
Doc ID 17074 Rev 6 7/31
20 CS_DIS Ac tive high CMOS c ompatibl e pin to disable c urrent sense
pin.
21 EN
B
/DIAG
B
Status of high-side and low-side switches b;
open drain output.
22 IN
B
Counter clockwise input.
25, 26, 27, 29, 35 OUT
B
,
Heat Slug3 Source of high-side switch B / drain of low-side switch B.
30, 31, 33, 34 GND
B
Source of low-side switch B.
2, 8, 10, 11, 12 OUT
A,
Heat Slug2 Source of high-side switch A / drain of low-side switch A.
3, 4, 6, 7 GND
A
Source of low-side switch A.
Table 5. Pin functions description
Name Description
V
CC
Battery connection.
GND Power ground.
OUT
A
OUT
B
Power connections to the motor.
IN
A
IN
B
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins
control the st ate of the brid ge in no rmal ope ration ac cording t o the truth ta ble (brak e to
V
CC
, Brake to GND, clockwise and counterclockwise).
PWM Voltage controlled input pin with hysteresis, CMOS compatible. Gates of low-side
FETS ge t modulated by the PWM sign al during their ON phase allowing s peed co ntrol
of the motor.
EN
A
/DIAG
A
EN
B
/DIAG
B
Open drain bidirectional logic pins.These pins must be connected to an external pull
up resis tor . Whe n external ly pulled low, they dis able half-b ridge A or B. In case of fa ult
detection (thermal shutdown of a high-side FET or excessive ON-state voltage drop
across a low-side FET), these pins are pulled low by the device (see Table 14: Truth
table in fault conditions (det ected on OU TA)).
CS Analog current sense output. This output delivers a current proportional to the motor
current if CS_DIS is low or left open. The information can be read back as an analog
voltage across an external resistor.
CS_DIS Active high CMOS compatible pin to disable the current sense pin.
Table 4. Pin definitions and functions (continued)
Pin N° Symbol Function
Electrical specifications VNH5180A-E
8/31 Doc ID 17074 Rev 6
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the Table 6: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
V
CC
IN
A
I
S
I
OUTA
I
INA
V
INA
V
CC
V
OUTA
I
SENSE
V
OUTB
DIAG
A
/EN
A
I
ENA
I
GND
I
OUTB
IN
B
I
INB
DIAG
B
/EN
B
I
ENB
V
ENB
V
ENA
V
INB
V
SENSE
OUT
A
OUT
B
PWM
CS
I
pw
V
pw
GND
V
CSD
I
CSD
CS_DIS
Table 6. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
Supply voltage + 41 V
I
max
Maximum output current (continuous) Internally limited A
I
R
Reverse output current (continuous) -15 A
I
IN
Input current (IN
A
and IN
B
pins ) +/- 10 mA
I
EN
Enable input current (DIAG
A
/EN
A
and DIAG
B
/EN
B
pins) +/- 10 mA
I
pw
PWM Input current +/- 10 mA
I
CS_DIS
CS_DIS input current +/- 10 mA
V
CS
Current sense maximum voltage V
CC
-41/+V
CC
V
V
ESD
Electrostatic discharge
(Human body model: R=1.5 kΩ, C=100 pF) 2kV
T
c
Jun c tion operat ing temperature -40 to 150 °C
T
STG
Storage temperature -55 to 150 °C
I
GND
DC reverse ground pin current 200 mA
VNH5180A-E Electrical specification s
Doc ID 17074 Rev 6 9/31
2.2 Thermal data
2.3 Electrical characteristics
Values specified in this section are for V
CC
= 9 V up to 18 V; -40 °C < T
J
< 150 °C, unless
otherwise specified.
Table 7. Thermal data
Symbol Parameter Max. value Unit
R
thj-case
Thermal resistance junction-case (per leg) HSD 4.8 °C/W
LSD 4.6
R
thj-amb
Thermal resistance junction-ambient See Figure 17 °C/W
Table 8. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
Operating supply voltage 5.5 18 V
I
S
Supply current
Off-state with all fault cleared and
ENx = 0 (standby)
IN
A
=IN
B
=PWM=0; T
j
= 25 °C;
V
CC
=13V
36µA
Off-state with all fault cleared and
ENx = 0 (standby)
IN
A
=IN
B
=PWM=0;
V
CC
=13V; T
j
=- 40
to
150 °C
10 µA
Off-state (no standby)
IN
A
=IN
B
=PWM=0; ENx=5V;
T
j
=- 40
to
150 °C 5mA
On-state:
IN
A
or IN
B
= 5 V; no PWM 36mA
On-state:
IN
A
or IN
B
= 5 V; PWM = 20 kHz 6mA
R
ONHS
Static hig h-s ide resis t an ce
I
OUT
= 2.5 A; T
j
= -40 °C 75 mΩ
I
OUT
= 2.5 A; T
j
=25°C 115 mΩ
I
OUT
= 2.5 A; T
j
= 150 °C 230 mΩ
I
OUT
= 2.5 A; T
j
=- 40
to
150 °C 250 mΩ
R
ONLS
Static low-side resistance I
OUT
= 2.5A; T
j
=25°C 53.5 mΩ
I
OUT
= 2.5A; T
j
=- 40
to
150 °C 110 mΩ
V
f
High-side free-wheeling
diode forward voltage I
OUT
=-2.5A; T
j
= 150 °C 0.7 0.9 V
Electrical specifications VNH5180A-E
10/31 Doc ID 17074 Rev 6
I
L(off)
High-side off-state out put
current (per channel)
T
j
=25°C; V
OUTX
=EN
X
=0V;
V
CC
=13V 03µA
T
j
= 125 °C; V
OUTX
=EN
X
=0V;
V
CC
=13V 05µA
I
RM
Dynamic cross-
conduction current I
OUT
= 2.5A (see Figure 6)0.6A
Table 9. Logic inputs (IN
A
, IN
B
, EN
A
, EN
B
, PWM, CS_DIS)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level voltage Normal operat ion
(DIAG
X
/EN
X
pin a cts as an
input pin) 0.9 V
V
IH
Input high level voltage Normal operation
(DIAG
X
/EN
X
pin a cts as an
input pin) 2.1 V
V
IHYST
Input hysteresis voltage Normal operat ion
(DIAG
X
/EN
X
pin a cts as an
input pin) 0.15 V
V
ICL
Input clamp voltage I
IN
= 1 mA 5.5 6.3 7.5 V
I
IN
=-1mA -1.0-0.7-0.3 V
I
INL
Input current V
IN
=0.9V 1 µA
I
INH
Input current V
IN
=2.1V 10 µA
V
DIAG
Enable output low
lev el voltage
Fault operation
(DIAG
X
/EN
X
pin a cts as an
output pin); I
EN
=1mA 0.4 V
Table 10. Switching (V
CC
=13V, R
LOAD
=5Ω)
Symbol Parameter Test conditions Min. Typ. Max. Unit
f PWM freq uen cy 0 2 0 kHz
t
d(on)
Turn-on delay time Input rise time < 1µs
(see Figure 6)250 µs
t
d(off)
Turn-o f f del ay time Input rise time < 1µs
(see Figure 6)250 µs
t
r
Rise time See Figure 5 12µs
t
f
Fall time See Figure 5 12µs
t
DEL
Delay time during change
of operating mode See Figure 4 200 400 1600 µs
t
rr
High-side free wheeling
diode reverse recovery
time See Figure 7 400 ns
Table 8. Power section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VNH5180A-E Electrical specification s
Doc ID 17074 Rev 6 11/31
Table 11. Protections and diagnostics
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
USD
Undervo lt age shut do w n 3 5 V
V
USDhyst
Undervo lt age shut do w n
hysteresis 0.5 V
I
LIM_H
High-side current limitation 8 12 16 A
I
SD_LS
Shutdown LS current 16 30 52 A
V
CLPH
High-side clamp voltage (V
CC
to
OUT
A
=0 or OUT
B
=0) I
OUT
= 2.5 A 41 46 52 V
V
CLPLS
Low-si de clamp voltage
(OUT
A
=V
CC
or
OUT
B
= V
CC
to GND) I
OUT
=2.5A 41 46 52 V
T
TSD(1)
1. T
TSD
is the minimum threshold temperature between HS and LS
Thermal shutdown temperature V
IN
= 2.1 V 150 175 200 °C
T
TR(2)
2. Valid for both HSD and LSD.
Thermal reset temperature 135 °C
T
HYST(2)
Thermal hysteresis (T
SD
-T
R
)7°C
T
TSD_LS
Low-side thermal shutdown
temperature V
IN
= 2.1 V 150 175 200 °C
V
CLP
Tot al c lam p vol t age (V
CC
to GND) I
OUT
=2.5A 41 46 52 V
t
SD_LS
T ime to shut dow n for the l ow-side 10 µs
Table 12. Current sense (9 V < V
CC
<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
0
I
OUT
/I
SENSE
I
OUT
=0.35A; V
SENSE
= 0.32 V;
V
CSD
=0V; T
j
= - 40 to 150 °C 645 840 1140
K
1
I
OUT
/I
SENSE
I
OUT
= 1 A; V
SENSE
= 0.98 V;
V
CSD
=0V; T
j
= - 40 to 150 °C 700 820 955
K
2
I
OUT
/I
SENSE
I
OUT
= 2.5 A; V
SENSE
= 2.4 V;
V
CSD
= 0 V; T
j
= - 40 to 150 °C 710 810 900
K
3
I
OUT
/I
SENSE
I
OUT
= 4 A; V
SENSE
= 4 V; V
CSD
= 0 V;
T
j
= - 40 to 150 °C 690 790 900
dK
0
/K
0(1)
Analog sense
current drift I
OUT
= 0.35A;
V
SENSE
= 0.32V;
V
CSD
= 0 V; T
j
= - 40 to 150 °C -18 18 %
dK
1
/K
1(1)
Analog sense
current drift I
OUT
=1A;
V
SENSE
= 0.98 V;
V
CSD
= 0 V; T
j
= - 40 to 150 °C -13 13 %
dK
2
/K
2(1)
Analog sense
current drift I
OUT
=2.5A;
V
SENSE
= 2.4V;
V
CSD
= 0 V; T
j
= - 40 to 150 °C -13 13 %
dK
3
/K
3(1)
Analog sense
current drift I
OUT
=4A;
V
SENSE
= 4V; V
CSD
= 0 V;
T
j
= - 40 to 150 °C -13 13 %
V
SENSE
Max ana log sens e
output voltage I
OUT
= 2.5A; V
CSD
=0V;
R
SENSE
=2KΩ5V
Electrical specifications VNH5180A-E
12/31 Doc ID 17074 Rev 6
Figure 4. Definition of the delay times measurement
I
SENSE0
Analog sense
leakage current
I
OUT
= 0 A; V
SENSE
=0V; V
CSD
=5V;
V
IN
=0V; T
j
= - 40 to 150 °C 05µA
V
CSD
=0V; V
IN
=5V;
T
j
= - 40 to
.
150 °C 0 180 µA
V
CSD
=5V; V
IN
=5V; I
OUT
= 2.5 A;
T
j
= - 40 to
.
150 °C 05µA
t
DSENSEH
Delay response time
from falling edge of
CS_DIS pin
V
IN
=5V; V
SENSE
<4V, I
OUT
=2.5A,
I
SENSE
=90% of I
SENSEmax
(see Figure 8)50 µs
t
DSENSEL
Delay response time
from rising edge of
CS_DIS pin
V
IN
=5V; V
SENSE
<4V; I
OUT
=2.5A;
I
SENSE
=10% of I
SENSEmax
(see Figure 8)20 µs
1. Analog sense current drift is deviation of factor K for a given device over (-40 °C to 150 °C and
9V < V
CC
< 18 V) with respect to its value measured at T
J
= 25 °C, V
CC
= 13 V.
Table 12. Current sense (9 V < V
CC
< 18 V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
t
V
INB
V
INA
t
PWM
t
I
LOAD
t
DEL
t
DEL
VNH5180A-E Electrical specification s
Doc ID 17074 Rev 6 13/31
Figure 5. Definition of the low-side switching times
Figure 6. Definition of the high-side switching times
t
f
PWM
t
t
V
OUTA, B
20%
90% 80%
10%
t
r
t
t
V
OUTA
V
INA
90%
10%
t
D(on)
t
D(off)
Electrical specifications VNH5180A-E
14/31 Doc ID 17074 Rev 6
Figure 7. Definition of dynamic cross conduction current during a PWM operation
Figure 8. Definition of delay response time of sense current
t
t
I
MOTOR
PWM
t
V
OUTB
t
I
CC
t
rr
I
RM
IN
A
= 1, IN
B
=0
SENSE CURRENT
INPUT
LOAD CURREN T
CS_DIS
t
DSENSEH
t
DSENSEL
VNH5180A-E Electrical specification s
Doc ID 17074 Rev 6 15/31
Note: In normal operating conditions the DIAG
X
/EN
X
pin is consider ed as an input pin by the
device. This pin must be externally pulled high.
Table 13. Truth table in normal operating conditions
IN
A
IN
B
DIAG
A
/EN
A
DIAG
B
/EN
B
OUT
A
OUT
B
CS Operating mode
11
11
HH High Imp. Brake to V
CC
0L
I
SENSE
=I
OUT
/K Clockwise (CW)
01LH Counterclockwise (CCW)
0 L High Imp. Brake to GND
Table 14. Truth table in fault cond itions (detected on OUT
A
)
IN
A
IN
B
DIAG
A
/EN
A
DIAG
B
/EN
B
OUT
A
OUT
B
CS
(V
CSD
=0V)
11
01OPEN
HHigh Imp.
0L
01HI
OUTB
/K
0L
High Imp.
X X 0 OPEN
Fault Information Protection Action
Electrical specifications VNH5180A-E
16/31 Doc ID 17074 Rev 6
Table 15. Electrical transient requirements (part 1)
ISO 7637 -2:
2004(E)
Test pulse
Test levels
(1)
1. The above test levels must be considered referred to V
CC
= 13.5 V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/p ulse
repetition time Delays and
Impedance
III IV Min. Max.
1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω
2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω
3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω
3b +75V +100 V 1h 90ms 100ms 0.1µs, 50Ω
4 -6V -7V 1 pulse 100ms, 0.01Ω
5b
(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
+65V +87V 1 pulse 400ms, 2Ω
Table 16. Electrical transient requirements (part 2)
ISO 7637-2:
2004(E)
Test pulse
Test level results
(1)
1. The above test levels must be considered referred to V
CC
= 13.5 V except for pulse 5b.
III IV
1C C
2a C C
3a C C
3b C C
4C C
5b
(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Table 17. Electrical transient requirements (part 3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or m ore funct ions of th e device are not pe rformed as de signed a fter exp osure to
disturba nce and cannot be retu rned to pro per opera tion with out repla cing th e devic e.
VNH5180A-E Electrical specification s
Doc ID 17074 Rev 6 17/31
2.4 Waveforms
Figure 9. Waveforms in full-bridge operation
NORMAL OPE RATION (DIAG
A
/EN
A
=1, DIAG
B
/EN
B
=1)
IN
A
IN
B
PWM
OUT
A
OUT
B
I
OUTA
->
OUTB
DIAG
A
/EN
A
DIAG
B
/EN
B
DIAG
B
/EN
B
IN
A
IN
B
PWM
OUT
A
OUT
B
DIAG
A
/EN
A
NORMAL OPERATION (DIAG
A
/EN
A
=1, DIAG
B
/EN
B
=0 and DIAG
A
/EN
A
=0, DIAG
B
/EN
B
=1)
CS (*)
CS
I
OUTA
->
OUTB
t
DEL
t
DEL
LOAD CONNECTED BETWEEN OUT
A
, OUT
B
LOAD CONNECTED BETWEEN OUT
A
, OUT
B
(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE
CS_DIS
CS_DIS
IN
A
IN
B
T
jHSA
DIAG
A
/EN
A
DIAG
B
/EN
B
I
LIM
T
TSD_HSA
T
TR_HSA
T
j
> T
TR
CURRENT LIMITATION/THERMAL SHUT DOWN or OUT
A
SHORTED T O GROU ND
CS
I
OUTA
->
OUTB
norm al op er a ti on OUT
A
shorted to gr ound norm al op er at i on
CS_DIS
T
j
< T
TSD
T
j
=T
TSD
powe r limitati on
limitation
current
Electrical specifications VNH5180A-E
18/31 Doc ID 17074 Rev 6
Figure 10. Waveforms in full-bridge operation (continued)
norm al operation OUT
A
softly shorted to V
CC
normal operati on undervo l tage shutdown
IN
A
IN
B
OUT
A
OUT
B
DIAG
B
/EN
B
DIAG
A
/EN
A
OUT
A
shorted to V
CC
(resistive short) and undervoltage shutdown
CS V<nominal
I
OUTA
->
OUTB
CS_DIS
T
j_LSA
T
TSD_LS
normal operation OUT
A
hardly shorted to V
CC
normal operation undervoltage shutdown
IN
A
IN
B
OUT
A
OUT
B
DIAG
B
/EN
B
DIAG
A
/EN
A
OUT
A
shorted to V
CC
(pure short) and undervoltage shutdown
CS V<nominal
I
OUTA
->
OUTB
CS_DIS
I
LSA
I
SD_LS
I
LSA
I
SD_LS
T
j_LSA
T
TSD_LS
VNH5180A-E Application information
Doc ID 17074 Rev 6 19/31
3 Application information
In normal operating conditions the DIAG
X
/EN
X
pin is consider ed as an input pin by the
device. This pin must be externally pulled high.
PWM pin usage: In all cases, a “0” on the PWM pin turns off both LS
A
and LS
B
switches.
When PWM rises back to “1”, LS
A
or LS
B
turn on again depending on the input pin state.
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit
protection
Note: The value of the blocking capacitor (C) depends on the application conditions and defines
voltage and current ripple on supply line at PWM operation. Stored energy of the motor
inductance may fly back into the blocking capacitor, if the bridge driver goes into 3-state.
This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation,
500 µF per 10 A load current is recommended.
In case of a fault condition the DIAG
X
/EN
X
pin is considered as an output pin by the device.
The fault conditions are:
– Overtemperature on one or both high-sides
– Short to battery condition on the output (overcurrent detection on the low-side
Power M O SFET)
Possible origins of fault conditions may be:
OUT
A
is shorted to ground
→
overtemperature detection on high-side A
OUT
A
is shorted to V
CC
→
low-side Power MOSFET overcurrent detection
When a fault condition is detected, the user can identify which power element is in fault by
monitoring the IN
A
, IN
B
, DIAG
A
/EN
A
and DIAG
B
/EN
B
pins.
DIAG
B
/EN
B
+5V
1K
3.3K
IN
B1K
GND GND
Vcc
CS_DIS
1k
100K
Application information VNH5180A-E
20/31 Doc ID 17074 Rev 6
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUT
X
) again, the input signal must rise from low to high level.
Figure 12. Behavior in fault condition (how a fault can be cleared)
Note: In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: IN
A
if EN
A
= 0 or IN
B
if EN
B
=0)
- Pull low all inputs, PWM and Diag/EN pins within t
DEL
.
If the Diag/En pins are already low, PWM = 0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.
3.1 Reverse battery protection
Three possible solutions can be considered:
– A Schottky diode D connected to V
CC
pin
– An N-channel MOSF ET co nnec te d to the GND pin (see Figure 11: Typical
application circuit for DC to 20 kHz PWM operation short circuit protection)
– A P-channel MOSFET connected to the V
CC
pin
The device sustains no more than -15 A in reverse battery conditions because of the two
Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5180A-E is pulled down to the V
CC
line (approximately -1.5 V).
VNH5180A-E Application information
Doc ID 17074 Rev 6 21/31
Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If
I
Rmax
is the maximum target reverse current through microcontroller I/Os, series resistor is:
Figure 13. Half-bridge configuration
Note: The VNH5180A-E can be used as a high power half-bridge driver achieving an On
resistance per leg of 90 mΩ.
Figure 14. Multi-motors configuration
Note: The VNH5180A-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAG
X
/EN
X
pins allow
to put unused half-bridges in high impedance.
RVIOs VCC
–
IRmax
---------------------------------=
M
OUT
A
OUT
A
OUT
B
OUT
B
V
CC
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
GND GND
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
M
2
OUT
A
OUT
A
OUT
B
OUT
B
V
CC
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
GND GND
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
M
1
M
3
Package and PCB thermal data VNH5180A-E
22/31 Doc ID 17074 Rev 6
4 Package and PCB thermal data
4.1 PowerSSO-36 thermal data
Figure 15. PowerSSO-36™ PC board
Double layers: footprint
Double layers: 2cm
2
of Cu
Double layers: 8cm
2
of Cu
Note:
Board finish thickness 1.6 mm +/- 10 %, Board double layers, Board dimension 129 mm x 60 mm, Board Material FR4, Cu
thickness 0.070 mm (front and back side), Thermal vias spaced on a 1.2 mm x 1.2 mm grid, Vias pad clearance thickness
0.2 mm, Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm.
VNH5180A-E Package and PCB thermal data
Doc ID 17074 Rev 6 23/31
Figure 16. Chipset configuration
Figure 17. Auto and mutual R
thj-amb
vs PCB copper area in open box free air
condition
4.1.1 Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
CHIP 1
R
thA
CHIP 2 CHIP 3
R
thB
R
thC
R
thAB
R
thAC
R
thBC
0
10
20
30
40
50
60
70
80
0123456789
cm
2
of Cu Area (refer to PCB layout)
°C/W
RthA
RthB = RthC
RthAB = RthAC
RthBC
Table 18. Thermal calculation in clockwise and anti-clockwise operation in steady-
state mode
HS
A
HS
B
LS
A
LS
B
T
jHSAB
T
jLSA
T
jLSB
ON OFF OFF ON P
dHSA
x R
thHS
+ P
dLSB
x R
thHSLS
+ T
amb
P
dHSA
x R
thHSLS
+
P
dLSB
x R
thLSLS
+ T
amb
P
dHSA
x R
thHSLS
+ P
dLSB
x R
thLS
+ T
amb
OFF ON ON OFF P
dHSB
x R
thHS
+ P
dLSA
x R
thHSLS
+ T
amb
P
dHSB
x R
thHSLS
+
P
dLSA
x R
thLS
+ T
amb
P
dHSB
x R
thHSLS
+ P
dLSA
x R
thLSLS
+ T
amb
Package and PCB thermal data VNH5180A-E
24/31 Doc ID 17074 Rev 6
4.1.2 T hermal ca lculation in t ransient mode
T
hs
= P
dhs
• Z
hs
+ Z
hsls
• (P
dlsA
+ P
dlsB
) + T
amb
T
lsA
= P
dlsA
• Z
ls
+ P
dhs
• Z
hsls
+ P
dlsB
• Z
hsls
+ T
amb
T
lsB
= P
dlsB
• Z
ls
+ P
dhs
• Z
hsls
+ P
dlsA
• Z
hsls
+ T
amb
Figure 18. Detailed chipset configuration
Equation 1: pulse calculation formula
where
CHIP 1
Z
ts
CHIP 2 CHIP 3
Z
ls
Z
ls
Z
hsls
Z
hsls
Z
lsls
ZTHδRTH δZTHtp 1δ–()+⋅=
δt
p
T⁄=
VNH5180A-E Package and PCB thermal data
Doc ID 17074 Rev 6 25/31
Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse
ZTH - HSD @ c u ar ea
0.1
1
10
100
0.001 0.01 0.1 1 10 100 1000ti me (sec)
°C/W
HS D-8 c m^2 Cu
HS D-2 c m^2 Cu
HSD-footprint
HsLsD-8 cm^2 Cu
HsLsD-2 cm^2 Cu
HsLsD-footprint
ZTH -LSD @ c u area
0.1
1
10
100
0.001 0.01 0.1 1 10 100 1000ti me (sec)
°C/W
LSD-8 cm^2 Cu
LSD-2 cm^2 Cu
LSD-footprint
LsL sD-8 cm^2 Cu
LsL sD-2 cm^2 Cu
LsLsD-footprint
Z
ls
Z
lsls
Package and PCB thermal data VNH5180A-E
26/31 Doc ID 17074 Rev 6
Figure 21. Thermal fitting model of an H-bridge in PowerSS O-36
Table 19. Thermal parameters
(1)
1. The blank space means that the value is the same as the previous one.
Area/island (cm
2
) Footprint 2 8
R1 = R7 (°C/W) 0.4
R2 = R8 (°C/W) 3.5
R3 (°C/W) 8
R4 (°C/W) 30 16 11
R5 (°C/W) 40 30 14
R6 (°C/W) 36 34 21
R9 = R15 (°C/W) 0.1
R10 = R1 6 (°C/W) 5.2
R11 = R17 (°C/W) 32 14 14
R12 = R1 8 (°C/W) 4 9 21 21
R13 = R1 9 (°C/W) 5 2 36 24
R14 = R2 0 (°C/W) 5 0 40 33
R21 = R22 = R23 (°C/W) 80 77 75
C1 = C7 = C 9 = C15 (W.s/°C) 0.0005
C2 = C8 (W.s/°C) 0.008
C3 (W.s/°C) 0.09
C4 (W.s/°C) 0.5 0.8 0.8
C5 (W.s/°C) 0.8 1 .4 2
C6 (W.s/°C) 7 8 10
C10 = C16 (W.s/°C) 0.009
C11 = C17 (W.s/°C) 0.09 0.07 0.07
C12 = C18 (W.s/°C) 0.45 0.45 0.45
C13 = C19 (W.s/°C) 0.8 1.2 1.4
C14 = C20 (W.s/°C) 4 5 8
C21 = C2 2 = C23 (W.s/°C) 0.005 0.003 0.003
VNH5180A-E Package and packing information
Doc ID 17074 Rev 6 27/31
5 Package and packing information
5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
5.2 PowerSSO-36 TP package information
Figure 22. PowerSSO-36 TP p ackage dimensions
Package and packing information VNH5180A-E
28/31 Doc ID 17074 Rev 6
Table 20. PowerSSO-36 TP mechanical data
Symbol Millimeters
Min. Typ. Max.
A 2.15 - 2.47
A2 2.15 - 2.40
a1 0 - 0.1
b 0.18 - 0.36
c 0.23 - 0.32
D 10.10 - 10.50
E 7.4 - 7.6
e-0.5-
e3 - 8.5 -
F2.3
G- -0.1
H 10.1 - 10.5
h--0.4
k 0 deg 8 deg
L0.6- 1
M4.3
N - - 10 deg
O1.2
Q0.8
S2.9
T3.65
U1.0
X1 1.85 2.35
Y1 3 3.5
X2 1.85 2.35
Y2 3 3.5
X3 4.7 - 5.2
Y3 3 - 3.5
Z1 0.4
Z2 0.4
VNH5180A-E Package and packing information
Doc ID 17074 Rev 6 29/31
5.3 PowerSSO-36 TP packing information
Figure 23. PowerSSO-36 TP tube shipment (no suffix)
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Qty 49
Bulk Qty 1225
Tube length (±0.5) 532
A3.5
B13.8
C (±0.1) 0.6
A
CB
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F20.2
G (+2 / -0) 24.4
N (min) 100
T (max ) 30.4
Reel dimensions
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment D ep th K (max) 2.85
Hole Spacing P1 (±0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500m m m i n 500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Revision history VNH5180A-E
30/31 Doc ID 17074 Rev 6
6 Revision history
Table 21. Document revision history
Date Revision Changes
11-Feb-2010 1 Initial release.
28-Sep-2010 2
Updated following tables:
–Table 7: Thermal data
–Table 8: Power section
–Table 12: Current sense (9 V < VCC < 18 V)
13-Oct-2010 3
Updated Chapter 3: Application information
Updated following tables:
–Table 18: Thermal calculation in clockwise and anti-clockwise
operation in steady-state mode
–Table 19: Thermal parameters
20-Oct-2010 4 Changed document status from target specification to definitive
datasheet
22-Dec-2011 5
Updated Figure 1: Block diagram
Added Table 3: Suggested connections for unused and not
connected pins
Table 11: Protections and diagnostics:
–T
TSD
, T
TR
, T
HYST
: added note
Updated Figure 9: Waveforms in full-bridge operation and
Figure 10: Waveforms in full-bridge operation (continued)
19-Sep-2013 6 Updated Disclaimer.
VNH5180A-E
Doc ID 17074 Rev 6 31/31
Please Read Carefully:
Informa tion in this do cument is prov ided solely in connec tion with ST products. STMic roelect ronics NV and its subsidiari es (“ST”) reser ve the
right to mak e chang es, c or recti ons , modif ic ations or improv ement s, t o th is documen t, and the prod ucts an d servic es des crib ed he rein a t any
time, without notice.
All ST produ cts are sold purs uant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, sele ct ion or use of the ST products and se rvices described herein.
No license, express o r implied, by estoppel or otherwise, to any intellectual property rights is grant ed under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST produ cts with provisions different from t he statement s and/or technical features se t forth in this doc ument shall imme diately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liabili ty of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all informa tion previously supplied.
The ST logo is a registered t rademark of STMi croelectron ics. All other names are the propert y of their respective owners.
© 2013 STMicroelec tronics - All right s re se rv ed
STMicroelectronic s group of compani es
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - Unit ed States of Americ a
www.st.com
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
STMicroelectronics:
VNH5180A-E VNH5180ATR-E