1
FEATURES
3
2
4
61
VCCA VCCB
B
GND
A
DBV PACKAGE
(TOP VIEW) DCK PACKAGE
(TOP VIEW)
3
2
4
61
VCCA VCCB
B
GND
A
3
2
4
61
VCCA VCCB
B
GND
A
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
DIR DIR DIR
5
55
YZP PACKAGE
(BOTTOM VIEW)
C1
B1
A1
C2
B2
A2
B
DIR
VCCB
A
GND
VCCA
3
2
1
4
5
6
DESCRIPTION/ORDERING INFORMATION
SN74AVC1T45SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008www.ti.com
2
•Available in the Texas Instruments NanoFree™ •Typical Max Data RatesPackage
– 500 Mbps (1.8-V to 3.3-V Translation)•Fully Configurable Dual-Rail Design Allows
– 320 Mbps (<1.8-V to 3.3-V Translation)Each Port to Operate Over the Full 1.2-V to
– 320 Mbps (Translate to 2.5 V or 1.8 V)3.6-V Power-Supply Range
– 280 Mbps (Translate to 1.5 V)•V
CC
Isolation Feature - If Either V
CC
Input Is at
– 240 Mbps (Translate to 1.2 V)GND, Both Ports Are in the High-Impedance
•Latch-Up Performance Exceeds 100 mA PerState
JESD 78, Class II•DIR Input Circuit Referenced to V
CCA
•ESD Protection Exceeds JESD 22•± 12-mA Output Drive at 3.3 V
– 2000-V Human-Body Model (A114-A)•I/Os Are 4.6-V Tolerant
– 200-V Machine Model (A115-A)•I
off
Supports Partial-Power-Down Mode
– 1000-V Charged-Device Model (C101)Operation
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. TheSN74AVC1T45 is optimized to operate with V
CCA
/V
CCB
set at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
aslow as 1.2 V. The A port is designed to track V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. TheB port is designed to track V
CCB
. V
CCB
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universallow-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 SN74AVC1T45YZPR _ _ _TC_0.23-mm Large Bump – YZP (Pb-free)SOT (SOT-23) – DBV Reel of 3000 SN74AVC1T45DBVR DT1_– 40 °C to 85 °C
SOT (SC-70) – DCK Reel of 3000 SN74AVC1T45DCKR TC_SOT (SOT-553) – DRL Reel of 4000 SN74AVC1T45DRLR TC_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one followingcharacter to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
B
DIR 5
4
A3
VCCA VCCB
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels ofthe direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits datafrom the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when theA-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logicHIGH or LOW level applied to prevent excess I
CC
and I
CCZ
.
The SN74AVC1T45 is designed so that the DIR input is powered by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, then both ports are in the high-impedancestate.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as thepackage.
FUNCTION TABLE
(1)
INPUT
OPERATIONDIR
L B data to A busH A data to B bus
(1) Input circuits of the data I/Osalways are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
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Absolute Maximum Ratings
(1)
SN74AVC1T45SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CCA
Supply voltage range – 0.5 4.6 VV
CCB
I/O ports (A port) – 0.5 4.6V
I
Input voltage range
(2)
I/O ports (B port) – 0.5 4.6 VControl inputs – 0.5 4.6A port – 0.5 4.6Voltage range applied to any output in the high-impedance orV
O
Vpower-off state
(2)
B port – 0.5 4.6A port – 0.5 V
CCA
+ 0.5V
O
Voltage range applied to any output in the high or low state
(2) (3)
VB port – 0.5 V
CCB
+ 0.5I
IK
Input clamp current V
I
< 0 – 50 mAI
OK
Output clamp current V
O
< 0 – 50 mAI
O
Continuous output current ± 50 mAContinuous current through V
CCA
, V
CCB
, or GND ± 100 mADBV package 165DCK package 259θ
JA
Package thermal impedance
(4)
°C/WDRL package 142YZP package 123T
stg
Storage temperature range – 65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current ratings are observed.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
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Recommended Operating Conditions
(1) (2) (3)
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
V
CCI
V
CCO
MIN MAX UNIT
V
CCA
Supply voltage 1.2 3.6 VV
CCB
Supply voltage 1.2 3.6 V1.2 V to 1.95 V V
CCI
×0.65High-levelV
IH
Data inputs 1.95 V to 2.7 V 1.6 Vinput voltage
2.7 V to 3.6 V 21.2 V to 1.95 V V
CCI
×0.35Low-levelV
IL
Data inputs 1.95 V to 2.7 V 0.7 Vinput voltage
2.7 V to 3.6 V 0.81.2 V to 1.95 V V
CCA
×0.65High-level DIRV
IH
1.95 V to 2.7 V 1.6 Vinput voltage (referenced to V
CCA
)
2.7 V to 3.6 V 21.2 V to 1.95 V V
CCA
×0.35Low-level DIRV
IL
1.95 V to 2.7 V 0.7 Vinput voltage (referenced to V
CCA
)
2.7 V to 3.6 V 0.8V
I
Input voltage 0 3.6 VActive state 0 V
CCOV
O
Output voltage V3-state 0 3.61.2 V – 31.4 V to 1.6 V – 6I
OH
High-level output current 1.65 V to 1.95 V – 8 mA2.3 V to 2.7 V – 93 V to 3.6 V – 121.2 V 31.4 V to 1.6 V 6I
OL
Low-level output current 1.65 V to 1.95 V 8 mA2.3 V to 2.7 V 93 V to 3.6 V 12
Δt/ Δv Input transition rise or fall rate 5 ns/VT
A
Operating free-air temperature – 40 85 °C
(1) V
CCI
is the V
CC
associated with the input port.(2) V
CCO
is the V
CC
associated with the output port.(3) All unused data inputs of the device must be held at V
CCI
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics
(1) (2)
SN74AVC1T45SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
over recommended operating free-air temperature range (unless otherwise noted)
T
A
= 25 °C – 40 °C to 85 °CPARAMETER TEST CONDITIONS V
CCA
V
CCB
UNITMIN TYP MAX MIN MAX
V
CCOI
OH
= – 100 µA 1.2 V to 3.6 V 1.2 V to 3.6 V
– 0.2I
OH
= – 3 mA 1.2 V 1.2 V 0.95I
OH
= – 6 mA 1.4 V 1.4 V 1.05V
OH
V
I
= V
IH
VI
OH
= – 8 mA 1.65 V 1.65 V 1.2I
OH
= – 9 mA 2.3 V 2.3 V 1.75I
OH
= – 12 mA 3 V 3 V 2.3I
OL
= 100 µA 1.2 V to 3.6 V 1.2 V to 3.6 V 0.2I
OL
= 3 mA 1.2 V 1.2 V 0.15I
OL
= 6 mA 1.4 V 1.4 V 0.35V
OL
V
I
= V
IL
VI
OL
= 8 mA 1.65 V 1.65 V 0.45I
OL
= 9 mA 2.3 V 2.3 V 0.55I
OL
= 12 mA 3 V 3 V 0.7I
I
DIR V
I
= V
CCA
or GND 1.2 V to 3.6 V 1.2 V to 3.6 V ± 0.025 ± 0.25 ± 1 µAA port 0 V 0 to 3.6 V ± 0.1 ± 1 ± 5I
off
V
I
or V
O
= 0 to 3.6 V µAB port 0 to 3.6 V 0 V ± 0.1 ± 1 ± 5B port 0 V 3.6 V ± 0.5 ± 2.5 ± 5V
O
= V
CCO
or GND,I
OZ
µAV
I
= V
CCI
or GNDA port 3.6 V 0 V ± 0.5 ± 2.5 ± 51.2 V to 3.6 V 1.2 V to 3.6 V 10I
CCA
V
I
= V
CCI
or GND, I
O
= 0 0 V 3.6 V – 2 µA3.6 V 0 V 101.2 V to 3.6 V 1.2 V to 3.6 V 10I
CCB
V
I
= V
CCI
or GND, I
O
= 0 0 V 3.6 V 10 µA3.6 V 0 V – 2I
CCA
+ I
CCB
V
I
= V
CCI
or GND, I
O
= 0 1.2 V to 3.6 V 1.2 V to 3.6 V 20 µA(see Table 1 )ControlC
i
V
I
= 3.3 V or GND 3.3 V 3.3 V 2.5 pFinputs
A or BC
io
V
O
= 3.3 V or GND 3.3 V 3.3 V 6 pFport
(1) V
CCO
is the V
CC
associated with the output port.(2) V
CCI
is the V
CC
associated with the input port.
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Switching Characteristics
Switching Characteristics
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
over recommended operating free-air temperature range, V
CCA
= 1.2 V (see Figure 1 )
V
CCB
= 1.2 V V
CCB
= 1.5 V V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 VFROM TOPARAMETER UNIT(INPUT) (OUTPUT)
TYP TYP TYP TYP TYP
t
PLH
3.3 2.7 2.4 2.3 2.4A B nst
PHL
3.3 2.7 2.4 2.3 2.4t
PLH
3.3 3.1 2.9 2.8 2.7B A nst
PHL
3.3 3.1 2.9 2.8 2.7t
PHZ
5.1 5.2 5.3 5.2 3.7DIR A nst
PLZ
5.1 5.2 5.3 5.2 3.7t
PHZ
5.3 4.3 4 3.3 3.7DIR B nst
PLZ
5.3 4.3 4 3.3 3.7t
PZH
(1)
8.6 7.3 6.8 6.1 6.4DIR A nst
PZL
(1)
8.6 7.3 6.8 6.1 6.4t
PZH
(1)
8.3 7.8 7.7 7.5 5.8DIR B nst
PZL
(1)
8.3 7.8 7.7 7.5 5.8
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
over recommended operating free-air temperature range, V
CCA
= 1.5 V ± 0.1 V (see Figure 1 )
V
CCB
= 1.5 V V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 VV
CCB
= 1.2 VFROM TO
± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
2.9 0.7 5.6 0.6 5.2 0.5 4.2 0.5 3.8A B nst
PHL
2.9 0.7 5.6 0.6 5.2 0.5 4.2 0.5 3.8t
PLH
2.6 0.6 5.5 0.4 5.3 0.3 4.9 0.3 4.8B A nst
PHL
2.6 0.6 5.5 0.4 5.3 0.3 4.9 0.3 4.8t
PHZ
3.8 1.6 6.7 1.5 6.8 0.3 6.9 0.9 6.9DIR A nst
PLZ
3.8 1.6 6.7 1.5 6.8 0.3 6.9 0.9 6.9t
PHZ
5.1 1.8 8.1 1.6 7.1 1.1 4.7 1.4 4.5DIR B nst
PLZ
5.1 1.8 8.1 1.6 7.1 1.1 4.7 1.4 4.5t
PZH
(1)
7.7 13.6 12.4 9.6 9.3DIR A nst
PZL
(1)
7.7 13.6 12.4 9.6 9.3t
PZH
(1)
6.7 12.3 12 11.1 10.7DIR B nst
PZL
(1)
6.7 12.3 12 11.1 10.7
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
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Switching Characteristics
Switching Characteristics
SN74AVC1T45SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
over recommended operating free-air temperature range, V
CCA
= 1.8 V ± 0.15 V (see Figure 1 )
V
CCB
= 1.5 V V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 VV
CCB
= 1.2 VFROM TO
± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
2.7 0.6 5.3 0.5 5 0.4 3.9 0.4 3.4A B nst
PHL
2.7 0.6 5.3 0.5 5 0.4 3.9 0.4 3.4t
PLH
2.3 0.5 5.2 0.4 5 0.3 4.6 0.2 4.4B A nst
PHL
2.3 0.5 5.2 0.4 5 0.3 4.6 0.2 4.4t
PHZ
3.8 1.6 5.9 1.6 5.9 1.6 5.9 0.5 6DIR A nst
PLZ
3.8 1.6 5.9 1.6 5.9 1.6 5.9 0.5 6t
PHZ
5 1.8 7.7 1.4 6.8 1 4.4 1.4 5.3DIR B nst
PLZ
5 1.8 7.7 1.4 6.8 1 4.4 1.4 5.3t
PZH
(1)
7.3 12.9 11.8 9 8.7DIR A nst
PZL
(1)
7.3 12.9 11.8 9 8.7t
PZH
(1)
6.5 11.2 10.9 9.8 9.4DIR B nst
PZL
(1)
6.5 11.2 10.9 9.8 9.4
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
over recommended operating free-air temperature range, V
CCA
= 2.5 V ± 0.2 V (see Figure 1 )
V
CCB
= 1.5 V V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 VV
CCB
= 1.2 VFROM TO
± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
2.6 0.5 4.9 0.4 4.6 0.3 3.4 0.3 3A B nst
PHL
2.6 0.5 4.9 0.4 4.6 0.3 3.4 0.3 3t
PLH
2.2 0.4 4.2 0.3 3.8 0.2 3.4 0.2 3.3B A nst
PHL
2.2 0.4 4.2 0.3 3.8 0.2 3.4 0.2 3.3t
PHZ
2.8 0.3 3.8 0.8 3.8 0.4 3.8 0.5 3.8DIR A nst
PLZ
2.8 0.3 3.8 0.8 3.8 0.4 3.8 0.5 3.8t
PHZ
4.9 2 7.6 1.5 6.5 0.6 4.1 1 4DIR B nst
PLZ
4.9 2 7.6 1.5 6.5 0.6 4.1 1 4t
PZH
(1)
7.1 11.8 10.3 7.5 7.3DIR A nst
PZL
(1)
7.1 11.8 10.3 7.5 7.3t
PZH
(1)
5.4 8.6 8.1 7 6.6DIR B nst
PZL
(1)
5.4 8.6 8.1 7 6.6
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
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Switching Characteristics
Operating Characteristics
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
over recommended operating free-air temperature range, V
CCA
= 3.3 V ± 0.3 V (see Figure 1 )
V
CCB
= 1.5 V V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 VV
CCB
= 1.2 VFROM TO
± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
t
PLH
2.6 0.4 4.7 0.3 4.4 0.2 3.3 0.2 2.8A B nst
PHL
2.6 0.4 4.7 0.3 4.4 0.2 3.3 0.2 2.8t
PLH
2.2 0.4 3.8 0.3 3.4 0.2 3 0.1 2.8B A nst
PHL
2.2 0.4 3.8 0.3 3.4 0.2 3 0.1 2.8t
PHZ
3.1 1.3 4.3 1.3 4.3 1.3 4.3 1.3 4.3DIR A nst
PLZ
3.1 1.3 4.3 1.3 4.3 1.3 4.3 1.3 4.3t
PHZ
4 0.7 7.4 0.6 6.5 0.7 4 1.5 4.9DIR B nst
PLZ
4 0.7 7.4 0.6 6.5 0.7 4 1.5 4.9t
PZH
(1)
6.2 11.2 9.9 7 6.7DIR A nst
PZL
(1)
6.2 11.2 9.9 7 6.7t
PZH
(1)
5.7 8.9 8.5 7.2 6.8DIR B nst
PZL
(1)
5.7 8.9 8.5 7.2 6.8
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
T
A
= 25 °C
V
CCA
= V
CCA
= V
CCA
= V
CCA
= V
CCA
=TEST
V
CCB
= 1.2 V V
CCB
= 1.5 V V
CCB
= 1.8 V V
CCB
= 2.5 V V
CCB
= 3.3 VPARAMETER UNITCONDITIONS
TYP TYP TYP TYP TYP
A-port input,
33334C
L
= 0 pF,B-port outputC
pdA
(1)
f = 10 MHz, pFB-port input,
t
r
= t
f
= 1 ns
13 13 14 15 15A-port outputA-port input,
13 13 14 15 15C
L
= 0 pF,B-port outputC
pdB
(1)
f = 10 MHz, pFB-port input,
t
r
= t
f
= 1 ns
33333A-port output
(1) Power dissipation capacitance per transceiver
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Power-Up Considerations
SN74AVC1T45SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:1. Connect ground before any supply voltage is applied.2. Power up V
CCA
.3. V
CCB
can be ramped up along with or after V
CCA
.
Table 1. Typical Total Static Power Consumption (I
CCA
+ I
CCB
)
V
CCAV
CCB
UNIT0 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
0 V 0 <0.5 <0.5 <0.5 <0.5 <0.5
1.2 V <0.5 <1 <1 <1 <1 1
1.5 V <0.5 <1 <1 <1 <1 1
µA1.8 V <0.5 <1 <1 <1 <1 <1
2.5 V <0.5 1 <1 <1 <1 <1
3.3 V <0.5 1 <1 <1 <1 <1
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TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
tPHL - ns
CL - pF
0
1
2
3
4
5
6
0 10 20 30 40 50 60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
0
1
2
3
4
5
6
0 10 20 30 40 50
tPLH - ns
CL - pF
60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
tPHL - ns
CL - pF
0
1
2
3
4
5
6
0 10 20 30 40 50 60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
0
1
2
3
4
5
6
0 10 20 30 40 50
tPLH - ns
CL - pF
60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
T
A
= 25 °C, V
CCA
= 1.2 V
T
A
= 25 °C, V
CCA
= 1.5 V
10 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AVC1T45
www.ti.com
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
tPHL - ns
CL - pF
0
1
2
3
4
5
6
0 10 20 30 40 50 60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
0
1
2
3
4
5
6
0 10 20 30 40 50
tPLH - ns
CL - pF
60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
tPHL - ns
CL - pF
0
1
2
3
4
5
6
0 10 20 30 40 50 60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
0
1
2
3
4
5
6
0 10 20 30 40 50
tPLH - ns
CL - pF
60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
SN74AVC1T45SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
T
A
= 25 °C, V
CCA
= 1.8 V
T
A
= 25 °C, V
CCA
= 2.5 V
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN74AVC1T45
www.ti.com
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
tPHL - ns
CL - pF
0
1
2
3
4
5
6
0 10 20 30 40 50 60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
0
1
2
3
4
5
6
0 10 20 30 40 50
tPLH - ns
CL - pF
60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
T
A
= 25 °C, V
CCA
= 3.3 V
12 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AVC1T45
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2 × VCCO
Open
GND
RL
RL
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCCA/2VCCA/2
VCCI/2 VCCI/2 VCCI
0 V
VCCO/2 VCCO/2VOH
VOL
0 V
VCCO/2 VOL + VTP
VCCO/2 VOH − VTP
0 V
VCCI
0 V
VCCI/2 VCCI/2
tw
Input
VCCA
VCCO
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
VCCO RL0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VTP
CL
15 pF
15 pF
15 pF
15 pF
15 pF
SN74AVC1T45SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN74AVC1T45
www.ti.com
APPLICATION INFORMATION
1
2
3
6
5
4
VCC1 VCC1 VCC2 VCC2
SYSTEM-1 SYSTEM-2
SN74AVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Figure 2 shows an example of the SN74AVC1T45 being used in a unidirectional logic level-shifting application.
PIN NAME FUNCTION DESCRIPTION
1 V
CCA
V
CC1
SYSTEM-1 supply voltage (1.2 V to 3.6 V)2 GND GND Device GND3 A OUT Output level depends on V
CC1
voltage.4 B IN Input threshold value depends on V
CC2
voltage.5 DIR DIR GND (low level) determines B-port to A-port direction.6 V
CCB
V
CC2
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
Figure 2. Unidirectional Logic Level-Shifting Application
14 Submit Documentation Feedback Copyright © 2003 – 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AVC1T45
www.ti.com
APPLICATION INFORMATION
1
2
3
6
5
4
VCC1 VCC1 VCC2
SYSTEM-1 SYSTEM-2
DIR CTRL
I/O-1 I/O-2
Pullup/Pulldown
or Bus Hold†
VCC2
Pullup/Pulldown
or Bus Hold†
Enable Times
SN74AVC1T45SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES530G – DECEMBER 2003 – REVISED JANUARY 2008
Figure 3 shows the SN74AVC1T45 being used in a bidirectional logic level-shifting application. Since theSN74AVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoidbus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 toSYSTEM-1.
STATE DIR CTRL I/O-1 I/O-2 DESCRIPTION
1 H Out In SYSTEM-1 data to SYSTEM-2SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The2 H Hi-Z Hi-Z
bus-line state depends on pullup or pulldown.
(1)
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or3 L Hi-Z Hi-Z
pulldown.
(1)
4 L In Out SYSTEM-2 data to SYSTEM-1
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Calculate the enable times for the SN74AVC1T45 using the following formulas:•t
PZH
(DIR to A) = t
PLZ
(DIR to B) + t
PLH
(B to A)•t
PZL
(DIR to A) = t
PHZ
(DIR to B) + t
PHL
(B to A)•t
PZH
(DIR to B) = t
PLZ
(DIR to A) + t
PLH
(A to B)•t
PZL
(DIR to B) = t
PHZ
(DIR to A) + t
PHL
(A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit isswitched until an output is expected. For example, if the SN74AVC1T45 initially is transmitting from A to B, thenthe DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the Bport has been disabled, an input signal applied to it appears on the corresponding A port after the specifiedpropagation delay.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): SN74AVC1T45
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74AVC1T45DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DBVTE4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DCKT ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DRLR ACTIVE SOT DRL 6 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AVC1T45YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jan-2012
Addendum-Page 2
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AVC1T45DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AVC1T45DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AVC1T45DCKR SC70 DCK 6 3000 180.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3
SN74AVC1T45DCKR SC70 DCK 6 3000 180.0 8.4 2.3 2.52 1.2 4.0 8.0 Q3
SN74AVC1T45DCKT SC70 DCK 6 250 180.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3
SN74AVC1T45DRLR SOT DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74AVC1T45YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jun-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AVC1T45DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0
SN74AVC1T45DBVT SOT-23 DBV 6 250 202.0 201.0 28.0
SN74AVC1T45DCKR SC70 DCK 6 3000 202.0 201.0 28.0
SN74AVC1T45DCKR SC70 DCK 6 3000 214.0 199.0 55.0
SN74AVC1T45DCKT SC70 DCK 6 250 202.0 201.0 28.0
SN74AVC1T45DRLR SOT DRL 6 4000 202.0 201.0 28.0
SN74AVC1T45YZPR DSBGA YZP 6 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jun-2012
Pack Materials-Page 2
D: Max =
E: Max =
1.418 mm, Min =
0.918 mm, Min =
1.358 mm
0.858 mm
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