IN74HC4051
1
ANALOG MULTIPLEXER DEMULTIPLEXER
High-Performance Silicon-Gate CMOS
The IN74HC4051 utilize silicon-gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
OFF leakage currents. These analog multiplexers/demultiplexers
control analog voltages that may vary across the complete power
supply range (from VCC to VEE).
The Channel-Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog
switch, to the Common Output/Input.When the Enable pin is
high, all analog switches are turned off.
The Channel-Select and Enable inputs are compatible with
standard CMOS outputs; with pullup resistors, they are
compatible with LS/ALSTTL outputs.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V
• Low Noise
ORDERING INFORMATION
IN74HC4051N Plastic
IN74HC4051DW SOIC
TA = -55° to 125° C for all
p
acka
g
es
PIN ASSIGNMENT
FUNCTION TABLE
Control Inputs ON
Enable Select Channels
C B A
L L L L X0
L L L H X1
L L H L X2
L L H H X3
L H L L X4
L H L H X5
L H H L X6
L H H H X7
H X X X None
X = don’t care
LOGIC DIAGRAM
Single-Pole, 8-Position Plus Common Off
PIN 16 =VCC
PIN 7 = VEE
PIN 8 = GND
IN74HC4051
2
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage (Referenced to
GND)
(Referenced to VEE)
-0.5 to +7.0
-0.5 to +14.0
V
VEE Negative DC Supply Voltage (Referenced to
GND)
-7.0 to +0.5 V
VIS Analog Input Voltage VEE - 0.5 to
VCC+0.5
V
VIN Digital Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
I DC Input Current Into or Out of Any Pin ±25 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10
Seconds
(Plastic DIP or SOIC Package)
260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC Positive Supply Voltage (Referenced to GND)
(Referenced to VEE)
2.0
2.0
6.0
12.0
V
VEE Negative DC Supply Voltage (Referenced to GND) - 6.0 GND V
VIS Analog Input Voltage VEE V
CC V
VIN Digital Input Voltage (Referenced to GND) GND VCC V
VIO* Static or Dynamic Voltage Across Switch - 1.2 V
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Channel
Select or Enable Inputs)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
* For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be
drawn;
i. e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
VOUT should be constrained to the range indicated in the Recommended Operating Conditions..
Unused digital input pins must always be tied to an appropriate logic voltage level (e.g.,
either GND or VCC). Unused Analog I/O pins may be left open or terminated.
IN74HC4051
3
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE=GND,
Except Where Noted
V
CC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C to
-55°C
≤85
°C
≤125
°C
Unit
VIH Minimum High-Level
Input Voltage,
Channel-Select or
Enable Inputs
RON = Per Spec 2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low -Level
Input Voltage,
Channel-Select or
Enable Inputs
RON = Per Spec 2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
IIN Maximum Input
Leakage Current,
Channel-Select or
Enable Inputs
VIN=VCC or GND,
VEE=-6.0 V
6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent
Supply Current (per
Package)
Channel Select = VCC or GND
Enable = VCC or GND
VIS = VCC or GND
VIO= 0 V VEE = GND
VEE = - 6.0
6.0
6.0
2
8
20
80
40
160
µA
DC ELECTRICAL CHARACTERISTICS Analog Section
V
CC V
EE Guaranteed Limit
Symbol Parameter Test Conditions V V
25 °C to
-55°C
≤85
°C
≤125
°C
Unit
RON Maximum “ON”
Resistance
VIN=VIL or VIH
VIS = VCC or VEE
IS ≤ 2.0 mA(Figure 1)
4.5
4.5
6.0
0.0
-4.5
-6.0
190
120
100
240
150
125
280
170
140
Ω
V
IN=VIL or VIH
VIS = VCC or VEE
(Endpoints)
IS ≤ 2.0 mA(Figure 1)
4.5
4.5
6.0
0.0
-4.5
-6.0
150
100
80
190
125
100
230
140
115
∆RON Maximum Difference in
“ON” Resistance Between
Any Two Channels in the
Same Package
VIN=VIL or VIH
VIS = 1/2 (VCC- VEE)
IS ≤ 2.0 mA
4.5
4.5
6.0
0.0
-4.5
-6.0
30
12
10
35
15
12
40
18
14
Ω
IOFF Maximum Off- Channel
Leakage Current, Any
One Channel
VIN=VIL or VIH
VIO= VCC- VEE
Switch Off (Figure 2)
6.0 -6.0 0.1 0.5 1.0 µA
Maximum Off- Channel
Leakage Current,
Common Channel
VIN=VIL or VIH
VIO = VCC- VEE
Switch Off (Figure 3)
6.0 -6.0 0.2 2.0 4.0
ION Maximum On- Channel
Leakage Current,
Channel to Channel
VIN=VIL or VIH
Switch to Switch =
VCC- VEE (Figure 4)
6.0 -6.0 0.2 2.0 4.0 µA
IN74HC4051
4
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
V
CC Guaranteed Limit
Symbol Parameter V
25 °C
to
-55°C
≤85°C ≤125
°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Channel-
Select to Analog Output (Figures 8 and
9)
2.0
4.5
6.0
370
74
63
465
93
79
550
110
94
ns
tPLH,
tPHL
Maximum Propagation Delay , Analog
Input to Analog Output (Figures 10 and
11)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tPLZ,
tPHZ
Maximum Propagation Delay , Enable to
Analog Output (Figures 12 and 13)
2.0
4.5
6.0
290
58
49
364
73
62
430
86
73
ns
tPZL,
tPZH
Maximum Propagation Delay , Enable to
Analog Output (Figures 12 and 13)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
ns
CIN Maximum Input Capacitance, Channel-
Select or Enable Inputs
- 10 10 10 pF
CI/O Maximum Capacitance
Analog
I/O
All Switches
Off
- 35 35 35 pF
Common O/I - 130 130 130
Feedthrough - 1.0 1.0 1.0
Power Dissipation Capacitance (Per
Package) (Figure 14)
Typical @25°C,VCC=5.0 V,
VEE=0 V
CPD Used to determine the no-load dynamic
power consumption:
PD=CPDVCC2f+ICCVCC
45 pF
IN74HC4051
5
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)
V
CC V
EE Limit*
Symbol Parameter Test Conditions V V 25 °CUnit
BW Maximum On-
Channel
Bandwidth or
Minimum
Frequency
Response
(Figure 5)
fin=1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at
VOS
Increase fin Frequence Until dB
Meter
Reads -3 dB
RL =50 Ω, CL=10 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
80
80
80
MHz
- Off-Channel
Feedthrough
Isolation
(Figure 6)
fin= Sine Wave
Adjust fin Voltage to Obtain 0 dBm at
VIS
fin = 10 kHz, RL =600 Ω, CL=50 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
-50
-50
-50
dB
fin = 1.0 MHz, RL =50 Ω, CL=10 pF 2.25
4.50
6.00
-2.25
-4.50
-6.00
-40
-40
-40
- Feedthrough
Noise,
Channel
Select Input to
Common O/I
(Figure 7)
VIN≤ 1 Mhz Square Wave (tr = tf = 6
ns)
Adjust RL at Setup so that IS= 0 A
Enable = GND
RL =600 Ω, CL=50 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
25
105
135
mVP
P
RL =10 Ω, CL=10 pF 2.25
4.50
6.00
-2.25
-4.50
-6.00
35
145
190
THD Total
Harmonic
Distortion
(Figure 15)
fin= 1 kHz, RL =10 kΩ, CL=50 pF
THD = THDMeasured - THDSource
VIS =4.0 VPP sine wave
VIS =8.0 VPP sine wave
VIS =11.0 VPP sine wave
2.25
4.50
6.00
-2.25
-4.50
-6.00
0.10
0.08
0.05
%
* Limits not tested. Determined by design and verified by qualification.
Figure 1. On Resistance Test Set-Up
IN74HC4051
6
Figure 2. Maximum Off Channel Leakage
Current, Any One Channel, Test Set-UP
Figure 3. Maximum Off Channel Leakage Current,
Common Channel, Test Set-UP
Figure 4. Maximum On Channel Leakage
Current, Channel to Channel, Test Set-UP
* Includes all probe and jig capacitance.
Figure 5. Maximum On Channel Bandwidth,
Test Set-UP
* Includes all probe and jig capacitance.
Figure 6. Off Channel Feedthrough
Isolation, Test Set-UP
* Includes all probe and jig capacitance.
Figure 7.Feedthrough Noise, Channel Select to
Common Out, Test Set-UP
IN74HC4051
7
Figure 8. Switching Weveforms
* Includes all probe and jig capacitance.
Figure 9. Test Set-UP, Channel Select to Analog
Out
Figure 10. Switching Weveforms
* Includes all probe and jig capacitance.
Figure 11. Test Set-UP, Analog In to Analog Out
Figure 12. Switching Weveforms Figure 13. Test Set-UP, Enable to Analog Out
IN74HC4051
8
Figure 14. Power Dissipation
Capacitance, Test Set-Up
* Includes all probe and jig capacitance
Figure 15. Total Harmonic Distortion, Test Set-UP
EXPANDED LOGIC DIAGRAM
