Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
1
Smart Quad Low-Side Switch
Features Product Summary
• Short Circuit Protection
• Overtemperature Protection
• Overvoltage Protection
• 8 bit Serial Data Input and Diag-
nostic Output (SPI protocol)
• Direct Parallel Control of Four
Channels for PWM Applications
• Cascadable with Other Quad
Switches
• Low Quiescent Current
• µC Compatible Input
• Electostatic Discharge (ESD) Protection
• Green Product (RoHS compliant)
• AEC qualified
Application
• µC Compatible Power Switch for 12 V and 24 V Applications
• Switch for Automotive and Industrial System
• Solenoids, Relays and Resistive Loads
• Injectors
• Robotic controls
General Description
Quad Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and
four open drain DMOS output stages. The TLE 6220 GP is protected by embedded protection func-
tions and designed for automotive and industrial applications. The output stages can be controlled
direct in parallel for PWM applications (injector coils), or through serial control via the SPI. Therefore
the TLE 6220 GP is particularly suitable for engine management and powertrain systems.
Block Diagram
Supply voltage VS 4.5 – 5.5 V
Drain source voltage VDS(AZ) max 60 V
On resistance RON 0.32 Ω
Output current (all outp. ON equal) ID(NOM) 1 A
(individually) 3 A
PG-DSO-20
FAULT
RESET
CS
Output Stage
Output Control
Buffer
Serial Interface
SPI
LOGIC
SCLK
SI 8 4
GND
VS
SO
14
IN1
IN2
IN3
IN4 OUT1
OUT4
PRG
VBB
VS
as Ch. 1
as Ch. 1
as Ch. 1
8
GND
normal function
SCB / overload
open load
short to ground
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
2
Pin Description Pin Configuration (Top view)
Pin Symbol Function
1 GND Ground
2 IN2 Input Channel 2
3 OUT1 Power Output Channel 1
4 VS Supply Voltage
5
RESET
Reset
6
CS
Chip Select
7 PRG Program (inputs high or low active)
8 OUT2 Power Output Channel 2
9 IN1 Input Channel 1
10 GND Ground
11 GND Ground
12 IN4 Input Channel 4
13 OUT3 Power Output Channel 3
14
FAULT
General Fault Flag
15 SO Serial Data Output
16 SCLK Serial Clock
17 SI Serial Data Input
18 OUT4 Power Output Channel 4
19 IN3 Input Channel 3
20 GND Ground
Heat slug internally connected to ground pins
GND
1
•
20
GND
IN2
2 19
IN3
OUT1
3 18
OUT4
VS
4 17
SI
RESET
5 16
SCLK
CS
6 15
SO
PRG
7 14
FAULT
OUT2
8 13
OUT3
IN1
9 12
IN4
GND
10 11
GND
Power SO-20
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
3
Maximum Ratings for Tj = – 40°C to 150°C
Parameter Symbol Values Unit
Supply Voltage VS -0.3 ... +7 V
Continuous Drain Source Voltage (OUT1...OUT4) VDS 45 V
Input Voltage, All Inputs and Data Lines VIN - 0.3 ... + 7 V
Load Dump Protection VLoad Dump = UP+US; UP=13.5 V
With Automotive Injector Valve RL = 14 Ω
RI1)=2 Ω; td=400ms; IN = low or high
With RL= 6.8 Ω (ID = 2A)
RI=2 Ω; td=400ms; IN = low or high
VLoad Dump2)
62
52
V
Operating Temperature Range
Storage Temperature Range Tj
Tstg - 40 ... + 150
- 55 ... + 150 °C
Output Current per Channel (see el. characteristics) ID(lim) ID(lim) min A
Output Current per Channel @ TA = 25°C
(All 4 Channels ON; Mounted on PCB ) 3) ID 1 A
Output Clamping Energy
ID = 1A EAS 50 mJ
Power Dissipation (DC, mounted on PCB) @ TA = 25°C Ptot 3 W
Electrostatic Discharge Voltage (human body model)
according to MIL STD 883D, method 3015.7 and EOS/ESD
assn. standard S5.1 - 1993
VESD 2000 V
DIN Humidity Category, DIN 40 040 E
IEC Climatic Category, DIN IEC 68-1 40/150/56
Thermal resistance
junction – case (die soldered on the frame)
junction - ambient @ min. footprint
junction - ambient @ 6 cm2 cooling area
RthJC
RthJA
2
50
38
K/W
1) RI=internal resistance of the load dump test pulse generator LD200
2) VLoadDump is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839.
3) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output
current has to be calculated using RthJA according mounting conditions.
PCB with heat pipes,
backside 6 cm2 cooling area
Minimum footprint
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
4
Electrical Characteristics
Parameter and Conditions Symbol Values Unit
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified) min typ max
1. Power Supply, Reset
Supply Voltage4 VS 4.5 -- 5.5 V
Supply Current 5 IS -- 1 2 mA
Minimum Reset Duration
(After a reset all parallel inputs are ORed with the SPI
data bits)
tReset,min 10
µs
2. Power Outputs
ON Resistance VS = 5 V; ID = 1 A TJ = 25°C
TJ = 150°C RDS(ON) --
-- 0.32
-- 0.4
0.7 Ω
Output Clamping Voltage output OFF VDS(AZ) 45 53 60 V
Current Limit ID(lim) 3 4.5 6 A
Output Leakage Current VRESET = L ID(lkg) -- -- 10 µA
Turn-On Time ID = 1 A, resistive load tON -- 5 10 µs
Turn-Off Time ID = 1 A, resistive load tOFF -- 5 10 µs
3. Digital Inputs
Input Low Voltage VINL - 0.3 -- 1.0 V
Input High Voltage VINH 2.0 -- VS+0.3 V
Input Voltage Hysteresis VINHys 50 100 200 mV
Input Pull Down/Up Current (IN1 ... IN4) IIN(1..4) 20 50 100 µA
PRG,
RESET
Pull Up Current IIN(PRG,Res) 20 50 100 µA
Input Pull Down Current (SI, SCLK) IIN(SI,SCLK) 10 20 50 µA
Input Pull Up Current (
CS
) IIN(CS) 10 20 50 µA
4. Digital Outputs (SO,
FAULT
)
SO High State Output Voltage ISOH = 2 mA VSOH VS - 0.4
-- -- V
SO Low State Output Voltage ISOL = 2.5 mA VSOL -- -- 0.4 V
Output Tri-state Leakage Current
CS
= H, 0 ≤ VSO ≤ VS ISOlkg -10 0 10 µA
FAULT
Output Low Voltage IFAULT = 1.6 mA VFAULTL -- -- 0.4 V
Current Limitation; Overload Threshold Current ID(lim) 1...4 3 4.5 6 A
Overtemperature Shutdown Threshold
Hysteresis6 Tth(sd)
Thys 170
--
--
10 200
-- °C
K
4 For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched
off. This undervoltage reset gets active at VS = 3V (typ. value) and is guaranteed by design.
5 If Reset = L the supply current is reduced to typ. 20µA
6 This parameter will not be tested but guaranteed by design
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
5
Electrical Characteristics cont.
Parameter and Conditions Symbol Values Unit
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified) min typ max
5. Diagnostic Functions
Open Load Detection Voltage VDS(OL) VS -2.5
VS -2
V
S -1.3
V
Output Pull Down Current IPD(OL) 50 90 150 µA
Fault Delay Time td(fault) 50 110 200 µs
Short to Ground Detection Voltage VDS(SHG) VS –3.3
VS -2.9
V
S -2.5
V
Short to Ground Detection Current ISHG -50 -100 -150 µA
6. SPI-Timing
Serial Clock Frequency (depending on SO load) fSCK DC -- 5 MHz
Serial Clock Period (1/fclk) tp(SCK) 200 -- -- ns
Serial Clock High Time tSCKH 50 -- -- ns
Serial Clock Low Time tSCKL 50 -- -- ns
Enable Lead Time (falling edge of
CS
to rising edge of
CLK) tlead 250 -- -- ns
Enable Lag Time (falling edge of CLK to rising edge of
CS
)
tlag 250 --- -- ns
Data Setup Time (required time SI to falling of CLK) tSU 20 -- -- ns
Data Hold Time (falling edge of CLK to SI) tH 20 -- -- ns
Disable Time @ CL = 50 pF8 tDIS -- -- 150 ns
Transfer Delay Time7
(
CS
high time between two accesses) tdt 200 -- -- ns
Data Valid Time CL = 50 pF
CL = 100 pF8
CL = 220 pF8
tvalid --
--
--
--
--
--
110
120
150
ns
7 This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay
time has to be extended to the maximum fault delay time td(fault)max = 200µs.
8 This parameter will not be tested but guaranteed by design
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
6
Functional Description
The TLE 6220 GP is an quad-low-side power switch which provides a serial peripheral inter-
face (SPI) to control the 4 power DMOS switches, as well as diagnostic feedback. The power
transistors are protected against short to VBB, overload, overtemperature and against over-
voltage by an active zener clamp.
The diagnostic logic recognises a fault condition which can be read out via the serial diagnos-
tic output (SO).
Circuit Description
Power Transistor Protection Functions9)
Each of the four output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 3 A. The continuous current for each channel is 1A (all
channels ON; depending on cooling).
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protection
level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shut-
down with restart) to prevent critical chip temperatures.
SPI Signal Description
CS
- Chip Select. The system microcontroller selects the TLE 6220 GP by means of the
CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS
High to Low transition: - Diagnostic status information is transferred from the power
outputs into the shift register.
- Serial input data can be clocked in from then on.
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits.
CS
Low to High transition: - Transfer of SI bits from shift register into output buffers
- Reset of diagnosis register.
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of
CS
. When
CS
is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
9 )The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or permanently.
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
7
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE
6220 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select
CS
makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-
mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of one byte, made up of four control bits and four data bits. The con-
trol word is used to program the device, to operate it in a certain mode as well as providing
diagnostic information (see page 11). The four data bits contain the input information for the
four channels, and are high active.
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the
CS
pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET
- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip. As long as the re-
set pin is low the device is in low quiescent current mode and the supply current is reduced to
typ. 20µA.
Output Stage Control
The four outputs of the TLE 6220 GP can either be controlled in parallel (IN1...IN4), or via the
Serial Peripheral Interface (SPI).
Parallel Control
A Boolean operation (either AND or OR) is performed on each of the parallel inputs and re-
spective SPI data bits, in order to determine the states of the respective outputs. The type of
Boolean operation performed is programmed via the serial interface.
The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins
are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4
are switched OFF. PRG pin itself is internally pulled up when it is not connected.
PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 4 are high active
PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active.
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
8
Serial Control of the Outputs: SPI protocol
Each output is independently controlled by an output latch and a common reset line, which
disables all four outputs. The Serial Input (SI) is read on the falling edge of the serial clock. A
logic high input 'data bit' turns the respective output channel ON, a logic low 'data bit' turns it
OFF.
CS
must be low whilst shifting all the serial data into the device. A low-to-high transition
of
CS
transfers the serial data input bits to the output control buffer.
As mentioned above, the serial input byte consists of a 4 bit control word and a 4 bit data
word. Via the control word, the specific mode of the device is programmable.
MSB LSB
321321Bits DataBits Control
DDDDCCCC : Serial input byte
Five specific control words are recognised, having the following functions:
No. Serial Input Byte Function
1 LLLL XXXX Only 'Full Diagnosis' performed. No change to output states.
2 HHLL XXXX State of four parallel inputs and '1-bit Diagnosis' outputted.
3 HLHL XXXX Echo-function of SPI; SI direct connected to SO
4 LLHH DDDD IN1...4 and serial data bits 'OR'ed. 'Full Diagnosis' performed.
5 HHHH DDDD
IN1...4 and serial data bits 'AND'ed. 'Full Diagnosis' performed.
Note: 'X' means 'don't care', because this bit will be ignored
'D' represents the data bit, either being H (=ON) or L (=OFF)
1. LLLL XXXX - Diagnosis only
By clocking in this control byte, it is possible to get pure diagnostic information (two bits per
channel) in accordance with Figure 1 (page 11). The data bits are ignored, so that the state of
the outputs are not influenced. This command is only active once unless the next control com-
mand is again "Diagnosis only".
2. HHLL XXXX - Reading back of input, and ‘1-bit Diagnosis’
If the TLE 6220 GP is used as bare die in a hybrid application, it is necessary to know if
proper connections exist between the µC-port and parallel inputs. By entering ‘HHLL’ as the
control word, the first four bits of the SO give the state of the parallel inputs, depending on the
µC signals. By comparing the four IN-bits with the corresponding µC-port signal, the neces-
sary connection between the µC and the TLE 6220 can be verified - i.e. ‘read back of the in-
puts’.
The second 4-bit word fed out at the serial output contains ‘1-bit’ fault information of the out-
puts ( H = no fault, L = fault ). In the expression given below for the output byte, ‘FX’ is the
fault bit for channel X.
MSB LSB
IN4 IN3 IN2 IN1 F4 F3 F2 F1 : Serial Output byte
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
9
SI H H L L X X X X
SO H H H H H H H H
CS
CS
SI H H H H L H H L
SO IN4 IN3 IN2 IN1 F4 F3 F2 F1
SI command: No change of the
output state; reading back of
inputs and 1bit diagnosis
SO diagnosis: No fault, normal
function
CS
SI H H H H L L L L
SO H H H H H H H H
SI command: AND-Operation;
Ch1 and 4 OFF, Ch2 and 3 ON.
SO diagnosis: State of four parallel
inputs and 1 bit diagnosis performed
SI command: AND-Operation and
all channels OFF.
SO diagnosis: No fault, normal
function
3. HLHL XXXX - Echo-function of SPI
To check the proper function of the serial interface the TLE 6220 GP provides a "SPI Echo
Function". By entering HLHL as control word, SI and SO are connected during the next
CS
period. By comparing the bits clocked in with the serial output bits, the proper function of the
SPI interface can be verified. This internal loop is only closed once (for one
CS
period).
SI H L H L X X X X
SO H H H H L H H H
CS
CS
SI SO
SI command: No change of the
output states; Echo function of SPI
SO diagnosis: Open load condition
at channel 2, other channels ok.
SI word
Echo-function of SPI, i.e. SI
directly connected to SO.
SI information will be accepted
during this cycle and the
outputs set accordingly after
chip select rising edge
4. LLHH DDDD - OR operation, and ‘full diagnosis’
With LLHH as the control word, each of the input signals IN1...IN4 are 'OR'ed with the corre-
sponding data bits (DDDD).
≥ 1 Output
Driver
IN 1...4
Serial Input,
data bits 0...3
This OR operation enables the serial interface to switch the channel ON, even though the cor-
responding parallel input might be in the off state.
⇒ SPI Priority for ON-State
Also parallel control of the outputs is possible without an SPI input.
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
10
The OR-function is the default Boolean operation if the device restarts after a Reset, or when
the supply voltage is switched on for the first time.
If the OR operation is programmed it is latched until it is overwritten by the AND operation.
5. HHHH DDDD - AND operation, and ‘full diagnosis’
With HHHH as the control word, each of the input signals IN1...IN4 are 'AND'ed with the cor-
responding data bits (DDDD).
&Output
Driver
IN 1...4
Serial Input,
data bits 0...3
The AND operation implies that the output can be switched off by the SPI data bit input, even
if the corresponding parallel input is in the ON state.
⇒ SPI Priority for OFF-state
This also implies that the serial input data bit can only switch the output channel ON if the cor-
responding parallel input is in the ON state.
If the AND operation is programmed it is latched until it is overwritten by the OR operation.
Control words beside No. 1- 5
All control words except those for Diag Only, Read Back of Inputs, SPI echo, will be accepted
as an OR or an AND command with valid data bits depending on the boolean operation which
was programmed before.
Example 1:
LLHH HLLH: OR operation between parallel inputs and data bits, i.e channel 1 and 4 will be
switched on.
The next command is now: LHHH HHLH
LHHH as command word has no special meaning but it will be accepted as an OR operation
and the data bits will be ORed with the inputs and the outputs 1,3 and 4 will be switched on.
See above: 'If the OR operation is programmed it is latched until it is overwritten by the AND
operation.'
Example 2:
HHHH LLHL means: Data bits will be ANDed with the parallel inputs and the outputs switch
accordingly. Then HLLH HHLH is clocked in: AND was latched by the command before and is
now valid again by using the HLLH command word. So the data bits will be accepted and
again ANDed with the parallel input signals.
See above: 'If the AND operation is programmed it is latched until it is overwritten by the OR
operation.'
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
11
Diagnostics
FAULT
- Fault pin. There is a general fault pin (open drain) which shows a high to low transi-
tion as soon as an error occurs for any one of the four channels. This fault indication can be
used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called
after this fault indication. This saves processor time compared to a cyclic reading of the SO
information.
As soon as a fault occurs, the fault information is latched into the diagnosis register. A new
error will over-write the old error report. Serial data out pin (SO) is in a high impedance state
when
CS
is high. If
CS
receives a LOW signal, all diagnosis bits can be shifted out serially.
The rising edge of
CS
will reset all error registers.
Full Diagnosis
For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 1.
Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal
function.
Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current
limitation gets active, i.e. there is a overload, short to supply or overtemperature condition.
Open load: An open load condition is detected when the drain voltage decreases below 3 V
(typ.). LH bit combination is set.
Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current
exceeds 100 µA, short to ground is detected and the LL bit combination is set.
A definite distinction between open load and short to ground is guaranteed by design.
The standard way of obtaining diagnostic information is as follows:
Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs to
settle. Clock in the identical serial information once again - during this process the data com-
ing out at SO contains the bit combinations representing the diagnosis conditions as de-
scribed in Figure 1.
Diagnostic Serial OUT (SO)
HH Normal function
HL Overload, Shorted Load or Overtemperature
LH Open Load
LL Shorted to Ground
Ch.4
Ch.3
Ch.2
Ch.1
7 6 5 4 3 2 1 0
Figure 1: Two bits per channel diagnostic feedback
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
12
Timing Diagrams
Figure 2: Serial Interface
Figure 3: Input Timing Diagram
Figure 4:
SO Valid Time Waveforms Enable and Disable Time Waveforms
Data
Bits
674444 84444
Control
Bits
674444 84444
CS
SCLK
SI
OLD NEW
765 4 3 2 1 0
SO 765 4 3 2 1 0
MSB LSB
Outputs
tlead
tSCKH
0.2VS
tlag
tH
tSCKL
0.2 VS
tSU 0.7VS
0.2VS
CS
SCLK
SI
0.7VS tdt
0.7VS
tvalid
SCLK CS
SO
tDis
0.2 VS
SO
0.7 VS
0.7 VS
0.2 VS
SO 0.7 VS
0.2 VS
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
13
Figure 5: Power Outputs
Application Circuit
t
t
tON tOFF
80%
VDS
VIN
20%
OUT1
OUT2
OUT4
TLE
6220
GP
SI
SO
CLK
CS
VS
VS
RESET
GND
VBB
CLK
MTSR
MRST
P xy
µC
e.g. C166
IN1
IN2
IN3
IN4
FAULT
PRG
10k
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
14
Typical electrical Characteristics
Drain-Source on-resistance
RDS(ON) = f (Tj) ; Vs = 5V
Output Clamping Voltage
VDS(AZ) = f (Tj) ; Vs = 5V
Figure 6 : Typical ON Resistance versus Junction-Temperature
Channel 1-4
Figure 7 : Typical Clamp Voltage versus Junction-Temperature
Channel 1-4
Typical Drain- Source ON-Resistance
0,23
0,28
0,33
0,38
0,43
0,48
0,53
0,58
-50 -25 0 25 50 75 100 125 150 175
Tj[°C]
RDS(ON) [Ohm]
Channel 1-4
Typical Clamping Voltage
48
49
50
51
52
53
54
55
-50 -25 025 50 75 100 125 150 175
Tj[°C]
VDS (AZ) [V]
Channel 1-4
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
15
Parallel SPI Configuration
Engine Management Application
TLE 6230 GP in combination with TLE 6240 GP (16-fold switch) for relays and general purpose loads
and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous
loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16
can be controlled direct in parallel for PWM applications.
Daisy Chain Application TLE 6220 GP
4
SI
CLK
SO
4
SI
CLK
SO
CS
CS
MTSR
MRST
CLK
P x.y
P x.1-4
P x.y
P x.1-4
µC
C167
4 PWM
Channels
4 PWM
Channels
CS
Injector 1
Injector 2
Injector 3
Injector 4
TLE
6220 GP
Quad
TLE
6230 GP
Octal
8
SI
CLK
SO
CS
8 PWM
Channels
TLE
6240 GP
16-fold
P x.y
P x.1-8
CS
SI
CLK
SO
TLE
6220 GP
Quad
CS
SI
CLK
SO
TLE
6220 GP
Quad
CS
SI
CLK
SO
TLE
6220 GP
Quad
CS
Px.1
Px.2
µC
MTSR
MRST
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
16
Package and Ordering Code
(all dimensions in mm)
PG - DSO - 20
TLE 6220 GP
0.1
8°
1.3
1.2
-0.3
15.9
+/-0.15
A
2.8 8° 8°
8°
6.3
11
+/-0.15 1)
14.2
+/-0.3
1 10
1120
PIN 1 INDEX MARKING
1 x 45°
13.7
-0.2
9 x =11.431.27
1.27 0.25 AM
0.4
+0.13
3.2
+/-0.1
5.9
+/-0.1
15.74
+/- 0.1
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
17
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be com-
pliant with government regulations the device is available as a green product. Green products are
RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to
IPC/JEDEC J-STD-020).
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
18
Revision History
Version Date Changes
V2.1 ->
V2.2 18.11.2009 Package changed to PG-DSO-20
Ordering code removed
V2.0 ->
V2.1 20.04.2007 Ordering Code removed
Layout Changes
Correct green package name implemented P-DSO-20-12 à PG-DSO-
20-26
V1.1 ->
V2.0 20.05.2003 Changes to Green Product Version:
- AEC, RoHS Logo and Feature List content added
- Package Name P-DSO -> PGDSO
- Change History added
- Disclaimer re-newed
V1.1 28.08.2007 Initial Version of “grey” product
Data Sheet TLE 6220 GP
V2.2 Page 2009-11-18
19
Edition 2007-04-17
Published by
Infineon Technologies AG
81726 Munich, Germany
© 11/19/09 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or characteris-
tics. With respect to any examples or hints given herein, any typical values stated herein and/or any information
regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabili-
ties of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any
third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest In-
fineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body or to support and/or maintain and
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other per-
sons may be endangered.
