ST7LITE2 8-BIT MICROCONTROLLER WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI Memories - 8 Kbytes single voltage Flash Program memory with read-out protection, In-Circuit Programming and In-Application programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55C. - 384 bytes RAM Clock, Reset and Supply Management - Enhanced reset system - Enhanced low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures - Clock sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock - Internal 32-MHz input clock for Auto-reload timer - Optional x4 or x8 PLL for 4 or 8 MHz internal clock - Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt I/O Ports - Up to 15 multifunctional bidirectional I/O lines - 7 high sink outputs 4 Timers - Configurable Watchdog Timer - Two 8-bit Lite Timers with prescaler, 1 realtime base and 1 input capture - One 12-bit Auto-reload Timer with 4 PWM outputs, input capture and output compare functions Device Summary Features Program memory - bytes RAM (stack) - bytes Data EEPROM - bytes Peripherals ST7LITE20 Lite Timer with Watchdog, Autoreload Timer, SPI, 10-bit ADC with Op-Amp Operating Supply CPU Frequency Operating Temperature Packages Up to 8Mhz (w/ ext OSC up to 16MHz) DIP20 SO20 300" 1 Communication Interface - SPI synchronous serial interface Interrupt Management - 10 interrupt vectors plus TRAP and RESET - 15 external interrupt lines (on 4 vectors) A/D Converter - 7 input channels - Fixed gain Op-amp - 13-bit resolution for 0 to 430 mV (@ 5V VDD) - 10-bit resolution for 430 mV to 5V (@ 5V VDD) Instruction Set - 8-bit data manipulation - 63 basic instructions with illegal opcode detection - 17 main addressing modes - 8 x 8 unsigned multiply instructions Development Tools - Full hardware/software development package - DM (Debug Module) ST7LITE25 ST7LITE29 8K 384 (128) 256 Lite Timer with Watchdog, Autoreload Timer with 32-MHz input clock, SPI, 10-bit ADC with Op-Amp 2.4V to 5.5V Up to 8Mhz (w/ ext OSC up to 16MHz and int 1MHz RC 1% PLLx8/4MHz) -40C to +85C SO20 300", DIP20 Rev. 4 July 2006 1/133 1 Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 133 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.6 10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2/133 1 Table of Contents 10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2 12-BIT AUTORELOAD TIMER 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 113 13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 15 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 124 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16.2 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16.3 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . 130 16.4 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 130 3/133 Table of Contents 16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 130 16.6 USING PB4 AS EXTERNAL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16.7 TIMEBASE 2 INTERRUPT IN SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet Please also pay special attention to the Section "IMPORTANT NOTES" on page 130. 133 4/133 ST7LITE2 1 INTRODUCTION The ST7LITE2 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE2 features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and InApplication Programming (IAP) capability. Under software control, the ST7LITE2 device can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in section 13 on page 91. The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual. Figure 1. General Block Diagram Int. 1% RC 1MHz PLL 8MHz -> 32MHz 12-Bit Auto-Reload TIMER 2 PLL x 8 or PLL X4 CLKIN 8-Bit LITE TIMER 2 /2 OSC1 OSC2 Ext. OSC 1MHz to 16MHz Internal CLOCK VDD VSS RESET POWER SUPPLY CONTROL 8-BIT CORE ALU PORT B ADDRESS AND DATA BUS LVD PORT A PA7:0 (8 bits) PB6:0 (7 bits) ADC + OpAmp SPI Debug Module PROGRAM MEMORY (8K Bytes) DATA EEPROM (256 Bytes) RAM (384 Bytes) WATCHDOG 5/133 1 ST7LITE2 2 PIN DESCRIPTION Figure 2. 20-Pin SO Package Pinout VSS 1 20 OSC1/CLKIN VDD RESET 2 19 3 18 OSC2 PA0 (HS)/LTIC SS/AIN0/PB0 4 SCK/AIN1/PB1 5 MISO/AIN2/PB2 6 15 PA3 (HS)/ATPWM1 MOSI/AIN3/PB3 7 14 PA4 (HS)/ATPWM2 CLKIN/AIN4/PB4 8 13 AIN5/PB5 AIN6/PB6 9 12 PA5 (HS)/ATPWM3/ICCDATA PA6/MCO/ICCCLK/BREAK 10 11 PA7(HS) ei0 ei3 ei2 ei1 17 PA1 (HS)/ATIC 16 PA2 (HS)/ATPWM0 (HS) 20mA high sink capability eix associated external interrupt vector Figure 3. 20-Pin DIP Package Pinout MISO/AIN2/PB2 1 ei3 ei3 20 SCK/AIN1/PB1 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 2 19 3 18 SS/AIN0/PB0 RESET AIN5/PB5 4 17 VDD AIN6/PB6 5 16 VSS PA7(HS) 6 15 OSC1/CLKIN ei2 MCO/ICCCLK/BREAK/PA6 7 14 OSC2 ATPWM3/ICCDATA/PA5(HS) 8 13 ATPWM2/PA4(HS) ATPWM1/PA3(HS) 9 12 PA0(HS)/LTIC PA1(HS)/ATIC 11 PA2(HS)/ATPWM0 10 ei1 ei0 ei0 (HS) 20mA high sink capability eix associated external interrupt vector 6/133 1 ST7LITE2 PIN DESCRIPTION (Cont'd) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: - Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog - Output: OD = open drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 1. Device Pin Description Port / Control PP OD Output ana int wpu Input float Output Pin Name Input Level Type DIP20 SO20 Pin No. Main Function (after reset) Alternate Function 1 16 VSS S Ground 2 17 VDD S Main power supply 3 18 RESET I/O CT 4 19 PB0/AIN0/SS I/O X CT X X X X X ei3 Top priority non maskable interrupt (active low) ADC Analog Input 0 or SPI Slave Select (active low) Caution: No negative current Port B0 injection allowed on this pin. For details, refer to section 13.2.2 on page 92 ADC Analog Input 1 or SPI Serial Clock Caution: No negative current Port B1 injection allowed on this pin. For details, refer to section 13.2.2 on page 92 ADC Analog Input 2 or SPI Port B2 Master In/ Slave Out Data ADC Analog Input 3 or SPI Port B3 Master Out / Slave In Data ADC Analog Input 4 or ExterPort B4 nal clock input 5 20 PB1/AIN1/SCK I/O CT X X X X 6 1 PB2/AIN2/MISO I/O CT X X X X 7 2 PB3/AIN3/MOSI I/O CT X X X X 8 3 PB4/AIN4/CLKIN I/O CT X X X X 9 4 PB5/AIN5 I/O CT X X X X Port B5 ADC Analog Input 5 10 5 PB6/AIN6 I/O CT X X X X Port B6 ADC Analog Input 6 11 6 PA7 I/O CT HS X X Port A7 X ei2 ei1 7/133 1 ST7LITE2 Port / Control PP OD Output ana int wpu Input float Output Type DIP20 SO20 Pin Name Input Level Pin No. Main Function (after reset) Alternate Function Main Clock Output or In Circuit Communication Clock or External BREAK 12 7 PA6 /MCO/ ICCCLK/BREAK I/O 13 8 PA5 /ATPWM3/ ICCDATA I/O CT HS X CT X ei1 X X Port A6 X X Port A5 ei1 14 9 PA4/ATPWM2 I/O CT HS X X X Port A4 Auto-Reload Timer PWM2 15 10 PA3/ATPWM1 I/O CT HS X X X Port A3 Auto-Reload Timer PWM1 16 11 PA2/ATPWM0 I/O CT HS X X X Port A2 Auto-Reload Timer PWM0 ei0 17 12 PA1/ATIC I/O CT HS X X X Port A1 Auto-Reload Timer Input Capture 18 13 PA0/LTIC I/O CT HS X X X Port A0 Lite Timer Input Capture 19 14 OSC2 O Resonator oscillator inverter output 20 15 OSC1/CLKIN I Resonator oscillator inverter input or External clock input 8/133 1 Caution: During normal operation this pin must be pulledup, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up Auto-Reload Timer PWM3 or In Circuit Communication Data ST7LITE2 3 REGISTER & MEMORY MAP As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh. The highest address bytes contain the user reset and interrupt vectors. The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7 ad- dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). The size of Flash Sector 0 and other device options are configurable by Option byte (refer to section 15.1 on page 122). IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device. Figure 4. Memory Map 0080h Short Addressing RAM (zero page) 0000h 007Fh 0080h HW Registers (see Table 2) 00FFh 0100h 16-bit Addressing RAM RAM (384 Bytes) 017Fh 0180h Reserved 01FFh 01FFh 0200h 128 Bytes Stack 0FFFh 1000h 10FFh 1100h 1000h Data EEPROM (256 Bytes) 1001h Reserved DFFFh E000h E000h Flash Memory (8K) FFDFh FFE0h FFFFh 8K FLASH PROGRAM MEMORY FBFFh FC00h FFFFh Interrupt & Reset Vectors (see Table 5) RCCR0 RCCR1 see section 7.1 on page 23 7 Kbytes SECTOR 1 1 Kbyte SECTOR 0 FFDEh FFDFh RCCR0 RCCR1 see section 7.1 on page 23 9/133 1 ST7LITE2 Table 2. Hardware Register Map Address Block Register Label 0000h 0001h 0002h Port A PADR PADDR PAOR Port A Data Register Port A Data Direction Register Port A Option Register FFh1) 00h 40h R/W R/W R/W 0003h 0004h 0005h Port B PBDR PBDDR PBOR Port B Data Register Port B Data Direction Register Port B Option Register FFh 1) 00h 00h R/W R/W R/W2) 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h Reset Status Remarks Reserved Area (2 bytes) LITE TIMER 2 AUTORELOAD TIMER 2 LTCSR2 LTARR LTCNTR LTCSR1 LTICR Lite Timer Control/Status Register 2 Lite Timer Auto-reload Register Lite Timer Counter Register Lite Timer Control/Status Register 1 Lite Timer Input Capture Register 00h 00h 00h 0X00 0000h 00h R/W R/W Read Only R/W Read Only ATCSR CNTRH CNTRL ATRH ATRL PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L ATICRH ATICRL TRANCR BREAKCR Timer Control/Status Register Counter Register High Counter Register Low Auto-Reload Register High Auto-Reload Register Low PWM Output Control Register PWM 0 Control/Status Register PWM 1 Control/Status Register PWM 2 Control/Status Register PWM 3 Control/Status Register PWM 0 Duty Cycle Register High PWM 0 Duty Cycle Register Low PWM 1 Duty Cycle Register High PWM 1 Duty Cycle Register Low PWM 2 Duty Cycle Register High PWM 2 Duty Cycle Register Low PWM 3 Duty Cycle Register High PWM 3 Duty Cycle Register Low Input Capture Register High Input Capture Register Low Transfer Control Register Break Control Register 0X00 0000h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 01h 00h R/W Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W 0023h to 002Dh Reserved area (11 bytes) 002Eh WDG WDGCR Watchdog Control Register 7Fh R/W 0002Fh FLASH FCSR Flash Control/Status Register 00h R/W 00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W 0031h 0032h 0033h SPI SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register SPI Control Status Register xxh 0xh 00h R/W R/W R/W 0034h 0035h 0036h ADC ADCCSR ADCDRH ADCDRL A/D Control Status Register A/D Data Register High A/D Amplifier Control/Data Low Register 00h xxh 0xh R/W Read Only R/W 10/133 1 Register Name ST7LITE2 Address Block 0037h ITC 0038h MCC 0039h 003Ah Clock and Reset Register Label 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h to 007Fh Remarks External Interrupt Control Register 00h R/W MCCSR Main Clock Control/Status Register 00h R/W RCCR SICSR RC oscillator Control Register System Integrity Control/Status Register FFh 0000 0XX0h R/W R/W 0Ch R/W Reserved area (1 byte) ITC EISR 003Dh to 0048h 0049h 004Ah Reset Status EICR 003Bh 003Ch Register Name External Interrupt Selection Register Reserved area (12 bytes) AWU AWUPR AWUCSR AWU Prescaler Register AWU Control/Status Register FFh 00h R/W R/W DM3) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W Reserved area (47 bytes) Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ICC reference manual. 11/133 1 ST7LITE2 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features ICP (In-Circuit Programming) IAP (In-Application Programming) ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Sector 0 size configurable by option byte Read-out and write protection 4.3 PROGRAMMING MODES The ST7 can be programmed in three different ways: - Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased. - In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board. - In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing 12/133 1 the device from the application board and while the application is running. 4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. - Download ICP Driver code in RAM from the ICCDATA pin - Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.). IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. ST7LITE2 FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC interface A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the CLKIN/PB4 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC1 and OSC2 grounded in this case. 5. With any programming tool, while the ICP option is disabled, the external clock has to be provided on PB4. Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are: - RESET: device reset - VSS: device power supply ground - ICCCLK: ICC output serial clock pin - ICCDATA: ICC input serial data pin - CLKIN/PB4: main clock input for external source - VDD: application board power supply (optional, see Note 3) Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). Figure 5. Typical ICC Interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE (See Note 3) OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION BOARD APPLICATION RESET SOURCE See Note 2 APPLICATION POWER SUPPLY ICCDATA ICCCLK ST7 RESET CLKIN/PB4 (See Note 5) VDD See Note 1 and Caution APPLICATION I/O 13/133 1 ST7LITE2 FLASH PROGRAM MEMORY (Cont'd) 4.5 Memory Protection There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read-out Protection Read-out protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E2 memory are protected. In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E2 memory are automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: - In Flash devices it is enabled and removed through the FMP_R bit in the option byte. - In ROM devices it is enabled by mask option specified in the Option List. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E2 data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. 14/133 1 Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) 7 0 0 0 0 0 0 OPT LAT PGM Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically. ST7LITE2 5 DATA EEPROM 5.1 INTRODUCTION 5.2 MAIN FEATURES The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Up to 32 Bytes programmed in the same cycle EEPROM mono-voltage (charge pump) Chained erase and programming cycles Internal control of the global programming cycle duration WAIT mode management Read-out protection Figure 6. EEPROM Block Diagram HIGH VOLTAGE PUMP EECSR 0 0 0 ADDRESS DECODER 0 0 4 0 E2LAT E2PGM EEPROM ROW MEMORY MATRIX DECODER (1 ROW = 32 x 8 BITS) 128 4 128 DATA 32 x 8 BITS MULTIPLEXER DATA LATCHES 4 ADDRESS BUS DATA BUS 15/133 1 ST7LITE2 DATA EEPROM (Cont'd) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes. Read Operation (E2LAT=0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. On this device, Data EEPROM can also be used to execute machine code. Take care not to write to the Data EEPROM while executing from it. This would result in an unexpected code being executed. Write Operation (E2LAT=1) To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the 32 data latches according to its address. When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change. At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously. Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data. This note is illustrated by the Figure 9. Figure 7. Data EEPROM Programming Flowchart READ MODE E2LAT=0 E2PGM=0 READ BYTES IN EEPROM AREA WRITE MODE E2LAT=1 E2PGM=0 WRITE UP TO 32 BYTES IN EEPROM AREA (with the same 11 MSB of the address) START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set by software) 0 CLEARED BY HARDWARE 16/133 1 E2LAT 1 ST7LITE2 DATA EEPROM (Cont'd) Figure 8. Data E2PROM Write Operation Row / Byte ROW DEFINITION 0 1 2 3 ... 30 31 Physical Address 0 00h...1Fh 1 20h...3Fh ... Nx20h...Nx20h+1Fh N Read operation impossible Byte 1 Byte 2 Byte 32 Read operation possible Programming cycle PHASE 1 PHASE 2 Writing data latches Waiting E2PGM and E2LAT to fall E2LAT bit Set by USER application Cleared by hardware E2PGM bit Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 17/133 1 ST7LITE2 DATA EEPROM (Cont'd) 5.4 POWER SAVING MODES 5.5 ACCESS ERROR HANDLING Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. If a read access occurs while E2LAT=1, then the data bus will not be driven. If a write access occurs while E2LAT=0, then the data on the bus will not be latched. If a programming cycle is interrupted (by a RESET action), the memory data will not be guaranteed. Active-Halt mode Refer to Wait mode. Halt mode The DATA EEPROM immediately enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. 5.6 Data EEPROM Read-out Protection The read-out protection is enabled through an option bit (see section 15.1 on page 122). When this option is selected, the programs and data stored in the EEPROM memory are protected against read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically erased. Note: Both Program Memory and data EEPROM are protected using the same option bit. Figure 9. Data EEPROM programming cycle READ OPERATION NOT POSSIBLE READ OPERATION POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE OF DATA LATCHES WRITE CYCLE tPROG LAT PGM 18/133 1 ST7LITE2 DATA EEPROM (Cont'd) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EECSR) Read/Write Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 E2LAT E2PGM Bit 0 = E2PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: if the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared. 0: Read mode 1: Write mode Table 3. DATA EEPROM Register Map and Reset Values Address (Hex.) 0030h Register Label 7 6 5 4 3 2 1 0 0 0 0 0 0 0 E2LAT 0 E2PGM 0 EECSR Reset Value 19/133 1 ST7LITE2 6 CENTRAL PROCESSING UNIT 6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt 6.3 CPU REGISTERS The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). Figure 10. CPU Registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh 15 PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 1 1 1 H I 0 N Z C CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 20/133 1 ST7LITE2 CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx 7 1 0 1 1 H I N Z because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. C The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. 21/133 1 ST7LITE2 CPU REGISTERS (Cont'd) STACK POINTER (SP) Read/Write Reset Value: 01FFh 15 0 8 0 0 0 0 0 0 7 1 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. Figure 11. Stack Manipulation Example CALL Subroutine PUSH Y Interrupt Event POP Y RET or RSP IRET @ 0180h SP SP CC A 1 CC A X X X PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL Stack Higher Address = 01FFh Stack Lower Address = 0180h 22/133 SP PCH SP @ 01FFh Y CC A SP SP ST7LITE2 7 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. Main features Clock Management - 1 MHz internal RC oscillator (enabled by option byte, available on ST7LITE25 and ST7LITE29 devices only) - 1 to 16 MHz or 32kHz External crystal/ceramic resonator (selected by option byte) - External Clock Input (enabled by option byte) - PLL for multiplying the frequency by 8 or 4 (enabled by option byte) - For clock ART counter only: PLL32 for multiplying the 8 MHz frequency by 4 (enabled by option byte). The 8 MHz input frequency is mandatory and can be obtained in the following ways: -1 MHz RC + PLLx8 -16 MHz external clock (internally divided by 2) -2 MHz. external clock (internally divided by 2) + PLLx8 -Crystal oscillator with 16 MHz output frequency (internally divided by 2) Reset Sequence Manager (RSM) System Integrity Management (SI) - Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) - Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (enabled by option byte) 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V-5.5V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a calibration value in the RCCR (RC Control Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3 and 5V VDD supply voltages at 25C, as shown in the following table. RCCR Conditions VDD=5V RCCR0 TA=25C fRC=1MHz VDD=3V RCCR1 TA=25C fRC=700KHz ST7LITE29 ST7LITE25 Address Address 1000h and FFDEh FFDEh 1001h and FFDFh FFDFh Note: - See "ELECTRICAL CHARACTERISTICS" on page 91. for more information on the frequency and accuracy of the RC oscillator. - To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. - These two bytes are systematically programmed by ST, including on FASTROM devices. Consequently, customers intending to use FASTROM service must not use these two bytes. - RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset after it has been set. See "Read-out Protection" on page 14. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal. 7.2 PHASE LOCKED LOOP The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor of 4 or 8 is selected by 2 option bits. - The x4 PLL is intended for operation with VDD in the 2.4V to 3.3V range - The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range Refer to Section 15.1 for the option byte description. If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1MHz. If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock. 23/133 1 ST7LITE2 PHASE LOCKED LOOP (Cont'd) Figure 12. PLL Output Frequency Timing Diagram LOCKED bit set 4/8 x input freq. tSTAB 7.3 REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0000 (00h) 7 Output freq. 0 0 0 0 0 0 0 MCO SMS tLOCK Bits 7:2 = Reserved, must be kept cleared. tSTARTUP t When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP. When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of tSTAB (see Figure 12 and 13.3.4 Internal RC Oscillator and PLL) Refer to section 7.6.4 on page 33 for a description of the LOCKED bit in the SICSR register. Bit 1 = MCO Main Clock Out enable This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled. Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. 0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32) RC CONTROL REGISTER (RCCR) Read / Write Reset Value: 1111 1111 (FFh) 7 0 CR70 CR60 CR50 CR40 CR30 CR20 CR10 CR0 Bits 7:0 = CR[7:0] RC Oscillator Frequency Adjustment Bits These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h. 24/133 1 ST7LITE2 Figure 13. Clock Management Block Diagram CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 fCPU Tunable 1% RC Oscillator RCCR PLL 8MHz -> 32MHz OSC,PLLOFF, OSCRANGE[2:0] Option bits 12-BIT AT TIMER 2 RC OSC PLLx4x8 CLKIN CLKIN CLKIN CLKIN /OSC1 OSC2 OSC 1-16 MHZ or 32kHz PLL 1MHz -> 8MHz PLL 1MHz -> 4MHz /2 DIVIDER OSC fOSC CLKIN/2 CLKIN/2 OSC/2 /2 DIVIDER OSC,PLLOFF, OSCRANGE[2:0] Option bits 8-BIT LITE TIMER 2 COUNTER fOSC /32 DIVIDER fOSC/32 fOSC 1 0 fLTIMER (1ms timebase @ 8 MHz fOSC) fCPU TO CPU AND PERIPHERALS MCO SMS MCCSR fCPU MCO 25/133 1 ST7LITE2 7.4 MULTI-OSCILLATOR (MO) 26/133 1 External Clock Hardware Configuration Crystal/Ceramic Resonators External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Note: when the Multi-Oscillator is not used, PB4 is selected by default as external clock. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1 on page 122 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Internal RC Oscillator In this mode, the tunable 1%RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground. Table 4. ST7 Clock Sources Internal RC Oscillator or External Clock on PB4 The main clock of the ST7 can be generated by four different source types coming from the multioscillator block (1 to 16MHz or 32kHz): an external source 5 crystal or ceramic resonator oscillators an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details. ST7 OSC1 OSC2 EXTERNAL SOURCE ST7 OSC1 CL1 OSC2 LOAD CAPACITORS ST7 OSC1 OSC2 CL2 ST7LITE2 7.5 RESET SEQUENCE MANAGER (RSM) 7.5.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 88 for further details. These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 14: Active Phase depending on the RESET source 256 or 4096 CPU clock cycle delay (see table below) RESET vector fetch The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte: Clock Source Internal RC Oscillator External clock (connected to CLKIN pin) External Crystal/Ceramic Oscillator (connected to OSC1/OSC2 pins) The RESET vector fetch phase duration is 2 clock cycles. If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP (see Figure 12). Figure 14. RESET Sequence Phases RESET Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR 7.5.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. CPU clock cycle delay 256 256 4096 Figure 15. Reset Block Diagram VDD RON RESET INTERNAL RESET Filter PULSE GENERATOR WATCHDOG RESET ILLEGAL OPCODE RESET 1) LVD RESET Note 1: See "Illegal Opcode Reset" on page 88. for more details on illegal opcode reset conditions. 27/133 1 ST7LITE2 RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 7.5.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 7.5.4 Internal Low Voltage Detector (LVD) RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 16. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. 7.5.5 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 16. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 16. RESET Sequences VDD VIT+(LVD) VIT-(LVD) LVD RESET RUN EXTERNAL RESET RUN ACTIVE PHASE ACTIVE PHASE WATCHDOG RESET RUN ACTIVE PHASE RUN tw(RSTL)out th(RSTL)in EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH 28/133 1 ST7LITE2 7.6 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 88 for further details. 7.6.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VIT+(LVD)when VDD is rising - VIT-(LVD) when VDD is falling The LVD function is illustrated in Figure 17. The voltage threshold can be configured by option byte to be low, medium or high. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: - under full software control - in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be selected by option byte. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 84 on page 112 and note 4. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. Figure 17. Low Voltage Detector vs Reset VDD Vhys VIT+(LVD) VIT-(LVD) RESET 29/133 1 ST7LITE2 Figure 18. Reset and Supply Management Block Diagram WATCHDOG STATUS FLAG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) AVD Interrupt Request SICSR 0 0 0 WDGRF LOCKED LVDRF AVDF AVDIE LOW VOLTAGE VSS DETECTOR VDD (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) 30/133 1 ST7LITE2 SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD functions only if the LVD is en- abled through the option byte. 7.6.2.1 Monitoring the VDD Main Supply The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see section 15.1 on page 122). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(LVD) or VIT-(AVD) threshold (AVDF bit is set). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 19. Figure 19. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset) Vhyst VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD) AVDF bit 0 1 RESET 1 0 AVD INTERRUPT REQUEST IF AVDIE bit = 1 INTERRUPT Cleared by reset INTERRUPT Cleared by hardware LVD RESET 31/133 1 ST7LITE2 SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.3 Low Power Modes Mode WAIT HALT Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. The AVD remains active. 7.6.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is 32/133 1 set and the interrupt mask in the CC register is reset (RIM instruction). Interrupt Event AVD event Enable Event Control Flag Bit Exit from Wait Exit from Halt AVDF Yes No AVDIE ST7LITE2 SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generatReset Value: 0000 0xx0 (0xh) ed by the LVD block. It is set by hardware (LVD reset) and cleared by software (by reading). When 7 0 the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. WDG 0 0 0 RF LOCKED LVDRF AVDF AVDIE Bit 7:5 = Reserved, must be kept cleared. Bit 4 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table. RESET Sources LVDRF WDGRF External RESET pin Watchdog LVD 0 0 1 0 1 X Bit 3 = LOCKED PLL Locked Flag This bit is set and cleared by hardware. It is set automatically when the PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure 19 and to Section 7.6.2.1 for additional details. 0: VDD over AVD threshold 1: VDD under AVD threshold Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not. 33/133 1 ST7LITE2 8 INTERRUPTS The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 20. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - The I bit of the CC register is set to prevent additional interrupts. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 34/133 1 8.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 20. 8.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 8.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: - The I bit of the CC register is cleared. - The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: - Writing "0" to the corresponding bit in the status register or - Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed. ST7LITE2 INTERRUPTS (Cont'd) Figure 20. Interrupt Processing Flowchart FROM RESET I BIT SET? N N Y INTERRUPT PENDING? Y FETCH NEXT INSTRUCTION N IRET? Y STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR EXECUTE INSTRUCTION RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT Table 5. Interrupt Mapping N Source Block RESET Description Reset TRAP Software Interrupt 0 AWU Auto Wake Up Interrupt 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 3 ei2 External Interrupt 2 ei3 External Interrupt 3 4 5 LITE TIMER LITE TIMER RTC2 interrupt 6 7 8 10 12 13 N/A Exit Exit Priority from from Order HALT or ACTIVE AWUFH -HALT Highest Priority AWUCSR yes yes AT TIMER LITE TIMER SPI AVD interrupt yes1) FFFAh-FFFBh FFF8h-FFF9h N/A yes no FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h LTCSR2 no FFF0h-FFF1h FFEEh-FFEFh SICSR AT TIMER Overflow Interrupt ATCSR LITE TIMER Input Capture Interrupt LITE TIMER RTC1 Interrupt SPI Peripheral Interrupts FFFEh-FFFFh FFFCh-FFFDh FFECh-FFEDh no AT TIMER Output Compare Interrupt PWMxCSR or Input Capture Interrupt or ATCSR Not usedNot used Address Vector no Not used SI 9 11 Register Label no FFEAh-FFEBh yes FFE8h-FFE9h LTCSR no FFE6h-FFE7h LTCSR yes FFE4h-FFE5h SPICSR Lowest Priority yes no FFE2h-FFE3h FFE0h-FFE1h Note 1: This interrupt exits the MCU from "Auto Wake-up from Halt" mode only. 35/133 1 ST7LITE2 INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 IS30 IS21 IS20 IS11 IS10 IS01 0 7 IS00 ei31 Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table 6. Bit 5:4 = IS2[1:0] ei2 sensitivity These bits define the interrupt sensitivity for ei2 (Port B3) according to Table 6. Bit 3:2 = IS1[1:0] ei1 sensitivity These bits define the interrupt sensitivity for ei1 (Port A7) according to Table 6. Bit 1:0 = IS0[1:0] ei0 sensitivity These bits define the interrupt sensitivity for ei0 (Port A0) according to Table 6. Notes: 1.These 8 bits can be written only when the I bit in the CC register is set. 2. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to section "External Interrupt Function" on page 46. Table 6. Interrupt Sensitivity Bits ISx1 ISx0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge 36/133 1 0 ei30 ei21 ei20 ei11 ei10 ei01 ei00 Bit 7:6 = ei3[1:0] ei3 pin selection These bits are written by software. They select the Port B I/O pin used for the ei3 external interrupt according to the table below. External Interrupt I/O pin selection ei31 ei30 I/O Pin 0 0 PB0 1) 0 1 PB1 1 0 PB2 Note: 1. Reset State Bits 5:4 = ei2[1:0] ei2 pin selection These bits are written by software. They select the Port B I/O pin used for the ei2 external interrupt according to the table below. External Interrupt I/O pin selection ei21 ei20 I/O Pin 0 0 PB3 1) 0 1 PB4 2) 1 0 PB5 1 1 PB6 External Interrupt Sensitivity 0 . EXTERNAL INTERRUPT SELECTION REGISTER (EISR) Read/Write Reset Value: 0000 1100 (0Ch) Notes: 1. Reset State 2. PB4 cannot be used as an external interrupt in HALT mode. ST7LITE2 INTERRUPTS (Cont'd) Bit 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt according to the table below. External Interrupt I/O pin selection ei11 ei10 I/O Pin 0 0 PA4 0 1 PA5 1 0 PA6 1 1 PA7* * Reset State Port A I/O pin used for the ei0 external interrupt according to the table below. External Interrupt I/O pin selection ei01 ei00 I/O Pin 0 0 PA0 * 0 1 PA1 1 0 PA2 1 1 PA3 * Reset State Bits 1:0 = Reserved. Bits 1:0 = ei0[1:0] ei0 pin selection These bits are written by software. They select the 37/133 1 ST7LITE2 9 POWER SAVING MODES 9.1 INTRODUCTION 9.2 SLOW MODE To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see Figure 21): Slow Wait (and Slow-Wait) Active Halt Auto Wake up From Halt (AWUFH) Halt After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode. In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode. Figure 22. SLOW Mode Clock Transition fOSC/32 fOSC fCPU Figure 21. Power Saving Mode Transitions fOSC High SMS RUN NORMAL RUN MODE REQUEST SLOW WAIT SLOW WAIT ACTIVE HALT AUTO WAKE UP FROM HALT HALT Low POWER CONSUMPTION 38/133 1 ST7LITE2 POWER SAVING MODES (Cont'd) 9.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 23. Figure 23. WAIT Mode Flow-chart WFI INSTRUCTION OSCILLATOR PERIPHERALS CPU I BIT ON ON OFF 0 N RESET Y N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 0 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BIT ON ON ON X 1) FETCH RESET VECTOR OR SERVICE INTERRUPT Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 39/133 1 ST7LITE2 POWER SAVING MODES (Cont'd) 9.4 HALT MODE Figure 25. HALT Mode Flow-chart The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when ACTIVE-HALT is disabled (see section 9.5 on page 41 for more details) and when the AWUEN bit in the AWUCSR register is cleared. The MCU can exit HALT mode on reception of either a specific interrupt (see Table 5, "Interrupt Mapping," on page 35) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 15.1 on page 122 for more details). HALT 256 OR 4096 CPU CYCLE DELAY HALT INSTRUCTION [Active Halt disabled] 40/133 1 ENABLE WDGHALT 1) WATCHDOG DISABLE 0 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I BIT 0 N N RESET Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON X 4) 256 OR 4096 CPU CLOCK CYCLE DELAY5) OSCILLATOR PERIPHERALS CPU I BIT ON ON ON X 4) FETCH RESET VECTOR OR SERVICE INTERRUPT Figure 24. HALT Timing Overview RUN HALT INSTRUCTION (Active Halt disabled) (AWUCSR.AWUEN=0) RUN RESET OR INTERRUPT FETCH VECTOR Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 5 Interrupt Mapping for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared whenthe CC register is popped. 5. If the PLL is enabled by option byte, it outputs the clock after a delay of tSTARTUP (see Figure 12). ST7LITE2 POWER SAVING MODES (Cont'd) 9.4.1 Halt Mode Recommendations - Make sure that an external event is available to wake up the microcontroller from Halt mode. - When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. - For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. - The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in program memory with the value 0x8E. - As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 9.5 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction. The decision to enter either in ACTIVEHALT or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table: ATCSR LTCSR1 ATCSR ATCSR OVFIE TB1IE bit CK1 bit CK0 bit bit 0 x x 0 0 0 x x 1 x x x x 1 0 1 Meaning ACTIVE-HALT mode disabled ACTIVE-HALT mode enabled The MCU can exit ACTIVE-HALT mode on reception of a specific interrupt (see Table 5, "Interrupt Mapping," on page 35) or a RESET. - When exiting ACTIVE-HALT mode by means of a RESET, a 256 or 4096 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 27). - When exiting ACTIVE-HALT mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 27). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately (see Note 3). In ACTIVE-HALT mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). Note: As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. 41/133 1 ST7LITE2 POWER SAVING MODES (Cont'd) Figure 26. ACTIVE-HALT Timing Overview RUN ACTIVE 256 OR 4096 CPU HALT CYCLE DELAY 1) HALT INSTRUCTION [Active Halt Enabled] RESET OR INTERRUPT RUN FETCH VECTOR Figure 27. ACTIVE-HALT Mode Flow-chart HALT INSTRUCTION (Active Halt enabled) (AWUCSR.AWUEN=0) OSCILLATOR ON PERIPHERALS 2) OFF CPU OFF I BIT 0 9.6 AUTO WAKE UP FROM HALT MODE Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wake-up (Auto Wake Up from Halt Oscillator). Compared to ACTIVE-HALT mode, AWUFH has lower power consumption (the main clock is not kept running, but there is no accurate realtime clock available. It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set. Figure 28. AWUFH Mode Block Diagram AWU RC oscillator fAWU_RC N to Timer input capture RESET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS 2) OFF CPU ON I BIT X 4) 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BIT ON ON ON X 4) FETCH RESET VECTOR OR SERVICE INTERRUPT Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the RTC1 interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode. Refer to Table 5, "Interrupt Mapping," on page 35 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 42/133 1 /64 divider AWUFH prescaler/1 .. 255 AWUFH interrupt (ei0 source) As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set by hardware and an interrupt wakes-up the MCU from Halt mode. At the same time the main oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency fAWU_RC and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects fAWU_RC to the input capture of the 12-bit Auto-Reload timer, allowing the fAWU_RC to be measured using the main oscillator clock as a reference timebase. ST7LITE2 POWER SAVING MODES (Cont'd) Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: - The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see Section 9.4 HALT MODE). - When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. - In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). - The compatibility of Watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET. Figure 29. AWUF Halt Timing Diagram tAWU RUN MODE HALT MODE 256 OR 4096 tCPU RUN MODE fCPU fAWU_RC Clear by software AWUFH interrupt 43/133 1 ST7LITE2 POWER SAVING MODES (Cont'd) Figure 30. AWUFH Mode Flow-chart HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE WDGHALT 1) WATCHDOG 0 DISABLE 1 WATCHDOG RESET AWU RC OSC ON MAIN OSC OFF PERIPHERALS 2) OFF CPU OFF I[1:0] BITS 10 N RESET N Y INTERRUPT 3) Y AWU RC OSC OFF MAIN OSC ON PERIPHERALS OFF CPU ON I[1:0] BITS XX 4) 256 OR 4096 CPU CLOCK CYCLE DELAY5) AWU RC OSC OFF MAIN OSC ON PERIPHERALS ON CPU ON I[1:0] BITS XX 4) FETCH RESET VECTOR OR SERVICE INTERRUPT 44/133 1 Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 5, "Interrupt Mapping," on page 35 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 5. If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP (see Figure 12). ST7LITE2 POWER SAVING MODES (Cont'd) 9.6.0.1 Register description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read/Write Reset Value: 0000 0000 (00h) AWUFH PRESCALER REGISTER (AWUPR) Read/Write Reset Value: 1111 1111 (FFh) 7 7 0 0 0 0 0 0 AWU AWU AWU F M EN 0 AWU AWU AWU AWU AWU AWU AWU AWU PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler These 8 bits define the AWUPR Dividing factor (as explained below: Bits 7:3 = Reserved. Bit 2 = AWUF Auto Wake Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: No AWU interrupt occurred 1: AWU interrupt occurred Bit 1= AWUM Auto Wake Up Measurement This bit enables the AWU RC oscillator and connects its output to the inputcapture of the 12-bit Auto-Reload timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPRE register. 0: Measurement disabled 1: Measurement enabled Bit 0 = AWUEN Auto Wake Up From Halt Enabled This bit enables the Auto Wake Up From Halt feature: once HALT mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software. 0: AWUFH (Auto Wake Up From Halt) mode disabled 1: AWUFH (Auto Wake Up From Halt) mode enabled AWUPR[7:0] Dividing factor 00h Forbidden 01h 1 ... ... FEh 254 FFh 255 In AWU mode, the period that the MCU stays in Halt Mode (tAWU in Figure 29 on page 43) is defined by t AWU 1 = 64 x AWUPR x -------------------------- + t RCSTRT f AWURC This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically. Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction, or the AWUPR remains inchanged. l Table 7. AWU Register Map and Reset Values Address (Hex.) 0049h 004Ah Register Label 7 6 5 4 3 2 1 0 AWUPR AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 Reset Value 1 1 1 1 1 1 1 1 AWUCSR 0 0 0 0 0 AWUF AWUM AWUEN Reset Value 45/133 1 ST7LITE2 10 I/O PORTS 10.1 INTRODUCTION The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for onchip peripherals or analog input. 10.2 FUNCTIONAL DESCRIPTION A Data Register (DR) and a Data Direction Register (DDR) are always associated with each port. The Option Register (OR), which allows input/output options, may or may not be implemented. The following description takes into account the OR register. Refer to the Port Configuration table for device specific information. An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port. Figure 31 shows the generic I/O block diagram. 10.2.1 Input Modes Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin. If an OR bit is available, different input modes can be configured by software: floating or pull-up. Refer to I/O Port Implementation section for configuration. Notes: 1. Writing to the DR modifies the latch value but does not change the state of the input pin. 2. Do not use read/modify/write instructions (BSET/BRES) to modify the DR register. 10.2.1.1 External Interrupt Function Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O generates an interrupt request via the corresponding interrupt vector (eix). Falling or rising edge sensitivity is programmed independently for each interrupt vector. The External Interrupt Control Register (EICR) or the Miscellaneous Register controls this sensitivity, depending on the device. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description in section 2 on page 6 and interrupt section). 46/133 1 If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register. To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again. Caution: In case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. This corresponds to the following steps: 1. To enable an external interrupt: - set the interrupt mask with the SIM instruction (in cases where a pin level change could occur) - select rising edge - enable the external interrupt through the OR register - select the desired sensitivity if different from rising edge - reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur) 2. To disable an external interrupt: - set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) - select falling edge ST7LITE2 - disable the external interrupt through the OR register - select rising edge - reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur) 10.2.2 Output Modes Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value. If an OR bit is available, different output modes can be selected by software: push-pull or opendrain. Refer to I/O Port Implementation section for configuration. DR Value and Output Pin Status DR Push-Pull Open-Drain 0 1 VOL VOH VOL Floating 10.2.3 Alternate Functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral's control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O's state is readable by addressing the corresponding I/O data register. Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur. Configure an I/O as input floating for an on-chip peripheral signal which can be input and output. Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function. 47/133 1 ST7LITE2 I/O PORTS (Cont'd) Figure 31. I/O Port General Block Diagram ALTERNATE OUTPUT REGISTER ACCESS From on-chip peripheral 1 VDD 0 P-BUFFER (see table below) ALTERNATE ENABLE BIT PULL-UP (see table below) DR VDD DDR PULL-UP CONDITION DATA BUS OR PAD If implemented OR SEL N-BUFFER DIODES (see table below) DDR SEL DR SEL ANALOG INPUT CMOS SCHMITT TRIGGER 1 0 EXTERNAL INTERRUPT REQUEST (eix) ALTERNATE INPUT Combinational Logic SENSITIVITY SELECTION To on-chip peripheral FROM OTHER BITS Note: Refer to the Port Configuration table for device specific information. Table 8. I/O Port Mode Options Configuration Mode Input Output Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Legend: NI - not implemented Off - implemented not activated On - implemented and activated 48/133 1 Pull-Up P-Buffer Off On Off Off NI On Off NI Diodes to VDD On to VSS On NI (see note) Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VOL is implemented to protect the device against positive stress. ST7LITE2 I/O PORTS (Cont'd) Table 9. I/O configurations Hardware Configuration VDD RPU DR REGISTER ACCESS NOTE 3 PULL-UP CONDITION DR REGISTER PAD W DATA BUS INPUT 1) R ALTERNATE INPUT To on-chip peripheral FROM OTHER PINS EXTERNAL INTERRUPT SOURCE (eix) INTERRUPT COMBINATIONAL POLARITY LOGIC SELECTION CONDITION PUSH-PULL OUTPUT 2) OPEN-DRAIN OUTPUT 2) ANALOG INPUT VDD NOTE 3 DR REGISTER ACCESS RPU PAD DR REGISTER VDD R/W DATA BUS DR REGISTER ACCESS NOTE 3 RPU PAD DR REGISTER ALTERNATE ENABLE BIT R/W DATA BUS ALTERNATE OUTPUT From on-chip peripheral Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content. 3. For true open drain, these elements are not implemented. 49/133 1 ST7LITE2 I/O PORTS (Cont'd) Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input. Analog Recommendations Do not change the voltage level or loading on any I/O while conversion is in progress. Do not have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 10.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific I/O port features such as ADC input or open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 32. Other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation. Figure 32. Interrupt I/O Port State Transitions 01 00 10 11 INPUT floating/pull-up interrupt INPUT floating (reset state) OUTPUT open-drain OUTPUT push-pull XX 10.4 UNUSED I/O PINS Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8. 10.5 LOW POWER MODES Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode. 10.6 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction). Interrupt Event External interrupt on selected external event 50/133 1 = DDR, OR Enable Event Control Flag Bit - DDRx ORx Exit from Wait Exit from Halt Yes Yes ST7LITE2 I/O PORTS (Cont'd) 10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION The I/O port register configurations are summarised as follows. Interrupt Ports Ports where the external interrupt capability is selected using the EISR register Standard Ports MODE floating input pull-up interrupt input open drain output push-pull output PA7:0, PB6:0 MODE floating input pull-up input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1 DDR 0 0 1 1 OR 0 1 0 1 Table 10. Port Configuration (Standard ports) Port Input Pin name Output OR = 0 OR = 1 OR = 0 OR = 1 pull-up pull-up open drain push-pull open drain push-pull Port A PA7:0 floating Port B PB6:0 floating Note: On ports where the external interrupt capability is selected using the EISR register, the configuration will be as follows: Port Input Pin name Output OR = 0 OR = 1 OR = 0 OR = 1 pull-up interrupt pull-up interrupt open drain push-pull open drain push-pull Port A PA7:0 floating Port B PB6:0 floating Table 11. I/O Port Register Map and Reset Values Address (Hex.) 0000h 0001h 0002h 0003h 0004h 0005h Register Label PADR Reset Value PADDR Reset Value PAOR Reset Value PBDR Reset Value PBDDR Reset Value PBOR Reset Value 7 6 5 4 3 2 1 1 1 1 1 1 1 0 0 0 0 0 0 MSB 1 LSB MSB 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 LSB MSB 0 0 LSB MSB 0 0 LSB MSB 1 1 LSB MSB 0 0 0 LSB 0 51/133 1 ST7LITE2 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 11.1.2 Main Features Programmable free-running downcounter (64 increments of 16000 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte 11.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 16000 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30s. Figure 33. Watchdog Block Diagram RESET WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 7-BIT DOWNCOUNTER fCPU 52/133 1 CLOCK DIVIDER /16000 T1 T0 ST7LITE2 WATCHDOG TIMER (Cont'd) The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 12 .Watchdog Timing): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. Table 12.Watchdog Timing fCPU = 8MHz WDG Counter Code min [ms] Notes: 1. The timing variation shown in Table 12 is due to the unknown status of the prescaler when writing to the CR register. 2. The number of CPU clock cycles applied during the RESET phase (256 or 4096) must be taken into account in addition to these timings. 11.1.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the Option Byte description in section 15 on page 122. 11.1.4.1 Using Halt Mode with the WDG (WDGHALT option) If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. Same behavior in active-halt mode. max [ms] C0h 1 2 FFh 127 128 53/133 1 ST7LITE2 WATCHDOG TIMER (Cont'd) 11.1.5 Interrupts None. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. 11.1.6 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). 0 T6 T5 T4 T3 T2 T1 T0 Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. Table 13. Watchdog Timer Register Map and Reset Values Address (Hex.) 002Eh 54/133 1 Register Label 7 6 5 4 3 2 1 0 WDGCR Reset Value WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 ST7LITE2 11.2 12-BIT AUTORELOAD TIMER 2 (AT2) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on a freerunning 12-bit upcounter with an input capture register and four PWM output channels. There are 6 external pins: - Four PWM outputs - ATIC pin for the Input Capture function - BREAK pin for forcing a break condition on the PWM outputs 11.2.2 Main Features 12-bit upcounter with 12-bit autoreload register (ATR) Maskable overflow interrupt Generation of four independent PWMx signals Frequency 2KHz-4MHz (@ 8 MHz fCPU) - Programmable duty-cycles - Polarity control - Programmable output modes - Maskable Compare interrupt Input Capture - 12-bit input capture register (ATICR) - Triggered by rising and falling edges - Maskable IC interrupt Figure 34. Block Diagram ATIC 12-BIT INPUT CAPTURE REGISTER IC INTERRUPT ATICR REQUEST OVF INTERRUPT REQUEST ATCSR 0 ICF fLTIMER (1 ms timebase @ 8MHz) ICIE CK1 CK0 OVF OVFIE CMPIE CMP INTERRUPT REQUEST CMPF0 CMPF1 CMPF2 CMPF3 fCOUNTER fCPU 12-BIT UPCOUNTER CNTR 32 MHz 12-BIT AUTORELOAD REGISTER ATR DCR0L Preload Preload on OVF Event IF TRAN=1 12-BIT DUTY CYCLE VALUE (shadow) CMPFx bit COMPPARE OPx bit fPWM POLARITY OUTPUT CONTROL DCR0H PWM GENERATION OEx bit PWMx 4 PWM Channels 55/133 1 ST7LITE2 12-BIT AUTORELOAD TIMER (Cont'd) 11.2.3 Functional Description PWM Mode This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins. The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register. PWM Frequency and Duty Cycle The four PWM signals have the same frequency (fPWM) which is controlled by the counter period and the ATR register value. fPWM = fCOUNTER / (4096 - ATR) Following the above formula, - If fCOUNTER is 32 MHz, the maximum value of fPWM is 8 MHz (ATR register value = 4092), the minimum value is 8 KHz (ATR register value = 0) - If fCOUNTER is 4 Mhz, the maximum value of fPWM is 2 MHz (ATR register value = 4094),the minimum value is 1 KHz (ATR register value = 0). Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. At reset, the counter starts counting from 0. When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are transferred to the Duty Cycle registers and the PWMx signals are set to a high level. When the upcounter matches the DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the contents of the corresponding DCRx register must be greater than the contents of the ATR register. The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the TRAN bit in the TRANCR register is set (reset value). See Figure 35. Figure 35. PWM Inversion Diagram inverter PWMx PWMx PIN PWMxCSR Register OPx TRAN DFF TRANCR Register counter overflow The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (4096 - ATR) Note: To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity. Figure 36. PWM Function COUNTER 4095 DUTY CYCLE REGISTER (DCRx) AUTO-RELOAD REGISTER (ATR) PWMx OUTPUT 000 56/133 1 WITH OE=1 AND OPx=0 WITH OE=1 AND OPx=1 t ST7LITE2 12-BIT AUTORELOAD TIMER (Cont'd) Figure 37. PWM Signal from 0% to 100% Duty Cycle fCOUNTER ATR= FFDh PWMx OUTPUT WITH OEx=1 AND OPx=1 PWMx OUTPUT WITH OEx=1 AND OPx=0 COUNTER FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh DCRx=000h DCRx=FFDh DCRx=FFEh DCRx=000h t Output Compare Mode To use this function, load a 12-bit value in the DCRxH and DCRxL registers. When the 12-bit upcounter (CNTR) reaches the value stored in the DCRxH and DCRxL registers, the CMPF bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set. Note: The output compare function is only available for DCRx values other than 0 (reset value). Break Function The break function is used to perform an emergency shutdown of the power converter. The break function is activated by the external BREAK pin (active low). In order to use the BREAK pin it must be previously enabled by software setting the BPEN bit in the BREAKCR register. When a low level is detected on the BREAK pin, the BA bit is set and the break function is activated. Software can set the BA bit to activate the break function without using the BREAK pin. When the break function is activated (BA bit =1): - The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx output pins (after the inverter). - The 12-bit PWM counter is set to its reset value. - The ARR, DCRx and the corresponding shadow registers are set to their reset values. - The PWMCR register is reset. When the break function is deactivated after applying the break (BA bit goes from 1 to 0 by software): - The control of PWM outputs is transferred to the port registers. 57/133 1 ST7LITE2 12-BIT AUTORELOAD TIMER (Cont'd) Figure 38. Block Diagram of Break Function BREAK pin (Active Low) BREAKCR Register BA BPEN PWM3 PWM2 PWM1 PWM0 PWM0 1 PWM1 PWM2 PWM0 PWM1 PWM3 PWM2 0 PWM3 (Inverters) When BA is set: PWM counter -> Reset value ARR & DCRx -> Reset value PWM Mode -> Reset value Note: The BREAK pin value is latched by the BA bit. 11.2.3.1 Input Capture The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter after a rising or falling edge is detected on the ATIC pin. When an input capture occurs, the ICF bit is set and the ATICR register contains the value of the free running upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading the ATICR register when the ICF bit is set. The ATICR is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. Any further input capture is inhibited while the ICF bit is set. Figure 39. Input Capture Timing Diagram fCOUNTER COUNTER 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah ATIC PIN INTERRUPT ATICR READ INTERRUPT ICF FLAG ICR REGISTER xxh 04h 09h t 58/133 1 ST7LITE2 12-BIT AUTORELOAD TIMER (Cont'd) 11.2.4 Low Power Modes Mode Description The input frequency is divided SLOW by 32 WAIT No effect on AT timer AT timer halted except if CK0=1, ACTIVE-HALT CK1=0 and OVFIE=1 HALT AT timer halted The OVF event is mapped on a separate vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). Note 2: Only if CK0=1 and CK1=0 (fCOUNTER = fLTIMER) 11.2.5 Interrupts Interrupt Event1) Overflow Event IC Event CMP Event Enable Exit Event Control from Flag Wait Bit OVF OVIE ICF ICIE CMPF0 CMPIE Exit Exit from from ActiveHalt Halt Yes No Yes2) Yes Yes No No No No Note 1: The CMP and IC events are connected to the same interrupt vector. 59/133 1 ST7LITE2 12-BIT AUTORELOAD TIMER (Cont'd) 11.2.6 Register Description Bit 2 = OVF Overflow Flag. This bit is set by hardware and cleared by software by reading the TCSR register. It indicates the transition of the counter from FFFh to ATR value. 0: No counter overflow occurred 1: Counter overflow occurred TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h) 7 6 0 ICF 0 ICIE CK1 CK0 OVF OVFIE CMPIE Bit 7 = Reserved. Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred 15 Bits 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. CK1 CK0 OFF 0 0 fLTIMER (1 ms timebase @ 8 MHz) 1) 0 1 fCPU 1 0 32 MHz 2) 1 1 Note 1: PWM mode and Output Compare modes are not available at this frequency. Note 2: ATICR counter may return inaccurate results when read. It is therefore not recommended to use Input Capture mode at this frequency. 60/133 1 Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. It can be used to mask the interrupt generated when the CMPF bit is set. 0: CMPF interrupt disabled. 1: CMPF interrupt enabled. COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (000h) Bit 5 = ICIE IC Interrupt Enable. This bit is set and cleared by software. 0: Input capture interrupt disabled 1: Input capture interrupt enabled Counter Clock Selection Bit 1 = OVFIE Overflow Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. 0: OVF interrupt disabled. 1: OVF interrupt enabled. 0 8 0 0 0 CNTR CNTR CNTR9 CNTR8 11 10 COUNTER REGISTER LOW (CNTRL) Read only Reset Value: 0000 0000 (000h) 7 0 CNTR7 CNTR6 CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0 Bits 15:12 = Reserved. Bits 11:0 = CNTR[11:0] Counter Value. This 12-bit register is read by software and cleared by hardware after a reset. The counter is incremented continuously as soon as a counter clok is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations, LSB first. When a counter overflow occurs, the counter restarts from the value specified in the ATR register. ST7LITE2 12-BIT AUTORELOAD TIMER (Cont'd) AUTORELOAD REGISTER (ATRH) Read / Write Reset Value: 0000 0000 (00h) PWMx CONTROL STATUS REGISTER (PWMxCSR) Read / Write Reset Value: 0000 0000 (00h) 15 0 8 0 0 0 ATR11 ATR10 ATR9 AUTORELOAD REGISTER (ATRL) Read / Write Reset Value: 0000 0000 (00h) 0 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Bits 11:0 = ATR[11:0] Autoreload Register. This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the PWM frequency. PWM OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) 7 0 0 OE3 0 OE2 0 OE1 6 0 0 0 0 0 0 0 OPx CMPFx Bits 7:2= Reserved, must be kept cleared. 7 ATR7 7 ATR8 0 OE0 Bits 7:0 = OE[3:0] PWMx output enable. These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx output alternate function disabled: I/O pin free for general purpose I/O after an overflow event. 1: PWM mode enabled Bit 1 = OPx PWMx Output Polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not inverted. 1: The PWM signal is inverted. Bit 0 = CMPFx PWMx Compare Flag. This bit is set by hardware and cleared by software by reading the PWMxCSR register. It indicates that the upcounter value matches the DCRx register value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value. BREAK CONTROL REGISTER (BREAKCR) Read/Write Reset Value: 0000 0000 (00h) 7 0 0 0 BA BPEN PWM3 PWM2 PWM1 PWM0 Bits 7:6 = Reserved. Forced by hardware to 0. Bit 5 = BA Break Active. This bit is read/write by software, cleared by hardware after reset and set by hardware when the BREAK pin is low. It activates/deactivates the Break function. 0: Break not active 1: Break active 61/133 1 ST7LITE2 12-BIT AUTORELOAD TIMER (Cont'd) Bit 4 = BPEN Break Pin Enable. This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled Bits 3:0 = PWM[3:0] Break Pattern. These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active. PWMx DUTY CYCLE REGISTER HIGH (DCRxH) Read / Write Reset Value: 0000 0000 (00h) 15 INPUT CAPTURE REGISTER HIGH (ATICRH) Read only Reset Value: 0000 0000 (00h) 15 0 8 0 0 0 ICR11 ICR10 ICR9 ICR8 INPUT CAPTURE REGISTER LOW (ATICRL) Read only Reset Value: 0000 0000 (00h) 7 ICR7 0 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 8 Bits 15:12 = Reserved. 0 0 0 0 DCR11 DCR10 DCR9 DCR8 PWMx DUTY CYCLE REGISTER LOW (DCRxL) Read / Write Reset Value: 0000 0000 (00h) 7 DCR7 DCR6 DCR5 DCR4 DCR3 0 DCR2 DCR1 DCR0 Bits 11:0 = ICR[11:0] Input Capture Data. This is a 12-bit register which is readable by software and cleared by hardware after a reset. The ATICR register contains captured the value of the 12-bit CNTR register when a rising or falling edge occurs on the ATIC pin. Capture will only be performed when the ICF flag is cleared. TRANSFER CONTROL REGISTER (TRANCR) Read/Write Reset Value: 0000 0001 (01h) 7 0 Bits 15:12 = Reserved. Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value This 12-bit value is written by software. It definesthe duty cycle of the corresponding PWM output signal (see Figure 36). In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see Figure 36). In Output Compare mode, they define the value to be compared with the 12-bit upcounter value. 62/133 1 0 0 0 0 0 0 0 TRAN Bits 7:1 Reserved. Forced by hardware to 0. Bit 0 = TRAN Transfer enable This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It allows the value of the DCRx registers to be transferred to the DCRx shadow registers after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. ST7LITE2 12-BIT AUTORELOAD TIMER (Cont'd) Table 14. Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 0D ATCSR Reset Value 0 ICF 0 ICIE 0 CK1 0 CK0 0 OVF 0 OVFIE 0 CMPIE 0 0E CNTRH Reset Value 0 0 0 0 CNTR11 0 CNTR10 0 CNTR9 0 CNTR8 0 0F CNTRL Reset Value CNTR7 0 CNTR8 0 CNTR7 0 CNTR6 0 CNTR3 0 CNTR2 0 CNTR1 0 CNTR0 0 10 ATRH Reset Value 0 0 0 0 ATR11 0 ATR10 0 ATR9 0 ATR8 0 11 ATRL Reset Value ATR7 0 ATR6 0 ATR5 0 ATR4 0 ATR3 0 ATR2 0 ATR1 0 ATR0 0 12 PWMCR Reset Value 0 OE3 0 0 OE2 0 0 OE1 0 0 OE0 0 13 PWM0CSR Reset Value 0 0 0 0 0 0 OP0 0 CMPF0 0 14 PWM1CSR Reset Value 0 0 0 0 0 0 OP1 0 CMPF1 0 15 PWM2CSR Reset Value 0 0 0 0 0 0 OP2 0 CMPF2 0 16 PWM3CSR Reset Value 0 0 0 0 0 0 OP3 0 CMPF3 0 17 DCR0H Reset Value 0 0 0 0 DCR11 0 DCR10 0 DCR9 0 DCR8 0 18 DCR0L Reset Value DCR7 0 DCR6 0 DCR5 0 DCR4 0 DCR3 0 DCR2 0 DCR1 0 DCR0 0 19 DCR1H Reset Value 0 0 0 0 DCR11 0 DCR10 0 DCR9 0 DCR8 0 1A DCR1L Reset Value DCR7 0 DCR6 0 DCR5 0 DCR4 0 DCR3 0 DCR2 0 DCR1 0 DCR0 0 1B DCR2H Reset Value 0 0 0 0 DCR11 0 DCR10 0 DCR9 0 DCR8 0 1C DCR2L Reset Value DCR7 0 DCR6 0 DCR5 0 DCR4 0 DCR3 0 DCR2 0 DCR1 0 DCR0 0 1D DCR3H Reset Value 0 0 0 0 DCR11 0 DCR10 0 DCR9 0 DCR8 0 1E DCR3L Reset Value DCR7 0 DCR6 0 DCR5 0 DCR4 0 DCR3 0 DCR2 0 DCR1 0 DCR0 0 1F ATICRH Reset Value 0 0 0 0 ICR11 0 ICR10 0 ICR9 0 ICR8 0 20 ATICRL Reset Value ICR7 0 ICR6 0 ICR5 0 ICR4 0 ICR3 0 ICR2 0 ICR1 0 ICR0 0 (Hex.) 63/133 1 ST7LITE2 Address Register Label 7 6 5 4 3 2 1 0 21 TRANCR Reset Value 0 0 0 0 0 0 0 TRAN 1 22 BREAKCR Reset Value 0 0 BA 0 BPEN 0 PWM3 0 PWM2 0 PWM1 0 PWM0 0 (Hex.) 64/133 1 ST7LITE2 11.3 LITE TIMER 2 (LT2) 11.3.1 Introduction The Lite Timer can be used for general-purpose timing functions. It is based on two free-running 8bit upcounters, an 8-bit input capture register. 11.3.2 Main Features Realtime Clock - One 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz fOSC) - One 8-bit upcounter with autoreload and programmable timebase period from 4s to 1.024ms in 4s increments (@ 8 MHz fOSC) - 2 Maskable timebase interrupts Input Capture - 8-bit input capture register (LTICR) - Maskable interrupt with wakeup from Halt Mode capability Figure 40. Lite Timer 2 Block Diagram fOSC/32 LTTB2 LTCNTR Interrupt request LTCSR2 8-bit TIMEBASE COUNTER 2 0 0 0 0 0 0 TB2IE TB2F 8 LTARR fLTIMER 8-bit AUTORELOAD REGISTER /2 8-bit TIMEBASE COUNTER 1 fLTIMER 8 To 12-bit AT TImer 1 0 Timebase 1 or 2 ms (@ 8MHz fOSC) LTICR LTIC 8-bit INPUT CAPTURE REGISTER LTCSR1 ICIE ICF TB TB1IE TB1F LTTB1 INTERRUPT REQUEST LTIC INTERRUPT REQUEST 65/133 1 ST7LITE2 LITE TIMER (Cont'd) 11.3.3 Functional Description 11.3.3.1 Timebase Counter 1 An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR1 register. When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1 register. 11.3.3.2 Input Capture The 8-bit input capture register is used to latch the free-running upcounter (Counter 1) 1 after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR1 register contains the MSB of Counter 1. The LTICR is a read-only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set. 11.3.3.3 Timebase Counter 2 Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR register. After an MCU reset, it increments at a frequency of fOSC/32 starting from the value stored in the LTARR register. A counter overflow event occurs when the counter rolls over from FFh to the LTARR reload value. Software can write a new value at anytime in the LTARR register, this value will be automatically loaded in the counter when the next overflow occurs. When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software reading the LTCSR2 register. Figure 41. Input Capture Timing Diagram. 4s (@ 8MHz fOSC) fCPU fOSC/32 8-bit COUNTER 1 01h 02h 03h 04h 05h 06h 07h CLEARED BY S/W READING LTIC REGISTER LTIC PIN ICF FLAG LTICR REGISTER xxh 04h 07h t 66/133 1 ST7LITE2 LITE TIMER (Cont'd) 11.3.4 Low Power Modes 11.3.6 Register Description Mode Description No effect on Lite timer SLOW (this peripheral is driven directly by fOSC/32) WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops counting 11.3.5 Interrupts Interrupt Event 7 0 0 0 0 0 0 0 TB2IE TB2F Bits 7:2 = Reserved, must be kept cleared. Exit from Wait Exit from Active Halt Exit from Halt TB1IE Yes Yes No TB2IE Yes No No ICIE Yes No No Enable Event Control Flag Bit Timebase 1 TB1F Event Timebase 2 TB2F Event IC Event ICF LITE TIMER CONTROL/STATUS REGISTER 2 (LTCSR2) Read / Write Reset Value: 0000 0000 (00h) Note: The TBxF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction). Bit 1 = TB2IE Timebase 2 Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled Bit 0 = TB2F Timebase 2 Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred LITE TIMER AUTORELOAD (LTARR) Read / Write Reset Value: 0000 0000 (00h) REGISTER 7 AR7 0 AR7 AR7 AR7 AR3 AR2 AR1 AR0 Bits 7:0 = AR[7:0] Counter 2 Reload Value. These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. 67/133 1 ST7LITE2 LITE TIMER (Cont'd) LITE TIMER COUNTER 2 (LTCNTR) Read only Reset Value: 0000 0000 (00h) 7 CNT7 0 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0 Bits 7:0 = CNT[7:0] Counter 2 Reload Value. This register is read by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. LITE TIMER CONTROL/STATUS REGISTER (LTCSR1) Read / Write Reset Value: 0x00 0000 (x0h) 7 Bit 5 = TB Timebase period selection. This bit is set and cleared by software. 0: Timebase period = tOSC * 8000 (1ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2ms @ 8 MHz) Bit 4 = TB1IE Timebase Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB1) interrupt disabled 1: Timebase (TB1) interrupt enabled Bit 3 = TB1F Timebase Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred 0 Bits 2:0 = Reserved ICIE ICF TB TB1IE TB1F - - - Bit 7 = ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled LITE TIMER INPUT CAPTURE REGISTER (LTICR) Read only Reset Value: 0000 0000 (00h) 7 ICR7 Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register 68/133 1 0 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Bits 7:0 = ICR[7:0] Input Capture Value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin. ST7LITE2 LITE TIMER (Cont'd) Table 15. Lite Timer Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 08 LTCSR2 Reset Value 0 0 0 0 0 0 TB2IE 0 TB2F 0 09 LTARR Reset Value AR7 0 AR6 0 AR5 0 AR4 0 AR3 0 AR2 0 AR1 0 AR0 0 0A LTCNTR Reset Value CNT7 0 CNT6 0 CNT5 0 CNT4 0 CNT3 0 CNT2 0 CNT1 0 CNT0 0 0B LTCSR1 Reset Value ICIE 0 ICF x TB 0 TB1IE 0 TB1F 0 0 0 0 0C LTICR Reset Value ICR7 0 ICR6 0 ICR5 0 ICR4 0 ICR3 0 ICR2 0 ICR1 0 ICR0 0 (Hex.) 69/133 1 ST7LITE2 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 Main Features Full duplex synchronous transfers (on 3 lines) Simplex synchronous transfers (on 2 lines) Master or slave operation Six master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) SS Management by software or hardware Programmable clock polarity and phase End of transfer interrupt flag Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 General Description Figure 42 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: - SPI Control Register (SPICR) - SPI Control/Status Register (SPICSR) - SPI Data Register (SPIDR) The SPI is connected to external devices through 3 pins: - MISO: Master In / Slave Out data - MOSI: Master Out / Slave In data - SCK: Serial Clock out by SPI masters and input by SPI slaves - SS: Slave select: This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master Device. Figure 42. Serial Peripheral Interface Block Diagram SPIDR Data/Address Bus Read Interrupt request Read Buffer MOSI MISO 8-Bit Shift Register SPICSR 7 SPIF WCOL OVR MODF SOD bit SS SPI STATE CONTROL 7 SPIE MASTER CONTROL SERIAL CLOCK GENERATOR 70/133 1 SOD SSM SSI Write SCK SS 0 0 1 0 SPICR 0 SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 43. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device re- sponds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 46) but master and slave must be programmed with the same timing mode. Figure 43. Single Master/ Single Slave Application SLAVE MASTER MSBit LSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR MSBit MISO MISO MOSI MOSI SCK SS LSBit 8-BIT SHIFT REGISTER SCK +5V SS Not used if SS is managed by software 71/133 1 ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 45) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: SS internal must be held high continuously. In Slave Mode: There are two cases depending on the data/clock timing relationship (see Figure 44): If CPHA=1 (data latched on 2nd clock edge): - SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the in the SPICSR register) If CPHA=0 (data latched on 1st clock edge): - SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.4.5.3). Figure 44. Generic SS Timing Diagram MOSI/MISO Byte 1 Byte 2 Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) Figure 45. Hardware/Software Slave Select Management SSM bit 72/133 1 SSI bit 1 SS external pin 0 SS internal Byte 3 ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). How to operate the SPI in master mode To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit ) may be not taken into account): 1. Write to the SPICR register: - Select the clock frequency by configuring the SPR[2:0] bits. - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 46 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: - Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: - Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high. Important note: if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not taken into account. The transmit sequence begins when software writes a byte in the SPIDR register. 11.4.3.4 Master Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 11.4.3.5 Slave Mode Operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 46). Note: The slave must have the same CPOL and CPHA settings as the master. - Manage the SS pin as described in Section 11.4.3.2 and Figure 44. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions. 11.4.3.6 Slave Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.4.5.2). 73/133 1 ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 46). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 46, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Figure 46. Data Clock Timing Diagram CPHA =1 SCK (CPOL = 1) SCK (CPOL = 0) MISO (from master) MOSI (from slave) MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit SS (to slave) CAPTURE STROBE CPHA =0 SCK (CPOL = 1) SCK (CPOL = 0) MISO (from master) MOSI (from slave) MSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit SS (to slave) CAPTURE STROBE Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. 74/133 1 ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.5 Error Flags 11.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: - The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the Device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the Device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device, the MODF bit can not be set, but in a multi master configuration the Device can be in slave mode with the MODF bit set. The MODF bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application default state. 11.4.5.2 Overrun Condition (OVR) An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs: - The OVR bit is set and an interrupt request is generated if the SPIE bit is set. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register. 11.4.5.3 Write Collision Error (WCOL) A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. See also Section 11.4.3.2 Slave Select Management. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the CPU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 47). Figure 47. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR RESULT 2nd Step Read SPIDR SPIF =0 WCOL=0 Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SPICSR RESULT 2nd Step Read SPIDR WCOL=0 Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit 75/133 1 ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.5.4 Single Master and Multimaster Configurations There are two types of SPI systems: - Single Master System - Multimaster System Single Master System A typical single master system may be configured, using a device as the master and four devices as slaves (see Figure 48). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission. For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with command fields. Multi-Master System A multi-master system may also be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system. The multi-master system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register. Figure 48. Single Master / Multiple Slave Configuration SS SCK Slave Device SS SCK Slave Device SS SCK Slave Device SS SCK Slave Device MOSI MISO MOSI MISO MOSI MISO MOSI MISO SCK Master Device 5V 76/133 1 SS Ports MOSI MISO ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.6 Low Power Modes Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the Device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the Device is woken up by an interrupt with "exit from HALT mode" capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device. 11.4.6.1 Using the SPI to wake-up the Device from Halt mode In slave configuration, the SPI is able to wake-up the Device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake-up the Device from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the Device enters Halt mode. So if Slave selection is configured as external (see Section 11.4.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode. 11.4.7 Interrupts Interrupt Event Event Flag SPI End of TransSPIF fer Event Master Mode MODF Fault Event Overrun Error OVR Enable Control Bit SPIE Exit from Wait Exit from Halt Yes Yes Yes No Yes No Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 77/133 1 ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) 11.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE 0 SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register) Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 11.4.5.1 Master Mode Fault (MODF)). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 16 SPI Master mode SCK Frequency. 0: Divider by 2 enabled 1: Divider by 2 disabled Note: This bit has no effect in slave mode. Bit 4 = MSTR Master Mode. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 11.4.5.1 Master Mode Fault (MODF)). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. 78/133 1 Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Bit 2 = CPHA Clock Phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Note: The slave must have the same CPOL and CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial Clock Frequency. These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode. Table 16. SPI Master mode SCK Frequency Serial Clock SPR2 SPR1 SPR0 fCPU/4 1 0 0 fCPU/8 0 0 0 fCPU/16 0 0 1 fCPU/32 1 1 0 fCPU/64 0 1 0 fCPU/128 0 1 1 ST7LITE2 SERIAL PERIPHERAL INTERFACE (Cont'd) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF 0 WCOL OVR MODF - SOD SSM SSI Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the Device and an external device has been completed. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Bit 6 = WCOL Write Collision status (Read only). This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 47). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 11.4.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11.4.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE=1 in the SPICR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared. Bit 2 = SOD SPI Output Disable. This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 11.4.3.2 Slave Select Management. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) Bit 0 = SSI SS Internal Mode. This bit is set and cleared by software. It acts as a `chip select' by controlling the level of the SS slave select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined 7 D7 0 D6 D5 D4 D3 D2 D1 D0 The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 42). 79/133 1 ST7LITE2 Table 17. SPI Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 0031h SPIDR Reset Value MSB x x x x x x x LSB x 0032h SPICR Reset Value SPIE 0 SPE 0 SPR2 0 MSTR 0 CPOL x CPHA x SPR1 x SPR0 x 0033h SPICSR Reset Value SPIF 0 WCOL 0 OVR 0 MODF 0 0 SOD 0 SSM 0 SSI 0 (Hex.) 80/133 1 ST7LITE2 11.5 10-BIT A/D CONVERTER (ADC) 11.5.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 7 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 7 different sources. The result of the conversion is stored in a 10-bit Data Register. The A/D converter is controlled through a Control/Status Register. Data register (DR) which contains the results Conversion complete status flag On/off bit (to reduce consumption) The block diagram is shown in Figure 49. 11.5.3 Functional Description 11.5.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. 11.5.2 Main Features 10-bit conversion Up to 7 channels with multiplexed input Linear successive approximation Figure 49. ADC Block Diagram fCPU DIV 4 DIV 2 1 fADC 0 0 1 EOC SPEED ADON SLOW bit 0 0 CH2 CH1 ADCCSR CH0 3 AIN0 HOLD CONTROL AIN1 ANALOG MUX x 1 or x8 RADC ANALOG TO DIGITAL CONVERTER CADC AINx AMPSEL bit ADCDRH D9 D8 ADCDRL D7 D6 0 D5 0 D4 0 D3 D2 AMP AMP SLOW CAL SEL D1 D0 81/133 1 ST7LITE2 10-BIT A/D CONVERTER (ADC) (Cont'd) 11.5.3.2 Input Voltage Amplifier The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the ADCDRL register. When the amplifier is enabled, the input range is 0V to VDD/8. For example, if VDD = 5V, then the ADC can convert voltages in the range 0V to 430mV with an ideal resolution of 0.6mV (equivalent to 13-bit resolution with reference to a VSS to VDD range). For more details, refer to the Electrical characteristics section. Note: The amplifier is switched on by the ADON bit in the ADCCSR register, so no additional startup time is required when the amplifier is selected by the AMPSEL bit. 11.5.3.3 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.5.3.4 A/D Conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the I/O ports chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register: - Select the CS[2:0] bits to assign the analog channel to convert. ADC Conversion mode In the ADCCSR register: Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: - The EOC bit is set by hardware. - The result is in the ADCDR registers. A read to the ADCDRH resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRL 3. Read ADCDRH. This clears EOC automatically. To read only 8 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRH. This clears EOC automatically. 11.5.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. Mode WAIT HALT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed. 11.5.5 Interrupts None. 82/133 1 ST7LITE2 10-BIT A/D CONVERTER (ADC) (Cont'd) 11.5.6 Register Description DATA REGISTER HIGH (ADCDRH) Read Only Reset Value: xxxx xxxx (xxh) CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 CH3 CH2 CH1 0 7 CH0 D9 Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRH register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED ADC clock selection This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description. Bit 5 = ADON A/D Converter on This bit is set and cleared by software. 0: A/D converter and amplifier are switched off 1: A/D converter and amplifier are switched on Bits 4:3 = Reserved. Must be kept cleared. Bits 2:0 = CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. Channel Pin* CH2 CH1 CH0 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 *The number of channels is device dependent. Refer to the device pinout description. 0 D8 D7 D6 D5 D4 D3 D2 Bits 7:0 = D[9:2] MSB of Analog Converted Value AMP CONTROL/DATA REGISTER LOW (ADCDRL) Read/Write Reset Value: 0000 00xx (0xh) 7 0 0 0 0 AMP CAL SLOW AMPSEL D1 D0 Bits 7:5 = Reserved. Forced by hardware to 0. Bit 4 = AMPCAL Amplifier Calibration Bit This bit is set and cleared by software. User is suggested to use this bit to calibrate the ADC when amplifier is ON. Setting this bit internally connects amplifier input to 0v. Hence, corresponding ADC output can be used in software to eliminate amplifier-offset error. 0: Calibration off 1: Calibration on (The input voltage of the amp is set to 0V) Note: It is advised to use this bit to calibrate the ADC when the amplifier is ON. Setting this bit internally connects the amplifier input to 0v. Hence, the corresponding ADC output can be used in software to eliminate an amplifier-offset error. Bit 3 = SLOW Slow mode This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below. fADC fCPU/2 fCPU fCPU/4 SLOW SPEED 0 0 1 0 1 x This bit is set and cleared by software. 83/133 1 ST7LITE2 Bit 2 = AMPSEL Amplifier Selection Bit 0: Amplifier is not selected 1: Amplifier is selected Bits 1:0 = D[1:0] LSB of Analog Converted Value Note: When AMPSEL=1 it is mandatory that fADC be less than or equal to 2 MHz. Table 18. ADC Register Map and Reset Values Address (Hex.) 7 6 5 4 3 2 1 0 0034h ADCCSR Reset Value EOC 0 SPEED 0 ADON 0 0 0 0 0 CH2 0 CH1 0 CH0 0 0035h ADCDRH Reset Value D9 x D8 x D7 x D6 x D5 x D4 x D3 x D2 x 0036h ADCDRL Reset Value 0 0 0 0 0 0 AMPCAL 0 SLOW 0 AMPSEL 0 D1 x D0 x 84/133 1 Register Label ST7LITE2 12 INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two submodes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Table 19. ST7 Addressing Mode Overview Mode Syntax Pointer Address (Hex.) Destination/ Source Pointer Size (Hex.) Length (Bytes) Inherent nop +0 Immediate ld A,#$55 +1 Short Direct ld A,$10 00..FF +1 Long Direct ld A,$1000 0000..FFFF +2 No Offset Direct Indexed ld A,(X) 00..FF + 0 (with X register) + 1 (with Y register) Short Direct Indexed ld A,($10,X) 00..1FE +1 Long Direct Indexed Short Indirect ld A,($1000,X) 0000..FFFF ld A,[$10] 00..FF +2 00..FF byte +2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2 Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2 byte +2 1) +1 Relative Direct jrne loop PC-128/PC+127 Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF Bit Direct bset $10,#7 00..FF Bit Indirect bset [$10],#7 00..FF Bit Direct btjt $10,#7,skip 00..FF Relative +1 00..FF byte +2 +2 Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte +3 Note: 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 85/133 1 ST7LITE2 ST7 ADDRESSING MODES (Cont'd) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Subroutine Return IRET Interrupt Subroutine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles 12.1.2 Immediate Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations 86/133 1 12.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three submodes: Indexed (No Offset) There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. ST7LITE2 ST7 ADDRESSING MODES (Cont'd) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two submodes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 12.1.7 Relative Mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. Available Relative Direct/ Indirect Instructions Function JRxx Conditional Jump CALLR Call Relative The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode. Table 20. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes Long and Short Instructions Function LD Load CP Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Addition/subtraction operations BCP Bit Compare Short Instructions Only Function CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations BTJT, BTJF Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles CALL, JP Call or Jump subroutine 87/133 1 ST7LITE2 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Load and Transfer LD CLR Stack operation PUSH POP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF Using a prebyte The instructions are described with 1 to 4 bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: 88/133 1 RSP RET PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 12.2.1 Illegal Opcode Reset In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. ST7LITE2 INSTRUCTION GROUPS (Cont'd) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear CP Arithmetic Compare tst(Reg - M) reg CPL One Complement A = FFH-A DEC Decrement dec Y reg, M HALT Halt IRET Interrupt routine return Pop CC, A, X, PC INC Increment inc X JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump JRIH Jump if ext. interrupt = 1 0 1 N Z C reg, M N Z 1 reg, M N Z N Z N Z M 0 H reg, M I C jrf * JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H=1? JRNH Jump if H = 0 H=0? JRM Jump if I = 1 I=1? JRNM Jump if I = 0 I=0? JRMI Jump if N = 1 (minus) N=1? JRPL Jump if N = 0 (plus) N=0? JREQ Jump if Z = 1 (equal) Z=1? JRNE Jump if Z = 0 (not equal) Z=0? JRC Jump if C = 1 C=1? JRNC Jump if C = 0 C=0? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned > 89/133 1 ST7LITE2 INSTRUCTION GROUPS (Cont'd) Mnemo Description Function/Example Dst Src JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg MUL Multiply X,A = X * A A, X, Y X, Y, A NEG Negate (2's compl) neg $10 reg, M NOP No Operation OR OR operation A=A+M A M POP Pop from the Stack pop reg reg M pop CC CC M M reg, CC H I N Z N Z 0 H C 0 I N Z N Z N Z C C PUSH Push onto the Stack push Y RCF Reset carry flag C=0 RET Subroutine Return RIM Enable Interrupts I=0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A=A-M-C N Z C SCF Set carry flag C=1 SIM Disable Interrupts I=1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A=A-M A N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt WFI Wait for Interrupt XOR Exclusive OR N Z 90/133 1 0 0 A M 1 1 M 1 0 A = A XOR M A M ST7LITE2 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 13.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, VDD=5V (for the 4.5VVDD5.5V voltage range) and VDD=3.3V (for the 3VVDD4V voltage range). They are given only as design guidelines and are not tested. 13.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 50. 13.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 51. Figure 51. Pin input voltage ST7 PIN VIN Figure 50. Pin loading conditions ST7 PIN CL 91/133 1 ST7LITE2 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi13.2.1 Voltage Characteristics Symbol VDD - VSS VIN VESD(HBM) tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Ratings Maximum value Supply voltage 7.0 Input voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3 Electrostatic discharge voltage (Human Body Model) see section 13.7.3 on page 105 Unit V V 13.2.2 Current Characteristics Symbol IVDD IVSS Ratings Maximum value Total current into VDD power lines (source) 3) 100 Total current out of VSS ground lines (sink) 3) 100 Output current sunk by any standard I/O and control pin IIO IINJ(PIN) 2) & 4) 50 Output current source by any I/Os and control pin - 25 Injected current on RESET pin 5 Injected current on OSC1 and OSC2 pins 5 Injected current on PB0 and PB1 pins 5) +5 Injected current on any other pin IINJ(PIN) 2) 25 Output current sunk by any high sink I/O pin 6) Total injected current (sum of all I/O and control pins) 6) Unit mA 5 20 13.2.3 Thermal Characteristics Symbol TSTG TJ Ratings Storage temperature range Value Unit -65 to +150 C Maximum junction temperature (see Table 21, "THERMAL CHARACTERISTICS," on page 120) Notes: 1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10k for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected 3. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. No negative current injection allowed on PB0 and PB1 pins. 6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation with IINJ(PIN) maximum current injection on four I/O port pins of the device. 92/133 1 ST7LITE2 13.3 OPERATING CONDITIONS 13.3.1 General operating conditions TA = -40 to +85C unless otherwise specified. Symbol Parameter VDD Supply voltage fCPU CPU clock frequency Conditions Min Max fCPU = 4 MHz. max., 2.4 5.5 fCPU = 8 MHz. max. 3.3 5.5 3.3V VDD5.5V up to 8 2.4VVDD<3.3V up to 4 Unit V MHz Figure 52. fCPU Maximum operating frequency versus VDD supply voltage FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAMETRIC DATA) fCPU [MHz] 8 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 4 2 SUPPLY VOLTAGE [V] 0 2.0 2.4 2.7 3.3 3.5 4.0 4.5 5.0 5.5 93/133 1 ST7LITE2 13.3.2 Operating conditions with Low Voltage Detector (LVD) TA = -40 to 85C, unless otherwise specified Symbol Parameter Conditions Min 1) Typ Max Reset release threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.00 3.40 1) 2.65 1) 4.25 3.60 2.90 4.50 3.80 3.15 VIT-(LVD) Reset generation threshold (VDD fall) High Threshold Med. Threshold Low Threshold 3.80 3.20 2.40 4.05 3.40 2.70 4.30 1) 3.65 1) 2.901) VIT+(LVD)-VIT-(LVD) VIT+(LVD) Vhys LVD voltage threshold hysteresis VtPOR VDD rise time rate 2)3) tg(VDD) Filtered glitch delay on VDD IDD(LVD) LVD/AVD current consumption 200 20 Not detected by the LVD Unit V mV 20000 s/V 150 ns A 220 Notes: 1. Not tested in production. 2. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU. 3. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 84 on page 112 and note 4. 13.3.3 Auxiliary Voltage Detector (AVD) Thresholds TA = -40 to 85C, unless otherwise specified Symbol Parameter Conditions Min Typ Max 4.401) 3.901) 3.201) 4.70 4.10 3.40 5.00 4.30 3.60 4.30 3.70 2.90 4.60 3.90 3.20 4.901) 4.101) 3.401) Unit VIT+(AVD) 1=>0 AVDF flag toggle threshold (VDD rise) High Threshold Med. Threshold Low Threshold VIT-(AVD) 0=>1 AVDF flag toggle threshold (VDD fall) High Threshold Med. Threshold Low Threshold Vhys AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 150 mV VIT- Voltage drop between AVD flag set and LVD reset activation VDD fall 0.45 V V Note: 1. Not tested in production. 13.3.4 Internal RC Oscillator and PLL The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Symbol Parameter Conditions Min Typ Max VDD(RC) Internal RC Oscillator operating voltage 2.4 5.5 VDD(x4PLL) x4 PLL operating voltage 2.4 3.3 VDD(x8PLL) x8 PLL operating voltage 3.3 5.5 tSTARTUP 94/133 1 PLL Startup time 60 Unit V PLL input clock (fPLL) cycles ST7LITE2 OPERATING CONDITIONS (Cont'd) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables. 13.3.4.1 RC oscillator and PLL characteristics (tested for TA = -40 to +85C) @ VDD = 4.5 to 5.5V Symbol Parameter Conditions fRC 1) Internal RC oscillator fre- RCCR = FF (reset value), TA=25C,VDD=5V quency 1) RCCR = RCCR03 ), TA=25C,VDD=5V ACCRC Accuracy of Internal RC oscillator with RCCR=RCCR03) Min Typ Max 760 Unit kHz 1000 TA=25C, VDD=4.5 to 5.5V -1 +1 % TA=-40 to +85C, VDD=5V -5 +2 % -22) +22) % TA=0 to +85C, VDD=4.5 to 5.5V IDD(RC) RC oscillator current conTA=25C, VDD=5V sumption tsu(RC) RC oscillator setup time A 9702) 103) TA=25C, VDD=5V 2) s fPLL x8 PLL input clock tLOCK PLL Lock time6) 2 ms tSTAB PLL Stabilization time6) 4 ms % ACCPLL x8 PLL Accuracy tw(JIT) PLL jitter period JITPLL PLL jitter (fCPU/fCPU) IDD(PLL) 1 MHz fRC = 1MHz@TA=25C, VDD=4.5 to 5.5V 0.15) fRC = 1MHz@TA=-40 to +85C, VDD=5V 0.15) % fRC = 1MHz 1254) s 14) % 6002) A PLL current consumption TA=25C Notes: 1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. Data based on characterization results, not tested in production 3. See "INTERNAL RC OSCILLATOR ADJUSTMENT" on page 23 4. Guaranteed by design. 5. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy. 6. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24. 95/133 1 ST7LITE2 OPERATING CONDITIONS (Cont'd) 13.3.4.2 RC oscillator and PLL characteristics (tested for TA = -40 to +85C) @ VDD = 2.7 to 3.3V Symbol Parameter Conditions fRC 1) Internal RC oscillator fre- RCCR = FF (reset value), TA=25C, VDD= 3.0V quency 1) RCCR=RCCR13) ,TA=25C,VDD= 3V ACCRC Accuracy of Internal RC TA=25C,VDD=3V oscillator when calibrated TA=25C,VDD=2.7 t 3.3V with RCCR=RCCR12)3) TA=-40 to +85C,VDD=3V IDD(RC) RC oscillator current conTA=25C,VDD=3V sumption tsu(RC) RC oscillator setup time fPLL x4 PLL input clock tLOCK PLL Lock time6) tSTAB PLL Stabilization Min Typ Unit kHz 700 -2 +2 % -25 +25 % 15 % -15 A 7002) 103) TA=25C,VDD=3V time6) Max 560 s 0.72) MHz 2 ms 4 ms fRC = 1MHz@TA=25C,VDD=2.7 to 3.3V 0.15) % fRC = 1MHz@TA=40 to +85C,VDD= 3V 0.15) % fRC = 1MHz 1254) s ACCPLL x4 PLL Accuracy tw(JIT) PLL jitter period JITPLL PLL jitter (fCPU/fCPU) IDD(PLL) PLL current consumption TA=25C 14) % 1902) A Notes: 1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. Data based on characterization results, not tested in production 3. See "INTERNAL RC OSCILLATOR ADJUSTMENT" on page 23. 4. Guaranteed by design. 5. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy 6. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24. 96/133 1 ST7LITE2 OPERATING CONDITIONS (Cont'd) Figure 53. RC Osc Freq vs VDD @ TA=25C (Calibrated with RCCR1: 3V @ 25C) Figure 54. RC Osc Freq vs VDD (Calibrated with RCCR0: 5V@ 25C) 0.90 Output Freq. (MHz) Output Freq (MHz) 1.00 0.80 0.70 0.60 0.50 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 4 -45 0 25 90 105 130 2.5 3 3.5 4 4.5 5 5.5 6 Vdd (V) VDD (V) Figure 55. Typical RC oscillator Accuracy vs temperature @ VDD=5V (Calibrated with RCCR0: 5V @ 25C) Figure 56. RC Osc Freq vs VDD and RCCR Value 1.80 Output Freq. (MHz) 1.60 2 (*) RC Accuracy 1 0 (*) -1 -2 -3 -4 -5 ( ) * -45 0 25 Temperature (C) (*) tested in production 85 125 1.40 1.20 1.00 rccr=00h 0.80 rccr=64h 0.60 rccr=80h 0.40 rccr=C0h 0.20 rccr=FFh 0.00 2.4 2.7 3 3.3 3.75 4 4.5 5 5.5 6 Vdd (V) 97/133 1 ST7LITE2 OPERATING CONDITIONS (Cont'd) Figure 57. PLL fCPU/fCPU versus time fCPU/fCPU Max t 0 Min tw(JIT) Figure 58. PLLx4 Output vs CLKIN frequency tw(JIT) Figure 59. PLLx8 Output vs CLKIN frequency 7.00 5.00 3.3 4.00 3 2.7 3.00 2.00 Output Frequency (MHz) Output Frequency (MHz) 11.00 6.00 9.00 7.00 5.5 5 5.00 4.5 4 3.00 1.00 1.00 1 1.5 2 2.5 0.85 3 1 1.5 2 2.5 External Input Clock Frequency (MHz) External Input Clock Frequency (MHz) Note: fOSC = fCLKIN/2*PLL4 0.9 Note: fOSC = fCLKIN/2*PLL8 13.3.4.3 32MHz PLL TA = -40 to 85C, unless otherwise specified Symbol Parameter VDD Voltage 1) fPLL32 Frequency 1) fINPUT Input Frequency Note 1: 32 MHz is guaranteed within this voltage range. 98/133 1 Min Typ Max 4.5 5 5.5 32 7 8 Unit V MHz 9 MHz ST7LITE2 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for vice consumption, the two current values must be the ST7 functional operating modes over temperaadded (except for HALT mode for which the clock ture range does not take into account the clock is stopped). source current consumption. To get the total de13.4.1 Supply Current TA = -40 to +85C unless otherwise specified, VDD=5.5V Symbol Parameter Conditions Typ External Clock, fCPU=1MHz 1) Supply current in RUN mode Max Internal RC, fCPU=1MHz 2.2 fCPU=8MHz 1) 7.5 External Clock, fCPU=1MHz 2) 0.8 Internal RC, fCPU=1MHz fCPU=8MHz 2) 1.8 3.7 6 Supply current in SLOW mode fCPU=250kHz 3) 1.6 2.5 Supply current in SLOW WAIT mode fCPU=250kHz 4) -40CTA+85C 1.6 1 2.5 10 TA= +125C 15 50 TA= +25C 20 30 Supply current in WAIT mode IDD Supply current in HALT mode 5) Supply current in AWUFH mode 6)7) Unit 1 12 mA A Notes: 1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 5. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results, tested in production at VDD max and fCPU max. 6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max. 7. This consumption refers to the Halt period only and not the associated run period which is software dependent. Figure 60. Typical IDD in RUN vs. fCPU Figure 61. Typical IDD in SLOW vs. fCPU 1.6 9.0 8.0 8Mhz 4Mhz 1Mhz 6.0 1.4 1.2 Idd (mA) Idd (mA) 7.0 5.0 4.0 3.0 2.0 250Khz 125Khz 62.5Hz 1.0 0.8 0.6 0.4 0.2 0.0 1.0 0.0 2.0 2.5 3.0 3.5 4.0 Vdd (V) 4.5 5.0 5.5 6.0 2 2.5 3 3.5 4 4.5 5 5.5 6 Vdd (V) 99/133 1 ST7LITE2 SUPPLY CURRENT CHARACTERISITCS (Cont'd) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Figure 64. Typical IDD in AWUFH mode at TA=25C 8Mhz 0.035 4Mhz fawu_rc ~125 KHz 0.030 1MHz 0.025 Idd(mA) Idd (mA) Figure 62. Typical IDD in WAIT vs. fCPU 0.020 0.015 0.010 0.005 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.000 6.0 2.0 2.5 3.0 3.5 Vdd (V) Figure 63. Typical IDD in SLOW-WAIT vs. fCPU 1.4 4.5 5.0 5.5 6.0 Figure 65. Typical IDD vs. Temperature at VDD = 5V and fCPU = 8MHz 250KHz 1.2 8.0 125KHz TB D 1.0 Idd (mA) 4.0 Vdd(V) 62.5Khz 0.8 0.6 0.4 25 -45 90 130 7.0 0.2 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Vdd (V) Idd (mA) 0.0 5.0 4.0 3.0 2.0 2.4 2.8 3.2 3.6 4 4.4 Vdd (V) 4.8 5.2 5.6 13.4.2 On-chip peripherals Symbol Parameter IDD(AT) 12-bit Auto-Reload Timer supply current 1) IDD(SPI) SPI supply current 2) IDD(ADC) ADC supply current when converting 3) Conditions Typ fCPU=4MHz VDD=3.0V 300 fCPU=8MHz VDD=5.0V 1000 fCPU=4MHz VDD=3.0V 50 fCPU=8MHz VDD=5.0V 300 fADC=4MHz VDD=3.0V 250 VDD=5.0V 1100 Unit A Notes: 1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM mode at fcpu=8MHz. 2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communication (data sent equal to 55h). 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with amplifier off. 100/133 1 ST7LITE2 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 13.5.1 General Timings Symbol tc(INST) tv(IT) Parameter 1) Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10 Conditions fCPU=8MHz 3) fCPU=8MHz Min Typ 2) Max Unit 2 3 12 tCPU 250 375 1500 ns 10 22 tCPU 1.25 2.75 s Notes: 1. Guaranteed by Design. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 13.5.2 Auto Wakeup from Halt Oscillator (AWU) Symbol Parameter 1) fAWU AWU Oscillator Frequency tRCSRT AWU Oscillator startup time Conditions Min Typ Max Unit 50 125 250 kHz 50 s Note: 1. Guaranteed by Design. 101/133 1 ST7LITE2 CLOCK AND TIMING CHARACTERISTICS (Cont'd) 13.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with eight different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as Symbol Parameter Conditions fCrOSC Crystal Oscillator Frequency 1) CL1 Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS) CL2 Supplier fCrOSC [MHz] 2 Murata 4 8 16 close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...). Min Reference CL1 4) [pF] CL2 4) [pF] SMD CSTCC2M00G56-R0 (47) (47) Type Max Unit 16 MHz See table below Typical Ceramic Resonators2) 3) Typ 2 pF Rd Supply Voltage Temperature [] Range [V] Range [C] 0 SMD CSTCR4M00G53-R0 (15) (15) 0 LEAD CSTLS4M00G53-B0 (15) (15) 0 SMD CSTCE8M00G52-R0 (10) (10) 0 LEAD CSTLS8M00G53-B0 (15) (15) 0 2.4V to 5.5V -40 to 85 SMD CSTCE16M0V51-R0 (5) (5) 0 LEAD CSTLS16M0X53-B0 (15) (15) 0 3.3V to 5.5V 4.5V to 5.5V LEAD CSALS16M0X55-B0 7 7 1.5k 3.8V to 5.5V Notes: 1. When PLL is used, please refer to the PLL characteristics chapter and to "SUPPLY, RESET AND CLOCK MANAGEMENT" on page 23 chapter (fCrOSC min. is 8 Mhz with PLL). 2. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators, please consult www.murata.com 3. SMD = -R0: Plastic tape package ( =180mm) . LEAD = -B0: Bulk 4. () means load capacitor built in resonator Figure 66. Typical application with a crystal or ceramic resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS i2 fOSC CL1 OSC1 RESONATOR CL2 OSC2 Rd 102/133 ST7LITE2 ST7LITE2 13.6 MEMORY CHARACTERISTICS TA = -40C to 85C, unless otherwise specified 13.6.1 RAM and Hardware Registers Symbol VRM Parameter Data retention mode 1) Conditions HALT mode (or RESET) Min Typ Max 1.6 Unit V 13.6.2 FLASH Program Memory Symbol VDD tprog Parameter Min Programming time for 1~32 bytes 2) TA=-40 to +85C Programming time for 1.5 kBytes TA=+25C 4) tRET Data retention Write erase cycles Supply current Typ 2.4 Operating voltage for Flash write/erase NRW IDD Conditions TA=+55C 3) Max Unit 5.5 V 5 10 ms 0.24 0.48 s 20 years TA=+25C 10K7) Read / Write / Erase modes fCPU = 8MHz, VDD = 5.5V No Read/No Write Mode Power down mode / HALT cycles 0 2.66) mA 100 0.1 A A 13.6.3 EEPROM Data Memory Symbol Parameter Conditions VDD Operating voltage for EEPROM write/erase tprog Programming time for 1~32 bytes TA=-40 to +85C Data retention 4) TA=+55C 3) Write erase cycles TA=+25C tret NRW Min Typ 2.4 5 Max Unit 5.5 V 10 ms 20 years 300K7) cycles Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 32 bytes can be programmed at a time. 3. The data retention time increases when the TA decreases. 4. Data based on reliability test results and monitored in production. 5. Data based on characterization results, not tested in production. 6. Guaranteed by Design. Not tested in production. 7. Design target value pending full product characterization. 103/133 ST7LITE2 13.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. 13.7.1.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It Symbol should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Parameter Level/ Class Conditions VFESD Voltage limits to be applied on any I/O pin to induce a VDD=5V, TA=+25C, fOSC=8MHz functional disturbance conforms to IEC 1000-4-2 3B VFFTB Fast transient voltage burst limits to be applied V =5V, TA=+25C, fOSC=8MHz through 100pF on VDD and VDD pins to induce a func- DD conforms to IEC 1000-4-4 tional disturbance 3B 13.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin. Symbol Parameter Conditions Monitored Frequency Band 0.1MHz to 30MHz SEMI Peak level VDD=5V, TA=+25C, 30MHz to 130MHz SO20 package, conforming to SAE J 1752/3 130MHz to 1GHz SAE EMI Level Note: 1. Data based on characterization results, not tested in production. 104/133 Max vs. [fOSC/fCPU] 8/4MHz 16/8MHz 9 17 31 36 25 27 3.5 4 Unit dBV - ST7LITE2 EMC CHARACTERISTICS (Cont'd) 13.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. 13.7.3.1 Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22A114A/A115A standard. Absolute Maximum Ratings Symbol VESD(HBM) Ratings Electro-static discharge voltage (Human Body Model) Conditions TA=+25C Maximum value 1) Unit 4000 V Note: 1. Data based on characterization results, not tested in production. 13.7.3.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical Sensitivities Symbol LU DLU Parameter Conditions Class 1) Static latch-up class TA=+25C A Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25C A Note: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 105/133 ST7LITE2 13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Min Typ Max VIL Input low level voltage VSS - 0.3 0.3xVDD VIH Input high level voltage 0.7xVDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis 1) IL Input leakage current VSSVINVDD IS Static current consumption induced by each floating input pin2) Floating input mode RPU Weak pull-up equivalent resistor3) VIN=V VDD=5V VDD=3V SS CIO 400 Unit V mV 1 A 400 50 120 160 I/O pin capacitance 5 tf(IO)out Output high to low level fall time 1) 25 tr(IO)out Output low to high level rise time 1) tw(IT)in External interrupt pulse time 4) CL=50pF Between 10% and 90% 25 1 250 k pF ns tCPU Notes: 1. Data based on characterization results, not tested in production. 2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 67). Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in production. This value depends on VDD and temperature values. 3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 68). 4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. Figure 67. Two typical applications with unused I/O Pin VDD ST7XXX 10k 10k UNUSED I/O PORT UNUSED I/O PORT ST7XXX Caution: During normal operation the ICCCLK pin must be pulled-up, internally or externally (external pull-up of 10k mandatory in noisy environment. This is to avoid entering ICC mode unexpectedly during a reset. Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost. Figure 68. Typical IPU vs. VDD with VIN=VSS 90 Ta=1 40C 80 Ta=9 5C 70 Ta=2 5C Ta=-45 C Ipu(uA) 60 50 TO BE CHARACTERIZED 40 30 20 10 0 2 106/133 2.5 3 3.5 4 4.5 Vdd(V) 5 5.5 6 ST7LITE2 I/O PORT PIN CHARACTERISTICS (Cont'd) 13.8.2 Output Driving Current Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol Parameter Conditions Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 72) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 74) IIO=+5mA TA85C TA85C 1.0 1.2 IIO=+2mA TA85C TA85C 0.4 0.5 IIO=+20mA, TA85C TA85C 1.3 1.5 IIO=+8mA TA85C TA85C 0.75 0.85 Output high level voltage for an I/O pin when 4 pins are sourced at same time Output low level voltage for a standard I/O pin when 8 pins are sunk at same time VOL 1)3) (see Figure 70) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time Output high level voltage for an I/O pin VOH 2)3) when 4 pins are sourced at same time (see Figure 77) VDD=3.3V IIO=-2mA Output low level voltage for a standard I/O pin when 8 pins are sunk at same time VOL 1)3) (see Figure 71) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time VOH 2)3) Max Unit IIO=-5mA, TA85C VDD-1.5 TA85C VDD-1.6 Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 80) VDD=2.7V VOH 2) VDD=5V VOL 1) Min TA85C VDD-0.8 TA85C VDD-1.0 IIO=+2mA TA85C TA85C 0.5 0.6 IIO=+8mA TA85C TA85C 0.5 0.6 IIO=-2mA TA85C VDD-0.8 TA85C VDD-1.0 IIO=+2mA TA85C TA85C 0.6 0.7 IIO=+8mA TA85C TA85C 0.6 0.7 IIO=-2mA V TA85C VDD-0.9 TA85C VDD-1.0 Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Not tested in production, based on characterization results. Figure 70. Typical VOL at VDD=2.7V (standard) 0.70 0.60 0.60 0.50 0.50 -45 0C 0.40 0.30 TO BE CHARACTERIZED 25C 90C 130C 0.20 VOL at VDD=2.7V VOL at VDD=2.4V Figure 69. Typical VOL at VDD=2.4V (standard) 0.40 -45C 0C 25C 90C 130C 0.30 0.20 0.10 0.10 0.00 0.00 0.01 1 lio (mA) 2 0.01 1 2 lio (mA) 107/133 ST7LITE2 I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 71. Typical VOL at VDD=3.3V (standard) Figure 72. Typical VOL at VDD=5V (standard) 0.70 0.80 0.60 VOL at VDD=5V VOL at VDD=3.3V 0.70 0.50 -45C 0C 25C 90C 130C 0.40 0.30 0.20 0.60 -45C 0C 25C 90C 130C 0.50 0.40 0.30 0.20 0.10 0.00 0.10 0.01 1 2 3 4 5 lio (mA) 0.00 0.01 1 2 3 lio (mA) Figure 73. Typical VOL at VDD=2.4V (high-sink) Figure 75. Typical VOL at VDD=3V (high-sink) 1.00 1.20 0.90 VOL at VDD=2.4V (HS) 0.70 -45 0C 25C 90C 130C 0.60 0.50 0.40 0.30 0.20 Vol (V) at VDD=3V (HS) 1.00 0.80 0.80 -45 0C 0.60 25C 90C 0.40 130C 0.20 0.10 0.00 0.00 6 7 8 9 6 10 lio (mA) 2. 50 2. 00 -45 0C 1. 50 25C 1. 00 90C 0. 50 130C 0. 00 7 8 9 10 15 l i o (mA ) 108/133 20 8 9 lio (mA) Figure 74. Typical VOL at VDD=5V (high-sink) 6 7 25 30 35 40 10 15 ST7LITE2 I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 78. Typical VDD-VOH at VDD=3V Figure 76. Typical VDD-VOH at VDD=2.4V 1.60 1.60 1.40 1.20 -45C 0C 25C 90C 130C 1.00 0.80 0.60 VDD-VOH at VDD=3V VDD-VOH at VDD=2.4V 1.40 0.40 1.20 -45C 0C 25C 90C 130C 1.00 0.80 0.60 0.40 0.20 0.20 0.00 0.00 -0.01 -1 -0.01 -2 -1 -3 Figure 79. Typical VDD-VOH at VDD=4V Figure 77. Typical VDD-VOH at VDD=2.7V 1.20 2.50 1.00 2.00 0.80 -45C 0C 25C 90C 130C 0.60 0.40 VDD-VOH at VDD=4V VDD-VOH at VDD=2.7V -2 lio (mA) lio (mA) -45C 0C 25C 90C 130C 1.50 1.00 0.50 0.20 0.00 0.00 -0.01 -1 -0.01 -2 -1 -2 -3 -4 -5 lio (mA) lio(mA) Figure 80. Typical VDD-VOH at VDD=5V 2.00 VDD-VOH at VDD=5V 1.80 1.60 1.40 1.20 1.00 TO BE CHARACTERIZED 0.80 0.60 -45C 0C 25C 90C 130C 0.40 0.20 0.00 -0.01 -1 -2 -3 -4 -5 lio (mA) 109/133 ST7LITE2 I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 81. Typical VOL vs. VDD (standard I/Os) 0.70 0.06 0.50 -45 0.40 0C 25C 0.30 90C 130C 0.20 Vol (V) at lio=0.01mA Vol (V) at lio=2mA 0.60 0.10 0.00 0.05 -45 0.04 0C 0.03 25C 90C 0.02 130C 0.01 0.00 2.4 2.7 3.3 5 2.4 2.7 VDD (V) 3.3 5 VDD (V) Figure 82. Typical VOL vs. VDD (high-sink I/Os) 1.00 0.60 0.50 -45 0.40 0C 25C 0.30 90C 130C 0.20 0.10 VOL vs VDD (HS) at lio=20mA VOL vs VDD (HS) at lio=8mA 0.70 0.90 0.80 0.70 -45 0.60 0C 0.50 25C 0.40 90C 0.30 0.20 130C 0.10 0.00 0.00 2.4 3 2.4 5 3 5 VDD (V) VDD (V) Figure 83. Typical VDD-VOH vs. VDD 1.80 1.10 VDD-VOH at lio=-5mA 1.60 1.50 -45C 0C 25C 90C 130C 1.40 1.30 1.20 1.10 1.00 VDD-VOH (V) at lio=-2mA 1.70 1.00 0.90 -45C 0.80 0C 25C 0.70 90C 130C 0.60 0.50 0.90 0.40 0.80 4 5 VDD 110/133 2.4 2.7 3 VDD (V) 4 5 ST7LITE2 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin TA = -40C to 85C, unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage VSS - 0.3 0.3xVDD VIH Input high level voltage 0.7xVDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis 1) VOL RON Output low level voltage 2) Pull-up equivalent resistor 3) 1) tw(RSTL)out Generated reset pulse duration th(RSTL)in External reset pulse hold time 4) tg(RSTL)in Filtered glitch duration 2 VDD=5V V IIO=+5mA TA85C TA85C 0.5 1.0 1.2 IIO=+2mA TA85C TA85C 0.2 0.4 0.5 VDD=5V 20 40 80 VDD=3V. 40 70 120 Internal reset sources 30 V V k s s 20 200 ns Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax and VDD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 111/133 ST7LITE2 CONTROL PIN CHARACTERISTICS (Cont'd) Figure 84. RESET pin protection when LVD is enabled.1)2)3)4) VDD Required Optional (note 3) ST72XXX RON EXTERNAL RESET INTERNAL RESET Filter 0.01F 1M PULSE GENERATOR WATCHDOG ILLEGAL OPCODE 5) LVD RESET Figure 85. RESET pin protection when LVD is disabled.1) VDD ST72XXX RON USER EXTERNAL RESET CIRCUIT INTERNAL RESET Filter 0.01F PULSE GENERATOR WATCHDOG ILLEGAL OPCODE 5) Required Note 1: - The reset network protects the device against parasitic resets. - The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). - Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in section 13.9.1 on page 111. Otherwise the reset will not be taken into account internally. - Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in section 13.2.2 on page 92. Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line. Note 3: In case a capacitive power supply is used, it is recommended to connect a 1M pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5A to the power consumption of the MCU). Note 4: Tips when using the LVD: - 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in Table 1 on page 7 and notes above) - 2. Check that the power supply is properly decoupled (100nF + 10F close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M pull-down on the RESET pin. - 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5F to 20F capacitor." Note 5: Please refer to "Illegal Opcode Reset" on page 88 for more details on illegal opcode reset conditions. 112/133 ST7LITE2 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol fSCK = 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) 1) Parameter Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Conditions SPI clock frequency Min Max Master fCPU=8MHz fCPU/128 = 0.0625 fCPU/4 = 2 Slave fCPU=8MHz 0 fCPU/2 = 4 SPI clock rise and fall time Slave (4 x TCPU) +150 SS hold time Slave 120 SCK high and low time Master Slave 100 90 tsu(MI) tsu(SI) Data input setup time Master Slave 100 100 th(MI) th(SI) Data input hold time Master Slave 100 100 ta(SO) Data output access time Slave 0 tdis(SO) Data output disable time Slave th(SS) tw(SCKH) tw(SCKL) tv(SO) Data output valid time th(SO) Data output hold time tv(MO) Data output valid time th(MO) Data output hold time MHz see I/O port pin description SS setup time 4) 1) Unit ns 120 240 120 Slave (after enable edge) 0 120 Master (after enable edge) 0 Figure 86. SPI Slave Timing Diagram with CPHA=0 3) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) MSB OUT see note 2 tsu(SI) MOSI INPUT tv(SO) th(SO) BIT6 OUT tdis(SO) tr(SCK) tf(SCK) LSB OUT see note 2 th(SI) MSB IN BIT1 IN LSB IN Notes: 1. Data based on design simulation and/or characterisation results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 4. Depends on fCPU. For example, if fCPU = 8MHz, then TCPU = 1/ fCPU = 125ns and tSU(SS) = 550ns 113/133 ST7LITE2 COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 87. SPI Slave Timing Diagram with CPHA=1 1) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT see note 2 tv(SO) th(SO) MSB OUT HZ tsu(SI) BIT6 OUT LSB OUT see note 2 th(SI) MSB IN MOSI INPUT tdis(SO) tr(SCK) tf(SCK) BIT1 IN LSB IN Figure 88. SPI Master Timing Diagram 1) SS INPUT tc(SCK) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT MOSI OUTPUT th(MI) MSB IN tv(MO) see note 2 tr(SCK) tf(SCK) BIT6 IN LSB IN th(MO) MSB OUT BIT6 OUT LSB OUT see note 2 Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. 114/133 ST7LITE2 13.11 10-BIT ADC CHARACTERISTICS Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified. Symbol fADC VAIN Parameter Conditions Conversion voltage range 2) RAIN External input resistor Internal sample and hold capacitor IADC VSSA - Sample capacitor loading time - Hold conversion time Max Unit 4 MHz VDDA V 10 3) k 6 0 Stabilization time after ADC enable Conversion time (Sample+Hold) tADC Typ 1) ADC clock frequency CADC tSTAB Min pF 4) s 3.5 fCPU=8MHz, fADC=4MHz 4 10 1/fADC Analog Part 1 Digital Part 0.2 mA Figure 89. Typical Application with ADC VDD VT 0.6V RAIN AINx 10-Bit A/D Conversion VAIN CAIN VT 0.6V IL 1A CADC 6pF ST72XXX Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD-VSS=5V. They are given only as design guidelines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS. 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the fi rst tLOAD. The first conversion after the enable is then always valid. 115/133 ST7LITE2 ADC CHARACTERISTICS (Cont'd) ADC Accuracy with VDD=5.0V Symbol Parameter Conditions |ET| Total unadjusted error |EO| Offset error 2) |EG| Gain Error 2) |ED| 2) fCPU=8MHz, fADC=4MHz 1), VDD=5.0V Differential linearity error |EL| Integral linearity error 2) 2) Typ Max 1) 3 6 1.5 5 2 4.5 2.5 4.5 2.5 4.5 Unit LSB Notes: 1. Data based on characterization results over the whole temperature range, not tested in production. 2. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 13.8 does not affect the ADC accuracy. Figure 90. ADC Accuracy Characteristics with amplifier disabled Digital Result ADCDR EG 1023 1022 1LSB 1021 IDEAL V -V DD SS = -------------------------------- 1024 (2) ET (3) 7 (1) 6 5 EO 4 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line EL 3 ED 2 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 1 LSBIDEAL 1 Vin (LSBIDEAL) 0 1 VSS 116/133 2 3 4 5 6 7 1021 1022 1023 1024 VDD ST7LITE2 ADC CHARACTERISTICS (Cont'd) Figure 91. ADC Accuracy Characteristics with amplifier enabled Digital Result ADCDR EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 704 1LSB IDEAL V -V DD SS = -------------------------------- 1024 (2) ET ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (3) (1) EO EL ED 1 LSBIDEAL 108 Vin (LSBIDEAL) 0 1 VSS 2 3 4 5 6 7 701 702 703 704 62.5mV 430mV Vin (OPAMP) Note: When the AMPSEL bit in the ADCDRL register is set, it is mandatory that fADC be less than or equal to 2 MHz. (if fCPU=8MHz. then SPEED=0, SLOW=1). Vout (ADC input) Vmax Noise Vmin 0V 430mV Vin (OPAMP input) 117/133 ST7LITE2 ADC CHARACTERISTICS (Cont'd) Symbol VDD(AMP) Parameter Conditions Amplifier operating voltage Min 350 VDD=5V 0 500 Amplifier output offset voltage5) VDD=5V VSTEP Step size for monotonicity3) VDD=3.6V 3.5 VDD=5V 4.89 Linearity Output Voltage Response Vmin Output Linearity Min Voltage 200 mV mV 8 VINmax = 430mV, VDD=5V 3.65 3.94 200 Notes: 1. Data based on characterization results over the whole temperature range, not tested in production. 2. For precise conversion results it is recommended to calibrate the amplifier at the following two points: - offset at VINmin = 0V - gain at full scale (for example VIN=430mV) 3. Monotonicity guaranteed if VIN increases or decreases in steps of min. 5mV. 4. Please refer to the Application Note AN1830 for details of TE% vs Vin. 5. Refer to the offset variation in temperature below 13.11.1 Amplifier output offset variation The offset is quite sensitive to temperature variations. In order to ensure a good reliability in measurements, the offset must be recalibrated periodically i.e. during power on or whenever the device is reset depending on the customer application and during temperature variation. The table below gives the typical offset variation over temperature: Typical Offset Variation (LSB) -45 -20 +25 +90 -12 -7 +13 118/133 mV Linear Gain2) Amplified Analog input V 5.5 0 VOFFSET Output Linearity Max Voltage Unit 3.6 Amplifier input voltage4) Vmax Max VDD=3.6V VIN Gain factor Typ UNIT C LSB V mV ST7LITE2 14 PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA Figure 92. 20-Pin Plastic Small Outline Package, 300-mil Width D Dim. h x 45x L A1 A c mm Min Typ inches Max Min Typ Max A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 a e B e E H 1.27 0.050 H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 L 0.40 8 0 8 1.27 0.016 0.050 Number of Pins N 20 Figure 93. 20-Pin Plastic Dual In-Line Package, 300-mil Width Dim. A2 A mm Min Typ A A1 b eB D1 b2 e D 20 11 10 Min Typ 5.33 Max 0.210 A1 0.38 A2 2.92 3.30 4.95 0.115 0.130 0.195 0.015 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 D 24.89 26.16 26.92 0.980 1.030 1.060 D1 0.13 e E1 1 c L inches Max 0.005 2.54 eB 0.100 10.92 0.430 E1 6.10 6.35 7.11 0.240 0.250 0.280 L 2.92 3.30 3.81 0.115 0.130 0.150 Number of Pins N 20 119/133 ST7LITE2 PACKAGE CHARACTERISTICS (Cont'd) Table 21. THERMAL CHARACTERISTICS Symbol Ratings SO20 DIP20 Value Unit 125 63 C/W RthJA Package thermal resistance (junction to ambient) TJmax Maximum junction temperature 1) 150 C PDmax Power dissipation 2) 500 mW Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation depending on the ports used in the application. 120/133 ST7LITE2 14.2 SOLDERING INFORMATION In accordance with the RoHS European directive, all STMicroelectronics packages have been converted to lead-free technology, named ECOPACKTM. TM packages are qualified according ECOPACK to the JEDEC STD-020C compliant soldering profile. Detailed information on the STMicroelectronics ECOPACKTM transition program is available on www.st.com/stonline/leadfree/, with specific technical Application notes covering the main technical aspects related to lead-free conversion (AN2033, AN2034, AN2035, AN2036). Backward and forward compatibility: The main difference between Pb and Pb-free soldering process is the temperature range. - ECOPACKTM TQFP, SDIP and SO packages are fully compatible with Lead (Pb) containing soldering process (see application note AN2034) - TQFP, SDIP and SO Pb-packages are compatible with Lead-free soldering process, nevertheless it's the customer's duty to verify that the Pbpackages maximum temperature (mentioned on the Inner box label) is compatible with their Leadfree soldering temperature. Table 22. Soldering Compatibility (wave and reflow soldering process) Package SDIP & PDIP TQFP and SO Plating material devices Sn (pure Tin) NiPdAu (Nickel-palladium-Gold) Pb solder paste Yes Yes Pb-free solder paste Yes * Yes * * Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label) is compatible with their Lead-free soldering process. 121/133 ST7LITE2 15 DEVICE CONFIGURATION Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). ST7FLITE2 devices are FLASH versions. ST7PLITE2 devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory programmed FLASH devices. ST7FLITE2 devices are shipped to customers with a default program memory content (FFh), while FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the FASTROM devices are factory configured. OSCRANGE External on OSC1 Clock source: on PB4 CLKIN Reserved OPT7 = Reserved, must always be 1. OSCRANGE Typ. frequency range with Resonator 1~2MHz 0 0 0 MP 2~4MHz 0 0 1 MS 4~8MHz 0 1 0 HS 8~16MHz 0 1 1 VLP 32.768kHz 1 0 0 Res. Default Value 122/133 1 1 1 1 1 1 1 0 SEC0 0.5k 0 0 1k 0 1 2k 1 0 4k 1 1 OPTION BYTE 1 7 0 FMP FMP PLL PLL SEC1 SEC0 R W x4x8 OFF 1 1 OPT0 = FMP_W FLASH write protection This option indicates if the FLASH program memory is write protected. Warning: When this option is selected, the program memory (and the option bit itself) can never be erased or programmed again. 0: Write protection off 1: Write protection on 0 1 1 SEC1 OPTION BYTE 0 7 OSCRANGE 2:0 0 OPT1 = FMP_R Read-out protection Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and section 4.5 on page 14 for more details 0: Read-out protection off 1: Read-out protection on OPT6:4 = OSCRANGE[2:0] Oscillator range When the internal RC oscillator is not selected (Option OSC=1), these option bits select the range of the resonator oscillator current source or the external clock source. LP 1 Sector 0 Size OPTION BYTE 0 0 0 OPT3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 according to the following table. The two option bytes allow the hardware configuration of the microcontroller to be selected. The option bytes can be accessed only in programming mode (for example using a standard ST7 programming tool). 1 1 Note: When the internal RC oscillator is selected, the OSCRANGE option bits must be kept at their default value in order to select the 256 clock cycle delay (see Section 7.5). 15.1 OPTION BYTES 2 2 1 0 0 1 1 PLL32 WDG WDG OSC LVD1 LVD0 OFF SW HALT 1 0 1 1 1 1 ST7LITE2 OPTION BYTES (Cont'd) OPT3:2 = LVD[1:0] Low voltage detection selection These option bits enable the LVD block with a selected threshold as shown in Table 23. OPTION BYTE 1 OPT7 = PLLx4x8 PLL Factor selection. 0: PLLx4 1: PLLx8 Table 23. LVD Threshold Configuration Configuration OPT6 = PLLOFF PLL disable. 0: PLL enabled 1: PLL disabled (by-passed) OPT5 = PLL32OFF 32MHz PLL disable. 0: PLL32 enabled 1: PLL32 disabled (by-passed) OPT4 = OSC RC Oscillator selection 0: RC oscillator on 1: RC oscillator off Notes: 1. 1% RC oscillator available on ST7LITE25 and ST7LITE29 devices only 2. If the RC oscillator is selected, then to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. LVD1 LVD0 LVD Off 1 1 Highest Voltage Threshold (4.1V) 1 0 Medium Voltage Threshold (3.5V) 0 1 Lowest Voltage Threshold (2.8V) 0 0 OPT1 = WDG SW Hardware or Software Watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) OPT0 = WDG HALT Watchdog Reset on Halt This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode Table 24. List of valid option combinations VDD range Operating conditions Clock Source Internal RC 1%1) 2.4V - 3.3V External clock or oscillator (depending on OPT6:4 selection) Internal RC 1% 1) 3.3V - 5.5V External clock or oscillator (depending on OPT6:4 selection) PLL off x4 x8 off x4 x8 off x4 x8 off x4 x8 Typ fCPU 0.7MHz @3V 2.8MHz @3V 0-4MHz 4MHz 1MHz @5V 8MHz @5V 0-8MHz 8 MHz OSC 0 0 1 1 0 0 1 1 Option Bits PLLOFF PLLx4x8 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 Note 1: Configuration available on ST7LITE25 and ST7LITE29 devices only Note: see Clock Management Block diagram in Figure 13 123/133 ST7LITE2 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the FASTROM contents and the list of the selected options (if any). The FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics us- ing the correctly completed OPTION LIST appended on page 125. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Table 25. Supported part numbers Part Number Program Memory (Bytes) RAM (Bytes) ST7FLITE20F2B6 ST7FLITE25F2M6 8K FLASH 384 ST7FLITE29F2B6 ST7PLITE20F2B6 8K FASTROM 384 ST7PLITE29F2B6 ST7PLITE29F2M6 Contact ST sales office for product availability 124/133 SO20 -40C to 85C 256 DIP20 SO20 DIP20 SO20 DIP20 - ST7PLITE20F2M6 ST7PLITE25F2M6 - Package DIP20 256 ST7FLITE29F2M6 ST7PLITE25F2B6 Temp. Range - ST7FLITE20F2M6 ST7FLITE25F2B6 Data EEPROM (Bytes) SO20 -40C to 85C DIP20 SO20 DIP20 SO20 ST7LITE2 ST7LITE2 FASTROM MICROCONTROLLER OPTION LIST Customer Address .......................................................................... .......................................................................... .......................................................................... Contact .......................................................................... Phone No .......................................................................... Reference/FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): --------------------------------- | ----------------------------------------- | FASTROM DEVICE: 8K --------------------------------- | ----------------------------------------- | SO20: | [ ] ST7PLITE20F2M6 | | [ ] ST7PLITE25F2M6 | | [ ] ST7PLITE29F2M6 | DIP20: | [ ] ST7PLITE20F2B6 | | [ ] ST7PLITE25F2B6 | | [ ] ST7PLITE29F2B6 | Warning: Addresses 1000h, 1001h, FFDEh and FFDFh are reserved areas for ST to program RCCR0 and RCCR1 (see section 7.1 on page 23). Conditioning (do not specify for DIP package): [ ] Tape & Reel [ ] Tube Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ " Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: DIP20/S020 (8 char. max) : _ _ _ _ _ _ _ _ Watchdog Selection: [ ] Software Activation [ ] Hardware Activation Watchdog Reset on Halt: [ ] Reset [ ] No Reset LVD Reset [ ] Disabled [ ] Enabled [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold Sector 0 size: [ ] 0.5K [ ] 1K Readout Protection: FLASH write Protection: [ ] Disabled [ ] Disabled [ ] Enabled [ ] Enabled Clock Source Selection: [ ] Resonator: [ ] VLP: Very Low power resonator (32 to 100 kHz) [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) [ ] External Clock: [ ] On OSC1 [ ] On PB4 [ ] Internal RC Oscillator (ST7PLITE25 and ST7PLITE29 only) PLL [ ] Disabled [ ] PLLx4 PLL32 [ ] Disabled [ ] Enabled [ ] 2K [ ] 4K [ ] PLLx8 Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes .......................................................................... Date: .......................................................................... Signature: .......................................................................... Important note: Not all configurations are available. See Table 24 on page 123 for authorized option byte combinations. 125/133 ST7LITE2 15.3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtained from the STMicroelectronics Internet site: http//www.st.com. Tools from these manufacturers include C compliers, evaluation tools, emulators and programmers. Emulators Two types of emulators are available from ST for the ST7LITE2 family: ST7 DVP3 entry-level emulator offers a flexible and modular debugging and programming solution. SO20 packages need a specific connection kit (refer to Table 26) ST7 EMU3 high-end emulator is delivered with everything (probes, TEB, adapters etc.) needed to start emulating the ST7LITE2. To configure it to emulate other ST7 subfamily devices, the active probe for the ST7EMU3 can be changed and the ST7EMU3 probe is designed for easy interchange of TEBs (Target Emulation Board). See Table 26. In-circuit Debugging Kit Two configurations are available from ST: ST7FLIT2-IND/USB: Low-cost In-Circuit Debugging kit from Softec Microsystems. Includes STX-InDART/USB board (USB port) and a specific demo board for ST7FLITE29 (DIP16) (A promotion package of 15 STFLIT2IND/USB can be ordered with the following order code: STFLIT2-IND/15) STxF-INDART/USB (A promotion package of 15 STxF-INDART/USB can be ordered with the following order code: STxF-INDART) Flash Programming tools ST7-STICK ST7 In-circuit Communication Kit, a complete software/hardware package for programming ST7 Flash devices. It connects to a host PC parallel port and to the target board or socket board via ST7 ICC connector. ICC Socket Boards provide an easy to use and flexible means of programming ST7 Flash devices. They can be connected to any tool that supports the ST7 ICC interface, such as ST7 EMU3, ST7-DVP3, inDART, ST7-STICK, or many third-party development tools. Evaluation boards One evaluation tool is available from ST: ST7FLIT2-COS/COM: STReal time starter kit from Cosmic software Table 26. STMicroelectronics Development Tools Emulation Supported Products ST7FLITE20 ST7FLITE25 ST7FLITE29 ST7 DVP3 Series Programming ST7 EMU3 series Emulator Connection kit Emulator Active Probe & T.E.B. ICC Socket Board ST7MDT10-DVP3 ST7MDT10-20/ DVP ST7MDT10-EMU3 ST7MDT10-TEB ST7SB10/123 1) Note 1: Add suffix /EU, /UK, /US for the power supply of your region. 126/133 ST7LITE2 15.4 ST7 APPLICATION NOTES Table 27. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE INAN1812 PUT VOLTAGES EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 IC COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR IC SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF IC BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141 AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS AN1130 WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 EMULATED 16 BIT SLAVE SPI AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS AN1753 SOFTWARE UART USING 12-BIT ART 127/133 ST7LITE2 Table 27. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK REFERENCE NOTE PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141 AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264 AN2200 GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB PRODUCT OPTIMIZATION AN 982 USING ST7 WITH CERAMIC RESONATOR AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLAAN1530 TOR AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE AN1946 SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC AN1953 PFC FOR ST7MC STARTER KIT AN1971 ST7LITE0 MICROCONTROLLED BALLAST PROGRAMMING AND TOOLS AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN 128/133 ST7LITE2 Table 27. ST7 Application Notes IDENTIFICATION AN1039 AN1064 AN1071 AN1106 DESCRIPTION ST7 MATH UTILITY ROUTINES WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROAN1179 GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL AN1603 USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK) AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY AN1905 ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY SYSTEM OPTIMIZATION AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09 AN2009 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC AN2030 BACK EMF DETECTION DURING PWM ON TIME BY ST7MC 129/133 ST7LITE2 16 IMPORTANT NOTES 16.1 EXECUTION OF BTJX INSTRUCTION When testing the address $FF with the "BTJT" or "BTJF" instructions, the CPU may perform an incorrect operation when the relative jump is negative and performs an address page change. To avoid this issue, including when using a C compiler, it is recommended to never use address $00FF as a variable (using the linker parameter for example). 16.2 ADC CONVERSION SPURIOUS RESULTS Spurious conversions occur with a rate lower than 50 per million. Such conversions happen when the measured voltage is just between 2 consecutive digital values. Workaround A software filter should be implemented to remove erratic conversion results whenever they may cause unwanted consequences. 16.3 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION When the ADC is enabled after being powered down (for example when waking up from HALT, ACTIVE-HALT or setting the ADON bit in the ADCCSR register), the first conversion (8-bit or 10bit) accuracy does not meet the accuracy specified in the datasheet. Workaround In order to have the accuracy specified in the datasheet, the first conversion after a ADC switch-on has to be ignored. Injecting a negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to ADC channel in use. 16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE When an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the CC register may be corrupted. Concurrent interrupt context The symptom does not occur when the interrupts are handled normally, i.e. when: - The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine - The interrupt request is cleared (flag reset or interrupt mask) within any interrupt routine - The interrupt request is cleared (flag reset or interrupt mask) in any part of the code while this interrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following sequence: Perform SIM and RIM operation before and after resetting an active interrupt request Ex: SIM reset flag or interrupt mask RIM 16.6 USING PB4 AS EXTERNAL INTERRUPT PB4 cannot be used as an external interrupt in HALT mode because the port pin PB4 is not active in this mode. 16.4 NEGATIVE INJECTION IMPACT ON ADC ACCURACY Injecting a negative current on an analog input pins significantly reduces the accuracy of the AD Converter. Whenever necessary, the negative injection should be prevented by the addition of a Schottky diode between the concerned I/Os and ground. 130/133 16.7 TIMEBASE 2 INTERRUPT IN SLOW MODE Timebase 2 interrupt is not available in slow mode. ST7LITE2 17 REVISION HISTORY Table 28. Revision History Date 30-August2004 Revision 3 Description of Changes Updated Figure 62. Typical IDD in WAIT vs. fCPU with correct data Added data for Fcpu @ 1MHz into Section 13.4.1 Supply Current table. EnabledProgramming Capability for EMU3, Table 26 Reset delay in section 11.1.3 on page 53 changed to 30s Altered note 1 for section 13.2.3 on page 94 removing references to RESET Removed sentence relating to an effective change only after overflow for CK[1:0], page 61 MOD00 replaced by 0Ex in Figure 37 on page 58 Added Note 2 related to Exit from Active Halt, section 11.2.5 on page 60 Changed section 11.4.2 on page 71 Changed section 11.4.3.3 on page 74 Added illegal opcode detection to page 1, section 7.6 on page 30, section 12 on page 87 Clarification of Flash read-out protection, section 4.5.1 on page 14 Added note 4 and description relating to Total Percentage in Error and Amplifier Output Offset Variation to the ADC Characteristics subsection and table, page 120 Added note 5 and description relating to Offset Variation in Temperature to ADC Characteristics subsection and table, page 120 fPLL value of 1MHz quoted as Typical instead of a Minimum in section 13.3.4.1 on page 97 Updated fSCK in section 13.10.1 on page 115 to fCPU/4 and fCPU/2 CorrectedfCPU in SLOW and SLOW WAIT modes in section 13.4.1 on page 101 Max values updated for ADC Accuracy, page 118 Socket Board development kit details added in Table 27 on page 126 Notes indicating that PB4 cannot be used as an external interrupt in HALT mode, section 16.6 on page 132 and Section 8.3 PERIPHERAL INTERRUPTS -Removed "optional" referring to VDD in Figure 5 on page 13 -Changed FMP_R option bit description in section 15.1 on page 124 -Added "CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE" on page 132 131/133 ST7LITE2 Date 07-Jul-06 132/133 Revision Description of Changes 4 Added 300K read/write cycles for EEPROM on first page Updated section 4.4 on page 13 and modified note 5 and Figure 5 Added note 2 in "EXTERNAL INTERRUPT CONTROL REGISTER (EICR)" on page 36 and changed "External Interrupt Function" on page 46 Modified read operation section in "MEMORY ACCESS" on page 16 Added note to section 7.1 on page 23 Modified one note in section 7.1 on page 23 Modified Table 4, "ST7 Clock Sources," on page 26 Added note on illegal opcode reset to section 7.5.1 on page 27 Added note to section 7.6.1 on page 29 Changed note below Figure 8 on page 17 and the last paragraph of "ACCESS ERROR HANDLING" on page 18 In section 11.2.6 on page 60, modified description of OE bits in the PWMCR register (added "after an overflow event"). Added important note to section 11.4.3.3 on page 73 Changed section 13.3.1 on page 93 (fOSC or fCLKIN replaced by fCPU and frequency values changed accordingly) Added note 1 and modified note 3 in section 13.3.4.1 on page 95 and section 13.3.4.2 on page 96 and changed table titles Added "Crystal and Ceramic Resonator Oscillators" on page 102 Changed IS value and note 2 in section 13.8.1 on page 106 Updated section 14.2 on page 121 Added note to Figure 67 on page 106 Changed notes 1 and 2 to Table 21, "THERMAL CHARACTERISTICS," on page 120 and added RthJA value for DIP20 package Changed Figure 84, Figure 85 on page 112 (and notes) and removed EMC protection circuitry in Figure 85 on page 112 (device works correctly without these components) Added note 2 to opt 4 (option byte 2) in section 15.1 on page 122 Modified section 14.2 on page 121 Changed section 15.3 on page 126 Added section 16.7 on page 130 Changed LTICR reset value in Table 2, "Hardware Register Map," on page 10 Modified "caution" in section 8.2 on page 34 Replaced bit1 by bit2 for AWUF bit in AWUCSR description in section 9.6.0.1 on page 45 Modified section 10.2.1.1 on page 46 Changed order of Section 11.3.3.2 and section 11.3.3.3 on page 66 and removed two paragraphs before section 11.3.4 on page 67 Added note 3 to section 13.3.2 on page 94 Modified section 13.10 on page 113: changed th(MO) and tv(MO), as well as tsu(SS) and th (SS) values and added note 4. The change made to tsu(SS) and th (SS) values applies from silicon rev B of this product. Changed tw(JIT) value in section 13.3.4.1 on page 95 and section 13.3.4.2 on page 96 Added note to section 13.5.2 on page 101 Changed LTCSR2 reset value in section 11.3.6 on page 67 Modified Figure 84 and Figure 85 on page 112 Added note 1 to the max column in table "ADC Accuracy with VDD=5.0V" on page 116 and modified the content of this note. ST7LITE2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 133/133