LP38841 LP38841 0.8A Ultra Low Dropout Linear RegulatorsStable with Ceramic Output Capacitors Literature Number: SNVS289B LP38841 0.8A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors General Description Features The LP38841 is a high current, fast response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in TO-220 and TO-263 packages. Dropout Voltage: 75 mV (typ) @ 0.8A load current. Quiescent Current: 30 mA (typ) at full load. Shutdown Current: 30 nA (typ) when S/D pin is low. Precision Output Voltage: 1.5% room temperature accuracy. n n n n n n n n n n n Ideal for conversion from 1.8V or 1.5V inputs Designed for use with low ESR ceramic capacitors 0.8V, 1.2V and 1.5V standard voltages available Ultra low dropout voltage (75mV @ 0.8A typ) 1.5% initial output accuracy Load regulation of 0.1%/A (typical) 30nA quiescent current in shutdown (typical) Low ground pin current at all loads Over temperature/over current protection Available in 5 lead TO220 and TO263 packages -40C to +125C junction temperature range Applications n ASIC Power Supplies In: - Desktops, Notebooks, and Graphics Cards, Servers - Gaming Set Top Boxes, Printers and Copiers n Server Core and I/O Supplies n DSP and FPGA Power Supplies n SMPS Post-Regulator Typical Application Circuit 20102801 * Minimum value required if Tantalum capacitor is used (see Application Hints). (c) 2006 National Semiconductor Corporation DS201028 www.national.com LP38841 0.8A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors September 2006 LP38841 Connection Diagrams 20102802 20102803 TO-220, Top View TO-263, Top View Pin Descriptions Pin Name BIAS OUTPUT Description The bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and provides drive voltage for the N-FET. The regulated output voltage is connected to this pin. GND This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together using the PC board copper trace material and connected to circuit ground. INPUT The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin. Because the bias voltage to operate the chip is provided seperately, the input voltage can be as low as a few hundered millivolts above the output voltage. SHUTDOWN This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if this function is not used. Ordering Information Order Number Package Type Package Drawing Supplied As LP38841S-0.8 TO263-5 TS5B Rail LP38841SX-0.8 TO263-5 TS5B Tape and Reel LP38841T-0.8 TO220-5 T05A Rail LP38841T-0.8 LB03 TO220-5 T05D Rail LP38841S-1.2 TO263-5 TS5B Rail LP38841SX-1.2 TO263-5 TS5B Tape and Reel LP38841T-1.2 TO220-5 T05A Rail LP38841T-1.2 LB03 TO220-5 T05D Rail LP38841S-1.5 TO263-5 TS5B Rail LP38841SX-1.5 TO263-5 TS5B Tape and Reel LP38841T-1.5 TO220-5 T05A Rail LP38841T-1.5 LB03 TO220-5 T05D Rail www.national.com 2 LP38841 Block Diagram 20102824 3 www.national.com LP38841 Absolute Maximum Ratings (Note 1) IOUT (Survival) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Output Voltage (Survival) Storage Temperature Range -0.3V to +6V Junction Temperature -65C to +150C Lead Temp. (Soldering, 5 seconds) Internally Limited -40C to +150C Operating Ratings 260C VIN Supply Voltage ESD Rating Human Body Model (Note 3) Machine Model (Note 9) (VOUT + VDO) to 5.5V Shutdown Input Voltage 2 kV 200V 0 to +5.5V IOUT 0.8A VIN Supply Voltage (Survival) -0.3V to +6V Operating Junction Temperature Range VBIAS Supply Voltage (Survival) -0.3V to +7V VBIAS Supply Voltage 4.5V to 5.5V -0.3V to +7V VOUT 0.8V to 1.5V Power Dissipation (Note 2) Internally Limited Shutdown Input Voltage (Survival) -40C to +125C Electrical Characteristics Limits in standard typeface are for TJ = 25C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 F CER, COUT = 22 F CER, CBIAS = 1 F CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical correlation, or design. Symbol VO Parameter Output Voltage Tolerance Conditions 10 mA < IL < 0.8A VO(NOM) + 1V VIN 5.5V 4.5V VBIAS 5.5V VO/VIN Output Voltage Line Regulation (Note 6) VO(NOM) + 1V VIN 5.5V VO/IL Output Voltage Load Regulation (Note 7) 10 mA < IL < 0.8A VDO Dropout Voltage (Note 8) IL = 0.8A IQ(VIN) Quiescent Current Drawn from VIN Supply 10 mA < IL < 0.8A V IQ(VBIAS) Quiescent Current Drawn from VBIAS Supply Short-Circuit Current Typ (Note 4) Max 0.788 0.776 0.8 0.812 0.824 1.182 1.164 1.2 1.218 1.236 1.478 1.455 1.5 1.523 1.545 0.01 0.3V 10 mA < IL < 0.8A V ISC S/D Min S/D 0.3V VOUT = 0V Units V %/V 0.1 0.4 1.3 %/A 75 120 205 mV 30 35 40 mA 0.06 1 30 A 2 4 6 mA 0.03 1 30 A 2.6 A Shutdown Input VSDT Output Turn-off Threshold Output = ON 0.7 Output = OFF 0.3 0.7 Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15 IS/D S/D Input Current V S/D =1.3V 1 0.3V -1 V J-A www.national.com Junction to Ambient Thermal Resistance S/D TO-220, No Heatsink 65 TO-263, 1 sq.in Copper 35 4 1.3 V s A C/W Symbol Parameter Conditions Min Typ (Note 4) Max Units AC Parameters PSRR (VIN) Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz VIN = VOUT + 1V, f = 1 kHz 80 65 PSRR (VBIAS) Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz VBIAS = VOUT + 3V, f = 1 kHz 58 en Output Noise Density f = 120 Hz 1 Output Noise Voltage VOUT = 1.5V BW = 10 Hz - 100 kHz 150 BW = 300 Hz - 300 kHz 90 dB 58 V/root-Hz V (rms) Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. J-A for TO-220 devices is 65C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a J-S value of 4C/W can be assumed. J-A for TO-263 devices is approximately 35C/W if soldered down to a copper plane which is at least 1 square inch in area. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Note 4: Typical numbers represent the most likely parametric norm for 25C operation. Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. Note 9: The machine model is a 220 pF capacitor discharged directly into each pin. 5 www.national.com LP38841 Electrical Characteristics Limits in standard typeface are for TJ = 25C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 F CER, COUT = 22 F CER, CBIAS = 1 F CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical correlation, or design. (Continued) LP38841 Typical Performance Characteristics Unless otherwise specified: TJ = 25C, CIN = 10 F CER, COUT = 22 F CER, CBIAS = 1 F CER,S/D Pin is tied to VBIAS, VOUT = 1.2V, IL = 10mA, VBIAS = 5V, VIN = VOUT + 1V. VBIAS Transient Response Dropout Voltage Over Temperature 20102836 20102839 VOUT vs Temperature VBIAS PSRR 20102840 20102841 VBIAS PSRR VIN PSRR 20102842 20102851 www.national.com 6 EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. OUTPUT CAPACITOR An output capacitor is required on the LP3884X devices for loop stability. The minimum value of capacitance necessary depends on type of capacitor: if a solid Tantalum capacitor is used, the part is stable with capacitor values as low as 4.7F. If a ceramic capacitor is used, a minimum of 22 F of capacitance must be used (capacitance may be increased without limit). The reason a larger ceramic capacitor is required is that the output capacitor sets a pole which limits the loop bandwidth. The Tantalum capacitor has a higher ESR than the ceramic which provides more phase margin to the loop, thereby allowing the use of a smaller output capacitor because adequate phase margin can be maintained out to a higher crossover frequency. The tantalum capacitor will typically also provide faster settling time on the output after a fast changing load transient occurs, but the ceramic capacitor is superior for bypassing high frequency noise. The output capacitor must be located less than one centimeter from the output pin and returned to a clean analog ground. Care must be taken in choosing the output capacitor to ensure that sufficient capacitance is provided over the full operating temperature range. If ceramics are selected, only X7R or X5R types may be used because Z5U and Y5F types suffer severe loss of capacitance with temperature and applied voltage and may only provide 20% of their rated capacitance in operation. where IGND is the operating ground current of the device. The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax- TAmax The maximum allowable value for junction to ambient Thermal Resistance, JA, can be calculated using the formula: JA = TRmax / PD These parts are available in TO-220 and TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of JA calculated above is 60 C/W for TO-220 package and 60 C/W for TO-263 package no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable JA falls below these limits, a heat sink is required. HEATSINKING TO-220 PACKAGE The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of JA will be same as shown in next section for TO263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, HA JA - CH - JC. In this equation, CH is the thermal resistance from the case to the surface of the heat sink and JC is the thermal resistance from the junction to the surface of the case. JC is about 3C/W for a TO220 package. The value for CH depends on method of attachment, insulator, etc. CH varies between 1.5C/W to 2.5C/W. If the exact value is unknown, 2C/W can be assumed. INPUT CAPACITOR The input capacitor is also critical to loop stability because it provides a low source impedance for the regulator. The minimum required input capacitance is 10 F ceramic (Tantalum not recommended). The value of CIN may be increased without limit. As stated above, X5R or X7R must be used to ensure sufficient capacitance is provided. The input capacitor must be located less than one centimeter from the input pin and returned to a clean analog ground. BIAS CAPACITOR The 0.1F capacitor on the bias line can be any good quality capacitor (ceramic is recommended). HEATSINKING TO-263 PACKAGE The TO-263 package uses the copper plane on the PCB as a heatsink. The tab of this package is soldered to the copper plane for heat sinking. The graph below shows a curve for the JA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. BIAS VOLTAGE The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage must be in the range of 4.5 - 5.5V to assure proper operation of the part. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage is below approximately 4V. SHUTDOWN OPERATION Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a pull-up resistor (10 k to 100 k) for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to VBIAS if not used. 7 www.national.com LP38841 POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN-VOUT)IOUT+ (VIN)IGND Application Hints LP38841 Application Hints Figure 2 shows the maximum allowable power dissipation for TO-263 packages for different ambient temperatures, assuming JA is 35C/W and the maximum junction temperature is 125C. (Continued) 20102825 FIGURE 1. JA vs Copper (1 Ounce) Area for TO-263 package 20102826 FIGURE 2. Maximum power dissipation vs ambient temperature for TO-263 package As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for JA for the TO-263 package mounted to a PCB is 32C/W. www.national.com 8 LP38841 Physical Dimensions inches (millimeters) unless otherwise noted TO220 5-lead, Molded, Stagger Bend Package (TO220-5) NS Package Number T05D TO220 5-lead, Molded, Straight Lead Package (TO220-5) NS Package Number T05A 9 www.national.com LP38841 0.8A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors Physical Dimensions inches (millimeters) unless otherwise noted (Continued) TO263 5-Lead, Molded, Surface Mount Package (TO263-5) NS Package Number TS5B National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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