SN74CBTLV3126
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS038H – DECEMBER 1997 – REVISED APRIL 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Standard ’126-Type Pinout
D
5-Ω Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
Latch-up Performance Exceeds 100 mA per
JESD 78, Class II
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1B
2OE
2A
2B
GND
VCC
4OE
4A
4B
3OE
3A
3B
D, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
1OE
1A
1B
2OE
2A
2B
GND
VCC
4OE
4A
4B
3OE
3A
3B
NC
DBQ PACKAGE
(TOP VIEW)
NC – No internal connection
RGY PACKAGE
(TOP VIEW)
114
78
2
3
4
5
6
13
12
11
10
9
4OE
4A
4B
3OE
3A
1A
1B
2OE
2A
2B
1OE
3B V
GND
CC
description/ordering information
The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled
when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver .
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
QFN – RGY Tape and reel SN74CBTLV3126RGYR CL126
SOIC D
Tube SN74CBTLV3126D
CBTLV3126
40°Cto85°C
SOIC
–
D
Tape and reel SN74CBTLV3126DR
CBTLV3126
–
40°C
to
85°C
SSOP (QSOP) – DBQ Tape and reel SN74CBTLV3126DBQR CL126
TSSOP – PW Tape and reel SN74CBTLV3126PWR CL126
TVSOP – DGV Tape and reel SN74CBTLV3126DGVR CL126
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each bus switch)
INPUT
OE FUNCTION
L Disconnect
HA port = B port
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74CBTLV3126
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS038H – DECEMBER 1997 – REVISED APRIL 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A
1OE
SW 1B
2A
2OE
SW 2B
3A
3OE
SW 3B
4A
4OE
SW 4B
2
1
5
4
9
10
12
13
3
6
8
11
Pin numbers shown are for the D, DGV, PW, and RGY packages.
simplified schematic, each FET switch
A
(OE)
B
SN74CBTLV3126
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS038H – DECEMBER 1997 – REVISED APRIL 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI/O < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DBQ package 90°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage 2.3 3.6 V
VIH
High level control in
p
ut voltage
VCC = 2.3 V to 2.7 V 1.7
V
V
IH
High
-
level
control
input
voltage
VCC = 2.7 V to 3.6 V 2
V
VIL
Low level control in
p
ut voltage
VCC = 2.3 V to 2.7 V 0.7
V
V
IL
Low
-
level
control
input
voltage
VCC = 2.7 V to 3.6 V 0.8
V
TAOperating free-air temperature –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
VIK VCC = 3 V, II = –18 mA –1.2 V
IIVCC = 3.6 V, VI = VCC or GND ±1µA
Ioff VCC = 0, VI or VO= 0 to 3.6 V 10 µA
ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA
∆ICC§Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA
CiControl inputs VI = 3 V or 0 2.5 pF
Cio(OFF) VO = 3 V or 0, OE = GND 7 pF
¶
V23V
VI=0
II = 64 mA 5 8
¶
V
CC =
2
.
3
V
,
TYP at VCC
=
2.5 V
V
I =
0
II = 24 mA 5 8
r¶
TYP
at
VCC
=
2
.
5
V
VI = 1.7 V, II = 15 mA 27 40
Ω
ron
¶
VI=0
II = 64 mA 5 7
Ω
VCC = 3 V
V
I =
0
II = 24 mA 5 7
VI = 2.4 V, II = 15 mA 10 15
‡All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
§This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
¶Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
SN74CBTLV3126
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS038H – DECEMBER 1997 – REVISED APRIL 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
± 0.2 V VCC = 3.3 V
±0.3 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
tpd†A or B B or A 0.15 0.25 ns
ten OE A or B 1.6 4.5 1.9 4.2 ns
tdis OE A or B 1.3 4.7 1 4.8 ns
†The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
SN74CBTLV3126
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SCDS038H – DECEMBER 1997 – REVISED APRIL 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC/2
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 2 × VCC
Open
GND
RL
RL
Data Input
Timing Input VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
Input
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V∆
VOH – V∆≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
VCC
VCC/2
VCC/2
2.5 V ±0.2 V
3.3 V ±0.3 V 500 Ω
500 Ω
VCC RL
0.15 V
0.3 V
V∆
CL
30 pF
50 pF
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA
MSOI004E JANUAR Y 1995 – REVISED MAY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DBQ (R–PDSO–G**) PLASTIC SMALL–OUTLINE PACKAGE
4073301/F 02/02
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.035 (0,89)
0.244 (6,20)
0.228 (5,80)
112
24 13
0.150 (3,81)
0.157 (3,99) 0.008 (0,20) NOM
0°–8°
Gauge Plane
0.012 (0,30)
0.008 (0,20)
0.197
(5,00)
(4,80)
0.189
A MAX
A MIN
PINS **
DIM 16
0.337
(8,56)
(8,74)
0.344
20 24
A
(8,74)
0.344
(8,56)
0.337
28
0.394
(10,01)
0.386
(9,80)
M0–137
VARIATION AB AD AE AF
D
0.025 (0,64) 0.005 (0,13)
0.004 (0,10)
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO–137.
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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Post Office Box 655303
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Copyright 2003, Texas Instruments Incorporated
