SN74CBTLV3126 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS038H - DECEMBER 1997 - REVISED APRIL 2003 D Standard '126-Type Pinout 5- Switch Connection Between Two Ports Isolation Under Power-Off Conditions D, DGV, OR PW PACKAGE (TOP VIEW) 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4B 3OE 3A 3B 1A 1B 2OE 2A 2B VCC 14 1 14 DBQ PACKAGE (TOP VIEW) 2 13 4OE 3 12 4A 4 11 4B 5 10 3OE 9 3A 6 7 8 3B 1 1OE 1OE 1A 1B 2OE 2A 2B GND Latch-up Performance Exceeds 100 mA per JESD 78, Class II RGY PACKAGE (TOP VIEW) GND D D D NC 1OE 1A 1B 2OE 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4OE 4A 4B 3OE 3A 3B NC NC - No internal connection description/ordering information The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION QFN - RGY TOP-SIDE MARKING Tape and reel SN74CBTLV3126RGYR Tube SN74CBTLV3126D Tape and reel SN74CBTLV3126DR SSOP (QSOP) - DBQ Tape and reel SN74CBTLV3126DBQR CL126 TSSOP - PW Tape and reel SN74CBTLV3126PWR CL126 TVSOP - DGV Tape and reel SN74CBTLV3126DGVR SOIC - D -40C 40C to 85C ORDERABLE PART NUMBER PACKAGE TA CL126 CBTLV3126 CL126 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each bus switch) INPUT OE FUNCTION L Disconnect H A port = B port Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74CBTLV3126 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS038H - DECEMBER 1997 - REVISED APRIL 2003 logic diagram (positive logic) 3 2 1A 1OE 1B SW 1 6 5 2A 2B SW 4 2OE 8 9 3A 3OE 3B SW 10 11 12 4A SW 4B 13 4OE Pin numbers shown are for the D, DGV, PW, and RGY packages. simplified schematic, each FET switch A B (OE) 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74CBTLV3126 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS038H - DECEMBER 1997 - REVISED APRIL 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 4) VCC Supply voltage VIH High level control input voltage High-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low level control input voltage Low-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 1.7 UNIT V V 2 0.7 0.8 V TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II VCC = 3 V, VCC = 3.6 V, II = -18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO= 0 to 3.6 V IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND ICC Control inputs Ci Control inputs Cio(OFF) VCC = 3.6 V, VI = 3 V or 0 MIN TYP MAX UNIT -1.2 V 1 A 10 A 10 A 300 A 2.5 pF 7 pF VO = 3 V or 0, OE = GND VI = 0 II = 64 mA II = 24 mA 5 8 VCC = 2.3 2 3 V, V TYP at VCC = 2.5 V 5 8 VI = 1.7 V, II = 15 mA 27 40 VI = 0 II = 64 mA II = 24 mA 5 7 5 7 ron VCC = 3 V VI = 2.4 V, II = 15 mA 10 15 All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74CBTLV3126 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS038H - DECEMBER 1997 - REVISED APRIL 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd A or B B or A ten OE A or B PARAMETER VCC = 2.5 V 0.2 V MIN MAX VCC = 3.3 V 0.3 V MIN 0.15 1.6 4.5 1.9 UNIT MAX 0.25 ns 4.2 ns tdis A or B 1.3 4.7 1 4.8 ns OE The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74CBTLV3126 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS038H - DECEMBER 1997 - REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION 2 x VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND RL LOAD CIRCUIT VCC CL RL V 2.5 V 0.2 V 3.3 V 0.3 V 30 pF 50 pF 500 500 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 0V t Output PZL Waveform 1 S1 at 2 x VCC (see Note B) tPLH VOH VCC Output Control tPLZ VCC VCC/2 VOL + V VOL tPHZ tPZH VCC/2 VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0- 8 A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI004E JANUARY 1995 - REVISED MAY 2002 DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 0.012 (0,30) 0.008 (0,20) 0.025 (0,64) 0.005 (0,13) 13 24 0.244 (6,20) 0.228 (5,80) 0.157 (3,99) 0.150 (3,81) 0.008 (0,20) NOM Gauge Plane 1 12 0.010 (0,25) A 0-8 0.035 (0,89) 0.016 (0,40) 0.069 (1,75) MAX Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 28 A MAX 0.197 (5,00) 0.344 (8,74) 0.344 (8,74) 0.394 (10,01) A MIN 0.189 (4,80) 0.337 (8,56) 0.337 (8,56) 0.386 (9,80) M0-137 VARIATION AB AD AE AF DIM D 4073301/F 02/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-137. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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