IS61C1024 IS61C1024L a 128K x 8 HIGH-SPEED CMOS STATIC RAM JULY 1997 FEATURES * High-speed access time: 12, 15, 20, 25 ns Low active power: 600 mW (typical) * Low standby power: 500 wW (typical) CMOS standby * Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications * Fully static required operation: no clock or refresh * TTL compatible inputs and outputs * Single 5V (+10%) power supply * Low power version available: |IS61C1024L * Commercial and industrial temperature ranges available FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The [SS7 1S61C1024 and 1S61C1024L are very high-speed, low power, 131,072-word by 8-bit CMOS static RAMs. They are fabricated using /SSI's high-performance CMOS technol- ogy. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The 186101024 and 1S61C1024L are available in 32-pin 300-mil and 400-mil plastic DIP and SOJ, and TSOP (type 1) packages. 512 X 2048 AO-A16 > DECODER > MEMORY ARRAY vcc -> GND -> VO 1/00-/07 DATA CIRCUIT = COLUMN I/O A cei CE2 q_ CONTROL OE SCCCIRRCUIT WE 4 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1997, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. $RO28-1H 07/8/97 IS61C1024 IS61C1024L a PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOJ 32-Pin TSOP (Type 1) NS nc (1 32[] vec Ai1 (1 327] OE Ais [2 310] At5 Ag T2 31{-] A10 A143 301] CE2 As (13 30{7] CEI Ai2 14 29[] WE A13 [1] 4 29[7] 1/07 a7 U5 28[] A13 WE (15 28(C] 1/06 A6 [6 27{] as CE2 CL] 6 97(_] 1/05 A5 [7 26{] Ag Ais (7 26] 1/04 A4 [8 25,] Att vec C8 25] 1/03 A3 [9 24{] OF Nc [49 241] GND A2 [10 23[] Ato Ai6 [J 10 93] 1/02 Ai O11 22[] CEI Ai4 (411 22[] ot Ao [] 12 211] vo7 At2 [4 12 21{-] 1/00 Vvoo [] 13 20f] os A7 C1 13 20{_] Ao voi 1] 14 19[] O05 As LI] 14 19 At vo2 [15 18] 04 A5 (1) 15 18[-] A2 GND [] 16 171] vos A4 (J 16 177) A3 PIN DESCRIPTIONS A0-A16 Address Inputs CET Chip Enable 1 Input CE2 Chip Enable 2 Input OE Output Enable Input WE Write Enable Input 1/00-I/O7 Input/Output Vcc Power GND Ground OPERATING RANGE Range Ambient Temperature Veco") Commercial 0C to +70C 5V+10% Industrial 40C to +85C 5V+10% Note: 1. Vec = 5V + 5% for 12 ns devices. TRUTH TABLE Mode WE CE1 CE2 OE (W/OOperation Vcc Current Not Selected Xx H Xx Xx High-2 IsB1, IsB2 (Power-down) xX xX L xX High-2 IsB1, IsB2 Output Disabled H L H H High-Z Icc1, lec Read H L H L Dout Icct, Icc2 Write L L H Xx DIN Icct, Icc2 Integrated Silicon Solution, Inc. $RO028-1H 07/18/97 IS61C1024 IS61C1024L ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND 0.5 to +7.0 Vv TBIAS Temperature Under Bias 55 to +125 C TsTG Storage Temperature 65 to +150 C Pr Power Dissipation 1.5 Ww lout DC Output Current (LOW) 20 mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE) Symbol Parameter Conditions Max. Unit CIN Input Capacitance Vin = OV 5 pF Court Output Capacitance Vout = OV 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vcc = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VoH Output HIGH Voltage Vcc = Min., loH = -4.0 mA 2.4 _ Vv VoL Output LOW Voltage Vcc = Min., lo. = 8.0 mA _ 0.4 Vv VIH Input HIGH Voltage 2.2 Veco + 0.5 Vv VIL Input LOW Voltage -0.3 0.8 Vv Iu Input Leakage GND < Vin s Vec Com. -2 2 LA Ind. -5 5 ILo Output Leakage GND < Vout < Vcc Com. -2 2 LA Outputs Disabled Ind. 5 5 Notes: 1. Vit = -3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. SR028-1H 07/18/97