ICL7136, ICL7137 S E M I C O N D U C T O R 31/2 Digit LCD/LED Low Power Display A/D Converter with Overrange Recovery January 1994 Features Description * First Reading Overrange Recovery in One Conversion Period The Harris ICL7136 and ICL7137 are high performance, low power 31/2 digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7136 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7137 will directly drive an instrument size, light emitting diode (LED) display. * Guaranteed Zero Reading for 0V Input on All Scales * True Polarity at Zero for Precise Null Detection * 1pA Typical Input Current * True Differential Input and Reference, Direct Display Drive - LCD ICL7136 - LED lCL7137 The ICL7136 and ICL7137 bring together a combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10V, zero drift of less than 1V/C, input bias current of 10pA max., and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7136), enables a high performance panel meter to be built with the addition of only 10 passive components and a display. * Low Noise - Less Than 15Vp-p * On Chip Clock and Reference * No Additional Active Circuits Required * Low Power - Less Than 1mW * Small Outline Surface Mount Package Available * Drop-In Replacement for ICL7126, No Changes Needed Ordering Information PART NUMBER TEMPERATURE RANGE o o PACKAGE ICL7136CPL 0 C to +70 C 40 Lead Plastic DIP ICL7136RCPL 0oC to +70oC 40 Lead Plastic DIP (Note 1) ICL7136CM44 0oC to +70oC 44 Lead Metric Plastic Quad Flatpack o o ICL7137CPL 0 C to +70 C 40 Lead Plastic DIP ICL7137RCPL 0oC to +70oC 40 Lead Plastic DIP (Note 1) o o 0 C to +70 C ICL7137CM44 44 Lead Metric Plastic Quad Flatpack The ICL7136 and ICL7137 are improved versions of the ICL7126, eliminating the overrange hangover and hysteresis effects, and should be used in its place in all applications. It can also be used as a plug-in replacement for the ICL7106 in a wide variety of applications, changing only the passive components. NOTE: 1. "R" indicates device with reversed leads. 6Pinouts (1's) (10's) 36 REF HI F1 6 35 REF LO G1 7 34 CREF+ E1 8 D2 9 32 COMMON C2 10 31 IN HI B2 11 30 IN LO A2 12 F2 13 33 CREF- 29 A-Z 28 BUFF 44 43 42 41 40 39 38 37 36 35 34 33 2 32 NC TEST 3 31 C3 OSC 3 4 30 A3 NC 5 29 G3 OSC 2 6 28 BP/GND OSC 1 7 27 POL V+ 8 26 AB4 D1 9 25 E3 NC NC 1 G2 E2 14 27 INT D3 15 26 V- B3 16 25 G2 (10's) C1 10 24 F3 F3 17 24 C3 B1 11 23 12 13 14 15 16 17 18 19 20 21 22 B3 E3 18 23 A3 (1000) AB4 19 22 G3 POL 20 21 BP/GND (100's) (MINUS) (100's) A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright V- 5 INT 37 TEST A1 BUFF 4 A-Z 38 OSC 3 B1 IN LO C1 IN HI 39 OSC 2 3 COMMON 40 OSC 1 2 CREF+ 1 CREF- V+ D1 REF LO (MQFP) TOP VIEW REF HI (PDIP) TOP VIEW (c) Harris Corporation 1993 2-68 File Number 3086 Specifications ICL7136, ICL7137 Absolute Maximum Ratings Thermal Information Supply Voltage ICL7136, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V ICL7137, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V ICL7137, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to VClock Input ICL7136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ ICL7137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+ Thermal Resistance JA 40 Lead PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50oC/W 44 Lead MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W Maximum Power Dissipation (Note 2) ICL7136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6W ICL7137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W Operating Temperature Range . . . . . . . . . . . . . . . . . . 0oC to +70oC Storage Temperature Range. . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s Max) . . . . . . . . . . . . . . . . +300oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications (Note 3) PARAMETERS TEST CONDITIONS SYSTEM PERFORMANCE Zero Input Reading VIN = 0.0V, Full-Scale = 200mV Ratiometric Reading VlN = VREF, VREF = 100mV MIN TYP MAX UNITS -000.0 000.0 +000.0 Digital Reading 999 999/ 1000 0.2 1000 Digital Reading Counts -VIN = +VlN 200mV Difference in Reading for Equal 1 Positive and Negative Inputs Near Full-Scale Linearity Full-Scale = 200mV or Full-Scale = 2V Maximum 0.2 1 Counts Deviation from Best Straight Line Fit (Note 5) Common Mode Rejection Ratio VCM = 1V, VIN = 0V, Full-Scale = 200mV (Note 5) 50 V/V Noise VIN = 0V, Full-Scale = 200mV (Pk-Pk Value Not 15 V Exceeded 95% of Time) (Note 5) Leakage Current Input VlN = 0 (Note 5) 1 10 pA Zero Reading Drift VlN = 0, 0o < TA < +70oC (Note 5) 0.2 1 V/oC Scale Factor Temperature Coefficient VIN = 199mV, 0o < TA < +70oC, (Ext. Ref. 0ppm/oC) 1 5 ppm/oC (Note 5) COMMON Pin Analog Common Voltage 25k Between Common and Positive Supply (With 2.4 2.8 3.2 V Respect to + Supply) Temperature Coefficient of Analog Common 25k Between Common and Positive Supply (With 150 ppm/oC Respect to + Supply) (Note 5) ICL7136 V+ Supply Current VIN = 0 (Does Not Include Common Current) 16kHz 70 100 A Oscillator (Note 6) ICL7137 V+ Supply Current VIN = 0 (Does Not Include Common Current) 16kHz 70 200 A Oscillator (Note 6) V- Supply Current 40 A DISPLAY DRIVER ICL7136 ONLY Pk-Pk Segment Drive Voltage V+ = to V- = 9V, (Note 4) 4 5 6 V Pk-Pk Backplane Drive Voltage ICL7137 ONLY Segment Sinking Current V+ = 5V, Segment Voltage = 3V (Except Pin 19 and 20) 5 8 mA Pin 19 Only 10 16 mA Pin 20 Only 4 7 mA NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to 100A. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. Unless otherwise noted, specifications apply to both the ICL7136 and ICL7137 at TA = +25oC, fCLOCK = 48kHz. ICL7136 is tested in the circuit of Figure 1. ICL7137 is tested in the circuit of Figure 2. 4. Back plane drive is in phase with segment drive for `off' segment, 180o out of phase for `on' segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. 6. 48kHz oscillator increases current by 20A (TYP). Rollover Error 2-69 ICL7136, ICL7137 Typical Applications and Test Circuits + - 9V IN R5 A3 23 G3 22 BP 21 19 AB4 20 POL C3 24 18 E3 17 F3 V- 26 G2 25 INT 27 14 E2 DISPLAY 16 B3 A-Z 29 BUFF 28 C3 13 F2 IN HI 31 IN LO 30 COM 32 C2 R2 15 D3 C5 CREF- 33 CREF+ 34 REF LO 35 TEST 37 REF HI 36 OSC 3 38 C4 OSC 2 39 OSC 1 40 R3 C1 R4 12 A2 R1 11 B2 D2 9 10 C2 E1 8 A1 5 F1 B1 4 G1 C1 3 7 D1 2 6 V+ 1 ICL7136 C1 C2 C3 C4 C5 R1 R2 R3 R4 R5 = 0.1F = 0.47F = 0.047F = 50pF = 0.01F = 240K = 180K = 180K = 10K = 1M DISPLAY FIGURE 1. ICL7136 TEST CIRCUIT & TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL-SCALE +5V + -5V IN R5 C2 R2 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 GND 21 15 D3 16 B3 17 F3 18 E3 19 AB4 20 POL DISPLAY 14 E2 A-Z 29 BUFF 28 C3 13 F2 IN LO 30 COM 32 IN HI 31 C5 CREF- 33 CREF+ 34 REF LO 35 REF HI 36 TEST 37 OSC 3 38 C4 OSC 2 39 OSC 1 40 R3 C1 R4 12 A2 R1 11 B2 D2 9 10 C2 E1 8 A1 5 F1 B1 4 G1 C1 3 7 D1 2 6 V+ 1 ICL7137 C1 C2 C3 C4 C5 R1 R2 R3 R4 R5 = 0.1F = 0.47F = 0.047F = 50pF = 0.01F = 240K = 180K = 180K = 10K = 1M DISPLAY FIGURE 2. ICL7137 TEST CIRCUIT & TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL-SCALE 2-70 ICL7136, ICL7137 Design Information Summary Sheet * OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50K fOSC Typ. = 48KHz * DISPLAY COUNT * OSCILLATOR PERIOD tOSC = RC/0.45 * CONVERSION CYCLE tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48KHz; tCYC = 333ms COUNT = 1000 x * INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC/4 V V IN REF * INTEGRATION PERIOD tINT = 1000 x (4/fOSC) * COMMON MODE INPUT VOLTAGE * 60/50Hz REJECTION CRITERION tINT/t60Hz or tlNT/t50Hz = Integer * AUTO-ZERO CAPACITOR 0.01F < CAZ < 1.0F * OPTIMUM INTEGRATION CURRENT IINT = 1.0A * REFERENCE CAPACITOR 0.1F < CREF < 1.0F * FULL-SCALE ANALOG INPUT VOLTAGE VlNFS Typically = 200mV or 2.0V * VCOM Biased between V+ and V-. * INTEGRATE RESISTOR V INFS R = INT I INT * VCOM V+ - 2.8V Regulation lost when V+ to V- < 6.8V. If VCOM is externally pulled down to (V + to V -)/2, the VCOM circuit will turn off. * INTEGRATE CAPACITOR (t ) (I ) INT INT C = INT V INT * ICL7136 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VTEST V+ - 4.5V * INTEGRATOR OUTPUT VOLTAGE SWING (t ) (I ) INT INT V = INT C INT * ICL7136 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. (V- + 1.0V) < VlN < (V+ - 0.5V) * VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT typically = 2.0V * ICL7137 POWER SUPPLY: DUAL 5.0V V+ = +5.0V to GND V- = -5.0V to GND Digital Logic and LED driver supply V+ to GND * ICL7137 DISPLAY: LED Type: Non-Multiplexed Common Anode Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC 2-71 ICL7136, ICL7137 Pin Description PIN NUMBER 40 PIN DIP 44 PIN FLATPACK 1 8 V+ SUPPLY Power Supply 2 9 D1 OUTPUT Driver Pin for Segment "D" of the display units digit 3 10 C1 OUTPUT Driver Pin for Segment "C" of the display units digit 4 11 B1 OUTPUT Driver Pin for Segment "B" of the display units digit 5 12 A1 OUTPUT Driver Pin for Segment "A" of the display units digit 6 13 F1 OUTPUT Driver Pin for Segment "F" of the display units digit 7 14 G1 OUTPUT Driver Pin for Segment "G" of the display units digit 8 15 E1 OUTPUT Driver Pin for Segment "E" of the display units digit NAME FUNCTION DESCRIPTION 9 16 D2 OUTPUT Driver Pin for Segment "D" of the display tens digit 10 17 C2 OUTPUT Driver Pin for Segment "C" of the display tens digit 11 18 B2 OUTPUT Driver Pin for Segment "B" of the display tens digit 12 19 A2 OUTPUT Driver Pin for Segment "A" of the display tens digit 13 20 F2 OUTPUT Driver Pin for Segment "F" of the display tens digit 14 21 E2 OUTPUT Driver Pin for Segment "E" of the display tens digit 15 22 D3 OUTPUT Driver pin for segment "D" of the display hundreds digit 16 23 B3 OUTPUT Driver pin for segment "B" of the display hundreds digit 17 24 F3 OUTPUT Driver pin for segment "F" of the display hundreds digit 18 25 E3 OUTPUT Driver pin for segment "E" of the display hundreds digit 19 26 AB4 OUTPUT Driver pin for both "A" and "B" segments of the display thousands digit 20 27 POL OUTPUT Driver pin for the negative sign of the display 21 28 BP/GND OUTPUT Driver pin for the LCD backplane/Power Supply Ground 22 29 G3 OUTPUT Driver pin for segment "G" of the display hundreds digit 23 30 A3 OUTPUT Driver pin for segment "A" of the display hundreds digit 24 31 C3 OUTPUT Driver pin for segment "C" of the display hundreds digit 25 32 G2 OUTPUT Driver pin for segment "G" of the display tens digit 26 34 V- SUPPLY Negative power supply 27 35 INT OUTPUT Integrator amplifier output. To be connected to integrating capacitor 28 36 BUFF OUTPUT Input buffer amplifier output. To be connected to integrating resistor 29 37 A-Z INPUT Integrator amplifier input.To be connected to auto-zero capacitor 30 31 38 39 IN LO IN HI INPUT Differential inputs. To be connected to input voltage to be measured. LO & HI designators are for reference and do not imply that LO should be connected to lower potential, e.g. for negative inputs IN LO has a higher potential than IN HI. 32 40 COMMON SUPPLY/ OUTPUT 33 34 41 42 CREFCREF+ 35 36 43 44 REF LO REF HI INPUT Input pins for reference voltage to the device. REF HI should be positive reference to REF LO. 37 3 TEST INPUT Display test. Turns on all segments when tied to V+. 38 39 40 4 6 7 OSC3 OSC2 OSC1 OUTPUT OUTPUT INPUT Internal voltage reference output. Connection pins for reference capacitor. Device clock generator circuit connection pins 2-72 ICL7136, ICL7137 Detailed Description Analog Section Figure 3 shows the Analog Section for the ICL7136 and ICL7137. Each measurement cycle is divided into four phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE), (4) zero integrate (ZI). Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10V. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. De-Integrate Phase capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is V IN DISPLAYREADING= 1000 V REF . Zero Integrator Phase The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Finally, a feedback loop is closed around the system to IN HI to cause the integrator output to return to zero. Under normal conditions, this phase lasts for between 11 to 140 clock pulses, but after a "heavy" overrange conversion, it is extended to 740 clock pulses. Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1.0V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full-scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference STRAY STRAY CREF RINT CREF+ REF HI 34 36 V+ REF LO 35 A-Z, ZI CREF 33 A-Z, ZI CAZ BUFFER V+ 1 28 CINT A-Z INT 29 27 INTEGRATOR - + 10A - + - + 2.8V 31 IN HI INT DE- DE+ 6.2V INPUT HIGH A-Z A-Z - N DE+ 32 + DE- COMPARATOR ZI COMMON INT 30 INPUT LOW A-Z AND DE() AND ZI IN LO 26 V- FIGURE 3. ANALOG SECTION OF ICL7136 AND ICL7137 2-73 TO DIGITAL SECTION ICL7136, ICL7137 Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N channel FET that can sink approximately 3mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10A of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. V+ V REF HI Analog COMMON 6.8V ZENER REF LO This pin is included primarily to set the common mode voltage for battery operation (ICL7136) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6.8V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (15), and a temperature coefficient typically less than 150ppm/oC. The limitations of the on chip reference should also be recognized, however. With the ICL7137, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full-scale from 25V to 80Vp-p. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over range condition. This is because over-range is a low dissipation mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between over range and a non-over range count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used. IZ ICL7136 ICL7137 VFIGURE 4A. V+ V 6.8k 20k ICL7136 ICL7137 ICL8069 1.2V REFERENCE REF HI REF LO COMMON FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE TEST The TEST pin serves two functions. On the ICL7136 it is coupled to the internally generated digital supply through a 500 resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a 1mA load should be applied. The ICL7136, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the 2-74 V+ 1M TO LCD DECIMAL POINT ICL7136 BP TEST 21 37 TO LCD BACKPLANE FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT ICL7136, ICL7137 Digital Section The second function is a "lamp test". When TEST is pulled high (to V+) all segments will be turned on and the display should read "-1888". The TEST pin will sink about 5mA under these conditions. Figures 7 and 8 show the digital section for the ICL7136 and ICL7137, respectively. In the ICL7136, an internal digital ground is generated from a 6V Zener diode and a large Pchannel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/second this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. CAUTION: On the ICL7136, in the lamp test mode, the segments have a constant DC voltage (no square-wave) and may burn the LCD display if left in this mode for several minutes. V+ V+ BP ICL7136 TO LCD DECIMAL POINTS DECIMAL POINT SELECT Figure 8 is the Digital Section of the ICL7137. It is identical to the ICL7136 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. TEST CD4030 GND FIGURE 6. EXCLUSIVE `OR' GATE FOR DECIMAL POINT DRIVE In both devices, the polarity indication is "on" for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. a a a f g b e a f b b f g c e c d b g c d e c d BACKPLANE 21 LCD PHASE DRIVER 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 7 SEGMENT DECODE 7 SEGMENT DECODE /200 0.5mA LATCH SEGMENT OUTPUT 2.0mA 1000's COUNTER 100's COUNTER 10's COUNTER 1's COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT 1 V+ CLOCK THREE INVERTERS ONLY ONE INVERTER SHOWN FOR CLARITY /4 LOGIC CONTROL 6.2V 500 INTERNAL DIGITAL GROUND TEST VTH = 1V 37 26 40 OSC 1 39 OSC 2 38 OSC 3 FIGURE 7. ICL7136 DIGITAL SECTION 2-75 V- ICL7136, ICL7137 a f a a g e b f b c c g e TYPICAL SEGMENT OUTPUT V+ b g e c d 7 SEGMENT DECODE a f b c d d 7 SEGMENT DECODE 7 SEGMENT DECODE LATCH 0.5mA TO SEGMENT 1000's COUNTER 100's COUNTER 10's COUNTER 1's COUNTER 8.0mA TO SWITCH DRIVERS FROM COMPARATOR OUTPUT DIGITAL GROUND V+ THREE INVERTERS ONLY ONE INVERTER SHOWN FOR CLARITY 1 V+ CLOCK /4 37 LOGIC CONTROL 500 27 40 OSC 1 39 OSC 2 TEST DIGITAL GROUND 38 OSC 3 FIGURE 8. ICL7137 DIGITAL SECTION System Timing Figure 9 shows the clocking arrangement used in the ICL7136 and ICL7137. Two basic clocking arrangements can be used: INTERNAL TO PART /4 CLOCK /4 CLOCK 1. An external oscillator connected to pin 40. 2. An R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and autozero (1000 to 3000 counts). For signals less than full-scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). 2-76 40 39 38 GND ICL7137 TEST ICL7136 INTERNAL TO PART 40 39 38 R C RC OSCILLATOR FIGURE 9. CLOCK CIRCUITS ICL7136, ICL7137 Component Value Selection Reference Voltage Integrating Resistor The analog input required to generate full-scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full-scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341 V. Suitable values for integrating resistor and capacitor would be 330k and 0.047F. This makes the system slightly quieter and also avoids a divider network on the input. The ICL7137 with 5V supplies can accept input signals up to 4V. Another advantage of this system occurs when a digital reading of zero is desired for VIN 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. Both the buffer amplifier and the integrator have a class A output stage with 100A of quiescent current. They can supply 1A of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full-scale, 1.8M is near optimum and similarly a 180k for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the ICL7136 or the ICL7137, when the analog COMMON is used as a reference, a nominal +2V fullscale integrator swing is fine. For the ICL7137 with +5V supplies and analog COMMON tied to supply ground, a 3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for ClNT are 0.047F and 0.5F, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. Auto-Zero Capacitor ICL7137 Power Supplies The ICL7137 is designed to work from 5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive l.C. Figure 10 shows this application. See ICL7660 data sheet for an alternative. In fact, in selected applications no negative supply is required. The conditions to use a single +5V supply are: 1. The input signal can be referenced to the center of the common mode range of the converter. The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full-scale where noise is very important, a 0.47F capacitor is recommended. On the 2V scale, a 0.047F capacitor increases the speed of recovery from overload and is adequate for noise on this scale. 2. The signal is less than 1.5V. 3. An external reference is used. V+ Reference Capacitor A 0.1F capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e. the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1.0F will hold the roll-over error to 0.5 count in this instance. CD4009 V+ OSC 1 IN914 OSC 2 OSC 3 0.047 F Oscillator Components ICL7137 For all ranges of frequency a 180k resistor is recommended and the capacitor is selected from the equation 0.45 For48kHzClock(3Readings/second), f = RC + 10 F - IN914 GND V- V- = 3.3V C = 50pF FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V 2-77 ICL7136, ICL7137 Typical Applications Application Notes The ICL7136 and ICL7137 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. A016 "Selecting A/D Converters" The following application notes contain very useful information on understanding and applying this part and are available from Harris semiconductor. A017 "The Integrating A/D Converter" A018 "Do's and Don'ts of Applying A/D Converters" A023 "Low Cost Digital Panel Meter Designs" A032 "Understanding the Auto-Zero and Common Mode Performance of the ICL7136/7/9 Family" A046 "Building a Battery-Operated Auto Ranging DVM with the ICL7136" A052 "Tips for Using Single Chip 31/2 Digit A/D Converters" Typical Applications TO PIN 1 OSC 1 40 TO PIN 1 OSC 1 40 180K OSC 2 39 OSC 2 39 OSC 3 38 TEST 37 OSC 3 38 SET VREF = 100mV 50pF TEST 37 REF HI 36 REF HI 36 REF LO 35 REF LO 35 CREF 34 CREF 33 20K 240K CREF 34 0.1F COMMON 32 CREF 33 1M A-Z 29 BUFF 28 IN LO 30 - A-Z 29 180K BUFF 28 9V INT 27 V - 26 A3 23 V - 26 0.1F 1M + IN 0.01F 0.47F - 180K 0.047F -5V G2 25 C3 24 TO DISPLAY A3 23 G3 22 BP 21 240K INT 27 0.047F G2 25 C3 24 +5V 20K IN HI 31 IN 0.01F 0.47F SET VREF = 100mV 50pF COMMON 32 + IN HI 31 IN LO 30 180K TO DISPLAY G3 22 GND 21 TO BACKPLANE Values shown are for 200mV full-scale, 3 readings/sec., floating supply voltage (9V battery). Values shown are for 200mV full-scale, 3 readings/sec. IN LO may be tied to either COMMON for inputs floating with respect to supplies, or GND for single ended inputs. (See discussion under Analog COMMON.) FIGURE 11. ICL7136 USING THE INTERNAL REFERENCE FIGURE 12. ICL7137 USING THE INTERNAL REFERENCE 2-78 ICL7136, ICL7137 Typical Applications (Continued) TO PIN 1 OSC 1 40 TO PIN 1 OSC 1 40 100K OSC 2 39 OSC 2 39 OSC 3 38 TEST 37 OSC 3 38 SET VREF = 100mV 50pF TEST 37 REF HI 36 CREF 33 V+ 20K 200K 27K A-Z 29 BUFF 28 CREF 34 CREF 33 1.2V (ICL8069) 1M IN LO 30 - A3 23 V- V - 26 C3 24 TO DISPLAY A3 23 G3 22 GND 21 IN LO is tied to supply COMMON establishing the correct common mode voltage. If COMMON is not shorted to GND, the input voltage may float with respect to the power supply and COMMON acts as a pre-regulator for the reference. If COMMON is shorted to GND, the input is single ended (referred to supply GND) and the pre-regulator is overridden. FIGURE 13. ICL7137 WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) 180K 0.047F Since low TC zeners have breakdown voltages ~ 6.8V, diode must be plasced across the total supply (10V). As in the case of Figure 14, IN LO may be tied to either COMMON or GND FIGURE 14. ICL7137 WITH ZENER DIODE REFERENCE TO PIN 1 OSC 1 40 180K OSC 2 39 50pF OSC 3 38 SET VREF = 100mV TEST 37 REF HI 36 CREF 34 0.1F CREF 33 1M IN LO 30 - A-Z 29 1.8M BUFF 28 0.047F V - 26 V- A3 23 + IN 0.01F 0.47F - 180K 0.047F G2 25 G2 25 C3 24 1.2V (ICL8069) 1M INT 27 INT 27 V - 26 0.1F IN HI 31 IN 0.01F 0.01F +5V 20K 100K 27K COMMON 32 + IN HI 31 BUFF 28 REF LO 35 250K 240K COMMON 32 A-Z 29 SET VREF = 100mV 50pF REF HI 36 V+ REF LO 35 IN LO 30 180k OSC 2 39 OSC 3 38 CREF 33 -5V TO DISPLAY TO PIN 1 CREF 34 - G2 25 G3 22 TEST 37 IN 0.01F INT 27 0.047F GND 21 OSC 1 40 + 0.33F BUFF 28 G2 25 C3 24 1M A-Z 29 180K INT 27 V - 26 6.8V 0.1F IN HI 31 IN 0.01F 0.47F 10K 1M COMMON 32 + IN HI 31 +5V REF LO 35 0.1F COMMON 32 IN LO 30 SET VREF = 100mV 50pF REF HI 36 REF LO 35 CREF 34 180K C3 24 A3 23 TO DISPLAY TO DISPLAY G3 22 G3 22 GND 21 BP/GND 21 An external reference must be used in this application, since the voltage between V+ and V- is insufficient for correct operation of the internal reference. FIGURE 15. ICL7136 AND ICL7137: RECOMMENDED COMPONENT VALUES FOR 2.0V FULL-SCALE 2-79 FIGURE 16. ICL7137 OPERATED FROM SINGLE +5V ICL7136, ICL7137 Typical Applications (Continued) TO PIN 1 OSC 1 40 TO PIN 1 V+ OSC 1 40 180K * OSC 2 39 OSC 2 39 OSC 3 38 OSC 3 38 TEST 37 REF HI 36 REF HI 36 REF LO 35 REF LO 35 CREF 34 CREF 34 0.1F CREF 33 CREF 33 100k 1M 200k 470k 0.1F 22K COMMON 32 COMMON 32 IN HI 31 IN HI 31 IN LO 30 IN LO 30 0.47F 180K BUFF 28 INT 27 0.047F V - 26 0.47F V - 26 SILICON NPN MPS 3704 OR SIMILAR 390K BUFF 28 INT 27 ZERO ADJUST 0.01F A-Z 29 A-Z 29 9V * G2 25 G2 25 C3 24 C3 24 TO DISPLAY A3 23 A3 23 TO DISPLAY G3 22 G3 22 BP 21 GND 21 The resistor values within the bridge are determined by the desired sensitivity. FIGURE 17. ICL7137 MEASUREING RATIOMETRIC VALUES OF QUAD LOAD CELL TO BACKPLANE A silicon diode-connected transistor has a temperature coefficient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. * Value depends on clock frequency. FIGURE 18. ICL7136 USED AS A DIGITAL CENTIGRADE THERMOMETER +5V V+ TO LOGIC VCC 1 V+ OSC 1 40 1 V+ OSC 1 40 2 D1 OSC 2 39 2 D1 OSC 2 39 3 C1 OSC 3 38 3 C1 OSC 3 38 4 B1 TEST 37 4 B1 TEST 37 5 A1 REF HI 36 5 A1 REF HI 36 6 F1 REF LO 35 6 F1 REF LO 35 7 G1 CREF 34 7 G1 8 E1 O /RANGE TO CREF 34 LOGIC GND CREF 33 9 D2 COMMON 32 10 C2 IN HI 31 11 B2 IN LO 30 12 A2 A-Z 29 13 F2 BUFF 28 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP 21 TO LOGIC VCC 12K The LM339 is required to ensure logic compatibility with heavy display loading. + - VO /RANGE + + - U /RANGE U /RANGE CD4023 OR 74C10 SCALE FACTOR ADJUST 50pF TEST 37 50pF CD4023 OR 74C10 + 8 E1 CREF 33 9 D2 COMMON 32 10 C2 IN HI 31 11 B2 IN LO 30 12 A2 A-Z 29 13 F2 BUFF 28 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP 21 V- 33K CD4077 FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM ICL7136 OUTPUTS FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7137 OUTPUT 2-80 ICL7136, ICL7137 Typical Applications (Continued) TO PIN 1 OSC 1 40 180k OSC 2 39 10F SCALE FACTOR ADJUST (VREF = 100mV FOR AC TO RMS) OSC 3 38 TEST 37 50pF 5F CA3140 REF HI 36 REF LO 35 CREF 34 CREF 33 1N914 20K 220K 470K 0.1F 2.2M COMMON 32 1F IN HI 31 IN LO 30 10K 1F 0.47F 0.22F 180K 10F INT 27 V - 26 1F 4.3K A-Z 29 BUFF 28 10K 0.047F 9V 100pF (FOR OPTIMUM BANDWIDTH) G2 25 C3 24 A3 23 TO DISPLAY G3 22 BP 21 TO BACKPLANE Test is used as a common-mode reference level to ensure compatibility with most op amps. FIGURE 21. AC TO DC CONVERTER WITH ICL7136 2-81 100k + - AC IN ICL7136, ICL7137 Die Characteristics DIE DIMENSIONS: 127 x 149 Mils METALLIZATION: Type: Al Thickness: 10kA 1kA GLASSIVATION: Type: PSG Nitride Thickness: 15kA 3kA WORST CASE CURRENT DENSITY: 9.1 x 104A/cm2 Metallization Mask Layout ICL7136, ICL7137 E2 F2 A2 B2 C2 D2 E1 G1 F1 A1 (14) (13) (12) (11) (10) (9) (8) (7) (6) (5) D3 (15) (4) B1 B3 (16) (3) C1 F3 (17) E3 (18) (2) D1 AB4 (19) (1) V+ POL (20) (40) OSC 1 BP/GND (21) G3 (22) A3 (23) (39) OSC 2 C3 (24) G2 (25) (38) OSC 3 (37) TEST V- (26) (27) (28) (29) (30) (31) (32) INT BUFF A/Z IN LO IN HI COMM 2-82 (33) (34) CREF- CREF+ (35) (36) LO HI REF REF