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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G11
SCES487H SEPTEMBER 2003REVISED NOVEMBER 2016
SN74LVC1G11 Single 3-Input Positive-AND Gate
1
1 Features
1 Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model (C101)
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Maximum tpd of 4.1 ns at 3.3 V
Low Power Consumption, 10-μA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode Operation
2 Applications
AV Receivers
DLP Front Projection System
Digital Picture Frames
Digital Radio
Digital Still Cameras
Digital Video Cameras (DVC)
Embedded PCs
E-Books
Ethernet Switchs
GPS: Personal Navigation Devices
Handset: Smartphones
High-Speed Data Acquisition and Generation
Military: Radar and Sonar
Mobile Internet Devices
Notebook PC and Netbooks
Network-Attached Storage (NAS)
Power Line Communication Modems
Server PSU
STB, DVR, and Streaming Media
Speakers: USB
Tablets: Enterprise
Video Broadcasting and Infrastructure: Scalable
Platform and IP-Based Multi-Format Transcoders
Wireless Headsets, Keyboards, and Mice
3 Description
The SN74LVC1G11 performs the Boolean function
in positive logic.
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1G11DBV SOT-23 (6) 2.90 mm × 1.60 mm
SN74LVC1G11DCK SC70 (6) 2.00 mm × 1.25 mm
SN74LVC1G11DRY SON (6) 1.45 mm × 1.00 mm
SN74LVC1G11DSF SON (6) 1.00 mm × 1.00 mm
SN74LVC1G11YZP DSBGA (6) 1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2
SN74LVC1G11
SCES487H SEPTEMBER 2003REVISED NOVEMBER 2016
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics, CL= 15 pF, TA= –40°C to
+85°C......................................................................... 6
6.7 Switching Characteristics, CL= 30 pF or 50 pF, TA=
–40°C to +85°C.......................................................... 6
6.8 Switching Characteristics, CL= 30 pF or 50 pF, TA=
–40°C to +125°C........................................................ 6
6.9 Operating Characteristics.......................................... 6
6.10 Typical Characteristics............................................ 7
7 Parameter Measurement Information .................. 8
8 Detailed Description............................................ 10
8.1 Overview................................................................. 10
8.2 Functional Block Diagram....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support................. 14
12.1 Documentation Support ........................................ 14
12.2 Receiving Notification of Documentation Updates 14
12.3 Community Resources.......................................... 14
12.4 Trademarks........................................................... 14
12.5 Electrostatic Discharge Caution............................ 14
13 Mechanical, Packaging, and Orderable
Information........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (December 2015) to Revision H Page
Deleted 200-V Machine Model from Features ....................................................................................................................... 1
Changed pinout images to improve clarity of pin names and pin numbers ........................................................................... 3
Added DSBGA pin numbers to Pin Functions table .............................................................................................................. 3
Added Operating free-air temperature, TAfor BGA package................................................................................................. 5
Added Receiving Notification of Documentation Updates section ....................................................................................... 14
Changes from Revision F (December2013) to Revision G Page
Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Feature
Description section, Device Functional Modes,Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
Changes from Revision E (December 2011) to Revision F Page
Updated document to new TI data sheet format.................................................................................................................... 1
Removed Ordering Information table. .................................................................................................................................... 1
Updated operating temperature range ................................................................................................................................... 4
Changes from Revision D (January 2007) to Revision E Page
Added DRY and DSF packages to data sheet ...................................................................................................................... 1
1A 6 C
2GND 5 VCC
3B 4 Y
Not to scale
1 2
C
B
A
Not to scale
B Y
GND VCC
A C
1A 6 C
2GND 5 VCC
3B 4 Y
Not to scale
1A 6 C
2GND 5 VCC
3B 4 Y
Not to scale
3
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5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
YZP Package
6-Pin DSBGA
Bottom View
DCK Package
6-Pin SC70
Top View
DRY Package
6-Pin SON
Top View
DSF Package
6-Pin SON
Top View
See mechanical drawings for dimensions.
Pin Functions
PIN I/O DESCRIPTION
NAME SOT-23, SC70,
SON, SON DSBGA
A 1 A1 I A Input
B 3 C1 I B Input
C 6 A2 I C Input
GND 2 B1 Ground
VCC 5 B2 Power Supply
Y 4 C2 O Y Output
SPACE
4
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SCES487H SEPTEMBER 2003REVISED NOVEMBER 2016
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VIInput voltage(2) –0.5 6.5 V
VOVoltage applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VOVoltage applied to any output in the high or low state(2)(3) 0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic
discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.3 Recommended Operating Conditions
See note(1).MIN MAX UNIT
VCC Supply voltage Operating 1.65 5.5 V
Data retention only 1.5
VIH High-level input voltage
VCC = 1.65 V to 1.95 V 0.65 × VCC
V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VIL Low-level input voltage
VCC = 1.65 V to 1.95 V 0.35 × VCC
V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
IOH High-level output current
VCC = 1.65 V –4
mA
VCC = 2.3 V –8
VCC = 3 V –16
–24
VCC = 4.5 V –32
5
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Recommended Operating Conditions (continued)
See note(1).MIN MAX UNIT
IOL Low-level output current
VCC = 1.65 V 4
mA
VCC = 2.3 V 8
VCC = 3 V 16
24
VCC = 4.5 V 32
Δt/Δv Input transition rise or fall rate VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 ns/VVCC = 3.3 V ± 0.3 V 10
VCC = 5 V ± 0.5 V 10
TAOperating free-air temperature BGA package –40 85 °C
All other packages –40 125
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
SN74LVC1G11
UNITDBV (SOT-23) DCK (SC70) DRY (SON) YZP (DSBGA) DSF (SON)
6 PINS 6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 195.9 260.1 424.6 105.8 413.7 °C/W
RθJCtop Junction-to-case (top) thermal resistance 177.4 98.1 309 1.6 226.6 °C/W
RθJB Junction-to-board thermal resistance 51.7 63.1 292 10.8 317 °C/W
ψJT Junction-to-top characterization parameter 61.3 2.2 135.4 3.1 37.4 °C/W
ψJB Junction-to-board characterization parameter 51.3 62.4 292 10.8 317 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance °C/W
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH
IOH = –100 μA 1.65 V to 5.5 V VCC 0.1
V
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
IOH = –16 mA 3 V 2.4
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
VOL
IOL = 100 μA 1.65 V to 5.5 V 0.1
V
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
IOL = 16 mA 3 V 0.4
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
IIAll inputs VI= 5.5 V or GND 0 to 5.5 V ±5 μA
Ioff VIor VO= 5.5 V 0 ±10 μA
ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 μA
ΔICC One input at VCC 0.6 V,
Other inputs at VCC or GND 3 V to 5.5 V 500 μA
CiVI= VCC or GND 3.3 V 3.5 pF
6
SN74LVC1G11
SCES487H SEPTEMBER 2003REVISED NOVEMBER 2016
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6.6 Switching Characteristics, CL= 15 pF, TA= –40°C to +85°C
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC MIN MAX UNIT
tpd A, B, or C Y
VCC = 1.8 V ± 0.15 V 2.6 15.2
ns
VCC = 2.5 V ± 0.2 V 1.6 5.6
VCC = 3.3 V ± 0.3 V 1.2 4.1
VCC = 5 V ± 0.5 V 1 3.1
6.7 Switching Characteristics, CL= 30 pF or 50 pF, TA= –40°C to +85°C
over recommended operating free-air temperature range, CL= 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC MIN MAX UNIT
tpd A, B, or C Y
VCC = 1.8 V ± 0.15 V 2.9 17.2
ns
VCC = 2.5 V ± 0.2 V 1.4 6.2
VCC = 3.3 V ± 0.3 V 1.3 4.9
VCC = 5 V ± 0.5 V 1 3.5
6.8 Switching Characteristics, CL= 30 pF or 50 pF, TA= –40°C to +125°C
over recommended operating free-air temperature range, CL= 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC MIN MAX UNIT
tpd A, B, or C Y
VCC = 1.8 V ± 0.15 V 2.9 20
ns
VCC = 2.5 V ± 0.2 V 1.4 7.8
VCC = 3.3 V ± 0.3 V 1.3 6.2
VCC = 5 V ± 0.5 V 1 4.6
6.9 Operating Characteristics
TA= 25°C PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd Power dissipation capacitance f = 10 MHz
VCC = 1.8 V 18
pF
VCC = 2.5 V 19
VCC = 3.3 V 20
VCC = 5 V 23
–100
–80
–60
–40
–20
0
20
40
60
–1 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
TA= 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
VOH V
IOH mA
7
SN74LVC1G11
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6.10 Typical Characteristics
Figure 1. Output Current Drive
vs HIGH-level Output Voltage
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
t /t
PLH PHL Open
TEST S1
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1MW
1MW
1MW
1MW
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
15pF
15pF
15pF
15pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
8
SN74LVC1G11
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7 Parameter Measurement Information
Figure 2. Load Circuit and Voltage Waveforms
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
9
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Parameter Measurement Information (continued)
Figure 3. Load Circuit and Voltage Waveforms
A
CY
B
10
SN74LVC1G11
SCES487H SEPTEMBER 2003REVISED NOVEMBER 2016
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8 Detailed Description
8.1 Overview
This 3-input AND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G11 device features a three-input AND gate. The output state is determined by eight patterns of
3-bit input. All inputs can be connected to VCC or GND.
This device is fully-specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
The SN74LVC1G11 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows use in a broad
range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when VCC = 0 V.
8.4 Device Functional Modes
Table 1 lists the functional modes of SN74LVC1G11.
Table 1. Function Table
INPUTS OUTPUT
Y
ABC
H H H H
L X X L
X L X L
X X L L
Supply 1
0.1 F
Supply2
Supply 3
Vcc 3.3v
MCU
11
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G11 device offers logical AND configuration for many design applications. This example
describes basic power sequencing using the AND gate configuration. Power sequencing is often used in
applications that require a processor or other delicate device with specific voltage timing requirements in order to
protect the device from malfunctioning. In the application below, the power-good signals from the supplies tell the
MCU to continue an operation.
9.2 Typical Application
Figure 5. Typical Application Diagram
9.2.1 Design Requirements
Recommended input conditions:
For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
Recommended output conditions:
Load currents must not exceed ±50 mA.
Frequency selection criterion:
Figure 6 illustrates the effects of frequency on output current.
Added trace resistance and capacitance can reduce maximum frequency capability. Follow the layout
practices listed in the Layout section.
0
1
2
3
4
5
012345678910
Signal (V)
Time (ns)
Vin
Vout
C001
12
SN74LVC1G11
SCES487H SEPTEMBER 2003REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G11
Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated
Typical Application (continued)
9.2.2 Detailed Design Procedure
The SN74LVC1G11 device uses CMOS technology and has balanced output drive. Avoid bus contentions that
can drive currents that can exceed maximum limits.
The SN74LVC1G11 allows for performing the logical AND function with digital signals. Maintain input signals as
close as possible to either 0 V or VCC for optimal operation.
9.2.3 Application Curve
VCC =5V
Figure 6. Simulated Input-to-Output Voltage Response Showing Propagation Delay
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
To prevent power disturbance, ensure good bypass capacitance for each VCC terminal. For devices with a single-
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual
supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. Place the bypass capacitor as close to the power
terminal as possible for best results.
Vcc
Unused Input
Input
Output
Input
Unused Input Output
13
SN74LVC1G11
www.ti.com
SCES487H SEPTEMBER 2003REVISED NOVEMBER 2016
Product Folder Links: SN74LVC1G11
Submit Documentation FeedbackCopyright © 2003–2016, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs must never float.
In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must
not be left unconnected, because the undefined voltages at the outside connections result in undefined
operational states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs
of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
must be applied to any particular unused input depends on the function of the device. Generally they are tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section of the
part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float when
disabled.
11.2 Layout Example
Figure 7. Layout Diagrams
14
SN74LVC1G11
SCES487H SEPTEMBER 2003REVISED NOVEMBER 2016
www.ti.com
Product Folder Links: SN74LVC1G11
Submit Documentation Feedback Copyright © 2003–2016, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Jul-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1G11DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (C115, C11F, C11K,
C11R)
SN74LVC1G11DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C11F
SN74LVC1G11DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C11F
SN74LVC1G11DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C35, C3F, C3K, C3
R)
SN74LVC1G11DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C35, C3F, C3K, C3
R)
SN74LVC1G11DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C35, C3F, C3K, C3
R)
SN74LVC1G11DRYR ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C3
SN74LVC1G11DSFR ACTIVE SON DSF 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C3
SN74LVC1G11YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 C3N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Jul-2018
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G11 :
Automotive: SN74LVC1G11-Q1
Enhanced Product: SN74LVC1G11-EP
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G11DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G11DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G11DBVRG4 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G11DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G11DCKR SC70 DCK 6 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G11DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1G11DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G11YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-May-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G11DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G11DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G11DBVRG4 SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G11DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1G11DCKR SC70 DCK 6 3000 205.0 200.0 33.0
SN74LVC1G11DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G11DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1G11YZPR DSBGA YZP 6 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-May-2017
Pack Materials-Page 2
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4207181/G
www.ti.com
PACKAGE OUTLINE
C
6X 0.25
0.15
4X
0.5
5X 0.35
0.25
2X
1
0.6 MAX
0.05
0.00
3X 0.6
0.4
0.3
B1.05
0.95 A
1.5
1.4
(0.05) TYP (0.127) TYP
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
SCALE 8.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
www.ti.com
EXAMPLE STENCIL DESIGN
5X (0.3)
6X (0.2)
4X (0.5)
(0.6)
(R0.05) TYP
(0.35)
4222894/A 01/2018
USON - 0.6 mm max heightDRY0006A
PLASTIC SMALL OUTLINE - NO LEAD
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
SYMM
1
34
6
SYMM
www.ti.com
C
6X 0.22
0.12
6X 0.45
0.35
2X
0.7 4X
0.35
0.4 MAX
0.05
0.00
A1.05
0.95 B
1.05
0.95
(0.11) TYP
(0.1)
PIN 1 ID
4208186/F 10/2014
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
1
34
6
0.07 C A B
0.05 C
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
MECHANICAL DATA
DSF (S-PX2SON-N6) PLASTIC SMALL OUTLINE NO-LEAD
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1
TYP
0.5 TYP
6X 0.25
0.21
0.5
TYP
B E A
D
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
NanoFree Is a trademark of Texas Instruments.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
A
12
0.015 C A B
SYMM
SYMM
C
SCALE 9.000
D: Max =
E: Max =
1.418 mm, Min =
0.918 mm, Min =
1.358 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
6X ( )0.225 (0.5) TYP
(0.5) TYP
()
METAL
0.225 0.05 MAX
SOLDER MASK
OPENING
METAL
UNDER
MASK
()
SOLDER MASK
OPENING
0.225
0.05 MIN
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
6X ( 0.25) (R ) TYP0.05
METAL
TYP
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
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Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
SN74LVC1G11DBVRG4 SN74LVC1G11DBVR SN74LVC1G11DBVRE4 SN74LVC1G11DCKR
SN74LVC1G11DCKRE4 SN74LVC1G11DCKRG4 SN74LVC1G11YZPR SN74LVC1G11DRYR SN74LVC1G11DSFR