SN74LVC1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES222N - APRIL 1999 - REVISED FEBRUARY 2007 FEATURES * * * * * * * Available in the Texas Instruments NanoFreeTM Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4 ns at 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode DBV PACKAGE (TOP VIEW) A 1 5 2 GND 3 * * DCK PACKAGE (TOP VIEW) A VCC B B Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) 1 5 DRL PACKAGE (TOP VIEW) A VCC B 2 GND GND 4 3 4 1 5 VCC YZP PACKAGE (BOTTOM VIEW) GND 3 4 2 B 2 3 A 1 5 4 Y Y VCC Y Y See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G86 performs the Boolean function Y = A B or Y = AB + AB in positive logic. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA -40C to 85C NanoFreeTM - WCSP (DSBGA) Reel of 3000 0.23-mm Large Bump - YZP (Pb-free) SN74LVC1G86YZPR Reel of 3000 SN74LVC1G86DBVR Reel of 250 SN74LVC1G86DBVT Reel of 3000 SN74LVC1G86DCKR Reel of 250 SN74LVC1G86DCKT SOT (SOT-23) - DBV SOT (SC-70) - DCK (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) _ _ _CH_ C86_ CH_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2007, Texas Instruments Incorporated SN74LVC1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES222N - APRIL 1999 - REVISED FEBRUARY 2007 FUNCTION TABLE INPUTS A B OUTPUT Y L L L L H H H L H H H L EXCLUSIVE-OR LOGIC An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT = The output is active (low) if all inputs stand at the same logic level (i.e., A = B). 2k ODD-PARITY ELEMENT 2k + 1 The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V -0.5 6.5 V -0.5 VCC + 0.5 state (2) VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA Continuous current through VCC or GND JA Tstg (1) (2) (3) (4) 2 UNIT Package thermal impedance (4) DBV package 206 DCK package 252 YZP package 132 Storage temperature range -65 150 V C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74LVC1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES222N - APRIL 1999 - REVISED FEBRUARY 2007 Recommended Operating Conditions VCC Supply voltage (1) Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 Low-level input voltage V 0.65 x VCC 1.7 V 2 0.7 x VCC VCC = 1.65 V to 1.95 V VIL UNIT 0.35 x VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 x VCC VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V -4 VCC = 2.3 V IOH High-level output current -8 -16 VCC = 3 V VCC = 4.5 V -32 VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current t/v Input transition rise or fall rate 8 16 VCC = 3 V 32 VCC = 1.8 V 0.15 V, 2.5 V 0.2 V 20 VCC = 3.3 V 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 4.5 V VCC = 5 V 0.5 V TA mA -24 ns/V 5 -40 85 C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74LVC1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES222N - APRIL 1999 - REVISED FEBRUARY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 A VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = -8 mA 2.3 V 1.9 4.5 V IOL = 100 A 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA 0.4 ICC VI = VCC or GND, IO = 0 ICC One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 0.55 0 to 5.5 V 5 A 0 10 A 1.65 V to 5.5 V 10 A 500 A A or B input VI = 5.5 V or GND VI or VO = 5.5 V V 0.55 4.5 V Ioff (1) 3.8 3V IOL = 24 mA II 2.3 IOH = -32 mA IOL = 16 mA UNIT V 2.4 3V IOH = -24 mA MAX VCC - 0.1 IOH = -4 mA IOH = -16 mA VOL MIN TYP (1) VCC 3 V to 5.5 V 3.3 V 6 pF All typical values are at VCC = 3.3 V, TA = 25C. Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.1 9.1 1 4.5 0.6 4 0.8 3.3 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3.5 9.9 1.8 5.5 1.3 5 1 4 ns Operating Characteristics TA = 25C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 22 22 22 24 Submit Documentation Feedback UNIT pF SN74LVC1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES222N - APRIL 1999 - REVISED FEBRUARY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 15 pF 15 pF 15 pF 15 pF 1 M 1 M 1 M 1 M 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 5 SN74LVC1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCES222N - APRIL 1999 - REVISED FEBRUARY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC1G86DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G86YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2008 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G86 : * Enhanced Product: SN74LVC1G86-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G86DBVR SOT-23 DBV 5 3000 180.0 9.2 SN74LVC1G86DBVR SOT-23 DBV 5 3000 178.0 SN74LVC1G86DBVT SOT-23 DBV 5 250 178.0 SN74LVC1G86DBVT SOT-23 DBV 5 250 SN74LVC1G86DCKR SC70 DCK 5 SN74LVC1G86DCKR SC70 DCK SN74LVC1G86DCKR SC70 DCK SN74LVC1G86DCKT SC70 SN74LVC1G86DCKT SN74LVC1G86DCKT SN74LVC1G86DRLR 3.17 3.23 1.37 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 9.0 3.23 3.17 1.37 4.0 8.0 Q3 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 DCK 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3 SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 SN74LVC1G86DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74LVC1G86YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G86DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0 SN74LVC1G86DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 SN74LVC1G86DBVT SOT-23 DBV 5 250 180.0 180.0 18.0 SN74LVC1G86DBVT SOT-23 DBV 5 250 205.0 200.0 33.0 SN74LVC1G86DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G86DCKR SC70 DCK 5 3000 205.0 200.0 33.0 SN74LVC1G86DCKR SC70 DCK 5 3000 180.0 180.0 18.0 SN74LVC1G86DCKT SC70 DCK 5 250 205.0 200.0 33.0 SN74LVC1G86DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G86DCKT SC70 DCK 5 250 180.0 180.0 18.0 SN74LVC1G86DRLR SOT DRL 5 4000 180.0 180.0 30.0 SN74LVC1G86DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74LVC1G86YZPR DSBGA YZP 5 3000 220.0 220.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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