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FEATURES
See mechanical drawings for dimensions.
DBV PACKAGE
(TOP VIEW)
5
1VCC
A
2
B
34
GND Y
DRL PACKAGE
(TOP VIEW)
2
B
VCC
5
1
A
34
GNDGND Y
DCK PACKAGE
(TOP VIEW)
2
B
34
GND
VCC
5
A
Y
1
YZP PACKAGE
(BOTTOM VIEW)
2
B
VCC
15
A
GND 4
3Y
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G86SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222N – APRIL 1999 – REVISED FEBRUARY 2007
•Available in the Texas Instruments OperationNanoFree™ Package
•Latch-Up Performance Exceeds 100 mA Per•Supports 5-V V
CC
Operation JESD 78, Class II•Inputs Accept Voltages to 5.5 V •ESD Protection Exceeds JESD 22•Max t
pd
of 4 ns at 3.3 V – 2000-V Human-Body Model (A114-A)•Low Power Consumption, 10-µA Max I
CC
– 200-V Machine Model (A115-A)• ± 24-mA Output Drive at 3.3 V – 1000-V Charged-Device Model (C101)•I
off
Supports Partial-Power-Down Mode
This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G86 performs the Boolean function Y = A ⊕B or Y = AB + A B in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in trueform at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as thepackage.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 SN74LVC1G86YZPR _ _ _CH_0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000 SN74LVC1G86DBVRSOT (SOT-23) – DBV C86_–40°C to 85°C
Reel of 250 SN74LVC1G86DBVT
Reel of 3000 SN74LVC1G86DCKRSOT (SC-70) – DCK CH_Reel of 250 SN74LVC1G86DCKT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one followingcharacter to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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EXCLUSIVE-OR LOGIC
= 1
EXCLUSIVE OR
These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be shown at any two ports.
= 2k 2k + 1
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
Absolute Maximum Ratings
(1)
SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222N – APRIL 1999 – REVISED FEBRUARY 2007
FUNCTION TABLE
INPUTS
OUTPUT
YA B
LLLL H HH L HH H L
An exclusive-OR gate has many applications, some of which can be represented better by alternative logicsymbols.
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high or low state
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CC
or GND ±100 mADBV package 206θ
JA
Package thermal impedance
(4)
DCK package 252 °C/WYZP package 132T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
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Recommended Operating Conditions
(1)
SN74LVC1G86SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222N – APRIL 1999 – REVISED FEBRUARY 2007
MIN MAX UNIT
Operating 1.65 5.5V
CC
Supply voltage VData retention only 1.5V
CC
= 1.65 V to 1.95 V 0.65 × V
CC
V
CC
= 2.3 V to 2.7 V 1.7V
IH
High-level input voltage VV
CC
= 3 V to 3.6 V 2V
CC
= 4.5 V to 5.5 V 0.7 × V
CC
V
CC
= 1.65 V to 1.95 V 0.35 × V
CC
V
CC
= 2.3 V to 2.7 V 0.7V
IL
Low-level input voltage VV
CC
= 3 V to 3.6 V 0.8V
CC
= 4.5 V to 5.5 V 0.3 × V
CC
V
I
Input voltage 0 5.5 VV
O
Output voltage 0 V
CC
VV
CC
= 1.65 V –4V
CC
= 2.3 V –8I
OH
High-level output current –16 mAV
CC
= 3 V
–24V
CC
= 4.5 V –32V
CC
= 1.65 V 4V
CC
= 2.3 V 8I
OL
Low-level output current 16 mAV
CC
= 3 V
24V
CC
= 4.5 V 32V
CC
= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20∆t/ ∆v Input transition rise or fall rate V
CC
= 3.3 V ± 0.3 V 10 ns/VV
CC
= 5 V ± 0.5 V 5T
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics
Switching Characteristics
Switching Characteristics
Operating Characteristics
SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222N – APRIL 1999 – REVISED FEBRUARY 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= –100 µA 1.65 V to 5.5 V V
CC
– 0.1I
OH
= –4 mA 1.65 V 1.2I
OH
= –8 mA 2.3 V 1.9V
OH
VI
OH
= –16 mA 2.43 VI
OH
= –24 mA 2.3I
OH
= –32 mA 4.5 V 3.8I
OL
= 100 µA 1.65 V to 5.5 V 0.1I
OL
= 4 mA 1.65 V 0.45I
OL
= 8 mA 2.3 V 0.3V
OL
VI
OL
= 16 mA 0.43 VI
OL
= 24 mA 0.55I
OL
= 32 mA 4.5 V 0.55I
I
A or B input V
I
= 5.5 V or GND 0 to 5.5 V ±5 µAI
off
V
I
or V
O
= 5.5 V 0 ±10 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 1.65 V to 5.5 V 10 µA∆I
CC
One input at V
CC
– 0.6 V, Other inputs at V
CC
or GND 3 V to 5.5 V 500 µAC
i
V
I
= V
CC
or GND 3.3 V 6 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
over recommended operating free-air temperature range, C
L
= 15 pF (unless otherwise noted) (see Figure 1 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A or B Y 2.1 9.1 1 4.5 0.6 4 0.8 3.3 ns
over recommended operating free-air temperature range, C
L
= 30 pF or 50 pF (unless otherwise noted) (see Figure 2 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A or B Y 3.5 9.9 1.8 5.5 1.3 5 1 4 ns
T
A
= 25°C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP TYP
C
pd
Power dissipation capacitance f = 10 MHz 22 22 22 24 pF
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH − V∆≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 MΩ
1 MΩ
1 MΩ
1 MΩ
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN74LVC1G86SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222N – APRIL 1999 – REVISED FEBRUARY 2007
Figure 1. Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH − V∆≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222N – APRIL 1999 – REVISED FEBRUARY 2007
Figure 2. Load Circuit and Voltage Waveforms
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LVC1G86DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DCKT ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DRLR ACTIVE SOT DRL 5 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G86YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2008
Addendum-Page 1
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G86 :
•Enhanced Product: SN74LVC1G86-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G86DBVR SOT-23 DBV 5 3000 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3
SN74LVC1G86DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G86DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G86DBVT SOT-23 DBV 5 250 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3
SN74LVC1G86DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G86DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G86DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G86DCKT SC70 DCK 5 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G86DCKT SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G86DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G86DRLR SOT DRL 5 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1G86DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G86YZPR DSBGA YZP 5 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G86DBVR SOT-23 DBV 5 3000 205.0 200.0 33.0
SN74LVC1G86DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74LVC1G86DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
SN74LVC1G86DBVT SOT-23 DBV 5 250 205.0 200.0 33.0
SN74LVC1G86DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G86DCKR SC70 DCK 5 3000 205.0 200.0 33.0
SN74LVC1G86DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74LVC1G86DCKT SC70 DCK 5 250 205.0 200.0 33.0
SN74LVC1G86DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G86DCKT SC70 DCK 5 250 180.0 180.0 18.0
SN74LVC1G86DRLR SOT DRL 5 4000 180.0 180.0 30.0
SN74LVC1G86DRLR SOT DRL 5 4000 202.0 201.0 28.0
SN74LVC1G86YZPR DSBGA YZP 5 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jul-2012
Pack Materials-Page 2
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