LMC6064 www.ti.com SNOS656D - AUGUST 2000 - REVISED MARCH 2013 LMC6064 Precision CMOS Quad Micropower Operational Amplifier Check for Samples: LMC6064 FEATURES DESCRIPTION 1 (Typical Unless Otherwise Noted) 2 * * * * * * * * Low Offset Voltage: 100 V Ultra Low Supply Current: 16 A/Amplifier Operates from 4.5V to 15V Single Supply Ultra Low Input Bias Current: 10 fA Output Swing within 10 mV of Supply Rail, 100k Load Input Common-Mode Range Includes V- High Voltage Gain: 140 dB Improved Latchup Immunity APPLICATIONS * * * * * * * Instrumentation Amplifier Photodiode and Infrared Detector Preamplifier Transducer Amplifiers Hand-Held Analytic Instruments Medical Instrumentation D/A Converter Charge Amplifier for Piezoelectric Transducers The LMC6064 is a precision quad low offset voltage, micropower operational amplifier, capable of precision single supply operation. Performance characteristics include ultra low input bias current, high voltage gain, rail-to-rail output swing, and an input common mode voltage range that includes ground. These features, plus its low power consumption make the LMC6064 ideally suited for battery powered applications. Other applications using the LMC6064 include precision full-wave rectifiers, integrators, references, sample-and-hold circuits, and true instrumentation amplifiers. This device is built with TI's advanced double-Poly Silicon-Gate CMOS process. For designs that require higher speed, see the LMC6084 precision quad operational amplifier. For single or dual operational amplifier with similar features, see the LMC6061 or LMC6062 respectively. PATENT PENDING Connection Diagram 14-Pin PDIP/SOIC Top View 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated LMC6064 SNOS656D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Low-Leakage Sample and Hold These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Differential Input Voltage Supply Voltage (V+) +0.3V, Voltage at Input/Output Pin (V-) -0.3V + - Supply Voltage (V - V ) 16V Output Short Circuit to V+ See (4) Output Short Circuit to V- See (5) Lead Temperature (Soldering, 10 sec.) 260C Storage Temp. Range -65C to +150C Junction Temperature 150C ESD Tolerance (6) 2 kV Current at Input Pin 10 mA Current at Output Pin 30 mA Current at Power Supply Pin 40 mA Power Dissipation See (7) (1) (2) (3) (4) (5) (6) (7) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. For ensured Military Temperature Range parameters see RETSMC6064X. Do not connect output to V+, when V+ is greater than 13V or reliability witll be adversely affected. Applies to both single-supply and split-supply operation. Continous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Output currents in excess of 30 mA over long term may adversely affect reliability. Human body model, 1.5 k in series with 100 pF. The maximum power dissipation is a function of TJ(Max), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(Max) - TA)/JA. Operating Ratings (1) Temperature Range -55C TJ +125C LMC6064AM LMC6064AI, LMC6064I 4.5V V+ 15.5V Supply Voltage Thermal Resistance (JA) (2) 14-Pin PDIP 81C/W 14-Pin SOIC 126C/W See (3) Power Dissipation (1) (2) (3) 2 -40C TJ +85C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. All numbers apply for packages soldered directly into a PC board. For operating at elevated temperatures the device must be derated based on the thermal resistance JA with PD = (TJ-TA)/JA. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 LMC6064 www.ti.com SNOS656D - AUGUST 2000 - REVISED MARCH 2013 DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol VOS Parameter Conditions Input Offset Voltage TCVOS Input Offset Voltage Average Drift IB Input Bias Current Typ (1) LMC6064AM LMC6064AI LMC6064I Limit (2) Limit (2) Limit (2) 350 350 800 V 1200 900 1300 Max 100 V/C 1.0 0.010 pA 100 IOS Input Offset Current RIN Input Resistance CMRR Common Mode 4 -PSRR 2 0V VCM 12.0V Max Tera 85 + 75 75 66 dB 70 72 63 Min 75 75 66 dB 70 72 63 Min 84 74 dB Min Rejection Ratio V = 15V Positive Power Supply 5V V+ 15V Rejection Ratio VO = 2.5V Negative Power Supply 0V V- -10V 100 84 70 81 71 Input Common-Mode V+ = 5V and 15V -0.4 -0.1 -0.1 -0.1 V Voltage Range for CMRR 60 dB 0 0 0 Max V+ - 2.3 V+ - 2.3 V+ - 2.3 V 85 + Large Signal RL = 100 k (3) RL = 25 k (3) + V - 2.6 V - 2.5 V+ - 2.5 Min 400 400 300 V/mV Sourcing 4000 200 300 200 Min Sinking 3000 180 180 90 V/mV 70 100 60 Min Sourcing 3000 400 400 200 V/mV 150 150 80 Min Sinking 2000 100 100 70 V/mV 35 50 35 Min Voltage Gain (1) (2) (3) 2 >10 V+ - 1.9 AV Max pA Rejection Ratio VCM 4 0.005 100 +PSRR Units Typical values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V VO 11.5V. For Sinking tests, 2.5V VO 7.5V. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 3 LMC6064 SNOS656D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol VO Parameter Conditions V+ = 5V Output Swing Typ (1) LMC6064AM LMC6064AI LMC6064I Limit (2) Limit (2) Limit (2) 4.990 4.990 4.950 V 4.970 4.980 4.925 Min 0.010 0.010 0.050 V 0.030 0.020 0.075 Max 4.975 4.975 4.950 V 4.955 4.965 4.850 Min 0.010 0.020 0.020 0.050 V 0.045 0.035 0.150 Max 14.990 14.975 14.975 14.950 V 14.955 14.965 14.925 Min 0.025 0.025 0.050 V 0.050 0.035 0.075 Max 14.900 14.900 14.850 V 14.800 14.850 14.800 Min 0.050 0.050 0.100 V 0.200 0.150 0.200 Max 13 mA Min 4.995 RL = 100 k to 2.5V 0.005 V+ = 5V 4.990 RL = 25 k to 2.5V V+ = 15V RL = 100 k to 7.5V 0.010 V+ = 15V 14.965 RL = 25 k to 7.5V 0.025 IO Output Current Sourcing, VO = 0V 22 16 16 8 10 8 Sinking, VO = 5V 21 16 16 16 mA 7 8 8 Min 15 15 15 mA 9 10 10 Min 20 20 20 mA 7 8 8 Min + V = 5V IO Output Current Sourcing, VO = 0V 25 V+ = 15V Sinking, VO = 13V (4) IS Supply Current 76 76 92 A 120 92 112 Max All Four Amplifiers 94 94 114 A 140 110 132 Max + V = +15V, VO = 7.5V (4) 4 26 V+ = +5V, VO = 1.5V All Four Amplifiers + Units 64 80 + Do not connect output to V , when V is greater than 13V or reliability witll be adversely affected. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 LMC6064 www.ti.com SNOS656D - AUGUST 2000 - REVISED MARCH 2013 AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol SR Parameter Slew Rate GBW Gain-Bandwidth Product m Phase Margin Conditions See (3) (4) Typ (1) 35 LMC6064AM LMC6064AI LMC6064I Limit (2) Limit (2) Limit (2) 20 20 15 8 10 7 Units V/ms Min 100 kHz 50 Deg Amp-to-Amp Isolation See 155 dB en Input-Referred Voltage Noise F = 1 kHz 83 nV/Hz in Input-Referred Current Noise F = 1 kHz 0.0002 pA/Hz T.H.D. Total Harmonic Distortion F = 1 kHz, AV = -5 0.01 % RL = 100 k, VO = 2 VPP 5V Supply (1) (2) (3) (4) Typical values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Input referred V+ = 15V and RL = 100 k connected to 7.5V. Each amp excited in turn with 100 Hz to produce VO = 12 VPP. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 5 LMC6064 SNOS656D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 6 Distribution of LMC6064 Input Offset Voltage (TA = +25C) Distribution of LMC6064 Input Offset Voltage (TA = -55C) Figure 1. Figure 2. Distribution of LMC6064 Input Offset Voltage (TA = +125C) Input Bias Current vs Temperature Figure 3. Figure 4. Supply Current vs Supply Voltage Input Voltage vs Output Voltage Figure 5. Figure 6. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 LMC6064 www.ti.com SNOS656D - AUGUST 2000 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Common Mode Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Figure 7. Figure 8. Input Voltage Noise vs Frequency Output Characteristics Sourcing Current Figure 9. Figure 10. Output Characteristics Sinking Current Gain and Phase Response vs Temperature (-55C to +125C) Figure 11. Figure 12. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 7 LMC6064 SNOS656D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 Gain and Phase Response vs Capacitive Load with RL = 20 k Gain and Phase Response vs Capacitive Load with RL = 500 k Figure 13. Figure 14. Open Loop Frequency Response Inverting Small Signal Pulse Response Figure 15. Figure 16. Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 17. Figure 18. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 LMC6064 www.ti.com SNOS656D - AUGUST 2000 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Non-Inverting Large Signal Pulse Response Crosstalk Rejection vs Frequency Figure 19. Figure 20. Stability vs Capacitive Load, RL = 20 k Stability vs Capacitive Load RL = 1 M Figure 21. Figure 22. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 9 LMC6064 SNOS656D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6064 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6064 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6064. Although the LMC6064 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins. When high input impedances are demanded, guarding of the LMC6064 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work). The effect of input capacitance can be compensated for by adding a capacitor. Place a capacitor, Cf, around the feedback resistor (as in Figure 23 ) such that: (1) or R1 CIN R2 Cf (2) Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on compensating for input capacitance. Figure 23. Canceling the Effect of Input Capacitance CAPACITIVE LOAD TOLERANCE All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is normally included in this integrator stage. The frequency location of the dominate pole is affected by the resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistive load in parallel with the capacitive load (see typical curves). Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 24. 10 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 LMC6064 www.ti.com SNOS656D - AUGUST 2000 - REVISED MARCH 2013 Figure 24. LMC6064 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 24, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 25). Typically a pull up resistor conducting 10 A or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). Figure 25. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6064, typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6064's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals etc. connected to the op-amp's inputs, as in Figure 26. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6064's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 would cause only 0.05 pA of leakage current. See Figure 27 for typical connections of guard rings for standard op-amp configurations. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 11 LMC6064 SNOS656D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com Figure 26. Example of Guard Ring in P.C. Board Layout Inverting Amplifier Non-Inverting Amplifier Follower Figure 27. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 28. 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 LMC6064 www.ti.com SNOS656D - AUGUST 2000 - REVISED MARCH 2013 Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC6064 and LMC6082 are designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will also inhibit latchup susceptibility. (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). Figure 28. Air Wiring Typical Single-Supply Applications (V+ = 5.0 VDC) The extremely high input impedance, and low power consumption, of the LMC6064 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. Figure 29 shows an instrumentation amplifier that features high differential and common mode input resistance (>1014), 0.01% gain accuracy at AV = 100, excellent CMRR with 1 k imbalance in bridge source resistance. Input current is less than 100 fA and offset drift is less than 2.5 V/C. R2 provides a simple means of adjusting gain over a wide range without degrading CMRR. R7 is an initial trim used to maximize CMRR without using super precision matched resistors. For good CMRR over temperature, low drift resistors should be used. If R1 = R5, R3 = R6, and R4 = R7; then Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 13 LMC6064 SNOS656D - AUGUST 2000 - REVISED MARCH 2013 www.ti.com AV 100 for circuit shown (R2 = 9.822k). Figure 29. Instrumentation Amplifier Figure 30. Low-Leakage Sample and Hold Figure 31. 1 Hz Square Wave Oscillator 14 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 LMC6064 www.ti.com SNOS656D - AUGUST 2000 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LMC6064 15 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMC6064AIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC6064 AIM LMC6064AIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC6064 AIM LMC6064IM/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC6064IM LMC6064IMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC6064IM LMC6064IN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS & no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 LMC6064IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6064AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6064IMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6064AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMC6064IMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NFF0014A N0014A N14A (Rev G) www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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