LT1374CR-5 SYNC - Linear Technology

LT1374

4.5A, 500kHz Step-Down

Switching Regulator

■

Constant 500kHz Switching Frequency

■

Easily Synchronizable

■

Uses All Surface Mount Components

■

Inductor Size Reduced to 1.8

■

Saturating Switch Design: 0.07Ω

■

Effective Supply Current: 2.5mA

■

Shutdown Current: 20µA

■

Cycle-by-Cycle Current Limiting

The LT

1374 is a 500kHz monolithic buck mode switching

regulator. A 4.5A switch is included on the die along with

all the necessary oscillator, control and logic circuitry. High

switching frequency allows a considerable reduction in the

size of external components. The topology is current mode

for fast transient response and good loop stability. Both

fixed output voltage and adjustable parts are available.

A special high speed bipolar process and new design tech-

niques achieve high efficiency at high switching frequency.

Efficiency is maintained over a wide output current range

by using the output to bias the circuitry

and by utilizing a

supply boost

capacitor to saturate the power switch.

The LT1374 fits into standard 7-pin DD, TO-220 and fused

lead SO-8 packages. Full cycle-by-cycle short-circuit

protection and thermal shutdown are provided. Standard

surface mount external parts are used, including the

inductor and capacitors. There is the optional function of

shutdown or synchronization. A shutdown signal reduces

supply current to 20µA. Synchronization allows an exter-

nal logic level signal to increase the internal oscillator from

580kHz to 1MHz.

, LTC and LT are registered trademarks of Linear Technology Corporation.

5V Buck Converter

LOAD CURRENT (A)

EFFICIENCY (%)

100

70 2.0 2.5 3.0 3.5

1374 TA02

0.5 1.0 1.5 4.0

OUT

= 5V

= 10V

L = 10µH

Efficiency vs Load Current

BOOST

LT1374-5

SHDN

OUTPUT**

5V, 4.25A

* RIPPLE CURRENT RATING ≥ I

OUT

** INCREASE L1 TO 10µH FOR LOAD CURRENTS ABOVE 3.5A AND TO 20µH ABOVE 4A

SEE APPLICATIONS INFORMATION

INPUT

6V TO 25V

1374 TA01

0.27µF

1.5nF

MBRS330T3

100µF, 10V

SOLID

TANTALUM

C3*

10µF TO

50µFDEFAULT

= ON

1N914

L1**

5µH

SENSE

BIAS

GND V

■

Portable Computers

■

Battery-Powered Systems

■

Battery Chargers

■

Distributed Power

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

LT1374

ABSOLUTE MAXIMUM RATINGS

Input Voltage

LT1374 ............................................................... 25V

LT1374HV .......................................................... 32V

BOOST Pin Voltage ................................................. 38V

BOOST Pin Above Input Voltage ............................. 15V

SHDN Pin Voltage..................................................... 7V

BIAS Pin Voltage ...................................................... 7V

FB Pin Voltage (Adjustable Part)............................ 3.5V

FB Pin Current (Adjustable Part)............................ 1mA

SENSE Voltage (Fixed 5V Part) ................................. 7V

SYNC Pin Voltage ..................................................... 7V

Operating Junction Temperature Range

LT1374C............................................... 0°C to 125° C

LT1374I ........................................... –40°C to 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

PACKAGE/ORDER INFORMATION

R PACKAGE

7-LEAD PLASTIC DD

FRONT VIEW

TAB

GND

FB OR SENSE*

BOOST

GND

SYNC OR SHDN*

TOP VIEW

S8 PACKAGE

8-LEAD PLASTIC SO

BOOST

FGND

BIAS

SYNC

OR SHDN*

FB OR

SENSE*

=80°C/W WITH FUSED (FGND) GROUND PIN

CONNECTED TO GROUND PLANE OR LARGE LANDS

ORDER PART NUMBER

LT1374IS8

LT1374IS8-5

LT1374IS8-SYNC

LT1374IS8-5 SYNC

LT1374HVIS8

LT1374CS8

LT1374CS8-5

LT1374CS8-SYNC

LT1374CS8-5 SYNC

LT1374HVCS8

S8 PART MARKING

JMAX

= 125°C, θ

= 30°C/W

WITH PACKAGE SOLDERED TO 0.5 SQUARE INCH

COPPER AREA OVER BACKSIDE GROUND PLANE

OR INTERNAL POWER PLANE. θ

CAN VARY

FROM 20°C/W TO >40°C/W DEPENDING ON

MOUNTING TECHNIQUES

ORDER PART NUMBER ORDER PART NUMBER

LT1374CR

LT1374CR-5

LT1374CR-SYNC

LT1374CR-5 SYNC

LT1374HVCR

LT1374IR

LT1374IR-5

LT1374IR-SYNC

LT1374IR-5 SYNC

LT1374HVIR

LT1374CT7

LT1374CT7-5

LT1374IT7

LT1374IT7-5

T7 PACKAGE

7-LEAD PLASTIC TO-220

FB OR SENSE*

BOOST

GND

SHDN

FRONT VIEW

TAB

GND

JMAX

= 125°C, θ

= 50°C/ W, θ

= 4°C/W

*Default is the adjustable output voltage device with FB pin and shutdown function. Option -5 replaces FB with SENSE pin for fixed 5V output applications.

-SYNC replaces SHDN with SYNC pin for applications requiring synchronization. Consult factory for Military grade parts.

1374

13745

1374SN

3745SN

1374HV

1374I

1374I5

374ISN

74I5SN

1374HVI

(Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Feedback Voltage (Adjustable) 2.39 2.42 2.45 V

All Conditions ●2.36 2.48 V

Sense Voltage (Fixed 5V) 4.94 5.0 5.06 V

All Conditions ●4.90 5.10 V

SENSE Pin Resistance 71014 kΩ

Reference Voltage Line Regulation 5V ≤ V

≤ 25V (5V ≤ V

≤ 32V for LT1374HV) 0.01 0.03 %/V

The ● denotes specifications which apply over the full operating tempera-

ture range, otherwise specifications are at TJ = 25°C. VIN = 15V, VC = 1.5V, Boost = VIN + 5V, switch open, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

LT1374

PARAMETER CONDITIONS MIN TYP MAX UNITS

Feedback Input Bias Current ●0.5 2 µA

Error Amplifier Voltage Gain (Notes 2, 8) 200 400

Error Amplifier Transconductance ∆I (V

) = ±10µA (Note 8) 1500 2000 2700 µMho

●1000 3100 µMho

Pin to Switch Current Transconductance 5.3 A/V

Error Amplifier Source Current V

= 2.1V or V

SENSE

= 4.4V ●140 225 320 µA

Error Amplifier Sink Current V

= 2.7V or V

SENSE

= 5.6V ●140 225 320 µA

Pin Switching Threshold Duty Cycle = 0 0.9 V

Pin High Clamp 2.1 V

Switch Current Limit V

Open, V

= 2.1V or V

SENSE

= 4.4V, DC ≤ 50% ●4.5 6 8.5 A

Slope Compensation (Note 9) DC = 80% 0.8 A

Switch On Resistance (Note 7) I

= 4.5A 0.07 0.1 Ω

●0.13 Ω

Maximum Switch Duty Cycle V

= 2.1V or V

SENSE

= 4.4V 90 93 %

●86 93 %

Switch Frequency V

Set to Give 50% Duty Cycle 460 500 540 kHz

●440 560 kHz

Switch Frequency Line Regulation 5V

≤ V

≤ 25V, (5V ≤ V

≤ 32V for LT1374HV) ●0 0.15 %/V

Frequency Shifting Threshold on FB Pin ∆f = 10kHz ●0.8 1.0 1.3 V

Minimum Input Voltage (Note 3) ●5.0 5.5 V

Minimum Boost Voltage (Note 4) I

≤ 4.5A ●2.3 3.0 V

Boost Current (Note 5) I

= 1A ●20 35 mA

= 4.5A ●90 140 mA

Supply Current (Note 6) V

BIAS

= 5V ●0.9 1.4 mA

BIAS Supply Current (Note 6) V

BIAS

= 5V ●3.2 4.0 mA

Shutdown Supply Current V

SHDN

= 0V, V

≤ 25V, V

= 0V, V

Open 20 50 µA

●75 µA

SHDN

= 0V, V

≤ 32V, V

= 0V, V

Open 30 75 µA

●100 µA

Lockout Threshold V

Open ●2.3 2.38 2.46 V

Shutdown Thresholds V

Open Device Shutting Down ●0.13 0.37 0.60 V

Device Starting Up ●0.25 0.45 0.7 V

Synchronization Threshold ●1.5 2.2 V

Synchronizing Range 580 1000 kHz

SYNC Pin Input Resistance 40 kΩ

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: Gain is measured with a V

swing equal to 200mV above the

switching threshold level to 200mV below the upper clamp level.

Note 3: Minimum input voltage is not measured directly, but is guaranteed

by other tests. It is defined as the voltage where internal bias lines are still

regulated so that the reference voltage and oscillator frequency remain

constant. Actual minimum input voltage to maintain a regulated output will

depend on output voltage and load current. See Applications Information.

Note 4: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

Note 5: Boost current is the current flowing into the boost pin with the pin

held 5V above input voltage. It flows only during switch on time.

Note 6: V

supply current is the current drawn when the BIAS pin is held

at 5V and switching is disabled. If the BIAS pin is unavailable or open

circuit, the sum of V

and BIAS supply currents will be drawn by the V

pin.

Note 7: Switch on resistance is calculated by dividing V

to V

voltage

by the forced current (4.5A). See Typical Performance Characteristics for

the graph of switch voltage at other currents.

Note 8: Transconductance and voltage gain refer to the internal amplifier

exclusive of the voltage divider. To calculate gain and transconductance,

refer to the SENSE pin on the fixed voltage parts. Divide values shown by

the ratio V

OUT

/2.42.

Note 9: Slope compensation is the current subtracted from the switch

current limit at 80% duty cycle. See Maximum Output Load Current in the

Applications Information section for further details.

The ● denotes specifications which apply over the full operating tempera-

ture range, otherwise specifications are at TJ = 25°C. VIN = 15V, VC = 1.5V, Boost = VIN + 5V, switch open, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

LT1374

TYPICAL PERFORMANCE CHARACTERISTICS

Switch Voltage Drop

SWITCH CURRENT (A)

SWITCH VOLTAGE (mV)

250

200

400 125°C

25°C

350

300

1374 G18

150

100

0123

500

450

–40°C

Feedback Pin Voltage

TEMPERATURE (°C)

–50

2.430

2.425

2.420

2.415

2.410 100

1374 G03

–25 0 25 50 75 125

FEEDBACK VOLTAGE (V)

Switch Peak Current Limit

DUTY CYCLE (%)

SWITCH PEAK CURRENT (A)

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0 80

1374 G02

20 40 60 100

TYPICAL

MINIMUM

Shutdown Pin Bias Current

TEMPERATURE (°C)

–50

500

400

300

200

025 75

1374 G04

–25 0 50 100 125

CURRENT (µA)

CURRENT REQUIRED TO FORCE SHUTDOWN

(FLOWS OUT OF PIN). AFTER SHUTDOWN,

CURRENT DROPS TO A FEW µA

AT 2.38V STANDBY THRESHOLD

(CURRENT FLOWS OUT OF PIN)

Standby and Shutdown Thresholds Shutdown Supply Current

JUNCTION TEMPERATURE (°C)

–50

2.40

2.36

2.32

0.8

0.4

025 75

1374 G05

–25 0 50 100 125

SHUTDOWN PIN VOLTAGE (V)

STANDBY

START-UP

SHUTDOWN

INPUT VOLTAGE (V)

INPUT SUPPLY CURRENT (µA)

05 101520

1374 G06

VSHDN = 0V

Shutdown Supply Current

SHUTDOWN VOLTAGE (V)

INPUT SUPPLY CURRENT (µA)

00.1 0.2 0.3 0.4

1374 G07

= 25V

= 10V

Error Amplifier Transconductance

FREQUENCY (Hz)

GAIN (µMho)

PHASE (DEG)

3000

2500

2000

1500

1000

500

200

150

100

–50

100 10k 100k 10M

1374 G09

1k 1M

GAIN

PHASE

ERROR AMPLIFIER EQUIVALENT CIRCUIT

OUT

200k

OUT

12pF

LOAD

= 50Ω

2 × 10

–3

)(

Error Amplifier Transconductance

JUNCTION TEMPERATURE (°C)

–50

TRANSCONDUCTANCE (µMho)

2500

2000

1500

1000

500

0050 75

1374 G08

–25 25 100 125

LT1374

TYPICAL PERFORMANCE CHARACTERISTICS

FEEDBACK PIN VOLTAGE (V)

SWITCHING FREQUENCY (kHz) OR CURRENT (µA)

500

400

300

200

100

02.0

1374 G10

0.5 1.0 1.5 2.5

SWITCHING

FREQUENCY

FEEDBACK PIN

CURRENT

Frequency Foldback

LOAD CURRENT (mA)

5.8

INPUT VOLTAGE (V)

6.0

6.2

6.4

10 100 1000

1374 G12

5.6

5.4

5.2

5.0

MINIMUM

RUNNING

VOLTAGE

MINIMUM

STARTING

VOLTAGE

Minimum Input Voltage

with 5V Output

TEMPERATURE (°C)

–50

550

540

530

520

510

500

490

480

470

460

450 100

1374 G11

–25 0 25 50 75 125

FREQUENCY (kHz)

Switching Frequency

Maximum Load Current

at VOUT = 10V

INPUT VOLTAGE (V)

CURRENT (A)

4.5

4.0

3.5

3.0 5101520

1374 G13

L = 20µH

L = 10µH

L = 5µH

OUT

= 10V

Maximum Load Current

at VOUT = 3.3V

INPUT VOLTAGE (V)

CURRENT (A)

4.5

4.0

3.5

3.0 5101520

1374 G14

L = 20µH

L = 10µH

L = 5µH

OUT

= 3.3V

Maximum Load Current

at VOUT = 5V

INPUT VOLTAGE (V)

CURRENT (A)

4.5

4.0

3.5

3.0 5101520

1374 G15

L = 20µH

L = 10µH

L = 5µH

OUT

= 5V

BOOST Pin Current

SWITCH CURRENT (A)

BOOST PIN CURRENT (mA)

12345

1374 G16

100

90 DUTY CYCLE = 100%

Inductor Core Loss

INDUCTANCE (µH)

CORE LOSS (W)

CORE LOSS (% OF 5W LOAD)

1.0

0.1

0.01

0.001 10 15 20

1.2

0.8

0.4

0.2

0.12

0.08

0.04

0.02

1374 G01

TYPE 52

POWDERED IRON

Kool Mµ

PERMALLOY

µ = 125

OUT

= 5V, V

= 10V, I

OUT

= 1A

CORE LOSS IS

INDEPENDENT OF LOAD

CURRENT UNTIL LOAD CURRENT FALLS

LOW ENOUGH FOR CIRCUIT TO GO INTO

DISCONTINUOUS MODE

VC Pin Shutdown Threshold

JUNCTION TEMPERATURE (°C)

–50

1.4

1.2

1.0

0.8

0.6

0.4 100

1374 G11

–25 0 25 50 75 125

THRESHOLD VOLTAGE (V)

SHUTDOWN

Kool Mµ is a registered trademark of Magnetics, Inc.

LT1374

PIN FUNCTIONS

UUU

FB/SENSE: The feedback pin is the input to the error

amplifier which is referenced to an internal 2.42V source.

An external resistive divider is used to set the output

voltage. The fixed voltage (-5) parts have the divider

included on-chip and the FB pin is used as a SENSE pin,

connected directly to the 5V output. Three additional

functions are performed by the FB pin. When the pin

voltage drops below 1.7V, switch current limit is reduced.

Below 1.5V the external sync function is disabled. Below

1V, switching frequency is also reduced. See Feedback Pin

Function section in Applications Information for details.

BOOST: The BOOST pin is used to provide a drive voltage,

higher than the input voltage, to the internal bipolar NPN

power switch. Without this added voltage, the typical

switch voltage loss would be about 1.5V. The additional

boost voltage allows the switch to saturate and voltage

loss approximates that of a 0.07Ω FET structure. Effi-

ciency improves from 75% for conventional bipolar de-

signs to > 89% for these new parts.

: This is the collector of the on-chip power NPN switch.

This pin powers the internal circuitry and internal regulator

when the BIAS pin is not present. At NPN switch on and off,

high dI/dt edges occur on this pin. Keep the external

bypass and catch diode close to this pin. All trace induc-

tance on this path will create a voltage spike at switch off,

adding to the V

voltage across the internal NPN.

GND: The GND pin connection needs consideration for

two reasons. First, it acts as the reference for the regulated

output, so load regulation will suffer if the “ground” end of

the load is not at the same voltage as the GND pin of the

IC. This condition will occur when load current or other

currents flow through metal paths between the GND pin

and the load ground point. Keep the ground path short

between the GND pin and the load and use a ground plane

when possible. The second consideration is EMI caused

by GND pin current spikes. Internal capacitance between

the V

pin and the GND pin creates very narrow (<10ns)

current spikes in the GND pin. If the GND pin is connected

to system ground with a long metal trace, this trace may

radiate excess EMI. Keep the path between the input

bypass and the GND pin short.

: The switch pin is the emitter of the on-chip power

NPN switch. This pin is driven up to the input pin voltage

during switch on time. Inductor current drives the switch

pin negative during switch off time. Negative voltage is

clamped with the external catch diode. Maximum negative

switch voltage allowed is –0.8V.

SYNC: (R and SO-8 packages only) The sync pin is used

to synchronize the internal oscillator to an external signal.

It is directly logic compatible and can be driven with any

signal between 10% and 90% duty cycle. The synchroniz-

ing range is equal to

initial

operating frequency, up to

1MHz. This pin replaces SHDN on -SYNC option parts. See

Synchronizing section in Applications Information for

details.

SHDN: The shutdown pin is used to turn off the regulator

and to reduce input drain current to a few microamperes.

Actually, this pin has two separate thresholds, one at

2.38V to disable switching, and a second at 0.4V to force

complete micropower shutdown. The 2.38V threshold

functions as an accurate undervoltage lockout (UVLO).

This can be used to prevent the regulator from operating

until the input voltage has reached a predetermined level.

: The V

pin is the output of the error amplifier and the

input of the peak switch current comparator. It is normally

used for frequency compensation, but can do double duty

as a current clamp or control loop override. This pin sits

at about 1V for very light loads and 2V at maximum load.

It can be driven to ground to shut off the regulator, but if

driven high, current must be limited to 4mA.

BIAS: (SO package only) The BIAS pin is used to improve

efficiency when operating at higher input voltages and

light load current. Connecting this pin to the regulated

output voltage forces most of the internal circuitry to draw

its operating current from the output voltage rather than

the input supply. This is a much more efficient way of

doing business if the input voltage is much higher than the

output.

Minimum output voltage setting for this mode of

operation is 3.3V

. Efficiency improvement at V

= 20V,

OUT

= 5V, and I

OUT

= 25mA is over 10%.

LT1374

BLOCK DIAGRAM

it much easier to frequency compensate the feedback loop

and also gives much quicker transient response.

Most of the circuitry of the LT1374 operates from an

internal 2.9V bias line. The bias regulator normally draws

power from the regulator input pin, but if the BIAS pin is

connected to an external voltage higher than 3V, bias

power will be drawn from the external source (typically the

regulated output voltage). This will improve efficiency if

the BIAS pin voltage is lower than regulator input voltage.

High switch efficiency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing the switch to saturate. This

boosted voltage is generated with an external capacitor

and diode. Two comparators are connected to the shut-

down pin. One has a 2.38V threshold for undervoltage

lockout and the second has a 0.4V threshold for complete

shutdown.

The LT1374 is a constant frequency, current mode buck

converter. This means that there is an internal clock and

two feedback loops that control the duty cycle of the power

switch. In addition to the normal error amplifier, there is a

current sense amplifier that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscilla-

tor pulse which sets the R

flip-flop to turn the switch on.

When switch current reaches a level set by the inverting

input of the comparator, the flip-flop is reset and the

switch turns off. Output voltage control is obtained by

using the output of the error amplifier to set the switch

current trip point. This technique means that the error

amplifier commands current to be delivered to the output

rather than voltage. A voltage fed system will have low

phase shift up to the resonant frequency of the inductor

and output capacitor, then an abrupt 180° shift will occur.

The current fed system will have 90° phase shift at a much

lower frequency, but will not have the additional 90° shift

until well beyond the LC resonant frequency. This makes

Figure 1. Block Diagram

–

–+

INPUT

2.9V BIAS

REGULATOR

500kHz

OSCILLATOR

FREQUENCY

SHIFT CIRCUIT

LOCKOUT

COMPARATOR

GND

1374 BD

SLOPE COMP

0.01Ω

BIAS* INTERNAL

CURRENT

SENSE

AMPLIFIER

VOLTAGE GAIN = 20

SYNC

SHDN

SHUTDOWN

COMPARATOR

CURRENT

COMPARATOR

ERROR

AMPLIFIER

= 2000µMho

FOLDBACK

CURRENT

LIMIT

CLAMP

BOOST

FLIP-FLOP DRIVER

CIRCUITRY

0.9V

POWER

SWITCH

2.42V2.38V

*BIAS PIN IS AVAILABLE ONLY ON THE S0-8 PACKAGE

–

0.4V

3.5µA

LT1374

Table 1

OUTPUT R1 % ERROR AT OUTPUT

VOLTAGE R2 (NEAREST 1%) DUE TO DISCREET 1%

(V) (k

Ω

)(k

Ω

) RESISTOR STEPS

3 4.99 1.21 +0.23

3.3 4.99 1.82 +0.08

5 4.99 5.36 +0.39

6 4.99 7.32 –0.5

8 4.99 11.5 –0.04

10 4.99 15.8 +0.83

12 4.99 19.6 –0.62

15 4.99 26.1 +0.52

More Than Just Voltage Feedback

The feedback pin is used for more than just output voltage

sensing. It also reduces switching frequency and current

limit when output voltage is very low (see the Frequency

Foldback graph in Typical Performance Characteristics).

This is done to control power dissipation in both the IC and

in the external diode and inductor during short-circuit

conditions. A shorted output requires the switching regu-

lator to operate at very low duty cycles, and the average

current through the diode and inductor is equal to the

short-circuit current limit of the switch (typically 6A for the

LT1374, folding back to less than 3A). Minimum switch on

APPLICATIONS INFORMATION

WUUU

Figure 2. Frequency and Current Limit Foldback

–

2.4V

GND

TO SYNC CIRCUIT

1374 F02

TO FREQUENCY

SHIFTING

1k R4

OUTPUT

ERROR

AMPLIFIER

1.6V Q1

LT1374

FEEDBACK PIN FUNCTIONS

The feedback (FB) pin on the LT1374 is used to set output

voltage and provide several overload protection features.

The first part of this section deals with selecting resistors

to set output voltage and the remaining part talks about

foldback frequency and current limiting created by the FB

pin. Please read both parts before committing to a final

design. The fixed 5V LT1374-5 has internal divider resis-

tors and the FB pin is renamed SENSE, connected directly

to the output.

The suggested value for the output divider resistor (see

Figure 2) from FB to ground (R2) is 5k or less, and a

formula for R1 is shown below. The output voltage error

caused by ignoring the input bias current on the FB pin is

less than 0.25% with R2 = 5k. A table of standard 1%

values is shown in Table 1 for common output voltages.

Please read the following if divider resistors are increased

above the suggested values.

RRV

OUT

12242

242

=−

()

LT1374

APPLICATIONS INFORMATION

WUUU

time limitations would prevent the switcher from attaining

a sufficiently low duty cycle if switching frequency were

maintained at 500kHz, so frequency is reduced by about

5:1 when the feedback pin voltage drops below 1V (see

Frequency Foldback graph). This does not affect operation

with normal load conditions; one simply sees a gear shift

in switching frequency during start-up as the output

voltage rises.

In addition to lower switching frequency, the LT1374 also

operates at lower switch current limit when the feedback

pin voltage drops below 1.7V. Q2 in Figure 2 performs this

function by clamping the V

pin to a voltage less than its

normal 2.1V upper clamp level. This

foldback current limit

greatly reduces power dissipation in the IC, diode and

inductor during short-circuit conditions. External synchro-

nization is also disabled to prevent interference with

foldback operation. Again, it is nearly transparent to the

user under normal load conditions. The only loads that may

be affected are current source loads which maintain full

load current with output voltage less than 50% of final value.

In these rare situations the feedback pin can be clamped

above 1.5V with an external diode to defeat foldback cur-

rent limit.

Caution:

clamping the feedback pin means that

frequency shifting will also be defeated, so a combination

of high input voltage and dead shorted output may cause

the LT1374 to lose control of current limit.

The internal circuitry which forces reduced switching

frequency also causes current to flow out of the feedback

pin when output voltage is low. The equivalent circuitry is

shown in Figure 2. Q1 is completely off during normal

operation. If the FB pin falls below 1V, Q1 begins to

conduct current and reduces frequency at the rate of

approximately 5kHz/µA. To ensure adequate frequency

foldback (under worst-case short-circuit conditions), the

external divider Thevinin resistance must be low enough

to pull 150µA out of the FB pin with 0.6V on the pin (R

DIV

≤ 4k).

The net result is that reductions in frequency and

current limit are affected by output voltage divider imped-

ance. Although divider impedance is not critical, caution

should be used if resistors are increased beyond the

suggested values and short-circuit conditions will occur

with high input voltage

. High frequency pickup will

increase and the protection accorded by frequency and

current foldback will decrease.

MAXIMUM OUTPUT LOAD CURRENT

Maximum load current for a buck converter is limited by

the maximum switch current rating (I

) of the LT1374.

This current rating is 4.5A up to 50% duty cycle (DC),

decreasing to 3.7A at 80% duty cycle. This is shown

graphically in Typical Performance Characteristics and as

shown in the formula below:

= 4.5A for DC ≤ 50%

= 3.21 + 5.95(DC) – 6.75(DC)

for 50% < DC < 90%

DC = Duty cycle = V

OUT

Example: with V

OUT

= 5V, V

= 8V; DC = 5/8 = 0.625, and;

SW(MAX)

= 3.21 + 5.95(0.625) – 6.75(0.625)

= 4.3A

Current rating decreases with duty cycle because the

LT1374 has internal slope compensation to prevent cur-

rent mode subharmonic switching. For more details, read

Application Note 19. The LT1374 is a little unusual in this

regard because it has nonlinear slope compensation which

gives better compensation with less reduction in current

limit.

Maximum load current would be equal to maximum

switch current

for an infinitely large inductor

, but with

finite inductor size, maximum load current is reduced by

one-half peak-to-peak inductor current. The following

formula assumes continuous mode operation, implying

that the term on the right is less than one-half of I

OUT(MAX)

Continuous Mode

For the conditions above and L = 3.3µH,

OUT MAX

(

)

−

=−

()

−

()











()

=− =

43 58 5

2 3 3 10 500 10 8

43 057 373

..• •

.. .

At V

= 15V, duty cycle is 33%, so I

is just equal to a fixed

4.5A, and I

OUT(MAX)

is equal to:

P−

()

−

()

()()( )

VVV

LfV

OUT IN OUT

LT1374

45 515 5

2 3 3 10 500 10 15

45 1 35

..• •

−

()

−

()











()

=−=

−

Note that there is less load current available at the higher

input voltage because inductor ripple current increases.

This is not always the case. Certain combinations of

inductor value and input voltage range may yield lower

available load current at the lowest input voltage due to

reduced peak switch current at high duty cycles. If load

current is close to the maximum available, please check

maximum available current at both input voltage

extremes. To calculate actual peak switch current with a

given set of conditions, use:

VVV

LfV

SW PEAK OUT OUT IN OUT

(

)

=+ −

()

()()( )

For lighter loads where discontinuous operation can be

used, maximum load current is equal to:

OUT(MAX)

Discontinuous mode

Example: with L = 1.2µH, V

OUT

= 5V, and V

IN(MAX

) = 15V,

OUT MAX

(

)

−

()











()

−

()

4 5 500 10 1 2 10 15

2 5 15 5 182

236

.•.• .

The main reason for using such a tiny inductor is that it is

physically very small, but keep in mind that peak-to-peak

inductor current will be very high. This will increase output

ripple voltage. If the output capacitor has to be made larger

to reduce ripple voltage, the overall circuit could actually

wind up larger.

APPLICATIONS INFORMATION

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CHOOSING THE INDUCTOR AND OUTPUT CAPACITOR

For most applications the output inductor will fall in the

range of 3µH to 20µH. Lower values are chosen to reduce

physical size of the inductor. Higher values allow more

output current because they reduce peak current seen by

the LT1374 switch, which has a 4.5A limit. Higher values

also reduce output ripple voltage, and reduce core loss.

Graphs in the Typical Performance Characteristics section

show maximum output load current versus inductor size

and input voltage. A second graph shows core loss versus

inductor size for various core materials.

When choosing an inductor you might have to consider

maximum load current, core and copper losses, allowable

component height, output voltage ripple, EMI, fault cur-

rent in the inductor, saturation, and of course, cost. The

following procedure is suggested as a way of handling

these somewhat complicated and conflicting requirements.

1. Choose a value in microhenries from the graphs of

maximum load current and core loss. Choosing a small

inductor may result in discontinuous mode operation

at lighter loads, but the LT1374 is designed to work

well in either mode. Keep in mind that lower core loss

means higher cost, at least for closed core geometries

like toroids. The core loss graphs show both absolute

loss and percent loss for a 5W output, so actual percent

losses must be calculated for each situation.

Assume that the average inductor current is equal to

load current and decide whether or not the inductor

must withstand continuous fault conditions. If maxi-

mum load current is 0.5A, for instance, a 0.5A inductor

may not survive a continuous 4.5A overload condition.

Dead shorts will actually be more gentle on the induc-

tor because the LT1374 has foldback current limiting.

2. Calculate peak inductor current at full load current to

ensure that the inductor will not saturate. Peak current

can be significantly higher than output current, espe-

cially with smaller inductors and lighter loads, so don’t

omit this step. Powdered iron cores are forgiving

because they saturate softly, whereas ferrite cores

IfLV

VVV

OUT IN OUT

()()()( )

()

−

()

LT1374

APPLICATIONS INFORMATION

WUUU

saturate abruptly. Other core materials fall somewhere

in between. The following formula assumes continu-

ous mode of operation, but it errs only slightly on the

high side for discontinuous mode, so it can be used for

all conditions.

VVV

fLV

PEAK OUT OUT IN OUT

=+ −

()

()()( )

= Maximum input voltage

f = Switching frequency, 500kHz

3. Decide if the design can tolerate an “open” core geom-

etry like a rod or barrel, with high magnetic field

radiation, or whether it needs a closed core like a toroid

to prevent EMI problems. One would not want an open

core next to a magnetic storage media, for instance!

This is a tough decision because the rods or barrels are

temptingly cheap and small and there are no helpful

guidelines to calculate when the magnetic field radia-

tion will be a problem.

4. Start shopping for an inductor (see representative

surface mount units in Table 2) which meets the

requirements of core shape, peak current (to avoid

saturation), average current (to limit heating), and fault

current (if the inductor gets too hot, wire insulation will

melt and cause turn-to-turn shorts). Keep in mind that

all good things like high efficiency, low profile, and high

temperature operation will increase cost, sometimes

dramatically. Get a quote on the cheapest unit first to

calibrate yourself on price, then ask for what you really

want.

5. After making an initial choice, consider the secondary

things like output voltage ripple, second sourcing, etc.

Use the experts in the Linear Technology’s applica-

tions department if you feel uncertain about the final

choice. They have experience with a wide range of

inductor types and can tell you about the latest devel-

opments in low profile, surface mounting, etc.

Table 2

SERIES CORE

VENDOR/ VALUE DC CORE RESIS- MATER- HEIGHT

PART NO. (

H) (Amps) TYPE TANCE(

Ω

) IAL (mm)

Coiltronics

CTX2-1 2 4.1 Tor 0.011 KMµ4.2

CTX5-4 5 4.4 Tor 0.019 KMµ6.4

CTX8-4 8 3.5 Tor 0.020 KMµ6.4

CTX2-1P 2 3.4 Tor 0.014 52 4.2

CTX2-3P 2 4.6 Tor 0.012 52 4.8

CTX5-4P 5 3.3 Tor 0.027 52 6.4

Sumida

CDRH125 10 4.0 SC 0.025 Fer 6

CDRH125 12 3.5 SC 0.027 Fer 6

CDRH125 15 3.3 SC 0.030 Fer 6

CDRH125 18 3.0 SC 0.034 Fer 6

Coilcraft

DT3316-222 2.2 5 SC 0.035 Fer 5.1

DT3316-332 3.3 5 SC 0.040 Fer 5.1

DT3316-472 4.7 3 SC 0.045 Fer 5.1

Pulse

PE-53650 4 4.8 Tor 0.017 Fer 9.1

PE-53651 5 5.4 Tor 0.018 Fer 9.1

PE-53652 9 5.5 Tor 0.022 Fer 10

PE-53653 16 5.1 Tor 0.032 Fer 10

Dale

IHSM-4825 2.7 5.1 Open 0.034 Fer 5.6

IHSM-4825 4.7 4.0 Open 0.047 Fer 5.6

IHSM-5832 10 4.3 Open 0.053 Fer 7.1

IHSM-5832 15 3.5 Open 0.078 Fer 7.1

IHSM-7832 22 3.8 Open 0.054 Fer 7.1

Tor = Toroid

SC = Semi-closed geometry

Fer = Ferrite core material

52 = Type 52 powdered iron core material

KMµ = Kool Mµ

LT1374

APPLICATIONS INFORMATION

WUUU

Output Capacitor

The output capacitor is normally chosen by its Effective

Series Resistance (ESR), because this is what determines

output ripple voltage. At 500kHz, any polarized capacitor

is essentially resistive. To get low ESR takes

volume

, so

physically smaller capacitors have high ESR. The ESR

range for typical LT1374 applications is 0.05Ω to 0.2Ω. A

typical output capacitor is an AVX type TPS, 100µF at 10V,

with a guaranteed ESR less than 0.1Ω. This is a “D” size

surface mount solid tantalum capacitor. TPS capacitors

are specially constructed and tested for low ESR, so they

give the lowest ESR for a given volume. The value in

microfarads is not particularly critical, and values from

22µF to greater than 500µF work well, but you cannot

cheat mother nature on ESR. If you find a tiny 22µF solid

tantalum capacitor, it will have high ESR, and output ripple

voltage will be terrible. Table 3 shows some typical solid

tantalum surface mount capacitors.

Table 3. Surface Mount Solid Tantalum Capacitor ESR

and Ripple Current

E Case Size ESR (Max.,

Ω

) Ripple Current (A)

AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1

AVX TAJ 0.7 to 0.9 0.4

D Case Size

AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1

C Case Size

AVX TPS 0.2 (typ) 0.5 (typ)

Many engineers have heard that solid tantalum capacitors

are prone to failure if they undergo high surge currents.

This is historically true, and type TPS capacitors are

specially tested for surge capability, but surge ruggedness

is not a critical issue with the

output

capacitor. Solid

tantalum capacitors fail during very high

turn-on

surges,

which do not occur at the output of regulators. High

discharge

surges, such as when the regulator output is

dead shorted, do not harm the capacitors.

Unlike the input capacitor, RMS ripple current in the

output capacitor is normally low enough that ripple cur-

rent rating is not an issue. The current waveform is

triangular with a typical value of 200mA

RMS

. The formula

to calculate this is:

Output Capacitor Ripple Current (RMS):

IVVV

LfV

RIPPLE RMS OUT IN OUT

(

)

()

−

()

()()( )

029.

Ceramic Capacitors

Higher value, lower cost ceramic capacitors are now

becoming available in smaller case sizes. These are tempt-

ing for switching regulator use because of their very low

ESR. Unfortunately, the ESR is so low that it can cause

loop stability problems. Solid tantalum capacitor’s ESR

generates a loop “zero” at 5kHz to 50kHz that is instrumen-

tal in giving acceptable loop phase margin. Ceramic

capacitors remain capacitive to beyond 300kHz and usu-

ally resonate with their ESL before ESR becomes effective.

They are appropriate for input bypassing because of their

high ripple current ratings and tolerance of turn-on surges.

Linear Technology plans to issue a design note on the use

of ceramic capacitors in the near future.

OUTPUT RIPPLE VOLTAGE

Figure 3 shows a typical output ripple voltage waveform

for the LT1374. Ripple voltage is determined by the high

frequency impedance of the output capacitor, and ripple

current through the inductor. Peak-to-peak ripple current

through the inductor into the output capacitor is:

IVVV

VLf

POUT IN OUT

-P =

()

−

()

()()()

For high frequency switchers, the sum of ripple current

slew rates may also be relevant and can be calculated

from:

ΣdI

LT1374

APPLICATIONS INFORMATION

WUUU

Peak-to-peak output ripple voltage is the sum of a

triwave

created by peak-to-peak ripple current times ESR, and a

square

wave created by parasitic inductance (ESL) and

ripple current slew rate. Capacitive reactance is assumed

to be small compared to ESR or ESL.

V I ESR ESL dI

RIPPLE

()( )

()

P-P

Example: with V

=10V, V

OUT

= 5V, L = 10µH, ESR = 0.1Ω,

ESL = 10nH:

RIPPLE

P-P

()

−

()









=

()()

+









=+=

−

510 5

10 10 10 500 10 05

10 10 10

05 01 10 10 10

0 05 0 01 60

••

•

.. •

regulator input voltage. Average forward current in normal

operation can be calculated from:

IIVV

D AVG OUT IN OUT

(

)

=−

()

This formula will not yield values higher than 3A with

maximum load current of 4.25A unless the ratio of input to

output voltage exceeds 3.4:1. The only reason to consider

a larger diode is the worst-case condition of a high input

voltage and

overloaded

(not shorted) output. Under short-

circuit conditions, foldback current limit will reduce diode

current to less than 2.6A, but if the output is overloaded

and does not fall to less than 1/3 of nominal output voltage,

foldback will not take effect. With the overloaded condi-

tion, output current will increase to a typical value of 5.7A,

determined by peak switch current limit of 6A. With

= 15V, V

OUT

= 4V (5V overloaded) and I

OUT

= 5.7A:

D AVG

()

=−

()

5 7 15 4

15 418

This is safe for short periods of time, but it would be

prudent to check with the diode manufacturer if continu-

ous operation under these conditions must be tolerated.

BOOST␣ PIN␣ CONSIDERATIONS

For most applications, the boost components are a 0.27µF

capacitor and a 1N914 or 1N4148 diode. The anode is

connected to the regulated output voltage and this gener-

ates a voltage across the boost capacitor nearly identical

to the regulated output. In certain applications, the anode

may instead be connected to the unregulated input volt-

age. This could be necessary if the regulated output

voltage is very low (< 3V) or if the input voltage is less than

5V. Efficiency is not affected by the capacitor value, but the

capacitor should have an ESR of less than 1Ω to ensure

that it can be recharged fully under the worst-case condi-

tion of minimum input voltage. Almost any type of film or

ceramic capacitor will work fine.

CATCH DIODE

The suggested catch diode (D1) is a 1N5821 Schottky, or

its Motorola equivalent, MBR330. It is rated at 3A average

forward current and 30V reverse voltage. Typical forward

voltage is 0.5V at 3A. The diode conducts current only

during switch off time. Peak reverse voltage is equal to

Figure 3. LT1374 Ripple Voltage Waveform

0.5µs/DIV 1374 F03

20mV/DIV

0.5A/DIV

OUT

= 1A

OUT

= 50mA

INDUCTOR

CURRENT

AT I

OUT

= 1A

INDUCTOR

CURRENT

AT I

OUT

= 50mA

LT1374

APPLICATIONS INFORMATION

WUUU

WARNING!

Peak voltage on the BOOST pin is the sum of

unregulated input voltage plus the voltage across the

boost capacitor. This normally means that peak BOOST

pin voltage is equal to input voltage plus output voltage,

but

when the boost diode is connected to the regulator

input, peak BOOST pin voltage is equal to twice the input

voltage. Be sure that BOOST pin voltage does not exceed

its maximum rating

For nearly all applications, a 0.27µF boost capacitor works

just fine, but for the curious, more details are provided

here. The size of the boost capacitor is determined by

switch drive current requirements. During switch on time,

drain current on the capacitor is approximately I

OUT

/ 50. At

peak load current of 4.25A, this gives a total drain of 85mA.

Capacitor ripple voltage is equal to the product of on time

and drain current divided by capacitor value;

∆V = (t

)(85mA/C). To keep capacitor ripple voltage to

less than 0.6V (a slightly arbitrary number) at the worst-

case condition of t

= 1.8µs, the capacitor needs to be

0.27µF. Boost capacitor ripple voltage is not a critical

parameter, but if the minimum voltage across the capaci-

tor drops to less than 3V, the power switch may not

saturate fully and efficiency will drop. An

approximate

formula for absolute minimum capacitor value is:

CIVV

fV V

MIN OUT OUT IN

OUT

()( )

()

−

()

//50

f = Switching frequency

OUT

= Regulated output voltage

= Minimum input voltage

This formula can yield capacitor values substantially less

than 0.27µF, but it should be used with caution since it

does not take into account secondary factors such as

capacitor series resistance, capacitance shift with tem-

perature and output overload.

SHUTDOWN FUNCTION AND

UNDERVOLTAGE LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT1374. Typically, UVLO is used in situations where

the input supply is

current limited

, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

load to the source and can cause the source to current limit

or latch low under low source voltage conditions. UVLO

–

2.38V

0.4V

GND

LT1374

INPUT

1374 F04

OUTPUT

SHDN

STANDBY

TOTAL

SHUTDOWN

3.5µA

Figure 4. Undervoltage Lockout

LT1374

prevents the regulator from operating at source voltages

where these problems might occur.

Threshold voltage for lockout is about 2.38V, slightly less

than the internal 2.42V reference voltage. A 3.5µA bias

current flows

out

of the pin at threshold. This internally

generated current is used to force a default high state on

the shutdown pin if the pin is left open. When low shut-

down current is not an issue, the error due to this current

can be minimized by making R

10k or less. If shutdown

current is an issue, R

can be raised to 100k, but the error

due to initial bias current and changes with temperature

should be considered.

RRV V

VR A

HI LO IN

()

=−

()

−

()

238

238 35

to 100k 25k suggested

..µ

= Minimum input voltage

Keep the connections from the resistors to the shutdown

pin short and make sure that interplane or surface capaci-

tance to the switching nodes are minimized. If high resis-

tor values are used, the shutdown pin should be bypassed

with a 1000pF capacitor to prevent coupling problems

from the switch node. If hysteresis is desired in the

undervoltage lockout point, a resistor R

can be added to

the output node. Resistor values can be calculated from:

RRV VV V

RRV V

LO IN OUT

FB HI OUT

=−+

()

[]

−

()

()( )

238 1

238 235

∆∆

∆

25k suggested for R

Input voltage at which switching stops as input

voltage descends to trip level

∆V = Hysteresis in input voltage level

APPLICATIONS INFORMATION

WUUU

Example: output voltage is 5V, switching is to stop if input

voltage drops below 12V and should not restart unless

input rises back to 13.5V. ∆V is therefore 1.5V and

= 12V. Let R

= 25k.

Rk k

=−+

()

[]

−

()

25 12 2 38 1 5 5 1 1 5

238 25 35

25 10 41

229 114

114 5 1 5 380

../ .

./.

SWITCH NODE CONSIDERATIONS

For maximum efficiency, switch rise and fall times are

made as short as possible. To prevent radiation and high

frequency resonance problems, proper layout of the com-

ponents connected to the switch node is essential. B field

(magnetic) radiation is minimized by keeping catch diode,

switch pin, and input bypass capacitor leads as short as

possible. E field radiation is kept low by minimizing the

length and area of all traces connected to the switch pin

and BOOST pin. A ground plane should always be used

under the switcher circuitry to prevent interplane cou-

pling. A suggested layout for the critical components is

shown in Figure 5. Note that the feedback resistors and

compensation components are kept as far as possible

from the switch node. Also note that the high current

ground path of the catch diode and input capacitor are kept

very short and separate from the analog ground line.

The high speed switching current path is shown schemati-

cally in Figure 6. Minimum lead length in this path is

essential to ensure clean switching and low EMI. The path

including the switch, catch diode, and input capacitor is

the only one containing nanosecond rise and fall times. If

you follow this path on the PC layout, you will see that it is

irreducibly short. If you move the diode or input capacitor

LT1374

APPLICATIONS INFORMATION

WUUU

CONNECT TO

GROUND PLANE

KEEP FB AND V

COMPONENTS

AWAY FROM HIGH FREQUENCY,

HIGH CURRENT COMPONENTS

PLACE FEEDTHROUGHS

AROUND GND PIN FOR GOOD

THERMAL CONDUCTIVITY

R3 D2

13745 F05

C5 C6GND

OUT

D1C3V

GND

CONNECT TO

GROUND PLANE

MINIMIZE LT1374, C3, D1 LOOP

KELVIN SENSE

OUT

TAKE OUTPUT

DIRECTLY FROM

END OF OUTPUT

CAPACITOR

Figure 5. Suggested Layout (Topside Only Shown)

Figure 6. High Speed Switching Path

1374 F06

HIGH

FREQUENCY

CIRCULATING

PATH

LOAD

SWITCH NODE

LT1374

APPLICATIONS INFORMATION

WUUU

away from the LT1374, get your resumé in order. The

other paths contain only some combination of DC and

500kHz triwave, so are much less critical.

PARASITIC RESONANCE

Resonance or “ringing” may sometimes be seen on the

switch node (see Figure 7). Very high frequency ringing

following switch rise time is caused by switch/diode/input

capacitor lead inductance and diode capacitance. Schot-

tky diodes have very high “Q” junction capacitance that

can ring for many cycles when excited at high frequency.

If total lead length for the input capacitor, diode and switch

path is 1 inch, the inductance will be approximately 25nH.

At switch off, this will produce a spike across the NPN

output device in addition to the input voltage. At higher

currents this spike can be in the order of 10V to 20V or

5V/DIV

Figure 7. Switch Node Resonance

20ns/DIV 1374 F07

INDUCTOR

CURRENT

20ns/DIV 1375/76 F11

0.5µs/DIV 1374 F08

Figure 8. Discontinuous Mode Ringing

5V/DIV

100mA/DIV

SWITCH NODE

VOLTAGE

RISE AND FALL

WAVEFORMS ARE

SUPERIMPOSED

(PULSE WIDTH IS

NOT

120ns)

higher with a poor layout, potentially exceeding the abso-

lute max switch voltage. The path around switch, catch

diode and input capacitor must be kept as short as

possible to ensure reliable operation. When looking at this,

a >100MHz oscilloscope must be used, and waveforms

should be observed on the leads of the package. This

switch off spike will also cause the SW node to go below

ground. The LT1374 has special circuitry inside which

mitigates this problem, but negative voltages over 1V

lasting longer than 10ns should be avoided. Note that

100MHz oscilloscopes are barely fast enough to see the

details of the falling edge overshoot in Figure 7.

A second, much lower frequency ringing is seen during

switch off time if load current is low enough to allow the

inductor current to fall to zero during part of the switch off

time (see Figure 8). Switch and diode capacitance reso-

nate with the inductor to form damped ringing at 1MHz to

10 MHz. This ringing is not harmful to the regulator and it

has not been shown to contribute significantly to EMI. Any

attempt to damp it with a resistive snubber will degrade

efficiency.

INPUT BYPASSING AND VOLTAGE RANGE

Input Bypass Capacitor

Step-down converters draw current from the input supply

in pulses. The average height of these pulses is equal to

load current, and the duty cycle is equal to V

OUT

. Rise

and fall time of the current is very fast. A local bypass

capacitor across the input supply is necessary to ensure

proper operation of the regulator and minimize the ripple

current fed back into the input supply.

The capacitor also

forces switching current to flow in a tight local loop,

minimizing EMI

Do not cheat on the ripple current rating of the Input

bypass capacitor, but also don’t get hung up on the value

in microfarads

. The input capacitor is intended to absorb

all the switching current ripple, which can have an RMS

value as high as one half of load current. Ripple current

ratings on the capacitor must be observed to ensure

reliable operation. In many cases it is necessary to parallel

LT1374

APPLICATIONS INFORMATION

WUUU

two capacitors to obtain the required ripple rating. Both

capacitors must be of the same value and manufacturer to

guarantee power sharing. The actual value of the capacitor

in microfarads is not particularly important because at

500kHz, any value above 5µF is essentially resistive. RMS

ripple current rating is the critical parameter. Actual RMS

current can be calculated from:

IIVVVV

RIPPLE RMS OUT OUT IN OUT IN

(

)

=−

()

The term inside the radical has a maximum value of 0.5

when input voltage is twice output, and stays near 0.5 for

a relatively wide range of input voltages. It is common

practice therefore to simply use the worst-case value and

assume that RMS ripple current is one half of load current.

At maximum output current of 4.5A for the LT1374, the

input bypass capacitor should be rated at 2.25A ripple

current. Note however, that there are many secondary

considerations in choosing the final ripple current rating.

These include ambient temperature, average versus peak

load current, equipment operating schedule, and required

product lifetime. For more details, see Application Notes

19 and 46, and Design Note 95.

Input Capacitor Type

Some caution must be used when selecting the type of

capacitor used at the input to regulators. Aluminum

electrolytics are lowest cost, but are physically large to

achieve adequate ripple current rating, and size con-

straints (especially height), may preclude their use.

Ceramic capacitors are now available in larger values, and

their high ripple current and voltage rating make them

ideal for input bypassing. Cost is fairly high and footprint

may also be somewhat large. Solid tantalum capacitors

would be a good choice, except that they have a history of

occasional spectacular failures when they are subjected to

large current surges during power-up. The capacitors can

short and then burn with a brilliant white light and lots of

nasty smoke. This phenomenon occurs in only a small

percentage of units, but it has led some OEM companies

to forbid their use in high surge applications. The input

bypass capacitor of regulators can see these high surges

when a battery or high capacitance source is connected.

Several manufacturers have developed a line of solid

tantalum capacitors specially tested for surge capability

(AVX TPS series for instance, see Table 3), but even these

units may fail if the input voltage surge approaches the

maximum voltage rating of the capacitor. AVX recom-

mends derating capacitor voltage by 2:1 for high surge

applications. The highest voltage rating is 50V, so 25V

may be a practical upper limit when using solid tantalum

capacitors for input bypassing.

Larger capacitors may be necessary when the input volt-

age is very close to the minimum specified on the data

sheet. Small voltage dips during switch on time are not

normally a problem, but at very low input voltage they may

cause erratic operation because the input voltage drops

below the minimum specification. Problems can also

occur if the input-to-output voltage differential is near

minimum. The amplitude of these dips is normally a

function of capacitor ESR and ESL because the capacitive

reactance is small compared to these terms. ESR tends to

be the dominate term and is inversely related to physical

capacitor size within a given capacitor type.

SYNCHRONIZING (Available as -SYNC Option)

The LT1374-SYNC has the SHDN pin replaced with a

SYNC pin, which is used to synchronize the internal

oscillator to an external signal. The SYNC input must pass

from a logic level low, through the maximum synchroni-

zation threshold with a duty cycle between 10% and 90%.

The input can be driven directly from a logic level output.

The synchronizing range is equal to

initial

operating fre-

quency up to 1MHz. This means that

minimum

practical

sync frequency is equal to the worst-case

high

self-

oscillating frequency (550kHz), not the typical operating

frequency of 500kHz. Caution should be used when syn-

chronizing above 700kHz because at higher sync frequen-

cies the amplitude of the internal slope compensation

used to prevent subharmonic switching is reduced. This

type of subharmonic switching only occurs at input volt-

ages less than twice output voltage. Higher inductor

values will tend to eliminate this problem. See Frequency

Compensation section for a discussion of an entirely

LT1374

APPLICATIONS INFORMATION

WUUU

different cause of subharmonic switching before assum-

ing that the cause is insufficient slope compensation.

Application Note 19 has more details on the theory of slope

compensation.

At power-up, when V

is being clamped by the FB pin (see

Figure 2, Q2), the sync function is disabled. This allows the

frequency foldback to operate in the shorted output con-

dition. During normal operation, switching frequency is

controlled by the internal oscillator until the FB pin reaches

1.5V, after which the SYNC pin becomes operational. If no

synchronization is required, this pin should be connected

to ground.

THERMAL CALCULATIONS

Power dissipation in the LT1374 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current, and input quiescent current. The following formu-

las show how to calculate each of these losses. These

formulas assume continuous mode operation, so they

should not be used for calculating efficiency at light load

currents.

Switch loss:

PRI V

Vns I V f

SW SW OUT OUT

IN OUT IN

()( )

()()()

Boost current loss:

PVI

BOOST OUT OUT

()

50/

Quiescent current loss:

PV V

Q IN OUT

OUT

()











()

0 001 0 005

0 002

.. .

= Switch resistance (≈0.07)

24ns = Equivalent switch current/voltage overlap time

f = Switch frequency

Example: with V

= 10V, V

OUT

= 5V and I

OUT

= 3A:

BOOST

( )()()

+





()( )







=+=

()( )

()

()( )

−

007 3 5

10 24 10 3 10 500 10

0 32 0 36 0 68

5350

10 015

10 0 001 5 0 005 5 0 002

10 004

.••

...

.. ..

Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W.

Thermal resistance for LT1374 package is influenced by

the presence of internal or backside planes. With a full

plane under the SO package, thermal resistance will be

about 80°C/W. No plane will increase resistance to about

120°C/W. To calculate die temperature, use the proper

thermal resistance number for the desired package and

add in worst-case ambient temperature:

= T

+ θ

TOT

)

With the SO-8 package (θ

= 80°C/W), at an ambient

temperature of 50°C,

= 50 + 80 (0.87) = 120°C

For the DD package with a good copper plane under the

device, thermal resistance will be about 30°C/W. For the

conditions above:

= 50 + 30 (0.87) = 76°C

Die temperature is highest at low input voltage, so use

lowest continuous input operating voltage for thermal

calculations.

FREQUENCY COMPENSATION

Loop frequency compensation of switching regulators

can be a rather complicated problem because the reactive

components used to achieve high efficiency also intro-

duce multiple poles into the feedback loop. The inductor

and output capacitor on a conventional step-down con-

verter actually form a resonant tank circuit that can exhibit

peaking and a rapid 180° phase shift at the resonant

LT1374

APPLICATIONS INFORMATION

WUUU

frequency. By contrast, the LT1374 uses a “current mode”

architecture to help alleviate phase shift created by the

inductor. The basic connections are shown in Figure 9.

Figure 10 shows a Bode plot of the phase and gain of the

power section of the LT1374, measured from the V

pin to

the output. Gain is set by the 5.3A/V transconductance of

the LT1374 power section and the effective complex

impedance from output to ground. Gain rolls off smoothly

above the 600Hz pole frequency set by the 100µF output

capacitor. Phase drop is limited to about 70°. Phase

recovers and gain levels off at the zero frequency (≈16kHz)

set by capacitor ESR (0.1Ω).

Error amplifier transconductance phase and gain are shown

in Figure 11. The error amplifier can be modeled as a

transconductance of 2000µMho, with an output imped-

ance of 200kΩ in parallel with 12pF. In all practical

applications, the compensation network from V

pin to

ground has a much lower impedance than the output

impedance of the amplifier at frequencies above 500Hz.

This means that the error amplifier characteristics them-

selves do not contribute excess phase shift to the loop, and

the phase/gain characteristics of the error amplifier sec-

tion are completely controlled by the external compensa-

tion network.

In Figure 12, full loop phase/gain characteristics are

shown with a compensation capacitor of 1.5nF, giving the

error amplifier a pole at 530Hz, with phase rolling off to 90°

and staying there. The overall loop has a gain of 74dB at

low frequency, rolling off to unity-gain at 100kHz. Phase

shows a two-pole characteristic until the ESR of the output

capacitor brings it back above 10kHz. Phase margin is

about 75° at unity-gain.

Figure 9. Model for Loop Response

Figure 10. Response from VC Pin to Output

FREQUENCY (Hz)

GAIN: V

PIN TO OUTPUT (dB)

PHASE: V

PIN TO OUTPUT (DEG)

–20

–40

–80

–120

10 1k 10k 1M

1374 F10

100 100k

GAIN

PHASE

= 10V

OUT

= 5V

OUT

= 2A

Figure 11. Error Amplifier Gain and Phase

FREQUENCY (Hz)

GAIN (µMho)

PHASE (DEG)

3000

2500

2000

1500

1000

500

200

150

100

–50

100 10k 100k 10M

1374 F11

1k 1M

GAIN

PHASE

OUT

200k

OUT

12pF

ERROR AMPLIFIER EQUIVALENT CIRCUIT

LOAD

= 50Ω

2 × 10

–3

)(

FREQUENCY (Hz)

LOOP GAIN (dB)

LOOP PHASE (DEG)

–20

200

150

100

–50

10 1k 10k 1M

1374 F12

100 100k

GAIN

PHASE

= 10V

OUT

= 5V, I

OUT

= 2A

OUT

= 100µF, 10V, AVX TPS

= 1.5nF, R

= 0, L = 10µH

Figure 12. Overall Loop Characteristics

–

2.42V

LT1374

GND

1374 F09

OUTPUT

ESR

ERROR

AMPLIFIER

CURRENT MODE

POWER STAGE

= 5.3A/V

LT1374

APPLICATIONS INFORMATION

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Analog experts will note that around 4.4kHz, phase dips

very close to the zero phase margin line. This is typical of

switching regulators, especially those that operate over a

wide range of loads. This region of low phase is not a

problem as long as it does not occur near unity-gain. In

practice, the variability of output capacitor ESR tends to

dominate all other effects with respect to loop response.

Variations in ESR

will

cause unity-gain to move around,

but at the same time phase moves with it so that adequate

phase margin is maintained over a very wide range of ESR

(≥ ±3:1).

What About a Resistor in the Compensation Network?

It is common practice in switching regulator design to add

a “zero” to the error amplifier compensation to increase

loop phase margin. This zero is created in the external

network in the form of a resistor (R

) in series with the

compensation capacitor. Increasing the size of this resis-

tor generally creates better and better loop stability, but

there are two limitations on its value. First, the combina-

tion of output capacitor ESR and a large value for R

may

cause loop gain to stop rolling off altogether, creating a

gain margin problem. An approximate formula for R

where gain margin falls to zero is:

R Loop V

G G ESR

COUT

MP MA

Gain =1

()

()()()()

242.

= Transconductance of power stage = 5.3A/V

= Error amplifier transconductance = 2(10

–3

)

ESR = Output capacitor ESR

2.42 = Reference voltage

With V

OUT

= 5V and ESR = 0.03Ω, a value of 6.5k for R

would yield zero gain margin, so this represents an upper

limit. There is a second limitation however which has

nothing to do with theoretical small signal dynamics. This

resistor sets high frequency gain of the error amplifier,

including the gain at the switching frequency. If switching

frequency gain is high enough, output ripple voltage will

appear at the V

pin with enough amplitude to muck up

proper operation of the regulator. In the marginal case,

subharmonic

switching occurs, as evidenced by alternat-

ing pulse widths seen at the switch node. In more severe

cases, the regulator squeals or hisses audibly even though

the output voltage is still roughly correct. None of this will

show on a theoretical Bode plot because Bode is an

amplitude insensitive analysis.

Tests have shown that if

ripple voltage on the V

is held to less than 100mV

P-P

, the

LT1374 will be well behaved

. The formula below will give

an estimate of V

ripple voltage when R

is added to the

loop, assuming that R

is large compared to the reactance

of C

at 500kHz.

VR G V V ESR

VLf

C RIPPLE C MA IN OUT

(

)

()( )

−

()()()

24.

= Error amplifier transconductance (2000µMho)

If a computer simulation of the LT1374 showed that a

series compensation resistor of 3k gave best overall loop

response, with adequate gain margin, the resulting V

ripple voltage with V

= 10V, V

OUT

= 5V, ESR = 0.1Ω,

L = 10µH, would be:

VkV

C RIPPLE

(

)

−

()





−

()()()

()









=

3 2 10 10 5 0 1 2 4

10 10 10 500 10 0 144

•..

••

This ripple voltage is high enough to possibly create

subharmonic switching. In most situations a compromise

value (<2k in this case) for the resistor gives acceptable

phase margin and no subharmonic problems. In other

cases, the resistor may have to be larger to get acceptable

phase response, and some means must be used to control

ripple voltage at the V

pin. The suggested way to do this

is to add a capacitor (C

) in parallel with the R

network

on the V

pin. Pole frequency for this capacitor is typically

set at one-fifth of switching frequency so that it provides

significant attenuation of switching ripple, but does not

add unacceptable phase shift at loop unity-gain frequency.

With R

= 3k,

CfR kpF

()()()

=





()

2 500 10 3 531

ππ•

LT1374

APPLICATIONS INFORMATION

WUUU

How Do I Test Loop Stability?

The “standard” compensation for LT1374 is a 1.5nF

capacitor for C

, with R

= 0. While this compensation will

work for most applications, the “optimum” value for loop

compensation components depends, to various extent, on

parameters which are not well controlled. These include

inductor value

(±30% due to production tolerance, load

current and ripple current variations),

output capacitance

(±20% to ±50% due to production tolerance, tempera-

ture, aging and changes at the load),

output capacitor ESR

(±200% due to production tolerance, temperature and

aging), and finally,

DC input voltage and output load

current

. This makes it important for the designer to check

out the final design to ensure that it is “robust” and tolerant

of all these variations.

I check switching regulator loop stability by pulse loading

the regulator output while observing transient response at

the output, using the circuit shown in Figure 13. The

regulator loop is “hit” with a small transient AC load

current at a relatively low frequency, 50Hz to 1kHz. This

causes the output to jump a few millivolts, then settle back

to the original value, as shown in Figure 14. A well behaved

loop will settle back cleanly, whereas a loop with poor

phase or gain margin will “ring” as it settles. The

number

of rings indicates the degree of stability, and the

frequency

of the ringing shows the approximate unity-gain fre-

quency of the loop.

Amplitude

of the signal is not particu-

larly important, as long as the amplitude is not so high that

the loop behaves nonlinearly.

The output of the regulator contains both the desired low

frequency transient information and a reasonable amount

of high frequency (500kHz) ripple. The ripple makes it

difficult to observe the small transient, so a two-pole,

100kHz filter has been added. This filter is not particularly

critical; even if it attenuated the transient signal slightly,

this wouldn’t matter because amplitude is not critical.

After verifying that the setup is working correctly, I start

varying load current and input voltage to see if I can find

any combination that makes the transient response look

suspiciously “ringy.” This procedure may lead to an ad-

justment for best loop stability or faster loop transient

response. Nearly always you will find that loop response

looks better if you add in several kΩ for R

. Do this only

if necessary, because as explained before, R

above 1k

may require the addition of C

to control V

pin ripple.

Figure 13. Loop Stability Test Circuit

OSCILLOSCOPE

SYNC

ADJUSTABLE

DC LOAD

ADJUSTABLE

INPUT SUPPLY

100Hz TO 1kHz

100mV TO 1V

P-P

100µF TO

1000µF

RIPPLE FILTER

1374 F13

TO X1

OSCILLOSCOPE

PROBE

3300pF 330pF

50Ω

470Ω4.7k

SWITCHING

REGULATOR

0.2ms/DIV 1374 F14

10mV/DIV

OUT

= 500mA

BEFORE FILTER

OUT

= 500mA

AFTER FILTER

LOAD PULSE

THROUGH 50Ω

f ≈ 780Hz

5A/DIV

OUT

= 50mA

AFTER FILTER

Figure 14. Loop Stability Check

LT1374

APPLICATIONS INFORMATION

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If everything looks OK, I use a heat gun and cold spray on

the circuit (especially the output capacitor) to bring out

any temperature-dependent characteristics.

Keep in mind that this procedure does not take initial

component tolerance into account. You should see fairly

clean response under all load and line conditions to ensure

that component variations will not cause problems. One

note here: according to Murphy, the component most

likely to be changed in production is the output capacitor,

because that is the component most likely to have manu-

facturer variations (in ESR) large enough to cause prob-

lems. It would be a wise move to lock down the sources of

the output capacitor in production.

A possible exception to the “clean response” rule is at very

light loads, as evidenced in Figure 14 with I

LOAD

= 50mA.

Switching regulators tend to have dramatic shifts in loop

response at very light loads, mostly because the inductor

current becomes discontinuous. One common result is very

slow but stable characteristics. A second possibility is low

phase margin, as evidenced by ringing at the output with

transients. The good news is that the low phase margin at

light loads is not particularly sensitive to component varia-

tion, so if it looks reasonable under a transient test, it will

probably not be a problem in production. Note that

fre-

quency

of the light load ringing may vary with component

tolerance but phase margin generally hangs in there.

POSITIVE-TO-NEGATIVE CONVERTER

The circuit in Figure 15 is a classic positive-to-negative

topology using a grounded inductor. It differs from the

standard approach in the way the IC chip derives its

feedback signal, however, because the LT1374 accepts

only positive feedback signals, the ground pin must be tied

to the regulated negative output. A resistor divider to

ground or, in this case, the sense pin, then provides the

proper feedback voltage for the chip.

Inverting regulators differ from buck regulators in the

basic switching network. Current is delivered to the output

square waves with a peak-to-peak amplitude much

greater than load current

. This means that

maximum load

current will be significantly less than the LT1374’s 4.5A

maximum switch current, even with large inductor values

The buck converter in comparison, delivers current to the

output as a triangular wave superimposed on a DC level

equal to load current, and load current can approach 4.5A

with large inductors. Output ripple voltage for the positive-

to-negative converter will be much higher than a buck

converter. Ripple current in the output capacitor will also

be much higher. The following equations can be used to

calculate operating conditions for the positive-to-negative

converter.

Maximum load current:

IVV

VVfL

VV VV

MAX

PIN OUT

OUT IN OUT IN

OUT IN OUT F

−

()( )

()()()













()

−

()

+−

()

2035

035

= Maximum rated switch current

= Minimum input voltage

OUT

= Output voltage

= Catch diode forward voltage

0.35 = Switch voltage drop at 4.5A

Example: with V

IN(MIN)

= 5.5V, V

OUT

= 5V, L = 10µH,

= 0.5V, I

= 4.5A: I

MAX

= 2A. Note that this equation does

not take into account that maximum rated switch current

) on the LT1374 is reduced slightly for duty cycles

above 50%. If duty cycle is expected to exceed 50% (input

voltage less than output voltage), use the actual I

value

from the Electrical Characteristics table.

OUTPUT**

–5V, 1.8A

INPUT

5.5V TO

20V

1374 F15

0.27µF

MBRS330T3

100µF

10V TANT

×2

10µF TO

50µF

1N4148

L1*

5µH

BOOST

LT1374-5

SENSE

GND V

* INCREASE L1 TO 10µH OR 20µH FOR HIGHER CURRENT APPLICATIONS.

SEE APPLICATIONS INFORMATION

** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE

AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

Figure 15. Positive-to-Negative Converter

LT1374

APPLICATIONS INFORMATION

WUUU

Operating duty cycle:

DC VV

VVV

OUT F

IN OUT F

−+ +03.

(This formula uses an average value for switch loss, so it

may be several percent in error.)

With the conditions above:

DC =+

−++=

505

55 03 5 05 51

.. . %

This duty cycle is close enough to 50% that I

can be

assumed to be 4.5A.

OUTPUT DIVIDER

If the adjustable part is used, the resistor connected to

OUT

(R2) should be set to approximately 5k. R1 is

calculated from:

RRV

OUT

12242

242

()

–.

INDUCTOR VALUE

Unlike buck converters, positive-to-negative converters

cannot use large inductor values to reduce output ripple

voltage. At 500kHz, values larger than 25µH make almost

no change in output ripple. The graph in Figure 16 shows

peak-to-peak output ripple voltage for a 5V to –5V con-

verter versus inductor value. The criteria for choosing the

inductor is therefore typically based on ensuring that peak

switch current rating is not exceeded. This gives the

lowest value of inductance that can be used, but in some

cases (lower output load currents) it may give a value that

creates unnecessarily high output ripple voltage. A com-

promise value is often chosen that reduces output ripple.

As you can see from the graph,

large

inductors will not

Figure 16. Ripple Voltage on Positive-to-Negative Converter

INDUCTOR SIZE (µH)

OUTPUT RIPPLE VOLTAGE (mV

P-P

)

250

200

150

100

020

1374 F16

510 15

5V TO – 5V CONVERTER

OUTPUT CAPACITOR’S

ESR = 0.05Ω

LOAD

= 0.25A

LOAD

= 1A

give arbitrarily low ripple, but

small

inductors can give

high ripple.

The difficulty in calculating the minimum inductor size

needed is that you must first know whether the switcher

will be in continuous or discontinuous mode at the critical

point where switch current is 4.5A. The first step is to use

the following formula to calculate the load current where

the switcher must use continuous mode. If your load

current is less than this, use the discontinuous mode

formula to calculate minimum inductor needed. If load

current is higher, use the continuous mode formula.

Output current where continuous mode is needed:

IVI

VV VV V

CONT IN P

IN OUT IN OUT F

()()

()

Minimum inductor discontinuous mode:

LVI

MIN OUT OUT

()()

()( )

LT1374

APPLICATIONS INFORMATION

WUUU

Minimum inductor continuous mode:

LVV

fV V I I VV

MIN IN OUT

IN OUT P OUT OUT F

()( )

()

−++

()

























For the example above, with maximum load current of 1A:

CONT

()()

()

55 45

455555505 115

.. .

This says that discontinuous mode can be used and the

minimum inductor needed is found from:

MIN

()()







()

25 1

500 10 4 5

•.

In practice, the inductor should be increased by about 30%

over the calculated minimum to handle losses and varia-

tions in value. This suggests a minimum inductor of 1.3µH

for this application, but looking at the ripple voltage chart

shows that output ripple voltage could be reduced by a fac-

tor of two by using a 15µH inductor. There is no rule of thumb

here to make a final decision. If modest ripple is needed and

the larger inductor does the trick, go for it. If ripple is non-

critical use the smaller inductor. If ripple is extremely criti-

cal, a second filter may have to be added in any case, and

the lower value of inductance can be used. Keep in mind

that the output capacitor is the other critical factor in deter-

mining output ripple voltage. Ripple shown on the graph

(Figure 16) is with two parallel capacitor’s ESR of 0.1Ω. This

reasonable for AVX type TPS “D” or “E” size surface mount

solid tantalum capacitors, but the final capacitor chosen

must be looked at carefully for ESR characteristics.

Ripple Current in the Input and Output Capacitors

Positive-to-negative converters have high ripple current in

both the input and output capacitors. For long capacitor

lifetime, the RMS value of this current must be less than

the high frequency ripple current rating of the capacitor.

The following formula will give an

approximate

value for

RMS ripple current.

This formula assumes continuous

mode and large inductor value

. Small inductors will give

somewhat higher ripple current, especially in discontinu-

ous mode. The exact formulas are very complex and

appear in Application Note 44, pages 30 and 31. For our

purposes here I have simply added a fudge factor (ff). The

value for ff is about 1.2 for higher load currents and

L ≥10µH. It increases to about 2.0 for smaller inductors at

lower load currents.

Capacitor ff I V

OUT OUT

IRMS =

()( )

ff = Fudge factor (1.2 to 2.0)

Diode Current

Average

diode current is equal to load current.

Peak

diode

current will be considerably higher.

Peak diode current:

Continuous

IVV

LfV V

Discontinuous V

OUT IN OUT

IN OUT

OUT

Mode

Mode = 2I

OUT

()

()( )

()()

()

()( )

()()

Keep in mind that during start-up and output overloads,

average diode current may be much higher than with

normal loads. Care should be used if diodes rated less than

3A are used, especially if continuous overload conditions

must be tolerated.

LT1374

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTION

R Package

7-Lead Plastic DD Pak

(LTC DWG # 05-08-1462)

R (DD7) 0396

0.026 – 0.036

(0.660 – 0.914)

0.143+0.012

–0.020

()

3.632+0.305

–0.508

0.040 – 0.060

(1.016 – 1.524) 0.013 – 0.023

(0.330 – 0.584)

0.095 – 0.115

(2.413 – 2.921)

0.004+0.008

–0.004

()

0.102+0.203

–0.102

0.050 ± 0.012

(1.270 ± 0.305)

0.059

(1.499)

TYP

0.045 – 0.055

(1.143 – 1.397)

0.165 – 0.180

(4.191 – 4.572)

0.330 – 0.370

(8.382 – 9.398)

0.060

(1.524)

TYP

0.390 – 0.415

(9.906 – 10.541)

15° TYP

0.300

(7.620)

0.075

(1.905)

0.183

(4.648)

0.060

(1.524)

0.060

(1.524)

0.256

(6.502)

BOTTOM VIEW OF DD PAK

HATCHED AREA IS SOLDER PLATED

COPPER HEAT SINK

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

1234

0.150 – 0.157**

(3.810 – 3.988)

8765

0.189 – 0.197*

(4.801 – 5.004)

0.228 – 0.244

(5.791 – 6.197)

0.016 – 0.050

0.406 – 1.270

0.010 – 0.020

(0.254 – 0.508)× 45°

0°– 8° TYP

0.008 – 0.010

(0.203 – 0.254)

SO8 0996

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

TYP

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

LT1374

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTION

T7 Package

7-Lead Plastic TO-220 (Standard)

(LTC DWG # 05-08-1422)

0.040 – 0.060

(1.016 – 1.524)

0.026 – 0.036

(0.660 – 0.914)

T7 (TO-220) (FORMED) 1197

0.135 – 0.165

(3.429 – 4.191)

0.700 – 0.728

(17.780 – 18.491)

0.045 – 0.055

(1.143 – 1.397)

0.165 – 0.180

(4.191 – 4.572)

0.095 – 0.115

(2.413 – 2.921)

0.013 – 0.023

(0.330 – 0.584)

0.620

(15.75)

TYP

0.155 – 0.195

(3.937 – 4.953)

0.152 – 0.202

(3.860 – 5.130)

0.260 – 0.320

(6.604 – 8.128)

0.147 – 0.155

(3.734 – 3.937)

DIA

0.390 – 0.415

(9.906 – 10.541)

0.330 – 0.370

(8.382 – 9.398)

0.460 – 0.500

(11.684 – 12.700)

0.570 – 0.620

(14.478 – 15.748)

0.230 – 0.270

(5.842 – 6.858)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT1374

1374fa LT/TP 0799 2K REV A • PRINTED IN USA

 LINEAR T ECHNOLOGY CORPORATION 1998

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●

www.linear-tech.com

TYPICAL APPLICATION

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Burst Mode is a trademark of Linear Technology Corporation.

Dual Output SEPIC␣ Converter

The circuit in Figure 17 generates both positive and

negative 5V outputs with a single piece of magnetics. The

two inductors shown are actually just two windings on a

standard BH Electronics inductor. The topology for the 5V

output is a standard buck converter. The –5V topology

would be a simple flyback winding coupled to the buck

converter if C4 were not present. C4 creates the SEPIC

(Single-Ended Primary Inductance Converter) topology

which improves regulation and reduces ripple current in

L1. Without C4, the voltage swing on L1B compared to

L1A would vary due to relative loading and coupling

losses. C4 provides a low impedance path to maintain an

equal voltage swing in L1B, improving regulation. In a

flyback converter, during switch on time, all the converter’s

energy is stored in L1A only, since no current flows in L1B.

At switch off, energy is transferred by magnetic coupling

into L1B, powering the –5V rail. C4 pulls L1B positive

during switch on time, causing current to flow, and energy

to build in L1B and C4. At switch off, the energy stored in

both L1B and C4 supply the –5V rail. This reduces the

current in L1A and changes L1B current waveform from

square to triangular. For details on this circuit see Design

Note 100.

BOOST

LT1374-5

OUTPUT

–5V

†

* L1 IS A SINGLE CORE WITH TWO WINDINGS

BH ELECTRONICS #501-0726

** TOKIN IE475ZY5U-C304

†

IF LOAD CAN GO TO ZERO, AN OPTIONAL

PRELOAD OF 1k TO 5k MAY BE USED TO

IMPROVE LOAD REGULATION

INPUT

TO 25V

GND

1374 F17

0.27µF

0.01µF

470ΩD1

MBRD340

C1**

100µF

10V TANT

C5**

100µF

10V TANT

22µF

35V TANT

C4**

4.7nF

1N914

MBRD340

L1A*

6.8µH

L1B*

SENSE

BIAS

GND

SHDN V

Figure 17. Dual Output SEPIC Converter