1. General description
The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops
with individual dat a input s (Dn) an d both Qn and Qn output s. The common clock (CP) and
master reset (MR) inputs load and reset all flip-flop s simult aneously. The D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is
stored in the flip-flop and appea rs at the Q output. A LOW on MR causes the flip-flop s and
outputs to be reset LOW.
The device is useful for applications where both the true and complement outputs are
required and the clock and master reset are common to all storage elements.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC175-Q100: CMOS level
For 74HCT175-Q100: TTL level
Four edge-triggered D-type flip-flops
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
Rev. 1 — 19 May 2014 Product data sheet
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 2 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperatur e ra nge Name Description Version
74HC175D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm SOT109-1
74HCT175D-Q100
74HC175PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT175PW-Q100
Fig 1. Logic symbol Fig 2. IEC logic symbol
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Fig 3. Logic diagra m
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74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 3 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration SO16 Fig 5. Pin configuration TSSOP16
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Table 2. Pin description
Symbol Pin Description
MR 1 asynchronous master reset input (active LOW)
Q0 to Q3 2, 7, 10, 15 flip-flop output
Q0 to Q3 3, 6, 11, 14 complementary flip-flop output
D0 to D3 4, 5, 12, 13 data input
GND 8 ground (0 V)
CP 9 clock input (LOW-to-HIGH edge-triggered)
VCC 16 positive supply voltage
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 4 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Table 3. Function table[1]
Operating modes Inputs Outputs
MR CP Dn Qn Qn
reset (clear) L X X L H
load “1” H hHL
load “0” H lLH
Fig 6. Functional diagram
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74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 5 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
7. Limiting values
[1] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V )
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5V - 20 mA
IOK output clamping current VO < 0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[1] - 500 mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC175-Q100 74HCT175-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V--83---ns/V
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 6 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC175-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1- 1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V --8.0- 80 - 160A
CIinput
capacitance -3.5-- - - - pF
74HCT175-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 5.5 V - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =5.5V --0.1 - 1- 1A
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 7 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
10. Dynamic characteristics
ICC supply current VI = VCC or GND; IO=0A;
VCC =5.5V --8.0- 80 - 160A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn input - 40 144 - 180 - 196 A
CP input - 60 216 - 270 - 294 A
MR input - 100 360 - 450 - 490 A
CIinput
capacitance -3.5-- - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC175-Q100
tpd propagation
delay CP to Qn, Qn;
see Figure 7 [1]
VCC = 2.0 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC =5V; C
L=15pF-17---- - ns
VCC = 6.0 V - 16 30 - 37 - 45 ns
tPHL HIGH to LOW
propagation
delay
MR to Qn, Qn;
see Figure 9
VCC = 2.0 V - 50 150 - 190 - 225 ns
VCC = 4.5 V - 18 30 - 38 - 45 ns
VCC =5V; C
L=15pF-15---- - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
tttransition time Qn output; see Figure 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 8 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
tWpulse width CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
MR input LOW;
see Figure 9
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
trec recovery time MR to CP; see Figure 9
VCC = 2.0 V 5 33 - 5 - 5 - ns
VCC = 4.5 V 5 12 - 5 - 5 - ns
VCC = 6.0 V 5 10 - 5 - 5 - ns
tsu set-up time Dn to CP; see Figure 7
VCC = 2.0 V 80 3 - 100 - 120 - ns
VCC = 4.5 V 16 1 - 20 - 24 - ns
VCC = 6.0 V 14 1 - 17 - 20 - ns
thhold time Dn to CP; see Figure 7
VCC = 2.0 V 25 2 - 30 - 40 - ns
VCC = 4.5 V 5 0 - 6 - 8 - ns
VCC = 6.0 V 4 0 - 5 - 7 - ns
fmax maximum
frequency CP input; see Figure 7
VCC = 2.0 V 6 25 - 4.8 - 4 - MHz
VCC = 4.5 V 30 75 - 24 - 20 - MHz
VCC =5V; C
L=15pF - 83 - - - - - MHz
VCC = 6.0 V 35 89 - 28 - 24 - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC
[3] -32---- - pF
74HCT175-Q100
tpd propagation
delay CP to Qn, Qn;
see Figure 7 [1]
VCC = 4.5 V - 19 33 - 41 - 50 ns
VCC =5V; C
L=15pF-16---- - ns
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 9 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure 9
VCC = 4.5 V - 22 38 - 48 - 57 ns
VCC =5V; C
L=15pF-19---- - ns
MR to Qn; see Figure 9
VCC = 4.5 V - 19 35 - 44 - 53 ns
VCC =5V; C
L=15pF-16---- - ns
tttransition time Qn output; see Figure 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width CP input; see Figure 7
VCC = 4.5 V 20 12 - 25 - 30 - ns
MR input LOW;
see Figure 9
VCC = 4.5 V 20 11 - 25 - 30 - ns
trec recovery time MR to CP; see Figure 9
VCC = 4.5 V 5 10 - 5 - 5 - ns
tsu set-up time Dn to CP; see Figure 7
VCC = 4.5 V 16 5 - 20 - 24 - ns
thhold time Dn to CP; see Figure 7
VCC = 4.5 V 5 0 - 5 - 5 - ns
fmax maximum
frequency CP input; see Figure 7
VCC = 4.5 V 25 49 - 20 - 17 - MHz
VCC =5V; C
L=15pF - 54 - - - - - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC 1.5 V [3] -34---- - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 10 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
11. Waveforms
Measurement points are given in Table 8.
Fig 7. Input to output propagation de la y, output tran s itio n time , cl oc k input pulse width and ma x imum
frequency
W:
W3+/
W3+/
W7/+
90
90
PD[
W3/+
W7+/
W3/+
90
3LQSXW
*1'
9,
92/
92+
92/
92+
Measurement points are given in Table 8.
Fig 8. Dat a set-u p and hold times for data input
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9
0
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3LQSXW
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4QRXWSXW
4QRXWSXW
9
0
9
0
9
0
W
VX
W
VX
W
K
W
K
*1'
9
,
*1'
9
,
9
2/
9
2+
9
2/
9
2+
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 11 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
Measurement points are given in Table 8.
Fig 9. Master reset to output propagation delays, master reset pulse width and master reset to clock reco very
time
4QRXWSXW
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9
0
W
:
W
UHP
9
0
9
0
9
0
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3+/
&3LQSXW
05LQSXW
4QRXWSXW
W
3/+
*1'
9
,
*1'
9
,
9
2/
9
2+
9
2/
9
2+
Table 8. Measurement points
Type Input Output
VIVMVM
74HC175-Q100 VCC 0.5VCC 0.5VCC
74HCT175-Q100 3 V 1.3 V 1.3 V
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 12 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 10. Test circuit for measuring switching times
001aah768
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 % VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
Table 9. Test data
Type Input Load Test
VItr, tfCLRL
74HC175-Q100 VCC 6ns 15pF, 50 pF 1ktPLH, tPHL
74HCT175-Q100 3 V 6 ns 15 pF, 50 pF 1 ktPLH, tPHL
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 13 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
12. Package outline
Fig 11. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 14 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
Fig 12. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 15 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT175_Q10 0 v.1 20140519 Product data sheet - -
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 16 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability t owards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by cust omer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT175_Q100 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 19 May 2014 17 of 18
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC175-Q100; 74HCT175-Q100
Quad D-type flip-flop with reset; positive-edge trigger
© NXP Semiconductors N.V. 2014. A ll rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 May 2014
Document identi fier: 74HC_HC T 175_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16 Contact information. . . . . . . . . . . . . . . . . . . . . 17
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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