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December 2015
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3
FSL4110LR — 1000 V SenseFET Integrated Power Switch
FSL4110LR
1000 V SenseFET Integrated Power Switch
Features
Built-in Avalanche Rugged 1000 V SenseFET
Precise Fixed Operating Frequency: 50 kHz
VCC can be supplied from either bias-winding or self-
biasing.
Soft Burst-Mode Operation Minimizing Audible Noise
Random Frequency Fluctuation for Low EMI
Pulse-by-Pulse Current Limit
Various Protection Functions: Overload Protection
(OLP), Over-Voltage Protection (OVP), Abnormal
Over-Current Protection (AOCP), Internal Thermal
Shutdown (TSD) with Hysteresis. Under-Voltage
Lockout (UVLO) and Line Over-Voltage Protection
(LOVP) with Hysteresis.
Built-in Internal Startup and Soft-Start Circuit
Fixed 1.6 s Restart Time for Safe Auto-Restart Mode
of All Protections
Applications
SMPS for Electric Metering
Auxiliary Power Supply for 3-Phase Input Industrial
Systems
Description
The FSL4110LR is an integrated pulse width
modulation (PWM) controller and 1000 V avalanche
rugged SenseFET specifically designed for high input
voltage offline Switching Mode Power Supplies (SMPS)
with minimal external components. VCC can be supplied
through integrated high-voltage power regulator without
auxiliary bias winding.
The integrated PWM controller includes a fixed-
frequency oscillator, Under-Voltage Lockout (UVLO),
Leading-Edge Blanking (LEB), optimized gate driver,
soft-start, temperature-compensated precise current
sources for loop-compensation, and variable protection
circuitry.
Compared with a discrete MOSFET and PWM controller
solution, the FSL4110LR reduces total cost, component
count, PCB size, and weight; while simultaneously
increasing efficiency, productivity, and system reliability.
This device provides a basic platform for cost-effective
design of a flyback converter.
Ordering Information
Part Number
Package
Operating
Junction
Temperature
Current
Limit
RDS(ON) (Max.)
Output Power Table(1)
45~460 VAC(2)
85~460 VAC(2)
FSL4110LRN
7-DIP
-40°C ~ 125°C
0.52 A
10 Ω
4 W(3)
9 W(3)
FSL4110LRLX
7-LSOP
Notes:
1. The junction temperature can limit the maximum output power.
2. Maximum practical continuous power in an open-frame design at 50 C ambient temperatures.
3. Bias winding condition.
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 2
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Typical Application Circuit
PWM
VSTR
Drain
GND
VCC
VOUT
FB
VIN
RSTR
RDLY
CFB
FSL4110LR
R1
R2
CVCC
Figure 1. Typical Application Circuit
Notes:
4. RSTR: See the functional description 1.
5. RDLY: See the functional description 3.1.
Internal Block Diagram
2 6,7
1
VREF
Internal
Bias
S
Q
Q
R
OSC
VOLP
TSD
VCC Drain
FB
GND
Gate
Driver
4
VCC Good
LEB
HVREG
RSENSE
VBURH
/VBURL
VIN
1.6 s Auto Restart
Timing Control
VINH
VSTART
/ VSTOP
VOVP
100 ms
Delay
VCC
PWM
Soft-
Start
3R
R
VREF
IFB
5
VSTR
VAOCP
VCC
3
Soft
Burst
Random
Line
Comp.
RDLY
CFB
Figure 2. Internal Block Diagram
(4)
(5)
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 3
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Pin Configuration
1
GND
VCC
VSTR
FB
VIN
Drain
FSL4110LR
Drain
2
3
4
7
6
5
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
GND
Ground. The SenseFET source terminal on primary side and the internal PWM control ground.
2
VCC
Power Supply Voltage Input. This pin is the positive supply input, which provides the internal
operating current for startup and steady-state operation. This voltage is supplied from internal
high-voltage regulator via pin 5 (VSTR) during startup (see Figure 2). When the external bias
voltage is higher than 10 V, internal high voltage regulator is disable. A ceramic capacitor need
to be placed as close as possible between this pin and pin 1 (GND). Recommended distance is
less than 3 mm.
3
FB
Feedback. This pin is internally connected to the inverting input to the PWM comparator. This
pin has a 100 μA current source internally. The collector of an opto-coupler is typically tied to
this pin. A capacitor should be placed between this pin and GND. A resitor should be
connected between this pin and pin 2 (VCC) to generate delay current (IDELAY) for overload
protection delay time. The resistance should not be exceed 5 M in self-biasing.
4
VIN
Line Over-Voltage Input. This pin is the input of divided line voltage. The voltage is devided by
resistors. When this voltage is higher than 2 V, the FSL4110LR is not operationed. If this pin is
not used, it should be connected to the ground.
5
VSTR
Startup. Connected to the rectified AC line voltage source. At startup, the internal switch
supplies internal bias and charges an external storage capacitor placed between VCC pin and
ground. Once VCC reaches 12 V, all internal blocks are activated. The internal high-voltage
regulator turns on and off to maintain VCC at 10 V without auxiliary bias winding.
6, 7
Drain
Drain. Designed to connect directly to the primary lead of the transformer and capable of
switching a maximum of 1000 V. Minimizing the length of the trace connecting these pins to the
transformer decreases leakage inductance.
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 4
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VSTR
VSTR Pin Voltage
700
V
VDS
Drain Pin Voltage
1000
V
VCC
VCC Pin Voltage
27
V
VFB
Feedback Pin Voltage(6)
-0.3
12.0
V
VIN
VIN Pin Voltage(6)
-0.3
12.0
V
IDM
Drain Current Pulsed
4
A
IDS
Continuous Switching Drain Current (7)
TC=25C
1
A
TC=100C
0.6
A
EAS
Single Pulsed Avalanche Energy(8)
51
mJ
PD
Total Power Dissipation (TC=25C)(9)
1.5
W
TJ
Maximum Junction Temperature
150
C
Operating Junction Temperature(10)
-40
+125
C
TSTG
Storage Temperature
-55
+150
C
Notes:
6. VFB and VIN are clamped by internal clamping diode (11 V, ICLAMP_MAX < 100 µA).
7. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (DMAX=0.73)
and junction temperature (see Figure 4).
8. IAS = 3.2 A, L = 10 mH, starting TJ=25C.
9. Infinite cooling condition (refer to the SEMI G30-88).
10. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
IDS
DMAX fS
Figure 4. Repetitive Peak Switching Current
Thermal Impedance
Symbol
Parameter
Value
Unit
θJA
Junction-to-Ambient Thermal Impedance(11)
85
°C/W
Note:
11. JEDEC recommended environment, JESD51-2, and test board, JESD51-3, with minimum land pattern.
ESD Capability
Symbol
Parameter
Value
Unit
ESD
Human Body Model, ANSI/ESDA/JEDEC JS-001-2012
5.0
KV
Charged Device Model, JESD22-C101
2.0
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 5
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Electrical Characteristics
TJ =-40C to 125C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
SenseFET Section
BVDSS
Drain-Source Breakdown Voltage(12)
VGS = 0 V, ID = 250 µA
1000
V
IDSS
Zero-Gate-Voltage Drain Current(12)
VDS = 1000 V, VGS = 0 V
250
A
RDS(ON)
Drain-Source On-State
Resistance(12)
VGS = 10 V, ID = 1.0 A
10
Ω
CISS
Input Capacitance(12)(13)
VDS = 25 V, VGS = 0 V,
f = 1 MHz
367
477
pF
COSS
Output Capacitance(12)(13)
37.5
48.8
pF
td(on)
Turn-On Delay Time(12)
VDD = 500 V, ID = 1.0 A,
VGS = 10 V, Rg = 25 Ω
13.7
ns
tr
Rise Time(12)
14
ns
td(off)
Turn-Off Delay Time(12)
33
ns
tf
Fall Time(12)
45
ns
Control Section
fS
Switching Frequency(12)
VCC = 14 V, VFB = 4 V
46.5
50.0
53.5
kHz
fM
Frequency Modulation(13)
±1.5
kHz
DMAX
Maximum Duty Ratio
VCC = 14 V, VFB = 4 V
61
67
73
%
IFB
Feedback Source Current(12)
VFB = 0 V
70
100
130
µA
VSTART
UVLO Threshold Voltage
VFB = 0 V, VCC Sweep
11
12
13
V
VSTOP
After Turn-on, VFB = 0 V
7
8
9
tS/S
Internal Soft-Start Time
VSTR = 40 V, VCC Sweep
20
ms
Burst-Mode Section
VBURH
Burst-Mode Voltage(12)
VCC = 14 V, VFB Sweep
0.45
0.50
0.55
V
VBURL
0.35
0.40
0.45
V
VHYS
100
mV
Protection Section
ILIM
Peak Drain Current Limit(12)
di/dt = 240 mA/s
0.45
0.52
0.59
A
VOLP
Overload Protection(12)
VCC = 14 V, VFB Sweep
4.0
4.4
4.8
V
VAOCP
Abnormal Over-Current
Protection(13)
1.0
V
tLEB
Leading-Edge Blanking Time(13)(14)
250
ns
tCLD
Current Limit Delay Time(13)
200
ns
VOVP
Over-Voltage Protection
VCC Sweep
23.0
24.5
26.0
V
VINH
Line Over-Voltage Protection
Threshold Voltage
VCC = 14 V, VIN Sweep
1.9
2.0
2.1
V
VINHYS
Line Over-Voltage Protection
Hysteresis(12)
VCC = 14 V, VIN Sweep
100
mV
tDELAY
Overload Protection Delay
100
ms
tRESTART
Restart Time After Protection(13)
1.6
s
TSD
Thermal Shutdown Temperature(13)
Shutdown Temperature
130
140
150
C
THYS
Hysteresis (FSL4110LRN)
60
THYS
Hysteresis (FSL4110LRLX)
30
Continued on the following page…
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 6
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Electrical Characteristics (Continued)
TJ =-40C to 125C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
High Voltage Regulator Section
VHVREG
HV Regulator Voltage
VFB = 0 V, VSTR = 40 V
9
10
11
V
Total Device Section
IOP
Operating Supply Current,
(Control Part in Burst Mode)(12)
VCC = 14 V, VFB = 0 V
0.40
0.50
mA
IOPS
Operating Switching Current,
(Control Part and SenseFET Part)(12)
VCC = 14 V, VFB = 2 V
1.00
1.35
mA
ISTART
Start Current(12)
VCC = 11 V (Before VCC
Reaches VSTART)
160
240
µA
ICH
Startup Charging Current(12)
VCC = VFB = 0 V, VSTR = 40 V
1.5
2.0
mA
VSTR
Minimum VSTR Supply Voltage
CVCC = 0.1 µF, VSTR Sweep
26
V
Notes:
12. TJ = 25C.
13. Although these parameters are guaranteed, they are not 100% tested in production.
14. tLEB includes gate turn-on time.
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 7
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Typical Performance Characteristics
Characteristic graphs are normalized at TA=25°C.
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
Operating Supply Current (IOP)
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
Operating Switching Current (IOPS)
Figure 5. Operating Supply Current (IOP) vs. TA
Figure 6. Operating Switching Current (IOPS) vs. TA
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
Startup Charging Current (ICH)
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
Peak Drain Current Limit (ILIM)
Figure 7. Startup Charging Current (ICH) vs. TA
Figure 8. Peak Drain Current Limit (ILIM) vs. TA
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
Feedback Source Current (IFB)
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
Startup Charging Current (VHVREG)
Figure 9. Feedback Source Current (IFB) vs. TA
Figure 10. HV Regulator Voltage (VHVREG) vs. TA
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 8
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Typical Performance Characteristics (Continued)
Characteristic graphs are normalized at TA=25°C.
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
UVLO Threshold Voltage (VSTART)
Figure 11. UVLO Threshold Voltage (VSTART) vs.
TA
Figure 12. UVLO Threshold Voltage (VSTOP) vs. TA
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
Over-Voltage Protection (VOVP)
Figure 13. OLP Feedback Voltage (VOLP) vs. TA
Figure 14. Over-Voltage Protection (VOVP) vs. TA
0.85
0.9
0.95
1
1.05
1.1
1.15
-40℃
-25℃
0℃
25℃
50℃
85℃
100℃
125℃
Normalized
Temperature (℃)
Switching Frequency (fS)
Figure 15. Switching Frequency (fS) vs. TA
Figure 16. Maximum Duty Ratio (DMAX) vs. TA
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 9
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Functional Description
1. Startup and High-Voltage Regulator
During startup, an internal high-voltage current source
(ICH) of the high-voltage regulator (HVREG) supplies the
internal bias current (ISTART) and charges the external
capacitor (CVCC) connected to VCC pin, as shown in
Figure 17. This internal high-voltage current source is
enabled until VCC reaches VSTART (12 V). During steady-
state operation, this internal high-voltage regulator
(HVREG) maintains the VCC with 10 V and provides
operating switching current (IOPS) for all internal circuits.
Therefore, FSL4110LR needs no external bias circuit.
The high-voltage regulator is disabled when VCC
supplied by the external bias is higher than 10 V.
However in the case of self-biasing, power consumption
is increased.
VREF
Internal
Bias
VCC
VCC Good
2
HVREG
VSTART
/ VSTOP
5
VSTR
RSTR CINH
Rectified
Line Input
(VDC)
CVCC
ICH
CINL
ISTART or IOPS
R1
R2
R3
Figure 17. Startup and HVREG Block
The startup resistor (RSTR) can be calculated by the
following equation (1).
CH
STARTMINDC
STR I
VV
R
_
(1)
where, IOPS < ICH < 2 mA,
RSTR + R1 = R2 + R3
2. Feedback Control
FSL4110LR employs current-mode control scheme. An
opto-coupler (such as FOD817) and shunt regulator
(such as KA431) in secondary-side are typically used to
implement the feedback network. Comparing the
feedback voltage with the voltage across RSENSE resistor
makes it possible to control the switching duty cycle.
When the input voltage is increased or the output load
is decreased, reference input voltage of shunt regulator
is increased. If this voltage exceeds internal reference
voltage of shunt regulator, opto-diode’s current of the
opto-coupler increases, pulling down the feedback
voltage and reducing drain current.
2.1. Pulse-by-Pulse Current Limit
Because current-mode control is employed, the peak
current flowing through the SenseFET is limited by the
inverting input of PWM comparator, as shown in Figure
18. Assuming that 100 µA current source (IFB) flows
only through the internal resistors (3R + R = 24 k), the
cathode voltage of diode D2 is about 2.4 V. Since D1 is
blocked when feedback voltage (VFB) exceeds 2.4 V,
the maximum voltage of the cathode of D2 is clamped
at this voltage. Therefore, the peak value of the current
of the SenseFET is limited at:
RatioSense
RV
SENSE
4.2
(2)
6,7
1
VOLP
Drain
FB
GND
Gate
Driver
RSENSE
PWM
3R
R
VREF
IFB
VAOCP
VCC
3
RDLY
OLP AOCP
OSC
CFB
D1 D2
LEB
FOD817
KA431
VOUT
Line
Comp.
IDLY
Figure 18. Pulse Width Modulation Circuit
2.2. Leading Edge Blanking (LEB)
At the instant, the internal SenseFET is turned on, a
high-current spike usually occurs through the
SenseFET, caused by primary-side capacitance and
secondary-side rectifier reverse recovery. Excessive
voltage across the RSENSE resistor leads to incorrect
feedback operation in the current-mode PWM control.
To counter this effect, FSL4110LR employs a leading-
edge blanking (LEB) circuit. This circuit inhibits the
PWM comparator for tLEB (250 ns) after the SenseFET
is turned on.
3. Protection Circuits
The protective functions include Overload Protection
(OLP), Over-Voltage Protection (OVP), Under-Voltage
Lockout (UVLO), Abnormal Over-Current Protection
(AOCP), and Thermal Shutdown (TSD). All of the
protections operate in auto-restart mode as shown in
Figure 19. Since these protection circuits are fully
integrated inside the IC without external components,
reliability is improved without increasing cost and PCB
space. If a fault condition occurs, switching is
terminated and the SenseFET remains off. At the same
time, internal protection timing control is activated to
decrease power consumption and stress on passive
and active components during auto-restart. When
internal protection timing control is activated, VCC is
regulated with 10 V through the internal high-voltage
regulator while switching is terminated. This internal
protection timing control continues until restart time
(1.6 s) duration is finished. After counting to 1.6 s, the
internal high-voltage regulator is disabled and VCC is
decreased. When VCC reaches the UVLO stop voltage,
VSTOP (8 V), the protection is reset and the internal high-
voltage current source charges the VCC capacitor via
the high voltage startup pin (VSTR) again. When VCC
reaches the UVLO start voltage, VSTART (12 V), the
FSL4110LR resumes normal operation. In this manner,
auto-restart function can alternately enable and disable
the switching of the power SenseFET until the fault
condition is eliminated.
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 10
FSL4110LR — 1000 V SenseFET Integrated Power Switch
Fault condition
VSTOP
VSTART
VCC
VDS
t
Fault
occurs Fault
removed
Normal
operation Normal
operation
Power
on
VHVREG
VAUX
t
Restart time (1.6 s)
Figure 19. Auto-Restart Protection Waveforms
3.1. Overload Protection (OLP)
Overload is defined as the load current exceeding its
normal level due to an unexpected abnormal event. In
this situation, the protection circuit should trigger to
protect the SMPS. However, even when the SMPS is in
normal operation, the overload protection circuit can be
triggered during load transition. To avoid this undesired
operation, the overload protection circuit is designed to
trigger only after a specified time to determine whether
it is a transient situation or a true overload situation.
Because of the pulse-by-pulse current-limit capability,
the maximum peak current through the SenseFET is
limited. If the output consumes more than this maximum
power, the output voltage decreases below the set
voltage. This reduces the current through the opto-
diode, which also reduces the opto-coupler transistor
current, thus increasing the feedback voltage (VFB). If
VFB exceeds 2.4 V, internal diode D1 is blocked and the
current (IDLY) by RDLY starts to charge CFB. If feedback
voltage reaches 4.4 V, internal fixed delay time (tDELAY)
starts counting. If feedback voltage maintains over
4.4 V after tDELAY (100 ms), the switching operation is
terminated (see Figure 20). The internal OLP circuit is
shown in Figure 21.
VCC
VFB
IDS
Overload
Disappear
Overload
Occurrence
VHVREG
VSTOP
4.4 V
2.4 V tRESTART
tDLY
VSTART
VAUX
tDELAY
t
t
t
Figure 20. OLP Waveforms
1
VOLP
Drain
FB
GND
Gate
Driver
RSENSE
PWM
3R
R
VREF
IFB
VCC
3
RDLY
OLP
OSC
CFB
D1 D2
100 ms
Delay
S
Q
Q
R
6,7
LEB
Line
Comp.
IDLY
OLP
Figure 21. OLP Circuit
Recommended the RDLY value is less than 5 MΩ in self-
biasing. The delay time (tDLY) can be calculated by
equation (3).
4.2
2
1ln
CC
FBDLYDLY V
CRt
(3)
Example:
When, RDLY = 3 MΩ, CFB = 68 nF, VCC = 15 V,
tDLY = 35 ms
∴ Total delay time for OLP: 135 ms
3.2. Abnormal Over-Current Protection (AOCP)
When the secondary rectifier diodes or the transformer
pins are shorted, a steep current with extremely high
di/dt can flow through the SenseFET during the
minimum turn-on time. Overload protection is not
enough to protect the FSL4110LR in that abnormal
case (see Figure 22); since severe current stress is
imposed on the SenseFET until OLP is triggered. The
internal AOCP circuit is shown in Figure 23. When the
gate turn-on signal is applied to the power SenseFET,
the AOCP block is enabled and monitors the current
through the sensing-resistor. The voltage across the
resistor is compared with a preset AOCP level. If the
sensing resistor voltage is greater than the AOCP level,
the high signal is applied to input of the NOR gate,
resulting in the shutdown of the SMPS.
VCC
AOCP
Disappear
VHVREG
VSTOP tRESTART
VSTART
VAUX
t
t
IDS
AOCP
Occurrence
Figure 22. AOCP Waveforms
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 11
FSL4110LR — 1000 V SenseFET Integrated Power Switch
1
Drain
FB
GND
Gate
Driver
RSENSE
PWM
3R
R
VREF
IFB
3
OSC
D1 D2
S
Q
Q
R
6,7
LEB
Line
Comp. AOCP
VAOCP
AOCP
Figure 23. AOCP Circuit
3.3. Over-Voltage Protection (OVP)
If the secondary-side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path,
the current through the opto-coupler transistor becomes
almost zero. Then VFB climbs in a similar manner to the
overload situation, forcing the preset maximum drain
current to flow until the overload protection is triggered.
Because more energy than required is provided to the
output, the output voltage may exceed the rated voltage
before the overload protection is triggered, resulting in
the breakdown of the devices in the secondary side. To
prevent this situation, an OVP circuit is employed. In
general, the VCC is proportional to the output voltage
when the bias-winding is used and the FSL4110LR
uses VCC instead of directly monitoring the output
voltage. If VCC exceeds 24.5 V, an OVP circuit is
triggered, resulting in the termination of the switching
operation. To avoid undesired activation of OVP during
normal operation, VCC s hould be designed to be below
24.5 V in the normal conditions. The internal OVP
circuit is shown in Figure 24.
1
Drain
FB
GND
Gate
Driver
RSENSE
PWM
3R
R
VREF
IFB
3
OSC
D1 D2
S
Q
Q
R
6,7
LEB
Line
Comp. OVP
VOVP
OVP
VCC 2
Figure 24. OVP Circuit
3.4. Thermal Shutdown (TSD)
The SenseFET and control IC integrated on the same
package makes it easier to detect the temperature of
the SenseFET. When the junction temperature exceeds
140°C, thermal shutdown is activated. The FSL4110LR
is restarted when the temperature decreases by 60°C
within tRESTART (1.6 s).
3.5. Line Over-Voltage Protection (LOVP)
If the line input voltage is increased to an undesirable
level, high line input voltage creates high-voltage stress
on the entire system. To protect the SMPS from this
abnormal condition, LOVP is included. It is comprised of
detecting VIN voltage by using divided resistors. When
voltage of VIN voltage is higher than 2.0 V, this condition
is recognized as an abnormal error and PWM switching
shuts down until voltage of VIN voltage decreases to
around 1.9 V within tRESTART (see Figure 25). The
internal LOVP circuit is shown in Figure 26.
VCC
LOVP
Disappear
VHVREG
VSTOP tRESTART
VSTART
VAUX
t
t
IDS
LOVP
Occurrence
Figure 25. LOVP Waveforms
VIN
1
Drain
FB
GND
Gate
Driver
RSENSE
PWM
3R
R
VREF
IFB
3
OSC
D1 D2
S
Q
Q
R
6,7
LEB
Line
Comp. LOVP
4
VINH
LOVP
R2 CVIN
R1
Rectified Line
Input (VDC)
Figure 26. LOVP Circuit
Equation (4) calculates the level of input over-voltage to
RMS value.
INHDC
INH VV RV
R
1
2
(4)
The resistance of divided resistor can be adjusted as
necessary. Small resistance can bring relatively large
stand-by power consumption at light-load condition.
To avoid this situation, a several MΩ resistor is
recommended. For stable operation, a several MΩ
resistor should accompany a capacitor (CVIN) with
hundreds of pF capacitance between the VIN pin and
GND.
4. Oscillator Block
The oscillator frequency is set internally and the
FSL4110LR has a random frequency fluctuation
function as shown in Figure 27. Fluctuation of the
switching frequency can reduce EMI by spreading the
energy over a wider frequency range than the
bandwidth measured by the EMI test equipment. The
range of frequency variation is fixed internally; however,
its selection is randomly chosen by the combination of
an external feedback voltage and an internal free-
running oscillator. This randomly chosen switching
frequency effectively spreads the EMI noise near
switching frequency and allows the use of a cost-
effective inductor instead of an AC input line filter to
satisfy world-wide EMI requirements.
© 2014 Fairchild Semiconductor Corporation www.fairchildsemi.com
FSL4110LR • Rev. 1.3 12
FSL4110LR — 1000 V SenseFET Integrated Power Switch
tS
Dt
IDS
t
t
fSW fS + 1/2DfSMAX
fS - 1/2DfSMAX
no repetition
several
mseconds
several
miliseconds
tS = 1/fS
Figure 27. Frequency Fluctuation Waveforms
5. Soft-Start
The internal soft-start circuit slowly increases the
SenseFET current after it starts. The typical soft-start
time is 20 ms, as shown in Figure 28, where
progressive increments of the SenseFET current are
allowed during startup. The pulse width to the power
switching device is progressively increased to establish
the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is gradually increased to smoothly establish
the required output voltage. Soft-start also helps to
prevent transformer saturation and reduces stress on
the secondary diode.
2.5ms
8-Steps
Soft start envelope
ILIM
t
Drain Current
Figure 28. Internal Soft-Start
6. Burst Mode Operation
To minimize power dissipation in standby mode, the
FSL4110LR enters burst mode. As the load decreases,
the feedback voltage decreases. The device
automatically enters burst mode when the feedback
voltage drops below VBURL (400 mV), as shown in
Figure 29. At this point, switching stops and the output
voltages start to drop at a rate dependent on standby
current load. This causes the feedback voltage to rise.
Once it passes VBURH (500 mV), switching resumes.
Feedback voltage then falls and the process repeats.
Burst Mode alternately enables and disables switching
of the SenseFET, reducing switching loss in standby
mode. Additionally to reduce the audible noise soft-
burst is implemented.
VFB
VDS
0.4V
0.5V
IDS
VO
t
Switching
disabled Switching
disabled
t
t
t
Figure 29. Burst Mode Operation
7. Line Compensation
All of switching devices have their own inherent
propagation delays. This propagation delay will cause a
current limit delay defined as tCLD. Because there is a
current limit delay, tCLD, there is a difference in the
current peak between low and high input voltage. The
variance in the current peak is related to the difference
between the input voltages, a wider gap in input voltage
will result in a greater variance of the current peak.
In order to have a constant current peak regardless of
the input voltage, line compensation is required.
FSL4110LR has line compensation, so the real peak
value of high input voltage is similar to that of low input
voltage. tCLD effect could be neglected as showed
Figure 30.
IDRAIN(460 VAC): 100 mA/div
IDRAIN(85 VAC): 100 mA/div
500 ns/div
Figure 30. ILIMIT Waveforms (85 VAC vs. 460 VAC)
6.70 10.70
1.784
1.252
2.00 2.54
7.62
3.60
3.20
0.10 MIN
2.54
7.62
3.70 MAX
C
10.00
9.10
6.60
6.20
0.56
1.62
1.47
0.56
0.36
1.09
0.94
0.56
0.36
9.90
9.30
1 4
57
A
B
0.35
0.20
7.62
A
9°
3°
1.60 REF
0.25
8°
0°
1.12
0.72
DETAIL A
SCALE 2:1
R0.20
R0.20
GAGE PLANE
SEATING
PLANE
TOP VIEW
FRONT VIEW
SIDE VIEW
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A. NO INDUSTRY STANDARD APPLIES TO
THIS PACKAGE
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-2009
E. DRAWING FILENAME: MKT-MLSOP07Arev2
0.10
C
0.10
M
C
B A
0.10
M
C
B A
3.429
3.175
12°
3.937
3.683
2.54
0.508 MIN
SEATING
PLANE
1.651
1.397
3.556
3.048
0.508
0.406
C
9.779
9.525
6.477
6.223
(0.787)
14
57
PIN #1
A
B
0.381
0.203
12°
9.398
7.874
7.874
7.620
7.53
TOP VIEW
FRONT VIEW
SIDE VIEW
NOTES:
A. REFERENCE JEDEC MS-001, VARIATION BA
EXCEPT FOR NUMBER OF LEADS.
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR EXTRUSIONS.
E. DRAWING FILENAME: MKT-NA07Drev2
0.10
M
C
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