DATA SH EET
Product specification
Supersedes data of 2003 May 14 2003 Nov 12
INTEGRATED CIRCUITS
74LVC541A
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state)
2003 Nov 12 2
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
FEATURES
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 2.7 to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74LVC541A is a high performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. This feature
allows the use of these devices as translators in a mixed
3.3 and 5 V environment.
The 74LVC541A is an octal non-inverting buffer/line driver
with 5 V tolerant inputs/outputs. The 3-state outputs are
controlled by the output enable inputs OE1and OE2.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay An to Yn CL= 50 pF; VCC = 3.3 V 3.3 ns
CIinput capacitance 5.0 pF
CPD power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 20 pF
2003 Nov 12 3
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
INPUT OUTPUT
OE1 OE2 An Yn
LLLL
LLHH
XHXZ
HXXZ
TYPE NUMBER TEMPERATURE RANGE PACKAGE
PINS PACKAGE MATERIAL CODE
74LVC541AD 40 to +125 °C 20 SO20 plastic SOT163-1
74LVC541ADB 40 to +125 °C 20 SSOP20 plastic SOT339-1
74LVC541APW 40 to +125 °C 20 TSSOP20 plastic SOT360-1
74LVC541ABQ 40 to +125 °C 20 DHVQFN20 plastic SOT764-1
PINNING
PIN SYMBOL DESCRIPTION
1OE1 output enable input
(active LOW)
2 A0 data input
3 A1 data input
4 A2 data input
5 A3 data input
6 A4 data input
7 A5 data input
8 A6 data input
9 A7 data input
10 GND ground (0 V)
11 Y7 bus output
12 Y6 bus output
13 Y5 bus output
14 Y4 bus output
15 Y3 bus output
16 Y2 bus output
17 Y1 bus output
18 Y0 bus output
19 OE2 output enable input
(active LOW)
20 VCC supply voltage
PIN SYMBOL DESCRIPTION
2003 Nov 12 4
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
handbook, halfpage
OE1
A0
A1
A2
A3
A4
541
A5
A6
A7
GND
VCC
OE2
Y0
Y1
Y3
Y4
Y2
Y5
Y6
Y7
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
MNA897
Fig.1 Pin configuration SO20 and (T)SSOP20.
handbook, halfpage
1
2
3
4
5
6
7
8
9
A0
A1
A2
A3
A4
A5
A6
A7
19
18
17
16
15
14
13
12
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
20
OE1 VCC
10 11
GND
Top view Y7
GND(1)
MDB202
Fig.2 Pin configuration DHVQFN20.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.3 Logic Symbol (IEEE/IEC).
handbook, halfpage
MNA898
911
12
13
14
15
16
2
3
4
5
6
7
8
18
17
19
1&EN
2003 Nov 12 5
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
handbook, halfpage
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
1
19
A0
A1
A2
A3
A4
A5
A6
A7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
OE1
OE2
MNA899
Fig.4 Logic symbol.
handbook, halfpage
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
1
19
A0
A1
A2
A3
A4
A5
A6
A7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
OE1
OE2
MNA900
Fig.5 Functional diagram.
2003 Nov 12 6
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low-voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage output HIGH or LOW state 0 VCC V
output 3-state 0 5.5 V
Tamb operating ambient temperature in free air 40 +125 °C
tr, tfinput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage 0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 0.5 +5.5 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage output HIGH or LOW state; note 1 0.5 VCC + 0.5 V
output 3-state or power down;
note 1 0.5 +6.5 V
IOoutput diode source or sink current VO=0toV
CC −±50 mA
ICC, IGND VCC or GND current −±100 mA
Tstg storage temperature 60 +150 °C
Ptot power dissipation Tamb =40 to +125 °C; note 2 500 mW
2003 Nov 12 7
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb =40 to +85 °C
VIH HIGH-level input
voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−0V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=100 µA 2.7 to 3.6 VCC 0.2 VCC V
IO=12 mA 2.7 VCC 0.5 −−V
I
O
=18 mA 3.0 VCC 0.6 −−V
I
O
=24 mA 3.0 VCC 0.8 −−V
V
OL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 0 0.2 V
IO=12mA 2.7 −−0.4 V
IO=24mA 3.0 −−0.55 V
ILI input leakage current VI= 5.5 Vor GND 3.6 −±0.1 ±5µA
IOZ 3-state output
OFF-state current VI=V
IH or VIL;
VO= 5.5 Vor GND 3.6 −±0.1 ±5µA
Ioff power-off leakage
supply VIor VO= 5.5 V 0.0 −±0.1 ±10 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 3.6 0.1 10 µA
ICC additional quiescent
supply current per pin VI=V
CC 0.6 V;
IO=0 2.7 to 3.6 5 500 µA
2003 Nov 12 8
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
Note
1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.
Tamb =40 to +125 °C
VIH HIGH-level input
voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−0V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=100 µA 2.7 to 3.6 VCC 0.3 −−V
I
O
=12 mA 2.7 VCC 0.65 −−V
I
O
=18 mA 3.0 VCC 0.75 −−V
I
O
=24 mA 3.0 VCC 1−−V
V
OL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.3 V
IO=12mA 2.7 −−0.6 V
IO=24mA 3.0 −−0.8 V
ILI input leakage current VI= 5.5 Vor GND 3.6 −−±20 µA
IOZ 3-state output
OFF-state current VI=V
IH or VIL;
VO= 5.5 Vor GND 3.6 −−±20 µA
Ioff power-off leakage
supply VIor VO= 5.5 V 0.0 −−±20 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 3.6 −−40 µA
ICC additional quiescent
supply current per pin VI=V
CC 0.6 V;
IO=0 2.7 to 3.6 −−5000 µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
2003 Nov 12 9
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
AC CHARACTERISTICS
GND = 0 V; tr=t
f2.5 ns; CL=50pF.
Notes
1. All typical values are measured Tamb =25°C.
2. These typical values are measured at VCC = 3.3 V.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
WAVEFORMS VCC (V)
Tamb =40 to +85 °C
tPHL/tPLH propagation delay An to Yn see Figs 6 and 8 1.2 14 ns
2.7 1.5 3.9 5.6 ns
3.0 to 3.6 1.0 3.3(2) 5.1 ns
tPZH/tPZL 3-state output enable time
OEn to Yn see Figs 7 and 8 1.2 20 ns
2.7 1.5 5.2 7.5 ns
3.0 to 3.6 1.0 4.4(2) 7.0 ns
tPHZ/tPLZ 3-state output disable time
OEn to Yn see Figs 7 and 8 1.2 11 ns
2.7 1.5 4.3 7.0 ns
3.0 to 3.6 1.0 3.8(2) 6.0 ns
Tamb =40 to +125 °C
tPHL/tPLH propagation delay An to Yn see Figs 6 and 8 1.2 −−−ns
2.7 1.5 7.0 ns
3.0 to 3.6 1.0 6.5 ns
tPZH/tPZL 3-state output enable time
OEn to Yn see Figs 7 and 8 1.2 −−−ns
2.7 1.5 9.5 ns
3.0 to 3.6 1.0 9.0 ns
tPHZ/tPLZ 3-state output disable time
OEn to Yn see Figs 7 and 8 1.2 −−−ns
2.7 1.5 9.0 ns
3.0 to 3.6 1.0 7.5 ns
2003 Nov 12 10
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
AC WAVEFORMS
Fig.6 Input (An) to output (YN) propagation delays.
handbook, halfpage
MNA901
An input
Yn output
tPHL tPLH
GND
VI
VM
VM
VOH
VOL
VOL and VOH are typical output voltage drop that occur with the
output load.
VCC VMINPUT
VItr=t
f
1.2 V 0.5 ×VCC VCC 2.5 ns
2.7 V 1.5 V 2.7 V 2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V 2.5 ns
Fig.7 3-state enable and disable times.
handbook, full pagewidth
MNA902
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OEn input
VOL
VOH
VCC
VI
VM
GND
GND
tPZL
tPZH
VM
VM
VOL and VOH are typical output voltage drop that occur with the
output load.
VCC VMINPUT
VItr=t
f
1.2 V 0.5 ×VCC VCC 2.5 ns
2.7 V 1.5 V 2.7 V 2.5 ns
3.0 to 3.6 V 1.5 V 2.7 V 2.5 ns
VX=V
OL + 0.3 V at VCC 2.7 V;
VX=V
OL + 0.1 V at VCC < 2.7 V;
VY=V
OH 0.3 V at VCC 2.7 V;
VY=V
OH 0.1 V at VCC < 2.7 V.
2003 Nov 12 11
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
handbook, full pagewidth
VEXT
VCC
VIVO
MNA616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
Fig.8 Load circuitry for switching times.
Definitions for test circuits:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
Note
1. The circuit performs better when RL= 1000 .
VCC VICLRLVEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
1.2 V VCC 50 pF 500 (1) open GND 2 ×VCC
2.7 V 2.7 V 50 pF 500 open GND 2 ×VCC
3.0 to 3.6 V 2.7 V 50 pF 500 open GND 2 ×VCC
2003 Nov 12 12
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
PACKAGE OUTLINES
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
2003 Nov 12 13
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
2003 Nov 12 14
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
2003 Nov 12 15
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
2003 Nov 12 16
Philips Semiconductors Product specification
Octal buffer/line driver with 5 V
tolerant inputs/outputs (3-state) 74LVC541A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratany other conditions above thosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Contact information
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Printed in The Netherlands R20/03/pp17 Date of release: 2003 Nov 12 Document order number: 9397 750 12259