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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. HUF75332P3 October 2013 Data Sheet Features N-Channel UltraFET Power MOSFET 55 V, 60 A, 19 m * 60A, 55V These N-Channel power MOSFETs are manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and batteryoperated products. * Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Models - SPICE and SABER Thermal Impedance Models Available on the WEB at: www.fairchildsemi.com * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Formerly developmental type TA75332. Symbol Ordering Information PART NUMBER HUF75332P3 PACKAGE TO-220AB D BRAND 75332P G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0 HUF75332P3 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS V V V 55 55 20 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 60 Figure 4 Figure 6 145 0.97 -55 to 175 A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current BVDSS IDSS IGSS ID = 250A, VGS = 0V (Figure 11) 55 - - V VDS = 50V, VGS = 0V - - 1 A VDS = 45V, VGS = 0V, TC = 150oC - - 250 A VGS = 20V - - 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 10) 2 - 4 V Drain to Source On Resistance rDS(ON) ID = 60A, VGS = 10V (Figure 9) - 0.016 0.019 THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RJC (Figure 3) - - 1.03 oC/W Thermal Resistance Junction to Ambient RJA TO-220 - - 62 oC/W VDD = 30V, ID 60A, RL = 0.50, VGS = 10V, RGS = 6.8 - - 130 ns - 9 - ns tr - 90 - ns td(OFF) - 50 - ns tf - 45 - ns tOFF - - 125 ns VDD = 30V, ID 60A, RL = 0.50 Ig(REF) = 1.0mA - 70 85 nC - 40 50 nC - 2.5 3.0 nC (Figure 13) - 6 - nC - 15 - nC SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Gate to Source Gate Charge Qgs Reverse Transfer Capacitance Qgd (c)2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0 HUF75332P3 TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) - 1300 - pF - 480 - pF - 115 - pF Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage MIN TYP MAX UNITS ISD = 60A - - 1.25 V trr ISD = 60A, dISD/dt = 100A/s - - 75 ns QRR ISD = 60A, dISD/dt = 100A/s - - 140 nC VSD Reverse Recovery Time Reverse Recovered Charge TEST CONDITIONS Typical Performance Curves 80 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 60 40 20 0.2 0 0 0 25 50 75 100 125 25 175 150 50 TC , CASE TEMPERATURE (oC) 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 THERMAL IMPEDANCE ZJC, NORMALIZED 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE (c)2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0 HUF75332P3 Typical Performance Curves (Continued) IDM, PEAK CURRENT (A) 1000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 500 TJ = MAX RATED TC = 25oC IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 500 100 100s 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 oC STARTING TJTJ = 25 STARTING = 25oC STARTING TJ = 150oC VDSS(MAX) = 55V 10 0.001 1 1 10 100 200 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 150 VGS = 20V VGS = 10V VGS = 7V ID, DRAIN CURRENT (A) 120 90 VGS = 6V 60 VGS = 5V 30 0 1.5 3.0 4.5 6.0 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS (c)2005 Fairchild Semiconductor Corporation 25oC 120 -55oC 90 175oC 60 30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 0 ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 7.5 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5 FIGURE 8. TRANSFER CHARACTERISTICS HUF75332P3 Rev. C0 HUF75332P3 Typical Performance Curves (Continued) 1.2 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 60A VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 2.0 1.5 1.0 1.0 0.8 0.6 0.5 -80 -40 0 40 80 120 160 -80 200 -40 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 40 80 120 160 200 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2000 1.2 ID = 250A C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) 1.1 1.0 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 1500 CISS 1000 COSS 500 CRSS 0.9 -80 -40 0 40 80 120 160 0 200 0 10 TJ , JUNCTION TEMPERATURE (oC) 20 30 40 50 60 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VGS , GATE TO SOURCE VOLTAGE (V) 10 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 60A ID = 45A ID = 30A ID = 15A 2 VDD = 30V 0 0 10 20 30 40 50 60 Qg, GATE CHARGE (nC) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT (c)2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0 HUF75332P3 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM VDS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + VGS - VDD 10% 10% 0 DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT (c)2005 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS HUF75332P3 Rev. C0 HUF75332P3 PSPICE Electrical Model .SUBCKT HUF75332 2 1 3 ; rev 17 February 1999 CA 12 8 1.8e-9 CB 15 14 1.73e-9 CIN 6 8 1.19e-9 LDRAIN DPLCAP DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DBREAK + RSLC2 5 51 ESLC 11 - EBREAK 11 7 17 18 58.85 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 RLDRAIN RSLC1 51 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 1e-9 LSOURCE 3 7 1e-9 K1 LSOURCE LGATE 0.0085 + 50 - EVTEMP RGATE + 18 22 9 20 21 EBREAK 17 18 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLSOURCE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 4.5e-3 RGATE 9 20 1.3 RLDRAIN 2 5 10 RLGATE 1 9 10 RLSOURCE 3 7 10 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 5.95e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B S2A 14 13 13 8 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS - 19 - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),4.6))} .MODEL DBODYMOD D (IS = 1.3e-12 RS = 3.0e-3 IKF = 20 XTI = 6 TRS1 = 2.7e-3 TRS2 = 7.0e-7 CJO = 1.7e-9 TT = 4.0e-8 M = 0.45 vj = 0.75) .MODEL DBREAKMOD D (RS = 1.71e-2 IKF = 1.0e-5 TRS1 = -4.0e-4 TRS2 = -1.55e-5) .MODEL DPLCAPMOD D (CJO = 1.8e-9 IS = 1e-30 N = 1 M = 0.9 vj = 1.45) .MODEL MMEDMOD NMOS (VTO = 3.183 KP = 2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.3) .MODEL MSTROMOD NMOS (VTO = 3.66 KP = 51.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.703 KP = 0.008 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 13) .MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = 4.5e-7) .MODEL RDRAINMOD RES (TC1 = 1.16e-2 TC2 = 1.7e-5) .MODEL RSLCMOD RES (TC1 = 3.96e-3 TC2 = 2.7e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-5) .MODEL RVTHRESMOD RES (TC1 = -2.8e-3 TC2 = -1.0e-5) .MODEL RVTEMPMOD RES (TC1 = -2.75e-3 TC2 = 5.0e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -8 VOFF= -3) VON = -3 VOFF= -8) VON = 0 VOFF= 0.5) VON = 0.5 VOFF= 0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0 HUF75332P3 SABER Electrical Model REV 17 February 1999 template huf75332 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 1.3e-12, xti = 6, cjo = 1.7e-9, tt = 4.0e-8, m = 0.45, vj = 0.75) d..model dbreakmod = () DPLCAP d..model dplcapmod = (cjo = 1.8e-9, is = 1e-30, m = 0.9, vj = 1.45) m..model mmedmod = (type=_n, vto = 3.183, kp = 2, is = 1e-30, tox = 1) 10 m..model mstrongmod = (type=_n, vto = 3.66, kp = 51.5, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.703, kp = 8.0e-3, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8, voff = -3) RSLC2 sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -8) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0) GATE 1 i.it n8 n17 = 1 21 DBODY EBREAK + 17 18 MSTRO - 8 LSOURCE 7 SOURCE 3 RSOURCE RLSOURCE S1A 12 m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 4.5e-7 res.rdbody n71 n5 = 3.0e-3, tc1 = 2.7e-3, tc2 = 7.0e-7 res.rdbreak n72 n5 = 1.71e-2, tc1 = -4.0e-4, tc2 = -1.55e-5 res.rdrain n50 n16 = 4.5e-3, tc1 = 1.16e-2, tc2 = 1.7e-5 res.rgate n9 n20 = 1.3 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10 res.rlsource n3 n7 = 10 res.rslc1 n5 n51 = 1e-6, tc1 = 3.96e-3, tc2 = 2.7e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.95e-3, tc1 = 1e-3, tc2 = 1e-5 res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 5.0e-7 res.rvthres n22 n8 = 1, tc1 = -2.8e-3, tc2 = -1.0e-5 MWEAK MMED CIN 71 11 16 6 RLGATE RDBODY DBREAK RDRAIN EVTEMP RGATE + 18 22 9 20 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 1.0e-9 l.lsource n3 n7 = 1.0e-9 k.kl i (l.lgate) i (l.lsource) = l (l.lgate), l (l.lsource), 0.0085 72 ISCL EVTHRES + 19 8 + LGATE RLDRAIN RDBREAK 50 6 8 ESG DRAIN 2 RSLC1 51 - c.ca n12 n8 = 1.8e-9 c.cb n15 n14 = 1.73e-9 c.cin n6 n8 = 1.19e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod LDRAIN 5 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 58.85 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 4.6)) } } (c)2005 Fairchild Semiconductor Corporation HUF75332P3 Rev. C0 HUF75332P3 SPICE Thermal Model th JUNCTION REV 11February 1999 HUF75332 CTHERM1 th 6 4.00e-3 CTHERM2 6 5 7.00e-3 CTHERM3 5 4 7.50e-3 CTHERM4 4 3 8.00e-3 CTHERM5 3 2 1.85e-2 CTHERM6 2 tl 12.55 RTHERM1 RTHERM1 th 6 7.09e-3 RTHERM2 6 5 1.77e-2 RTHERM3 5 4 4.97e-2 RTHERM4 4 3 2.79e-1 RTHERM5 3 2 4.21e-1 RTHERM6 2 tl 5.58e-2 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF75332 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 4.00e-3 ctherm.ctherm2 6 5 = 7.00e-3 ctherm.ctherm3 5 4 = 7.50e-3 ctherm.ctherm4 4 3 = 8.00e-3 ctherm.ctherm5 3 2 = 1.85e-2 ctherm.ctherm6 2 tl = 12.55 rtherm.rtherm1 th 6 = 7.09e-3 rtherm.rtherm2 6 5 = 1.77e-2 rtherm.rtherm3 5 4 = 4.97e-2 rtherm.rtherm4 4 3 = 2.79e-1 rtherm.rtherm5 3 2 = 4.21e-1 rtherm.rtherm6 2 tl = 5.58e-2 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl (c)2005 Fairchild Semiconductor Corporation CASE HUF75332P3 Rev. C0 HUF75332P3 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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