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FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
©2008 Fairchild Semiconductor Corporation
FDD3510H Rev. 1.4
www.fairchildsemi.com
1
FDD3510H
Dual N & P-Channel PowerTrench® MOSFET
N-Channel: 80V, 13.9A, 80mΩ P-Channel: -80V, -9.4A, 190mΩ
Features
Q1: N-Channel
Max rDS(on) = 80mΩ at VGS = 10V, ID = 4.3A
Max rDS(on) = 88mΩ at VGS = 6V, ID = 4.1A
Q2: P-Channel
Max rDS(on) = 190mΩ at VGS = -10V, ID = -2.8A
Max rDS(on) = 224mΩ at VGS = -4.5V, ID = -2.6A
100% UIL Tested
RoHS Compliant
General Description
These dual N and P- Channel enha ncement mode Pow er
MOSFETs ar e produ ced u sing Fa irchild Semiconductor ’s
advanced PowerT rench® process that has been especially
tailored to minimize on -state r esistance and yet maint ain
superior switching performance.
Applications
Inverter
H-Bridge
N-Channel P-Channel
D1 D2
S1
G1
S2
G2
Dual DPAK 4L
D1/D2
G2
S2
G1
S1
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Q1 Q2 Units
VDS Drain to Source Voltage 80 -80 V
VGS Gate to Source Voltage ±20 ±20 V
ID
Drain Current - Continuous TC = 25°C 13.9 -9.4
A - Continuous TA = 25°C 4.3 -2.8
- Pulsed 20 -10
PD
Power Dissipation for Single Operation TC = 25°C (Note 1) 35 32
W TA = 25°C (Note 1a) 3.1
TA = 25°C (Note 1b) 1.3
EAS Single Pulse Avalanche Energy (Note 3) 37 54 mJ
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJC Thermal Resistance, Junction to Case, Single Operation for Q1 (Note 1) 3.5 °C/W
RθJC Thermal Resistance, Junction to Case, Single Operation for Q2 (Note 1) 3.9
Device Marking Device Package Reel Size Tape Width Quantity
FDD3510H FDD3510H TO-252-4L 13” 16mm 2500 units
March 2015
FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
FDD3510H Rev. 1.4 www.fairchildsemi.com
2
Electrical Characteristics TJ = 25°C unless otherwise noted
Off Characteristic s
On Characteristics
Dynamic Characteristics
Switching Characteristics
Symbol Parameter Test Conditions Type Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID =250µA, VGS = 0V
ID = -250µA, VGS = 0V
Q1
Q2
80
-80
V
∆BVDSS
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250µA, referenced to 25°C
ID = -250µA, referenced to 25°C
Q1
Q2 84
-67 mV /°C
IDSS Zero Gate Voltage Drain Current VDS = 64V, VGS = 0V
VDS = -64V, VGS = 0V
Q1
Q2
1
-1 µA
IGSS Gate to Source Leakage Current VGS = ±20V, VDS = 0VQ1
Q2
±100
±100
nA
nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA
VGS = VDS, ID = -250µA
Q1
Q2
2.0
-1.0
2.6
-1.6
4.0
-3.0 V
∆VGS(th)
∆TJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250µA, referenced to 25°C
ID = -250µA, referenced to 25°C
Q1
Q2
-6.7
4.6 mV/°C
rDS(on) Static Drain to Source On Resistance
VGS = 10V, ID = 4.3A
VGS = 6.0V, ID = 4.1A
VGS = 10V, ID = 4.3A, TJ = 125°C
Q1
64
70
121
80
88
152 mΩ
VGS = -10V, ID = -2.8A
VGS = -4.5V, ID = -2.6A
VGS = -10V, ID = -2.8A, TJ = 125°C
Q2
153
184
259
190
224
322
gFS Forward Transconductance VDD = 10V, ID = 4.3A
VDD = -5V, ID = -2.8A
Q1
Q2
15
6.8 S
Ciss Input Capacitance Q1
VDS = 40V, VGS = 0V, f = 1MHZ
Q2
VDS = -40V, VGS = 0V, f = 1MHZ
Q1
Q2 600
660
800
880 pF
CossOutput Capacitance Q1
Q2
56
50
75
70 pF
CrssReverse Transfer Capacitance Q1
Q2
27
25
41
40 pF
RgGate Resistance f = 1MHz Q1
Q2
1.7
7.2 Ω
td(on) Turn-On Delay Time Q1
VDD = 40V, ID = 4.3A,
VGS = 10V, RGEN = 6Ω
Q2
VDD = -40V, ID = -2.8A,
VGS = -10V, RGEN = 6Ω
Q1
Q2 7
6
13
11 ns
trRise Time Q1
Q2 2
3
10
10 ns
td(off) Turn-Off Delay Time Q1
Q2 16
25
29
40 ns
tfFall Time Q1
Q2 2
5
10
10 ns
Qg(TOT) Total Gate Charge Q1
VGS = 10V, VDD = 40V, ID = 4.3A
Q2
VGS = -10V, VDD = -40V, ID = -2.8A
Q1
Q2
13
14
18
20 nC
Qgs Gate to Source Charge Q1
Q2 2.3
1.9 nC
Qgd Gate to Drain “Miller” Charge Q1
Q2 3.2
2.9 nC
FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
FDD3510H Rev. 1.4 www.fairchildsemi.com
3
Electrical Characteristics TJ = 25°C unless otherwise noted
Drain-Source Diode Characteristics
Notes:
1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined
by the user's board design.
2. Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
3. Starting TJ = 25°C, N-ch: L = 3mH, IAS = 5A, VDD = 80V, VGS = 10V; P-ch: L = 3mH, IAS = -6A, VDD = -80V, VGS = -10V.
Symbol Parameter Test Conditions Type Min Typ Max Units
VSD Source to Drain Diode Forward Voltage VGS = 0V, IS = 2.6A (Note 2)
VGS = 0V, IS = -2.6A (Note 2)
Q1
Q2 0.8
-0.8
1.2
-1.2 V
trr Reverse Recovery Time Q1
IF = 4.3A, di/dt = 100A/s
Q2
IF = -2.8A, di/dt = 100A/s
Q1
Q2
29
30
46
48 ns
Qrr Reverse Recovery Charge Q1
Q2 28
30
45
48 nC
a. 40°C/W when mounted on
a 1 in2 pad of 2 oz copper
b. 96°C/W when mounted on a
minimum pad of 2 oz copper
b. 96°C/W when mounted on a
minimum pad of 2 oz copper
Q1
Q2
Scale 1 : 1 on letter size paper
Scale 1 : 1 on letter size paper
a. 40°C/W when mounted on
a 1 in2 pad of 2 oz copper
FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
FDD3510H Rev. 1.4 www.fairchildsemi.com
4
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
Figure 1.
01234
0
5
10
15
20
VGS = 3.5V
VGS = 6V
PULSE DU RATION = Xµs
DUTY CYCLE = X%MAX
VGS = 4.5V
VGS = 4V
VGS = 10V
ID, DRAIN CURRENT (A )
VDS, DRAIN TO SOURCE VOLTAGE (V)
On Region Characteristics Figure 2.
05 10 15 20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 VGS = 3.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5%MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT(A)
VGS = 4V
VGS = 4.5V
VGS = 6V
VGS = 10V
Norma lized On-Resistance
vs Drain Current and Gate Voltage
Figure 3. Normalized On Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
ID = 4.3A
VGS = 10V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEM PER ATURE (oC)
vs Junction Te mperature Figure 4.
2468
10
0
100
200
300
TJ = 125oC
ID = 4.3A
TJ = 25oC
VGS, GATE TO S O U R C E VO L TAGE (V)
rDS(on), DRAIN TO
SOURCE ON-RESISTANCE (mΩ)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5%MAX
On-Resistance vs Gate to
Source Voltage
Figure 5. Transfer Characteristics
23456
0
5
10
15
20
TJ = 150oC
VDS = 5V
PULSE DUR ATION = 80µs
DUTY CYCLE = 0.5%MAX
TJ = -55oC
TJ = 25oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
20
TJ = -55oC
TJ = 25oC
TJ = 150oC
VGS = 0V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs Source Current
FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
FDD3510H Rev. 1.4 www.fairchildsemi.com
5
Figure 7.
02468101214
0
2
4
6
8
10
ID = 4.3A
VDD = 50V
VDD = 30V
VGS, GATE TO SOURCE VOLTAGE(V)
Qg, GATE CHARGE(nC)
VDD = 40V
Gate Charge Characteristics Figure 8.
0.1 1 10 100
10
100
1000
f = 1MHz
VGS = 0V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
Capa cit ance vs Dr ain
to Source Voltage
Figure 9.
0.01 0.1 1 10
1
2
3
4
5
TJ = 25oC
TJ = 125oC
tAV, TIME IN AVALANCHE(ms)
IAS, AVALANCHE CURRENT(A)
Un cl amped In du ct ive
Switching Capability Figure 10.
25 50 75 100 125 150
0
3
6
9
12
15
VGS = 6V
RθJC = 3.5oC/W
VGS = 10V
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
Maximum Continuous Drain
Current vs Case Temperature
Figure 11. Forward Bias Safe
Operating Area
0.5 1 10 100
0.05
0.1
1
10
50
DC
100ms
10ms
1ms
100us
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 3.5oC/W
TC = 25oC
Figure 12.
10-6 10-5 10-4 10-3 10-2 10-1 1
10
102
103
104
105
SINGLE PULSE
RθJC = 3.5oC/W
TC = 25oC
VGS = 10V
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Single Pulse Maximum
Power Dissipation
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
FDD3510H Rev.1 .4 www.fairchildsemi.com
6
Figure 13. Transient Thermal Response Cu rve
10-6 10-5 10-4 10-3 10-2 10-1 1
0.001
0.01
0.1
1
SINGLE PULSE
RθJC = 3.5oC/W
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJC
t, RECTANGULA R PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
2
PDM
t1t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJc + TC
Figure 14.
10-4 10-3 10-2 10-1 110
100 1000
0.001
0.01
0.1
1
SINGLE PULSE
RθJA = 96oC/W
(Note 1b)
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
2
PDM
t1t2
NOTES:
DUTY FACTO R : D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
Transient Thermal Response Curve
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
FDD3510H Rev. 1.4 www.fairchildsemi.com
7
Typical Characteristics (Q2 P-Channel) TJ = 25°C unless otherwise noted
Figure 15 . O n- R egion Characteristics Figure 16. Normalized on-Resistance vs Drain
Current and Gate Voltage
Figure 17. Normalized On-Resistance
vs Junction Temperature Figure 18. On-Resistance vs Gate to
Source Voltage
Figure 19. Transfer Characteristics Figure 20. Source to Drain Diode
Forward Voltage vs Source Current
012345
0
2
4
6
8
10
VGS = -3V
VGS = -4.5V
PULSE DUR ATION = 80µs
DUTY CYCLE = 0.5%MAX
VGS = -3 .5V
VGS = - 2.5V
VGS = -10V
-ID, DRAIN CURRENT (A)
-VDS, DRAIN TO SOURCE VOLTAGE (V) 0246810
0.5
1.0
1.5
2.0
2.5
VGS = -3.5V
VGS = -3V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
-ID, DRAIN CURRENT(A)
VGS = -4.5V
VGS = - 2.5V
VGS = -10V
-75 -50 -25 0 25 50 75 100 125 150
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ID = - 2 .8A
VGS = -10V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)246810
100
200
300
400
500
600
PULSE DU RATION = 80µs
DUTY CYCLE = 0.5%MAX
TJ = 125oC
TJ = 25oC
ID = -2.8A
rDS(on), DRAIN TO
SOURCE ON- RESISTANCE (mΩ)
-VGS, GATE TO SOURC E V O L TAGE (V )
12345
0
2
4
6
8
10
VDS = -5V
PULSE DU RATION = 80µs
DUTY CYCLE = 0.5%MAX
TJ = -55oC
TJ = 25oC
TJ = 150oC
-ID, DRAIN CURRENT (A)
-VGS, GA TE TO S O URC E V OLTAGE (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
TJ = -55oC
TJ = 25oC
TJ = 150oC
VGS = 0V
-IS, REVERSE DRAIN CURRENT (A)
-VSD, BODY DIODE FORWARD VOLTAGE (V)
FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
FDD3510H Rev. 1.4 www.fairchildsemi.com
8
Typical Characteristics (Q2 P-Channel)TJ = 25°C unless otherwise noted
Figure 21. Gate Charge Characteristics Figure 22. Capacitance vs Drain
to Source Voltage
Figure 23. Unc lamped Inductive
Switching Capability Figure 24. Maximum Continuous Drain
Current vs Case Temperature
Figure 25. Forward Bias Safe
Operating Area Figure 26. Single Pulse Maximum Power
Dissipation
0246810121416
0
2
4
6
8
10
ID = -2.8A
VDD = -50V
VDD = -30V
-VGS, GATE TO SOUR CE VOL TAGE(V)
Qg, GATE CHARGE(nC)
VDD = -40V
0.1 1 10 100
10
100
1000
f = 1MH z
VGS = 0V
CAPACITAN CE (pF)
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Crss
Coss
Ciss
0.1 1 10
1
2
3
4
TJ = 25oC
TJ = 125oC
tAV, TIME IN AVALANCHE(ms)
-IAS, AVALANCHE CURRENT(A)
25 50 75 100 125 150
0
2
4
6
8
10
RθJC = 3.9oC/W
VGS = -4.5V
VGS = -10V
-ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
11
0100200
0.05
0.1
1
10
20
100ms
DC
10ms
1ms
100us
TH IS ARE A IS
LIMITED BY rds(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 3.9oC/W
TC = 25oC
-ID, DRAIN CURRENT (A)
-VDS, DRAIN to SOURCE VOLTAGE (V)
I = I
25
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
XTx
–
125
-------------------
T
X
= 25
o
C
10-6 10-5 10-4 10-3 10-2 10-1 1
10
100
1000
10000
20000
VGS = -10V
SINGLE P ULS E
RθJC = 3.9oC/W
P(PK), PEAK TRANSIENT POW ER (W )
t, PULSE WIDTH (s)
Typical Characteristics (Q2 P-Channel)TJ = 25°C unless otherwise noted
Figure 27. Transient Thermal Response Curve
10-6 10-5 10-4 10-3 10-2 10-1 1
0.001
0.01
0.1
1
2
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJC
t, RECTANGULA R PULSE DURATION (s)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
SINGLE PULSE
RθJC = 3.9oC/W
PDM
t1t2
NOTES:
DUTY FACTO R : D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
Figure 28. T ransient Thermal Response Curve
10-4 10-3 10-2 10-1 11
0
100 1000
0.001
0.01
0.1
1
SINGLE PULSE
RθJA = 96oC/W
(Note 1b)
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.0 5
0.0 2
0.0 1
2
PDM
t1t2
NOTES:
DUTY FACTO R : D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
FDD3510H Dual N & P-Channel PowerTrench ® MOSFET
FDD3510H Rev. 1.4 www.fairchildsemi.com
9
6.00
MIN
6.50
MIN
0.80
MIN
1.14
4.56
6.25
3.00
MIN
4.32
MIN
5.21
MIN
SEE
NOTE D
0.61
0.46
2.39
2.18
10.41
9.40
SEE DETAIL "A"
0.10
C
C
5.46
5.21
1.25
1.15
1.01
0.64
6.22
5.97
0.68
0.70
0.55 1.14
4.56
6.73
6.35
0.81
0.61
F
0.10
M
C
A B
0.10
M
C
A B
A
B
0.61
0.46
(
2.82
)
F
0-10°
0.127
MAX
0.51
1.78
1.40
DETAIL A
SCALE 2:1
SEATING PLANE
GAGE PLANE
NOTES: UNLESS OTHERWISE SPECIFED
A. THIS PACKAGE CONFORMS TO JEDEC, TO252
VARIATION AD.
B. ALL DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS
D. HEATSINK TOP EDGE COULD BE IN CHAMFERED
CORNERS OR EDGE PROTRUSION.
E. DIMENSIONS AND TOLERANCES AS PER ASME
Y14.5-2009.
F
EXCEPTION TO TO-252 STANDARD.
G. FILE NAME: TO252B05REV3
H. FAIRCHILDSEMICONDUCTOR
15
51
www.onsemi.com
1
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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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