MC74LCX74DTG - ON Semiconductor

July, 2012 − Rev. 7

1Publication Order Number:

MC74LCX74/D

MC74LCX74

Low-Voltage CMOS Dual

D-Type Flip-Flop

With 5 V−Tolerant Inputs

The MC74LCX74 is a high performance, dual D−type flip−flop

with asynchronous clear and set inputs and complementary (O, O)

outputs. It operates from a 2.3 to 3.6 V supply. High impedance TTL

compatible inputs significantly reduce current loading to input drivers

while TTL compatible outputs offer improved switching noise

performance. A VI specification of 5.5 V allows MC74LCX74 inputs

to be safely driven from 5.0 V devices.

The MC74LCX74 consists of 2 edge−triggered flip−flops with

individual D−type inputs. The flip−flop will store the state of

individual D inputs, that meet the setup and hold time requirements, on

the LOW−to−HIGH Clock (CP) transition.

Features

•Designed for 2.3 V to 3.6 V VCC Operation

•5.0 V Tolerant Inputs − Interface Capability With 5.0 V TTL Logic

•LVTTL Compatible

•LVCMOS Compatible

•24 mA Balanced Output Sink and Source Capability

•Near Zero Static Supply Current in All Three Logic States (10 mA)

Substantially Reduces System Power Requirements

•Latchup Performance Exceeds 500 mA

•ESD Performance: Human Body Model >2000 V

Machine Model >200 V

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

MARKING

DIAGRAMS

TSSOP−14

DT SUFFIX

CASE 948G

SOIC−14

D SUFFIX

CASE 751A

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

LCX74G

AWLYWW

LCX

ALYWG

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74LCX74

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Figure 1. Pinout: 14−Lead (Top View)

1314 12 11 10 9 8

21 34567

VCC CD2 D2 CP2 SD2O2 O2

CD1 D1 CP1 SD1O1 O1 GND

Figure 2. Logic Diagram

SD1

D1 D

CP1 CP

CD1 1

SD2

D2 D

CP2 CP

CD2 13

PIN NAMES

Pins Function

CP1, CP2 Clock Pulse Inputs

D1−D2 Data Inputs

CD1, CD2Direct Clear Inputs

SD1, SD2Direct Set Inputs

On−On Outputs

TRUTH TABLE

Inputs Outputs

SDn CDn CPn Dn On On Operating Mode

L H X X H L Asynchronous Set

H L X X L H Asynchronous Clear

L L X X H H Undetermined

H H ↑h H L

Load and Read Register

H H ↑l L H

H H ↑X NC NC Hold

H = High Voltage Level

h = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition

L = Low Voltage Level

l = Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition

NC = No Change

X = High or Low Voltage Level and Transitions are Acceptable

↑= Low−to−High Transition

↑= Not a Low−to−High Transition

For ICC reasons, DO NOT FLOAT Inputs

MC74LCX74

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MAXIMUM RATINGS

Symbol Parameter Value Condition Units

VCC DC Supply Voltage −0.5 to +7.0 V

VIDC Input Voltage −0.5 ≤ VI ≤ +7.0 V

VODC Output Voltage −0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State (Note 1) V

IIK DC Input Diode Current −50 VI < GND mA

IOK DC Output Diode Current −50 VO < GND mA

+50 VO > VCC mA

IODC Output Source/Sink Current ±50 mA

ICC DC Supply Current Per Supply Pin ±100 mA

IGND DC Ground Current Per Ground Pin ±100 mA

TSTG Storage Temperature Range −65 to +150 °C

MSL Moisture Sensitivity Level 1

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

1. IO absolute maximum rating must be observed.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Type Max Units

VCC Supply Voltage

Operating

Data Retention Only

2.0

1.5

2.5, 3.3

3.6

VIInput Voltage 0 5.5 V

VOOutput Voltage (HIGH or LOW State) 0 VCC V

IOH HIGH Level Output Current

VCC = 3.0 V − 3.6 V

VCC = 2.7 V − 3.0 V

VCC = 2.3 V − 2.7 V

−24

−12

−8

IOL LOW Level Output Current

VCC = 3.0 V − 3.6 V

VCC = 2.7 V − 3.0 V

VCC = 2.3 V − 2.7 V

+24

+12

TAOperating Free−Air Temperature −40 +85 °C

Dt/DVInput Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V

ORDERING INFORMATION

Device Package Shipping†

MC74LCX74DG SOIC−14

(Pb−Free)

55 Units / Rail

MC74LCX74DR2G SOIC−14

(Pb−Free)

2500 Tape & Reel

MC74LCX74DTG TSSOP−14

(Pb−Free)

96 Units / Rail

MC74LCX74DTR2G TSSOP−14

(Pb−Free)

2500 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC74LCX74

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DC ELECTRICAL CHARACTERISTICS

TA = −40°C to +85°C

Symbol Characteristic Condition Min Max Units

VIH HIGH Level Input Voltage (Note 2) 2.3 V ≤ VCC ≤ 2.7 V 1.7 V

2.7 V ≤ VCC ≤ 3.6 V 2.0

VIL LOW Level Input Voltage (Note 2) 2.3 V ≤ VCC ≤ 2.7 V 0.7 V

2.7 V ≤ VCC ≤ 3.6 V 0.8

VOH HIGH Level Output Voltage 2.3 V ≤ VCC ≤ 3.6 V; IOH = −100 mAVCC −0.2 V

VCC = 2.3 V; IOH = −8 mA 1.8

VCC = 2.7 V; IOH = −12 mA 2.2

VCC = 3.0 V; IOH = −18 mA 2.4

VCC = 3.0 V; IOH = −24 mA 2.2

VOL LOW Level Output Voltage 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA0.2 V

VCC = 2.3 V; IOL = 8 mA 0.6

VCC = 2.7 V; IOL = 12 mA 0.4

VCC = 3.0 V; IOL = 16 mA 0.4

VCC = 3.0 V; IOL = 24 mA 0.55

IOFF Power Off Leakage Current VCC = 0, VIN = 3.6 V or VOUT = 3.6 V 10 mA

IIN Input Leakage Current VCC = 0 to 3.6 V, VIN = 3.6 V or GND ±5mA

ICC Quiescent Supply Current VCC = 3.6 V, VIN = 3.6 V or VOUT = 3.6 V 10 mA

DICC Increase in ICC per Input 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 mA

2. These values of VI are used to test DC electrical characteristics only.

AC CHARACTERISTICS tR = tF = 2.5 ns; RL = 500 W

Limits

TA = −40°C to +85°C

VCC = 3.3 V + 0.3 V VCC = 2.7 V VCC = 2.5 V + 0.2 V

CL = 50 pF CL = 50 pF CL = 30 pF

Symbol Parameter Waveform Min Max Min Max Min Max Units

fmax Clock Pulse Frequency 1 150 150 150 MHz

tPLH

tPHL

Propagation Delay

CPn to On or On

1 1.5

1.5

7.0

1.5

8.0

1.5

8.4

tPLH

tPHL

Propagation Delay

SDn or CDn to On or On

2 1.5

1.5

7.0

1.5

8.0

1.5

8.4

tsSetup Time,

HIGH or LOW Dn to CPn

1 2.5 2.5 4.0 ns

thHold Time, HIGH or LOW Dn to CPn 1 1.5 1.5 2.0 ns

twCPn Pulse Width, HIGH or LOW

SDn or CDn Pulse Width, LOW

4 3.3

3.3

3.6

4.0

trec Recovery Time SDn or CDn to CPn 3 2.5 3.0 4.5 ns

tOSHL

tOSLH

Output−to−Output Skew (Note 3) 1.0

1.0

3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.

The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter

guaranteed by design.

MC74LCX74

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DYNAMIC SWITCHING CHARACTERISTICS

TA = +25°C

Symbol Characteristic Condition Min Typ Max Units

VOLP Dynamic LOW Peak Voltage

(Note 4)

VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V

VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V

0.8

0.6

VOLV Dynamic LOW Valley Voltage

(Note 4)

VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V

VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V

−0.8

−0.6

4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is

measured in the LOW state.

CAPACITIVE CHARACTERISTICS

Symbol Parameter Condition Typical Units

CIN Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF

COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF

CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 25 pF

Figure 3. AC Waveforms

WAVEFORM 2 − PROPAGATION DELAYS

tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns

Vcc

0 V

SDn

CDn1.5 V

Vcc

0 V

VOH

Vmo

VOL

Vmo

tPLH tPHL

tPHL

tPLH

WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES

tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns

Vcc

0 V

CPn

Vmi

On,

Vcc

0 V

VOH

VOL

tPLH, tPHL

Vmi

Vmo

fmax

MC74LCX74

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WAVEFORM 4 − PULSE WIDTH

tR = tF = 2.5 ns (or fast as required) from 10% to 90%;

Output requirements: VOL ≤ 0.8 V, VOH ≥ 2.0 V

Vcc

0 V

Vcc

0 V

Vmi

CPn

SDn, CDn, CPn

trec

WAVEFORM 3 − RECOVERY TIME

tR = tF = 2.5 ns from 10% to 90%; f = 1 MHz; tw = 500 ns

Vcc

0 V

Vcc

0 V

Vmi

SDn, CDn

CPn

Vcc

Symbol 3.3 V + 0.3 V 2.7 V 2.5 V + 0.2 V

Vmi 1.5 V 1.5 V Vcc/2

Vmo 1.5 V 1.5 V Vcc/2

Figure 3. AC Waveforms (Continued)

PULSE

GENERATOR

DUT

VCC

CL= 50 pF at VCC = 3.3 ± 0.3 V or equivalent (includes jig and probe capacitance)

CL= 30 pF at VCC = 2.5 ± 0.2 V or equivalent (includes jig and probe capacitance)

RL= R1 = 500 W or equivalent

RT= ZOUT of pulse generator (typically 50 W)

Figure 4. Test Circuit

MC74LCX74

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PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

ÉÉÉ

DETAIL E

−W−

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

−V−

14X REFK

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

MC74LCX74

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PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

14 8

0.25 B M

X 45

SEATING

PLANE

0.25 B S

13X

DETAIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

__ __

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

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PUBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

MC74LCX74/D

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