DOCUMENT NUMBER
9S12DT128BDGV1/D
MC9S12DT128B
Device User Guide
V01.09
Covers also
MC9S12DG128B, MC9S12DJ128B,
MC9S12DB128B
Original Release Date: 18 June 2001
Revised: 31 October 2002
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC9S12DT128B Device User Guide — V01.09
Revision History
Version
Number Revision
Date Effective
Date Author Description of Changes
V01.00 18 Jun
2001 18 June
2001 Initial version (parent doc v2.03 dug for dp256).
V01.01 23 July
2001 23 July
2001 Updated version after review
V01.02 23 Sep
2001 23 Sep
2001
Changed Partname, added pierce mode, updated electrical
characteristics
some minor corrections
V01.03 12 Oct
2001 12 Oct
2001 Replaced Star12 by HCS12
V01.04 27 Feb
2002 27 Feb
2002
Updated electrical spec after MC-Qualification (IOL/IOH), Data for
Pierce, NVM reliability
New document numbering. Corrected Typos
V01.05 4 Mar
2002 4 Mar
2002 Increased VDD to 2.35V, removed min. oscillator startup
Removed Document order number except from Cover Sheet
V01.06 8 July
2002 22 July
2002
Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
V01.07 16 Aug
2002 16 Aug
2002 Minor corrections in table 1-1 & section 1.5.1
V01.08 12 Sep
2002 12 Sep
2002 Corrected register address mismatches in section 1.5.1
V01.09 31 Oct
2002 31 Oct
2002
Removed document order no. from Revision History page
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing CAN1,
BDLC, IIC and/or Byteflight
Added oscillator clock connection to BDM in S12_CORE in fig 3-1
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Corrected several register and bit names in “Local Enable” column
of Table 5.1 Interrupt Vector Locations.
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC9S12DT128B Device User Guide — V01.09
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC9S12DT128B Device User Guide — V01.09
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MC9S12DT128B Device User Guide — V01.09
Table of Contents
Section 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.1 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Section 2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.3 TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .55
2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .56
2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.15 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.17 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.18 PE1 / IRQ — Port E Input Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.19 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.20 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
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MC9S12DT128B Device User Guide — V01.09
2.3.21 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.22 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.23 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.25 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.26 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.27 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.30 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.31 PK7 / ECS / ROMCTL — Port K I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.32 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.33 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.34 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . .60
2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . . . .61
2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . .61
2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . . . .61
2.3.39 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.40 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.41 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.43 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.44 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.45 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.46 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.47 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.48 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.49 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.50 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.3.51 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.52 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.53 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.54 PS2 / RXD1 — Port S I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.55 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.3.56 PS0 / RXD0 — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
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MC9S12DT128B Device User Guide — V01.09
2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . . . .64
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
64
2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .65
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.4.7 VREGEN — On Chip Voltage Regulator Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Section 3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Section 5 Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Section 6 HCS12 Core Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
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MC9S12DT128B Device User Guide — V01.09
Section 7 Clock and Reset Generator (CRG) Block Description . . . . . . . . .77
7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Section 8 Enhanced Capture Timer (ECT) Block Description. . . . . . . . . . . .77
Section 9 Analog to Digital Converter (ATD) Block Description. . . . . . . . . .77
Section 10 Inter-IC Bus (IIC) Block Description . . . . . . . . . . . . . . . . . . . . . . .77
Section 11 Serial Communications Interface (SCI) Block Description. . . . .77
Section 12 Serial Peripheral Interface (SPI) Block Description . . . . . . . . . .78
Section 13 J1850 (BDLC) Block Description. . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 14 Byteflight (BF) Block Description . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 15 Pulse Width Modulator (PWM) Block Description. . . . . . . . . . . .78
Section 16 Flash EEPROM 128K Block Description . . . . . . . . . . . . . . . . . . .78
Section 17 EEPROM 2K Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . .78
Section 18 RAM Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Section 19 MSCAN Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Section 20 Port Integration Module (PIM) Block Description . . . . . . . . . . . .79
Section 21 Voltage Regulator (VREG) Block Description . . . . . . . . . . . . . . .79
Section 22 Printed Circuit Board Layout Proposal . . . . . . . . . . . . . . . . . . . .80
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
A.1.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
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MC9S12DT128B Device User Guide — V01.09
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.3 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Appendix B Package Information
B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
B.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
B.3 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
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List of Figures
Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 1-1 MC9S12DT128B Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 1-2 MC9S12DT128B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128B,
MC9S12DJ128B, MC9S12DB128B50
Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128B, MC9S12DJ128B Bondout . .51
Figure 2-3 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 2-4 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 2-5 Pierce Oscillator Connections (PE7=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 2-6 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .81
Figure 22-2 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .82
Figure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .83
Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .84
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure A-2 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure A-3 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure A-4 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure A-6 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-8 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 22-5 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . .122
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MC9S12DT128B Device User Guide — V01.09
List of Tables
Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 0-2 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
$0000 - $000F MEBI map 1 of 3 (Core User Guide) ........................................................24
$0010 - $0014 MMC map 1 of 4 (Core User Guide) ........................................................24
$0015 - $0016 INT map 1 of 2 (Core User Guide) ...........................................................25
$0017 - $0017 MMC map 2 of 4 (Core User Guide) ........................................................25
$0018 - $001B Miscellaneous Peripherals (Device User Guide, Table 1-3) ....................25
$001C - $001D MMC map 3 of 4 (Core and Device User Guide, Table 1-4) ...................25
$001E - $001E MEBI map 2 of 3 (Core User Guide) ........................................................25
$001F - $001F INT map 2 of 2 (Core User Guide) ...........................................................25
$0020 - $0027 Reserved ..................................................................................................26
$0028 - $002F BKP (Core User Guide) ...........................................................................26
$0030 - $0031 MMC map 4 of 4 (Core User Guide) ........................................................26
$0032 - $0033 MEBI map 3 of 3 (Core User Guide) ........................................................26
$0034 - $003F CRG (Clock and Reset Generator) ..........................................................27
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) .................................27
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ..............................30
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................31
$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................33
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................33
$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................34
$00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................34
$00E8 - $00EF BDLC (Byte Level Data Link Controller J1850) ........................................35
$00F0 - $00F7 SPI1 (Serial Peripheral Interface) ............................................................35
$00F8 - $00FF Reserved ..................................................................................................35
$0100 - $010F Flash Control Register (fts128k2) ............................................................36
$0110 - $011B EEPROM Control Register (eets2k) ........................................................36
$011C - $011F Reserved for RAM Control Register ........................................................37
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................37
$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ..............................................38
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .39
$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) ..............................................40
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$01C0 - $01FF Reserved ..................................................................................................41
$0200 - $023F Reserved ..................................................................................................41
$0240 - $027F PIM (Port Integration Module) ..................................................................42
$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ..............................................44
$02C0 - $02FF Reserved ..................................................................................................45
$0300 - $035F Byteflight ..................................................................................................45
$0360 - $03FF Reserved ..................................................................................................47
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 2-2 MC9S12DT128B Power and Ground Connection Summary. . . . . . . . . . . . . . . . .63
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 22-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table A-13 Voltage Regulator Recommended Load Capacitances. . . . . . . . . . . . . . . . . . . .103
Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table A-18 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
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MC9S12DT128B Device User Guide — V01.09
Derivative Differences and Document References
Derivative Differences
Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the
compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.
The following figure provides an ordering number example for the MC9S12D128B devices.
Figure 0-1 Order Partnumber Example
The following items should be considered when using a derivative.
• Registers
– Do not write or read CAN1 registers (after reset: address range $0180 - $01BF), if using a
derivative without CAN1 (see Table 0-1).
Table 0-1 Derivative Differences1
NOTES:
1. ✓: Available for this device, ✕: Not available for this device
Modules MC9S12DT128B MC9S12DG128B MC9S12DJ128B MC9S12DB128B
# of CANs 3 2 2 2
CAN4 ✓✓✓✓
CAN1 ✓✕✕✕
CAN0 ✓✓✓✓
J1850/BDLC ✕✕ ✓ ✕
IIC ✓✓ ✓ ✕
Byteflight ✕✕ ✕ ✓
Package 112 LQFP 112 LQFP/80 QFP 112 LQFP/80 QFP 112 LQFP
Package
Code PV PV/FU PV/FU PV
Mask set L85D L85D L85D L85D
Temp Options M, V, C M, V, C M, V, C M, V, C
Notes An errata exists
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MC9S12 DJ128B C FU Package Option
Temperature Option
Device Title
Controller Family
Temperature Options
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Options
FU = 80QFP
PV = 112LQFP
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– Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a
derivative without BDLC (see Table 0-1).
– Do not write or read IIC registers (after reset: address range $00E0 - $00E7), if using a
derivative without IIC (see Table 0-1).
– Do not write or read Byteflight registers (after reset: address range $0300 - $035F), if using a
derivative without Byteflight registers (see Table 0-1).
• Interrupts
– Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for
unused interrupts, if using a derivative without CAN1 (see Table 0-1).
– Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused
interrupts, if using a derivative without BDLC (see Table 0-1).
– Fill the IIC interrupt vector ($FFC0, $FFC1) according to your coding policies for unused
interrupts, if using a derivative without IIC (see Table 0-1).
– Fill the four Byteflight interrupt vectors ($FFA0 - $FFA7) according to your coding policies for
unused interrupts, if using a derivative without Byteflight (see Table 0-1).
• Ports
– The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if
using a derivative without CAN1 (see Table 0-1).
– The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a
derivative without BDLC (see Table 0-1).
– The IIC pin functionality (SCL, SCA) is not available on port PJ7 and PJ6, if using a derivative
without IIC (see Table 0-1).
– The Byteflight pin functionality (BF_PSLM, BF_PERR, BF_PROK, BF_PSYN, TX_BF,
RX_BF) is not available on port PM7, PM6, PM5, PM4, PM3 and PM2, if using a derivative
without Byteflight (see Table 0-1).
• Pins not available in 80 pin QFP package
–Port H
In order to avoid floating nodes the ports should be either configured as outputs by setting the
data direction register (DDRH at Base+$0262) to $FF, or enabling the pull resistors by writing
a $FF to the pull enable register (PERH at Base+$0264).
–Port J[1:0]
PortJpull-upresistorsare enabled out of reset on all four pins (7:6 and 1:0).Thereforecaremust
be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at
Base+$026C.
–Port K
Port K pull-up resistors are enabled out of reset, i.e. Bit 7 = PUKE = 1 in the register PUCR at
Base+$000C. Therefore care must be taken not to clear this bit.
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MC9S12DT128B Device User Guide — V01.09
–Port M[7:6]
PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–Port P6
PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input.
–Port S[7:4]
PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating
inputs.
–PAD[15:8] (ATD1 channels)
Out of reset the ATD1 is disabled preventing current flows in the pins. Do not modify the ATD1
registers!
Document References
The Device User Guide provides information about the MC9S12DT128B device made up of standard
HCS12 blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In a effort
to reduce redundancy all module specific information is located only in the respective Block User Guide.
If applicable, special implementation details of the module are given in the block description sections of
this document.
See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-2 Document References
User Guide Version Document Order Number
HCS12_V1.5 Core User Guide 1.2 HCS12COREUG
Clock and Reset Generator (CRG) Block User Guide V03 S12CRGV3/D
Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User Guide V01 S12ECT16B8CV1/D
Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User Guide V02 S12ATD10B8CV2/D
Inter IC Bus (IIC) Block User Guide V02 S12IICV2/D
Asynchronous Serial Interface (SCI) Block User Guide V02 S12SCIV2/D
Serial Peripheral Interface (SPI) Block User Guide V02 S12SPIV2/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide V01 S12PWM8B8CV1/D
128K Byte Flash (FTS128K) Block User Guide V01 S12FTS128KV1/D
2K Byte EEPROM (EETS2K) Block User Guide V01 S12EETS2KV1/D
Byte Level Data Link Controller -J1850 (BDLC) Block User Guide V01 S12BDLCV1/D
Motorola Scalable CAN (MSCAN) Block User Guide V02 S12MSCANV2/D
Voltage Regulator (VREG) Block User Guide V01 S12VREGV1/D
Port Integration Module (PIM_9DT128) Block User Guide V01 S12PIMDT128V1/D
Byteflight (BF) Block User Guide V01 S12BFV1/D
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MC9S12DT128B Device User Guide — V01.09
Section 1 Introduction
1.1 Overview
The MC9S12DT128B microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K
bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link
Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital
I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules
(MSCAN12), a Byteflight module and an Inter-IC Bus. The MC9S12DT128B has full 16-bit data paths
throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory
can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and
performance to be adjusted to suit operational requirements.
1.2 Features
• HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.20-bit ALU
iv.Instruction queue
v. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– BDM (Background Debug Mode)
• CRG (Clock and Reset Generator)
– Choice of low current Colpitts oscillator or standard Pierce Oscillator
– PLL
– COP watchdog
– real time interrupt
– clock monitor
• 8-bit and 4-bit ports with interrupt functionality
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MC9S12DT128B Device User Guide — V01.09
– Digital filtering
– Programmable rising or falling edge trigger
• Memory
– 128K Flash EEPROM
– 2K byte EEPROM
– 8K byte RAM
• Two 8-channel Analog-to-Digital Converters
– 10-bit resolution
– External conversion trigger capability
• Three 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Enhanced Capture Timer
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Two 8-bit or one 16-bit pulse accumulators
• 8 PWM channels
– Programmable period and duty cycle
– 8-bit 8-channel or 16-bit 4-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
• Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Two Synchronous Serial Peripheral Interface (SPI)
– Byteflight
• Byte Data Link Controller (BDLC)
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MC9S12DT128B Device User Guide — V01.09
• SAE J1850 Class B Data Communications Network Interface
– Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in
Automotive Applications
• Inter-IC Bus (IIC)
– Compatible with I2C Bus standard
– Multi-master operation
– Software programmable for one of 256 different serial clock frequencies
• 112-Pin LQFP and 80-Pin QFP package options
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
– Operation at 50MHz equivalent to 25MHz Bus Speed
– Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
1.3 Modes of Operation
User modes
• Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
• Special Operating Modes
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
Low power modes
• Stop Mode
• Pseudo Stop Mode
• Wait Mode
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MC9S12DT128B Device User Guide — V01.09
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12DT128B device.
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MC9S12DT128B Device User Guide — V01.09
Figure 1-1 MC9S12DT128B Block Diagram
128K Byte Flash EEPROM
8K Byte RAM
Enhanced Capture
RESET
EXTAL
XTAL
VDD1,2
VSS1,2
SCI0
2K Byte EEPROM
BKGD
R/W
MODB
XIRQ
NOACC/XCLKS
System
Integration
Module
(SIM)
VDDR
CPU12
Periodic Interrupt
COP Watchdog
Clock Monitor
Single-wire Background
Breakpoints
PLL
VSSPLL
XFC
VDDPLL
Multiplexed Address/Data Bus
VDDA
VSSA
VRH
VRL
ATD0
Multiplexed
Wide Bus
Multiplexed
VDDX
VSSX
Internal Logic 2.5V
Narrow Bus
PPAGE
V
DDPLL
VSSPLL
PLL 2.5V
IRQ
LSTRB
ECLK
MODA
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
TEST
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR15
ADDR14
ADDR13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA15
DATA14
DATA13
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ADDR7
ADDR6
ADDR5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD03
PAD04
PAD05
PAD06
PAD07
PAD00
PAD01
PAD02
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3
IOC4
IOC5
PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
VRH
VRL
VDDA
VSSA
VRH
VRL
ATD1
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD11
PAD12
PAD13
PAD14
PAD15
PAD08
PAD09
PAD10
VDDA
VSSA
RXD
TXD
MISO
MOSI
PS3
PS4
PS5
PS0
PS1
PS2
SCI1 RXD
TXD
PWM2
PWM6
PWM0
PWM7
PWM1
PWM3
PWM4
PWM5
PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
PIX2
PIX0
PIX1
PIX3
ECS
PK3
PK7
PK0
PK1
XADDR17
ECS
XADDR14
XADDR15
XADDR16
SCK
SS PS6
PS7
SPI0
IIC SDA
SCL PJ6
PJ7
CAN0 RxCAN
TxCAN PM1
PM0
CAN1 RxCAN
TxCAN PM2
PM3
PM4
PM5
PM6
PM7
KWH2
KWH6
KWH0
KWH7
KWH1
KWH3
KWH4
KWH5
PH3
PH4
PH5
PH6
PH7
PH0
PH1
PH2
KWJ0
KWJ1 PJ0
PJ1
I/O Driver 5V
VDDA
VSSA
A/D Converter 5V &
DDRA DDRB
PTA PTB
DDRE
PTE
AD1
AD0
PTK
DDRK
PTT
DDRT
PTP
DDRP PTS
DDRS
PTM
DDRM
PTH
DDRH PTJ
DDRJ
PK2
BDLC RxB
TxB
Clock and
Reset
Generation
Module
Voltage Regulator
VSSR
Debug Module
VDD1,2
VSS1,2
VREGEN
VDDR
VSSR
Voltage Regulator 5V & I/O
CAN4 RxCAN
TxCAN
MISO
MOSI
SCK
SS
SPI1
PIX4
PIX5 PK4
PK5 XADDR18
XADDR19
Voltage Regulator Reference
KWP2
KWP6
KWP0
KWP7
KWP1
KWP3
KWP4
KWP5
KWJ6
KWJ7
Timer
(J1850)
Signals shown in Bold are not available in the 80 Pin Package Option
Module to Port Routing
RX_BF
TX_BF
BYTE-
BF_PSYN
BF_PROK
BF_PERR
BF_PSLM
FLIGHT
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MC9S12DT128B Device User Guide — V01.09
1.5 Device Memory Map
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DT128B after reset. Note that
after reset the EEPROM ($0000 – $07FF) is hidden by the register space ($0000 - $03FF) and the RAM
($0000 - $1FFF). The bottom 1K Bytes of RAM ($0000 - $03FF) are hidden by the register space.
Table 1-1 Device Memory Map
Address Module Size
(Bytes)
$0000 – $0017 CORE (Ports A, B, E, Modes, Inits, Test) 24
$0018 – $0019 Reserved 2
$001A – $001B Device ID register (PARTID) 2
$001C – $001F CORE (MEMSIZ, IRQ, HPRIO) 4
$0020 – $0027 Reserved 8
$0028 – $002F CORE (Background Debug Mode) 8
$0030 – $0033 CORE (PPAGE, Port K) 4
$0034 – $003F Clock and Reset Generator (PLL, RTI, COP) 12
$0040 – $007F Enhanced Capture Timer 16-bit 8 channels 64
$0080 – $009F Analog to Digital Converter 10-bit 8 channels (ATD0) 32
$00A0 – $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
$00C8 – $00CF Serial Communications Interface (SCI0) 8
$00D0 – $00D7 Serial Communications Interface (SCI1) 8
$00D8 – $00DF Serial Peripheral Interface (SPI0) 8
$00E0 – $00E7 Inter IC Bus 8
$00E8 – $00EF Byte Level Data Link Controller (BDLC) 8
$00F0 – $00F7 Serial Peripheral Interface (SPI1) 8
$00F8 – $00FF Reserved 8
$0100 – $010F Flash Control Register 16
$0110 – $011B EEPROM Control Register 12
$011C – $011F Reserved 4
$0120 – $013F Analog to Digital Converter 10-bit 8 channels (ATD1) 32
$0140 – $017F Motorola Scalable CAN (CAN0) 64
$0180 – $01BF Motorola Scalable CAN (CAN1) 64
$01C0 – $01FF Reserved 64
$0200 – $023F Reserved 64
$0240 – $027F Port Integration Module (PIM) 64
$0280 – $02BF Motorola Scalable CAN (CAN4) 64
$02C0 – $02FF Reserved 64
$0300 – $035F Byteflight (BF) 96
$0360 – $03FF Reserved 160
$0000 – $07FF EEPROM array 2048
$0000 – $1FFF RAM array 8192
$4000 – $7FFF Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at start 16384
$8000 – $BFFF Flash EEPROM Page Window 16384
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MC9S12DT128B Device User Guide — V01.09
Figure 1-2 MC9S12DT128B Memory Map
$C000 – $FFFF Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80 – $FFFF 16384
Table 1-1 Device Memory Map
Address Module Size
(Bytes)
$0000
$FFFF
$C000
$8000
$4000
$0400
$0800
$1000
$2000
$FF00
EXT
NORMAL
SINGLE CHIP EXPANDED SPECIAL
SINGLE CHIP
VECTORSVECTORS VECTORS
$FF00
$FFFF
BDM
(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$8000
$BFFF
16K Page Window
eight * 16K Flash EEPROM Pages
$4000
$7FFF 16K Fixed Flash EEPROM
0.5K, 1K, 2K or 4K Protected Sector
$2000
$3FFF
8K Bytes RAM
Mappable to any 8K Boundary
$0800
$0FFF
2K Bytes EEPROM
Mappable to any 2K Boundary
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
The address does not show the map after reset, but a useful map. After reset the map is:
$0000 – $03FF: Register Space
$0000 – $1FFF: 8K RAM
$0000 – $07FF: 2K EEPROM (not visible)
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MC9S12DT128B Device User Guide — V01.09
1.5.1 Detailed Register Map
$0000 - $000F MEBI map 1 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0000 PORTA Read: Bit 7 654321Bit 0
Write:
$0001 PORTB Read: Bit 7 654321Bit 0
Write:
$0002 DDRA Read: Bit 7 654321Bit 0
Write:
$0003 DDRB Read: Bit 7 654321Bit 0
Write:
$0004 Reserved Read: 00000000
Write:
$0005 Reserved Read: 00000000
Write:
$0006 Reserved Read: 00000000
Write:
$0007 Reserved Read: 00000000
Write:
$0008 PORTE Read: Bit 7 65432
Bit 1 Bit 0
Write:
$0009 DDRE Read: Bit 7 6543Bit 2 00
Write:
$000A PEAR Read: NOACCE 0PIPOE NECLK LSTRE RDWE 00
Write:
$000B MODE Read: MODC MODB MODA 0IVIS 0EMK EME
Write:
$000C PUCR Read: PUPKE 00
PUPEE 00
PUPBE PUPAE
Write:
$000D RDRIV Read: RDPK 00
RDPE 00
RDPB RDPA
Write:
$000E EBICTL Read: 0000000
ESTR
Write:
$000F Reserved Read: 00000000
Write:
$0010 - $0014 MMC map 1 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0010 INITRM Read: RAM15 RAM14 RAM13 RAM12 RAM11 00
RAMHAL
Write:
$0011 INITRG Read: 0 REG14 REG13 REG12 REG11 000
Write:
$0012 INITEE Read: EE15 EE14 EE13 EE12 000
EEON
Write:
$0013 MISC Read: 0000
EXSTR1 EXSTR0 ROMHM ROMON
Write:
$0014 MTST0
Test Only Read: Bit 7 654321Bit 0
Write:
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MC9S12DT128B Device User Guide — V01.09
$0015 - $0016 INT map 1 of 2 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0015 ITCR Read: 0 0 0 WRINT ADR3 ADR2 ADR1 ADR0
Write:
$0016 ITEST Read: INTE INTC INTA INT8 INT6 INT4 INT2 INT0
Write:
$0017 - $0017 MMC map 2 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0017 MTST1
Test Only Read: Bit 7 654321Bit 0
Write:
$0018 - $001B Miscellaneous Peripherals (Device User Guide, Table 1-3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0018 Reserved Read: 00000000
Write:
$0019 Reserved Read: 00000000
Write:
$001A PARTIDH Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
Write:
$001B PARTIDL Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Write:
$001C - $001D MMC map 3 of 4 (Core and Device User Guide, Table 1-4)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001C MEMSIZ0 Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
Write:
$001D MEMSIZ1 Read: rom_sw1 rom_sw0 0000pag_sw1 pag_sw0
Write:
$001E - $001E MEBI map 2 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001E INTCR Read: IRQE IRQEN 000000
Write:
$001F - $001F INT map 2 of 2 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001F HPRIO Read: PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0
Write:
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MC9S12DT128B Device User Guide — V01.09
$0020 - $0027 Reserved
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0020 -
$0027 Reserved Read: 00000000
Write:
$0028 - $002F BKP (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0028 BKPCT0 Read: BKEN BKFULL BKBDM BKTAG 0000
Write:
$0029 BKPCT1 Read: BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
Write:
$002A BKP0X Read: 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0
Write:
$002B BKP0H Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
$002C BKP0L Read: Bit 7 654321Bit 0
Write:
$002D BKP1X Read: 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0
Write:
$002E BKP1H Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
$002F BKP1L Read: Bit 7 654321Bit 0
Write:
$0030 - $0031 MMC map 4 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0030 PPAGE Read: 0 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
Write:
$0031 Reserved Read: 00000000
Write:
$0032 - $0033 MEBI map 3 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0032 PORTK Read: Bit 7 654321Bit 0
Write:
$0033 DDRK Read: Bit 7 654321Bit 0
Write:
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MC9S12DT128B Device User Guide — V01.09
$0034 - $003F CRG (Clock and Reset Generator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0034 SYNR Read: 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
Write:
$0035 REFDV Read: 0000
REFDV3 REFDV2 REFDV1 REFDV0
Write:
$0036 CTFLG
TEST ONLY Read: 00000000
Write:
$0037 CRGFLG Read: RTIF PORF 0LOCKIF LOCK TRACK SCMIF SCM
Write:
$0038 CRGINT Read: RTIE 00
LOCKIE 00
SCMIE 0
Write:
$0039 CLKSEL Read: PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
Write:
$003A PLLCTL Read: CME PLLON AUTO ACQ 0PRE PCE SCME
Write:
$003B RTICTL Read: 0 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
Write:
$003C COPCTL Read: WCOP RSBCK 000
CR2 CR1 CR0
Write:
$003D FORBYP
TEST ONLY Read: 00000000
Write:
$003E CTCTL
TEST ONLY Read: 00000000
Write:
$003F ARMCOP Read: 00000000
Write: Bit 7 654321Bit 0
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0040 TIOS Read: IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Write:
$0041 CFORC Read: 00000000
Write: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
$0042 OC7M Read: OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
Write:
$0043 OC7D Read: OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Write:
$0044 TCNT (hi) Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
$0045 TCNT (lo) Read: Bit 7 654321Bit 0
Write:
$0046 TSCR1 Read: TEN TSWAI TSFRZ TFFCA 0000
Write:
$0047 TTOV Read: TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
Write:
$0048 TCTL1 Read: OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
Write:
$0049 TCTL2 Read: OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
Write:
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