2013-2018 Microchip Technology Inc. DS80000574G- page 1
PIC32MX330/350/370/430/450/470
The PIC32MX330/350/370/430/450/470 family of
devices that you have received conform functionally to
the current Device Data Sheet (DS60001185G), except
for the anomalies described in this doc ument.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1 through Table 4. The silicon issues are
summarized in Table 5.
The errata described in this document w ill be addressed
in future revisions of the PIC32MX330/350/370/430/450/
470 family silicon.
Data Sheet clarifications and corrections (if applicable)
start on page 14, following the discussion of silicon
issues.
The silicon revision level can be identified using the
current version of MPLAB
®
X IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
For example, to identify the silicon revision level
using MPLAB X IDE in conjunction with a hardware
debugger:
1. Using the appropriate interface, connect the
device to the hardware deb ugg er.
2. Open an MPLAB X IDE project.
3. Configure the MPLAB X IDE project for the
appropriate device and hardware debugger.
4. Select Window > Das hboard, and the n click
the Refresh Debug Tool Status icon
().
5. The part number and the Device and
Revision ID values appear in the Output
window.
The Device and Revision ID values for the various
PIC32MX330/350/370/430/450/470 silicon revisions
are shown in Table 1 and Table 4.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 5 apply to the current silicon
revision (A1).
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES FOR DEVICES WITH 64 KB FLASH MEMORY
Part Number Flash Memory Size
(KB) Device ID
(1)
Revision ID for
Silicon Revision
(1)
A0 A1
PIC32MX330F064H 64 0x05600053
0x0 0x1
PIC32MX330F064L 64 0x05601053
PIC32MX430F064H 64 0x05602053
PIC32MX430F064L 64 0x05603053
Note 1: Refer to the “Memory O rga niz ation ” and “Special Features” chapters in the current Device Data Sheet
(DS60001185G) for detailed information on Device and Revision IDs for your specific device.
PIC32MX330/350/370/430/450/470 Family Silicon Errata
and Data Sheet Clarif ication
2013-2018 Microchip Technology Inc. DS80000574G- page 2
PIC32MX330/350/370/430/450/470
TABLE 3: SILICON DEVREV VALUES FOR DEVICES WITH 256 KB FLASH MEMORY
TABLE 2: SILICON DEVREV VALUES FOR DEVICES WITH 128 KB FLASH MEMORY
Part Number Flash Memory Size
(KB) Device ID
(1)
Revision ID for Silicon Revision
(1)
A0 A1 B0
PIC32MX350F128H 128 0x0570C053
0x0 0x1 0x8
PIC32MX350F128L 128 0x0570D053
PIC32MX450F128H 128 0x0570E053
PIC32MX450F128L 128 0x0570F053
Note 1: Refer to th e “ Memory O rganizati on” and “ Spec ial Featur es” c hap ters in th e curre nt De vic e Dat a Shee t
(DS60001185G) for detailed information on Device and Revision IDs for your specific device.
Part Number Flash Memory Size
(KB) Device ID
(1)
Revision ID for Silicon Revision
(1)
A0 A1 B1
PIC32MX350F256H 256 0x05704053
0x0 0x1 0xA
PIC32MX350F256L 256 0x05705053
PIC32MX450F256H 256 0x05706053
PIC32MX450F256L 256 0x05707053
Note 1: Refer to th e “ Memory O rganizati on” and “ Spec ial Featur es” c hap ters in th e curre nt De vic e Dat a Shee t
(DS60001185G) for detailed information on Device and Revision IDs for your specific device.
TABLE 4: SILICON DEVREV VALUES FOR DEVICES WITH 512 KB FLASH MEMORY
Part Number Device ID
(1)
Revision ID for Silicon Revision
(1)
A0
PIC32MX370F512H 0x05808053
0x0
PIC32MX370F512L 0x05809053
PIC32MX470F512H 0x0580A053
PIC32MX470F512L 0x0580B053
Note 1: Refer to the “Mem ory Organi zation” and “Special Featu res” chapters in the current Device Data Sheet
(DS60001185G) for detailed information on Device and Revision IDs for your specific device.
2013-2018 Microchip Technology Inc. DS80000574G- page 3
PIC32MX330/350/370/430/450/470
TABLE 5: SILICON ISSUE SUMMARY
Module Feature Item
#Issue Summary
Affected Revisions
Flash
Memory
(KB) A0 A1 B0 B1
ADC Differential
Nonlinearity 1. The ADC module is not wi th in the published data sh eet
specific at i on when operating at a conversion r at e ab ove
500 ksp s.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Clock Clock Out 2.
A clock signal is present on the CLKO pin, regar dl ess of
the clock source and setti ng of the CLKO Enabl e
Configuration bit, during a Power-on Reset (POR)
condition.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Reserved — 3. — — ————
I/O I/O 4. Port pin RF6 is not 5V toler ant. Use RF6 as a non -5 V
tolerant pi n only.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
5V Tolerant
I/O Pins Pull-ups 5. Internal pull-up resistors may not guarantee a logical ‘1’ on
digital input s on 5V tolerant pins.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Non-5V
Tolerant I/O
Pins Pull-ups 6. Internal pull-up resistors may not guarantee a logical ‘1’ on
digital input s on non-5V tolera nt pi ns.
64 X — —
128 X —
256 X —
512 — — —
I
2
CSlave Mode 7. When the I
2
C slave re cei ves any of the re ser ve address
with STRICT = 1, an ACK will be generated, but an
interru pt will not be generated.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
JTAG Boundary Scan 8. Boundary Scan is not supported.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Legend: An ‘X’ indicates the issue is present in this revision of the silicon.
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue.
Blank cell s indi cate an issue has been correct ed o r does not exist in this revision of the sil icon.
2013-2018 Microchip Technology Inc. DS80000574G- page 4
PIC32MX330/350/370/430/450/470
Watchdog
Timer Window ed
Watchdog 9. Clearing the Watchdog Timer inside the window w hen in
Wind ow mode may cause a re set.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Debug De bug Pi ns 10. On-chip deb ug pi ns require spe cial consideratio n.
64 — —
128 X X X —
256 X X — X
512 — — —
USB Idle Interrupt 11. USB Idle interrupts cease if the IDLEIF flag is cleared and
the bus is le ft id le fo r m or e t han 3 ms.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
I/O Port Open Drai n 12. The Open Dra in selection (ODCx) on I/O port pins is no t
availabl e when the pin is conf i gur ed for anything oth er
tha n a stan dard port ou t put .
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Flash
Memory Flash Memory 13. The Program Write Protection (PWP) bits are not able to
protect all 512 KB of Flash memory on PIC32MX370/470
devices.
64 — —
128 —
256 —
512 X — — —
Timer1 Interrupts 14. Under specific conditions, Timer1 will not generate
interrupts.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
UART Auto-baud 15. The Automatic Baud Rate feature does not function t o set
the baud r ate.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
TABLE 5: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item
#Issue Summary
Affected Revisions
Flash
Memory
(KB) A0 A1 B0 B1
Legend: An ‘X’ indicates the issue is present in this revision of the silicon.
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue.
Blank cell s indi cate an issue has been correct ed o r does not exist in this revision of the sil icon.
2013-2018 Microchip Technology Inc. DS80000574G- page 5
PIC32MX330/350/370/430/450/470
UART Synchronization 16. On a RX FIFO overflow, shift registers stop receiving data,
which causes the UART to lose synchronizatio n.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
CTMU Module
Operation 17. The CTMU m odule is not functional
64 X X — —
128 X X X —
256 X X —X
512 X — — —
ADC IV
REF
Sensing 18. Testing t he IV
REF
setting with t he ADC mo dule does not
function as intended.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
HVD HVDR 19. On power-u p, th e Hi gh- Voltage Detect Re set event flag,
RCON<HVDR> is being set.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Power-
Saving
Modes Idle 20. On exit from Sleep mode, the SLEEP and IDLE status bits
in the RCO N register are be in g set .
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Flash
Memory Write Protection 21. When enabl ed, t he Boot Write Protect (BW P ) bit also
protects and overlaps the first page of user program space
below 0x1000 in addition to the boot segment
64 X X — —
128 X X X —
256 X X —X
512 X — — —
Flash
Memory Write Protecti on 22. Th e Program Wr i te Prot ection ( PWP) bit f i eld is off by one
page relat iv e t o th e definition in the da ta she et .
64 X X — —
128 X X X —
256 X X —X
512 X — — —
TABLE 5: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item
#Issue Summary
Affected Revisions
Flash
Memory
(KB) A0 A1 B0 B1
Legend: An ‘X’ indicates the issue is present in this revision of the silicon.
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue.
Blank cell s indi cate an issue has been correct ed o r does not exist in this revision of the sil icon.
2013-2018 Microchip Technology Inc. DS80000574G- page 6
PIC32MX330/350/370/430/450/470
Flash
Memory Write Protecti on 23. The Program Write Protection (PWP) bits are not enabled
unless the Boot Write Protect (BWP) bit is also enabled.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
I/O Pins Peripheral Pin
Select (PPS) 24. Th e RPF 3 pin is not avai l abl e f or PPS f unct i ons on USB
devices.
64 X X — —
128 X X X —
256 X X —X
512 X — — —
TABLE 5: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item
#Issue Summary
Affected Revisions
Flash
Memory
(KB) A0 A1 B0 B1
Legend: An ‘X’ indicates the issue is present in this revision of the silicon.
Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue.
Blank cell s indi cate an issue has been correct ed o r does not exist in this revision of the sil icon.
2013-2018 Microchip Technology Inc. DS80000574G- page 7
PIC32MX330/350/370/430/450/470
Silicon Errat a Issues
1. Module: ADC
When the ADC is configured for 10-bit operation,
the spec ifi ca tio ns in th e da ta s hee t are not met for
operation above 500 ksps.
Work around
For 600 ks ps ope rati on, R
IN
= 500 ohm s, T
SAMP
=
2 T
AD
. The module specifications are shown in
Table 6. For 100 0 ksps oper ation, R
IN
= 200 oh ms,
T
SAMP
= 2 T
AD
. The module specifications are
shown in Table 7.
Affected Silicon Revisions
Note 1: This do cument summarizes al l silicon errata issues from all revisions of si licon, previous as well as current.
The table provided in each issue indicates which issues exist for a particular revision of silicon based on
Flash memory size.
2: The following applies to the Affected Silicon Revision tables in each silicon issue:
• An ‘X’ indicates the issue is present in this revision of silicon
• Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue
• Blank cells indicate an issue has been corrected or does not exist in this revision of silicon.
TABLE 6: 600 KSPS OPERATION
Parameter No. Symbol Minimum Typical Maximum Units
AD17 R
IN
— — 200 Ohm
ADC Accuracy – Measurements taken with External V
REF
+/V
REF
-
AD21c INL -1.5 — 1.5 LSB
AD22c DNL -1.4 — 2.1 LSB
AD23c G
ERR
-1.2 — 1.2 LSB
ADC Accuracy – Measurements taken with Internal V
REF
+/V
REF
-
AD21d INL -1.5 — 1.5 LSB
AD22d DNL -1.4 — 2.1 LSB
TABLE 7: 1000 KSPS OPERATION
Parameter No. Symbol Minimum Typical Maximum Units
AD17 R
IN
— — 200 Ohm
ADC Accuracy – Measurements taken with External V
REF
+/V
REF
-
AD21c INL -5.2 — 6.5 LSB
AD22c DNL -3.4 — 7 LSB
AD23c G
ERR
-1.5 — 1.5 LSB
ADC Accuracy – Measurements taken with Internal V
REF
+/V
REF
-
AD21d INL -5.2 — 6.5 LSB
AD22d DNL -3.4 — 7 LSB
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X —
X
512 X — —
—
2013-2018 Microchip Technology Inc. DS80000574G- page 8
PIC32MX330/350/370/430/450/470
2. Module: Clock
A clock signal is present on the CLKO pin,
regardless of the clock source and setting of the
CLKO Enable Configuration bit, OSCIOFNC
(DEVCFG1<10>), during a Power-on Reset
(POR) condition.
Work around
Do not connect the CLKO pin to a device that
would be adversely affected by rapid pin toggling
or a frequency other than that defined by the
oscillator configuration. Do not use the CLKO pin
as an input if the device connected to the CLKO
pin would be adversely affected by the pin driving
a signal out.
Affected Silicon Revisions
3. Module: Reserved
The issu e, previously report ed in a prior revisio n of
this erra ta, is no lon ger relevant a nd was remo ved.
4. Module: I/O
The port pin, RF6, is not 5V tolerant. Use RF6
as a non-5V tolerant pin only.
Work around
None.
Affected Silicon Revisions
5. Module: 5V Tolerant I/O Pins
When internal pull-ups are enabled on 5V tolerant
pins, the level as measured on the pin and
availab le to e xternal d evice i nputs may not exc eed
the minimum value of V
IH
, and therefore qualify as
a logic “high”. However, with respect to the PIC32
device, as long as V
DD
3V and the load doesn't
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the device.
Work around
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA or V
DD
< 3V
Affected Silicon Revisions
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
2013-2018 Microchip Technology Inc. DS80000574G- page 9
PIC32MX330/350/370/430/450/470
6. Module: Non-5V Tolerant I/O Pins
When internal pull-ups are enabled on non-5V
toler ant pins, the leve l as mea sured on the pin an d
available to external device inputs may not exceed
the minimum value of V
IH
, and therefore qualify as
a logic “high”. However, with respect to the PIC32
device, as long as V
DD
3V and the load doesn't
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the device.
Work around
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA or V
DD
< 3V
Affected Silicon Revisions
7. Module: I
2
C
The slave address, 0x78, is one of a group of
reserve d addresses. It is us ed as the upper byte of
a 10-bit address when 10-bit addressing is
enabled. The I
2
C module control register allows
the programmer to enable both 10-bit addressing
and strict enforcement of reserved addressing,
with the A10M and STRICT bits, respectively.
When both bits are cleared, the device should
respond to the reserved address 0x78, but it does
not.
Work around
None.
Affected Silicon Revisions
8. Module: JTAG
Boundary Scan is not supported.
Work around
None.
Affected Silicon Revisions
9. Module: Watchdog Timer
When the Watchdog Timer module is used in
Windowed mode, the module may issue a reset
even if the use r tri es to clea r the m odule withi n the
allowed window.
Work around
None.
Affected Silicon Revisions
10. Module: Debug
For PIC32MX350/450 devices, the programming
pin pairs at PGEC2/PGED2 and PGEC3/PGED3
may not function for on-chip debugging if
PGEC1 is open or is a logical “high”.
Work arounds
1. Use the PGEC1/PGED1 pins for
debugging, or
2. Hold PGEC1 to V
SS
with an external
resistor with a value of 150k or less while
debuggi ng on another pair.
Affected Silicon Revisions
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X —
—
128 X
—
256 X
—
512 — —
—
Device Flash
Memory (KB) Device Sili con Revision
A0 A1 B0 B1
64 X X —
—
128 XXX
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Sili con Revision
A0 A1 B0 B1
64 —
—
128 X X X
—
256 X X —X
512 — —
—
2013-2018 Microchip Technology Inc. DS80000574G- page 10
PIC32MX330/350/370/430/450/470
11. Module: USB
If the bus has been idle for more than 3 ms, the
IDLEIF interrupt flag is set. If software clears the
inter rupt fl ag and the bus rem ain s idl e, the IDL EIF
interrupt flag will not be set again.
Work around
Software can leave the IDLEIF bit set until it has
received some indication of bus resumption (i.e.,
Resume, Reset, SOF, or Error).
Affected Silicon Revisions
12. Module: I/O Port
The Ope n D rai n s ele cti on (OD Cx ) on I /O port pins
is not available when the pin is configured for
anything other than a standard port output. In
additio n, the Open Drain feature is not available for
dedicated or remappable Peripheral Pin Select
(PPS) output features .
Work around
None.
Affected Silicon Revisions
13. Module: Flash Memory
The Program Write Protection (PWP) bits are not
able to protect all 512 KB of Flash memory on
PIC32MX370/470 devices.
Work around
The PWP<7:0> bits in the DEVCFG0
Configuration register can protect a maximum of
508 KB of Flash memory.
Use a PWP<7:0> value of 0x10000000 for a
maximum of 508 KB (memory location
0xBD07EFFF).
Affected Silicon Revisions
14. Module: Timer1
Timer1 fails to generate interrupts when
configu r ed as follows :
• Extern al Cloc k Inpu t and
• Asynchronous Clock and
• Prescaler other than 1:1
Work around
Any other combination of the timer will generate
interrupts as expected. For example, Synchronous
mode or leaving the prescaler at 1:1.
Affected Silicon Revisions
Note: Resum e and Res et are the o nly inter-
rupts that should be following IDLEIF
assertion. If the IDLEIF bit is set, it
should be okay to suspend the USB
module (as long as this code is
protected by the GUARD and/or
ACTPEND logic). This will require
software to clear the IDLEIF interrupt
enable bit to exit the USB ISR (if
using interrupt driven code).
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Sili con Revision
A0 A1 B0 B1
64 —
—
128
—
256
—
512 X — —
—
Device Flash
Memory (KB) Device Sili con Revision
A0 A1 B0 B1
64 X X —
—
128 XXX
—
256 X X
—
X
512 X — —
—
2013-2018 Microchip Technology Inc. DS80000574G- page 11
PIC32MX330/350/370/430/450/470
15. Module: UART
The UAR T Autom atic baud rate feature is intended
to set the baud rate during run-time based on
external data input . However, this fea ture does n ot
function.
Work around
None.
Affected Silicon Revisions
16. Module: UART
During a RX FIFO overflow condition, the shift
register stops receiving data. This causes the
UART to lose synchronization with the serial data
stream. The on ly way to rec over from thi s is to turn
the UART OFF and ON until it synchronizes. This
could require several OFF/ON sequences.
Work arounds
Work around 1:
Avoid the RX overrun condition by ensuring that
the UARTx module has a high enough interrupt
priority such that other peripheral interrupt
processing latencies do not exceed the time to
overrun the UART RX buffer based on the
application baud rate. Alternately or in addition to,
set the URXISEL bits in the UxSTA register to
generate an earlier RX interrupt based on RX
FIFO fill status to buy more time for interrupt
latency processing requirements.
Work around 2:
If avoiding RX FIFO overruns is not possible,
implement a ACK/NAK software handshake
protocol to repeat lost packet transfers after
restoring UART synchronization.
Affected Silicon Revisions
17. Module: CTMU
The CTMU module is not functional.
Work around
None.
Affected Silicon Revisions
18. Module: ADC
Converting the Internal Band Gap (IV
REF
) voltage
source generates a High-Voltage Detect (HVD)
event and aborts the conversion; therefore, this
feature is not functional.
Work around
None.
Affected Silicon Revisions
19. Module: HVD
On power-up, the High-Voltage Detect Reset,
event flag, RCON<HVDR>, is set incorrectly.
On a power-up, only the POR, BOR, and EXTR
bits should be set with the proper V
CAP
bypass
capacitor value, as stated in the current data
sheet.
Work around
Check the status of the POR bit in the RCON
register when checking the HVDR bit. If the POR
bit is se t, both b its can be cle ared as the HVDR bit
is a false detection. If the POR bit is clear, the
HVDR bit has been correctly detected and can be
handled according to the requirements of the
application.
Affected Silicon Revisions
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Sili con Revision
A0 A1 B0 B1
64 X X —
—
128 XXX
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Sili con Revision
A0 A1 B0 B1
64 X X —
—
128 XXX
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Sili con Revision
A0 A1 B0 B1
64 X X —
—
128 XXX
—
256 X X
—
X
512 X — —
—
2013-2018 Microchip Technology Inc. DS80000574G- page 12
PIC32MX330/350/370/430/450/470
20. Module: Power-Saving Modes
On exit from Sleep mode, both the SLEEP and
IDLE status bits in the RCON register are set.
Work around
Add the following code to the user application at
the point it wakes from Sleep mode:
rcon_var1 = RCON;
// ... enter Sleep mode
if (rcon_var1 & 0x4) Nop();
// If IDLE bit already set previously
// before sleep do nothing
else RCONbits.IDLE = 0x0;
// If IDLE bit is not set previously
// and is after Sleep mode then clear
Affected Silicon Revisions
21. Module: Flash Memory
When enabled, the Boot Write Protect (BWP) bit
inadvertently also protects and overlaps the first
page of PWP user program space below 0x1000,
(i.e., PWP<7:0> = 0xFE), in addition to the boot
segment, regardless of the state of the Program
Write Protection (PWP) bits (DEVCFG0<19:12>).
If BWP is enabled by setting the BWP bit
(DEVCFG0<24>) = 0, users cannot Page Erase or
program the first page of the PWP user program
space. Only u ser run -time P age Eras e or Pro gram
operations are affected, which does not include a
Bulk erase of the entire Flash.
Work around
None.
Please refer to silicon issues 22 and 23
for related information
Affected Silicon Revisions
22. Module: Flash Memory
The Progra m W rit e Protectio n (PWP ) bit fi eld is off
by one page rela tive to th e data sh eet defini tion. In
silicon, PWP<7:0> = (n + 1), where ‘n’ is the
DEVCFG0<19:12> value as defined in the data
sheet.
TABLE 8: PWP BITS (DEVCFG0<19:12>)
Work around
Set the PWP<7:0> bits (DEVCFG0<19:12>) =
(DEVCFG0<PWP> - 1) to correct for the first page
protection offset. Please refer to silicon issues 21
and 23 for related information.
Affected Silicon Revisions
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X
—
X
512 X — —
—
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X —X
512 X — —
—
Value Expected Actual
11111111 Disabled Disabled
11111110 Memory below
0x01000 is write
protected
Disabled
11111101 Memory below
0x02000 is write
protected
Memory below
0x01000 is w rite
protected
...
01111111 Memory below
0x80000 is write
protected
Memory below
0x7F000 is write
protected
Device Flash
Memory (KB) Device Sili con Revision
A0 A1 B0 B1
64 X X —
—
128 XXX
—
256 X X —X
512 X — —
—
2013-2018 Microchip Technology Inc. DS80000574G- page 13
PIC32MX330/350/370/430/450/470
23. Module: Flash Memory
The Program Write Protection (PWP) bits
(DEVCFG0<19:12>) are not enabled unless the
Boot Write Protect (BWP) bit (DEVCFG0<24> is
also enabled (i.e., = 0).
Work around
None.
Please refer to silicon issues 21 and 22
for related information.
Affected Silicon Revisions
24. Module: I/O Pins
The RPF3 PPS (i.e. Peripheral Pin Select)
functions are not available on PIN32MX4xx USB
device variants. The PIC32MX3xx General
Purpose devices are not affected.
Work around
None.
Affected Silicon Revisions
Device Flash
Memory (KB)
Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X —X
512 X — —
—
Device Flash
Memory (KB) Device Silicon Revision
A0 A1 B0 B1
64 X X —
—
128 X X X
—
256 X X —X
512 X — —
—
2013-2018 Microchip Technology Inc. DS80000574G- page 14
PIC32MX330/350/370/430/450/470
Data Sheet Clarifications
The foll owing ty pographic c orrections and clar ification s
are to be no ted for the late st versio n of the device data
sheet (DS60001185G):
No clarifications to report at this time.
2013-2018 Microchip Technology Inc. DS80000574G- page 15
PIC32MX330/350/370/430/450/470
APPENDIX A: REVISION HISTOR Y
Rev A Docume nt (4/2013)
Initial release of this document; issued for revision A0
silicon.
Includes silico n issues 1 (ADC), 2 (Clock), 3 (Reserved),
4(I/O), 5 (5V Tolerant I/O Pins), 6 (Non-5V Tolerant I/O
Pins), 7 (I
2
C), 8 (JTAG), and 9 (Watchdog T imer).
Rev B Document (6/2013)
Updated the silicon revision to Rev. A1 and added the
PIC32MX350/430/450 devices.
Added silicon issues 10 (Debug), 11 (USB), and 12 (I/O
Port). Updated silicon issue 3 (Reserved).
Rev C Document (10/2013)
Added the 512 KB Flash memory devices
(PIC32MX370/470).
Updated silicon i ssue 1 (ADC).
Added silicon issues 13 (Flash Memory) and
14 (Timer1).
Rev D Document (6/2014)
Added Data Sheet Clarification 1 (Packaging) and
2 (Power-Down Current (I
PD
)).
Rev E Document (2/2015)
The document was updated for silicon revision B0
devices:
• 128 KB devices were moved from Table 1 to
Table 2.
• Added separate 128 KB row to Affected Silicon
Revisions tabl es.
Added silicon issues 15 (UART), 16 (UART),
17 (CTMU), 18 (ADC), 19 (HVD), and 20 ( Power-Saving
Modes), 21 (Flash Memory), 22 (Flash Memo ry), and 23
(Flash Memory).
Deleted silicon issue 3 (CTMU).
Rev F Document (6/2015)
Deleted Data Sheet Clarification 1 (Packaging).
Added Data Sheet Clarification 1 (Power-Down
Current (I
PD
)).
Updated Table 31-7.
Rev G Document (6/2018)
Added issue 24 (I/O Pins).
Removed Data Sheet Clarification 1 (Power-Down
Current I
PD
).
Added TABLE 3: “Silicon DEVREV Values For
Devices With 256 KB Flash Memory” to reflect
updates for the 256 Flash Memory.
2013-2018 Microchip Technology Inc. DS80000574G- page 16
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be su perseded by u pdates. It is y our respons ibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microc hip name and logo, the Micr ochip log o, Any Rate, A VR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, fl exPWR, Heldo,
JukeBl ox, KeeLo q, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technol ogy Incorporated in the U.S.A.
and other c ountri es.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Spe ed Control, HyperLight Load, IntelliMO S,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technol ogy Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacito r , AnyIn, A nyOut, BodyCom, CodeGuard,
CryptoAuthenticat ion, CryptoAutomotive, Crypt oCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
Jitt erBlocke r, KleerNe t, Kl ee r N et logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, Mult iT RAK, NetDetach, Omniscient Code Gener ation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerS mart, PureS ilicon,
QMatrix, REAL ICE, Ripple Blocker , SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microch i p Technology In corporated in the U.S .A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon S torage Technology is a registere d trademark of Microchip
Technology Inc. in other countries.
GestIC i s a reg i stered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microc hip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technolog y Incorporated, All Rights Reserv ed.
ISBN: 978-1-5224- 3223-4
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specif ications cont ained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly e volving. We at M icrochip are c omm itted t o c ontinuously impr oving t he c ode pr otection feat ures of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Mi llennium Copyright Act. If suc h a cts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microch ip rece iv ed ISO/T S -16 94 9:20 09 certific at ion for i ts worldw id e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hoppin g
devices, Serial EEPROMs, microperiph erals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949
==
DS80000574G-page 17 2013-2018 Microchip Technology Inc.
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